From dddc84d9fa6bde8684fa6a64bd90e5322ff5e299 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 12 Nov 2023 00:56:56 -0800 Subject: [PATCH] fpga/mqnic: Merge AU50 into unified Alveo design Signed-off-by: Alex Forencich --- fpga/mqnic/AU50/fpga_100g/Makefile | 25 - fpga/mqnic/AU50/fpga_100g/README.md | 24 - fpga/mqnic/AU50/fpga_100g/app | 1 - fpga/mqnic/AU50/fpga_100g/boot.xdc | 4 - fpga/mqnic/AU50/fpga_100g/common/vivado.mk | 137 - fpga/mqnic/AU50/fpga_100g/hbm.xdc | 2 - fpga/mqnic/AU50/fpga_100g/ip/cmac_gty.tcl | 106 - fpga/mqnic/AU50/fpga_100g/ip/cmac_usplus.tcl | 21 - fpga/mqnic/AU50/fpga_100g/ip/cms.tcl | 16 - fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl | 23 - .../fpga_100g/ip/pcie4c_uscale_plus_0.tcl | 34 - fpga/mqnic/AU50/fpga_100g/lib | 1 - fpga/mqnic/AU50/fpga_100g/rtl/common | 1 - fpga/mqnic/AU50/fpga_100g/rtl/fpga.v | 2942 ---------------- fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v | 1339 -------- fpga/mqnic/AU50/fpga_100g/rtl/sync_signal.v | 62 - .../AU50/fpga_100g/tb/fpga_core/Makefile | 250 -- .../AU50/fpga_100g/tb/fpga_core/mqnic.py | 1 - .../fpga_100g/tb/fpga_core/test_fpga_core.py | 766 ----- fpga/mqnic/AU50/fpga_25g/Makefile | 25 - fpga/mqnic/AU50/fpga_25g/README.md | 23 - fpga/mqnic/AU50/fpga_25g/app | 1 - fpga/mqnic/AU50/fpga_25g/boot.xdc | 4 - fpga/mqnic/AU50/fpga_25g/common/vivado.mk | 137 - fpga/mqnic/AU50/fpga_25g/hbm.xdc | 2 - fpga/mqnic/AU50/fpga_25g/ip/cms.tcl | 16 - fpga/mqnic/AU50/fpga_25g/ip/eth_xcvr_gty.tcl | 103 - fpga/mqnic/AU50/fpga_25g/ip/hbm_0.tcl | 23 - .../AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl | 34 - fpga/mqnic/AU50/fpga_25g/lib | 1 - fpga/mqnic/AU50/fpga_25g/rtl/common | 1 - fpga/mqnic/AU50/fpga_25g/rtl/fpga.v | 3013 ----------------- fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v | 1531 --------- fpga/mqnic/AU50/fpga_25g/rtl/sync_signal.v | 62 - .../mqnic/AU50/fpga_25g/tb/fpga_core/Makefile | 261 -- .../mqnic/AU50/fpga_25g/tb/fpga_core/mqnic.py | 1 - .../fpga_25g/tb/fpga_core/test_fpga_core.py | 782 ----- fpga/mqnic/Alveo/fpga_100g/README.md | 2 + .../fpga_100g/fpga_AU50}/Makefile | 7 +- .../fpga_100g/fpga_AU50}/config.tcl | 3 + .../fpga_AU50_app_dma_bench}/Makefile | 7 +- .../fpga_AU50_app_dma_bench}/config.tcl | 3 + .../fpga_100g/fpga_au50.xdc} | 0 .../fpga_100g/placement_au50.xdc} | 0 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v | 3 + fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v | 3 + fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v | 1722 ++++++++++ fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v | 7 + .../fpga_100g/tb/fpga_core/test_fpga_core.v | 6 + fpga/mqnic/Alveo/fpga_25g/README.md | 2 + .../fpga_25g/fpga_AU50}/Makefile | 7 +- .../fpga_25g/fpga_AU50}/config.tcl | 1 + .../fpga_25g/fpga_AU50_10g}/Makefile | 7 +- .../fpga_25g/fpga_AU50_10g}/config.tcl | 1 + .../fpga.xdc => Alveo/fpga_25g/fpga_au50.xdc} | 0 .../fpga_25g/placement_au50.xdc} | 0 fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v | 3 + fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v | 3 + fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v | 1711 ++++++++++ fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v | 7 + .../fpga_25g/tb/fpga_core/test_fpga_core.v | 6 + 61 files changed, 3499 insertions(+), 11787 deletions(-) delete mode 100644 fpga/mqnic/AU50/fpga_100g/Makefile delete mode 100644 fpga/mqnic/AU50/fpga_100g/README.md delete mode 120000 fpga/mqnic/AU50/fpga_100g/app delete mode 100644 fpga/mqnic/AU50/fpga_100g/boot.xdc delete mode 100644 fpga/mqnic/AU50/fpga_100g/common/vivado.mk delete mode 100644 fpga/mqnic/AU50/fpga_100g/hbm.xdc delete mode 100644 fpga/mqnic/AU50/fpga_100g/ip/cmac_gty.tcl delete mode 100644 fpga/mqnic/AU50/fpga_100g/ip/cmac_usplus.tcl delete mode 100644 fpga/mqnic/AU50/fpga_100g/ip/cms.tcl delete mode 100644 fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl delete mode 100644 fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl delete mode 120000 fpga/mqnic/AU50/fpga_100g/lib delete mode 120000 fpga/mqnic/AU50/fpga_100g/rtl/common delete mode 100644 fpga/mqnic/AU50/fpga_100g/rtl/fpga.v delete mode 100644 fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/AU50/fpga_100g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/AU50/fpga_100g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py delete mode 100644 fpga/mqnic/AU50/fpga_25g/Makefile delete mode 100644 fpga/mqnic/AU50/fpga_25g/README.md delete mode 120000 fpga/mqnic/AU50/fpga_25g/app delete mode 100644 fpga/mqnic/AU50/fpga_25g/boot.xdc delete mode 100644 fpga/mqnic/AU50/fpga_25g/common/vivado.mk delete mode 100644 fpga/mqnic/AU50/fpga_25g/hbm.xdc delete mode 100644 fpga/mqnic/AU50/fpga_25g/ip/cms.tcl delete mode 100644 fpga/mqnic/AU50/fpga_25g/ip/eth_xcvr_gty.tcl delete mode 100644 fpga/mqnic/AU50/fpga_25g/ip/hbm_0.tcl delete mode 100644 fpga/mqnic/AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl delete mode 120000 fpga/mqnic/AU50/fpga_25g/lib delete mode 120000 fpga/mqnic/AU50/fpga_25g/rtl/common delete mode 100644 fpga/mqnic/AU50/fpga_25g/rtl/fpga.v delete mode 100644 fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/AU50/fpga_25g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/AU50/fpga_25g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py rename fpga/mqnic/{AU50/fpga_100g/fpga => Alveo/fpga_100g/fpga_AU50}/Makefile (98%) rename fpga/mqnic/{AU50/fpga_100g/fpga => Alveo/fpga_100g/fpga_AU50}/config.tcl (99%) rename fpga/mqnic/{AU50/fpga_100g/fpga_app_dma_bench => Alveo/fpga_100g/fpga_AU50_app_dma_bench}/Makefile (98%) rename fpga/mqnic/{AU50/fpga_100g/fpga_app_dma_bench => Alveo/fpga_100g/fpga_AU50_app_dma_bench}/config.tcl (99%) rename fpga/mqnic/{AU50/fpga_100g/fpga.xdc => Alveo/fpga_100g/fpga_au50.xdc} (100%) rename fpga/mqnic/{AU50/fpga_100g/placement.xdc => Alveo/fpga_100g/placement_au50.xdc} (100%) create mode 100644 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v rename fpga/mqnic/{AU50/fpga_25g/fpga => Alveo/fpga_25g/fpga_AU50}/Makefile (98%) rename fpga/mqnic/{AU50/fpga_25g/fpga => Alveo/fpga_25g/fpga_AU50}/config.tcl (99%) rename fpga/mqnic/{AU50/fpga_25g/fpga_10g => Alveo/fpga_25g/fpga_AU50_10g}/Makefile (98%) rename fpga/mqnic/{AU50/fpga_25g/fpga_10g => Alveo/fpga_25g/fpga_AU50_10g}/config.tcl (99%) rename fpga/mqnic/{AU50/fpga_25g/fpga.xdc => Alveo/fpga_25g/fpga_au50.xdc} (100%) rename fpga/mqnic/{AU50/fpga_25g/placement.xdc => Alveo/fpga_25g/placement_au50.xdc} (100%) create mode 100644 fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v diff --git a/fpga/mqnic/AU50/fpga_100g/Makefile b/fpga/mqnic/AU50/fpga_100g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/mqnic/AU50/fpga_100g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/AU50/fpga_100g/README.md b/fpga/mqnic/AU50/fpga_100g/README.md deleted file mode 100644 index f893eac2c..000000000 --- a/fpga/mqnic/AU50/fpga_100g/README.md +++ /dev/null @@ -1,24 +0,0 @@ -# Corundum mqnic for Alveo U50 - -## Introduction - -This design targets the Xilinx Alveo U50 FPGA board. - -* FPGA: xcu50-fsvh2104-2-e -* MAC: Xilinx 100G CMAC -* PHY: 100G CAUI-4 CMAC and internal GTY transceivers -* RAM: 8GB HBM2 - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/AU50/fpga_100g/app b/fpga/mqnic/AU50/fpga_100g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/AU50/fpga_100g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/AU50/fpga_100g/boot.xdc b/fpga/mqnic/AU50/fpga_100g/boot.xdc deleted file mode 100644 index 5fb323e94..000000000 --- a/fpga/mqnic/AU50/fpga_100g/boot.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for FPGA boot logic - -set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] -set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/AU50/fpga_100g/common/vivado.mk b/fpga/mqnic/AU50/fpga_100g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/fpga/mqnic/AU50/fpga_100g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/AU50/fpga_100g/hbm.xdc b/fpga/mqnic/AU50/fpga_100g/hbm.xdc deleted file mode 100644 index aa147b0a5..000000000 --- a/fpga/mqnic/AU50/fpga_100g/hbm.xdc +++ /dev/null @@ -1,2 +0,0 @@ -# force debug hub to use HBM APB clock to prevent CDC issues -connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK] diff --git a/fpga/mqnic/AU50/fpga_100g/ip/cmac_gty.tcl b/fpga/mqnic/AU50/fpga_100g/ip/cmac_gty.tcl deleted file mode 100644 index 6a14c1f28..000000000 --- a/fpga/mqnic/AU50/fpga_100g/ip/cmac_gty.tcl +++ /dev/null @@ -1,106 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2022-2023 The Regents of the University of California - -set base_name {cmac_gty} - -set preset {GTY-CAUI_4} - -set freerun_freq {125} -set line_rate {25.78125} -set sec_line_rate {0} -set refclk_freq {161.1328125} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {80} -set int_data_width $user_data_width -set rx_eq_mode {LPM} -set extra_ports [list] -set extra_pll_ports [list] -# DRP connections -lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out -lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out -# PLL reset and power down -lappend extra_pll_ports qpll0reset_in qpll1reset_in -lappend extra_pll_ports qpll0pd_in qpll1pd_in -# PLL clocking -lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out -lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out -# channel reset -lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out -lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out -# channel power down -lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in -# channel clock selection -lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in -# channel polarity -lappend extra_ports txpolarity_in rxpolarity_in -# channel TX driver -lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in -# channel CDR -lappend extra_ports rxcdrlock_out rxcdrhold_in -# channel EQ -lappend extra_ports rxlpmen_in -# channel digital monitor -lappend extra_ports dmonitorout_out -# channel PRBS -lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out -# channel eye scan -lappend extra_ports eyescandataerror_out -# channel loopback -lappend extra_ports loopback_in - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config RX_EQ_MODE $rx_eq_mode -if {$sec_line_rate != 0} { - dict set config SECONDARY_QPLL_ENABLE true - dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn - dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq -} else { - dict set config SECONDARY_QPLL_ENABLE false -} -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} -dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN} -dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip - - # enable only one site - set_property CONFIG.CHANNEL_ENABLE [lindex [get_property CONFIG.CHANNEL_ENABLE $ip] 0] $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/AU50/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/AU50/fpga_100g/ip/cmac_usplus.tcl deleted file mode 100644 index af9cc8265..000000000 --- a/fpga/mqnic/AU50/fpga_100g/ip/cmac_usplus.tcl +++ /dev/null @@ -1,21 +0,0 @@ - -create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus - -set_property -dict [list \ - CONFIG.CMAC_CAUI4_MODE {1} \ - CONFIG.NUM_LANES {4x25} \ - CONFIG.USER_INTERFACE {AXIS} \ - CONFIG.GT_DRP_CLK {125} \ - CONFIG.GT_LOCATION {0} \ - CONFIG.TX_FLOW_CONTROL {1} \ - CONFIG.RX_FLOW_CONTROL {1} \ - CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \ - CONFIG.RX_CHECK_ACK {1} \ - CONFIG.INCLUDE_RS_FEC {1} \ - CONFIG.ENABLE_TIME_STAMPING {1} -] [get_ips cmac_usplus] - -# disable LOC constraint -set_property generate_synth_checkpoint false [get_files [get_property IP_FILE [get_ips cmac_usplus]]] -generate_target synthesis [get_files [get_property IP_FILE [get_ips cmac_usplus]]] -set_property is_enabled false [get_files -of_objects [get_files [get_property IP_FILE [get_ips cmac_usplus]]] cmac_usplus.xdc] diff --git a/fpga/mqnic/AU50/fpga_100g/ip/cms.tcl b/fpga/mqnic/AU50/fpga_100g/ip/cms.tcl deleted file mode 100644 index 22126d4d6..000000000 --- a/fpga/mqnic/AU50/fpga_100g/ip/cms.tcl +++ /dev/null @@ -1,16 +0,0 @@ - -# create block design -create_bd_design "cms" - -# create CMS IP -set cms_block [create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem cms_subsystem_0] -make_bd_pins_external $cms_block -make_bd_intf_pins_external $cms_block - -# assign addresses -assign_bd_address -target_address_space /s_axi_ctrl_0 [get_bd_addr_segs $cms_block/s_axi_ctrl/Mem0] -force - -# save block design and create HDL wrapper -save_bd_design [current_bd_design] -add_files -norecurse [make_wrapper -files [get_files [get_property FILE_NAME [current_bd_design]]] -top] -close_bd_design [current_bd_design] diff --git a/fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl b/fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl deleted file mode 100644 index a8cbc2874..000000000 --- a/fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl +++ /dev/null @@ -1,23 +0,0 @@ - -create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0 - -set_property -dict [list \ - CONFIG.USER_HBM_DENSITY {8GB} \ - CONFIG.USER_HBM_STACK {2} \ - CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true} -] [get_ips hbm_0] diff --git a/fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl b/fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl deleted file mode 100644 index 936d8b1e1..000000000 --- a/fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl +++ /dev/null @@ -1,34 +0,0 @@ - -create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0 - -set_property -dict [list \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ - CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ - CONFIG.axisten_if_enable_client_tag {true} \ - CONFIG.axisten_if_width {512_bit} \ - CONFIG.extended_tag_field {true} \ - CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ - CONFIG.axisten_freq {250} \ - CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ - CONFIG.PF0_CLASS_CODE {020000} \ - CONFIG.PF0_DEVICE_ID {1001} \ - CONFIG.PF0_SUBSYSTEM_ID {9032} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_prefetchable {true} \ - CONFIG.pf0_bar0_scale {Megabytes} \ - CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_msi_enabled {false} \ - CONFIG.pf0_msix_enabled {true} \ - CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ - CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ - CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ - CONFIG.MSI_X_OPTIONS {MSI-X_External} \ - CONFIG.vendor_id {1234} \ - CONFIG.mode_selection {Advanced} \ -] [get_ips pcie4c_uscale_plus_0] diff --git a/fpga/mqnic/AU50/fpga_100g/lib b/fpga/mqnic/AU50/fpga_100g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/AU50/fpga_100g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/common b/fpga/mqnic/AU50/fpga_100g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/AU50/fpga_100g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v deleted file mode 100644 index 43e206093..000000000 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ /dev/null @@ -1,2942 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B77093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_9032, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 1, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLOCK_PIPELINE = 1, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 1, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 131072, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 131072, - parameter RX_RAM_SIZE = 131072, - - // RAM configuration - parameter HBM_CH = 32, - parameter HBM_ENABLE = 0, - parameter HBM_GROUP_SIZE = HBM_CH, - parameter AXI_HBM_ADDR_WIDTH = 33, - parameter AXI_HBM_MAX_BURST_LEN = 16, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock and reset - */ - // input wire clk_100mhz_0_p, - // input wire clk_100mhz_0_n, - input wire clk_100mhz_1_p, - input wire clk_100mhz_1_n, - - /* - * GPIO - */ - output wire qsfp_led_act, - output wire qsfp_led_stat_g, - output wire qsfp_led_stat_y, - output wire hbm_cattrip, - input wire [1:0] msp_gpio, - output wire msp_uart_txd, - input wire msp_uart_rxd, - - /* - * PCI express - */ - input wire [15:0] pcie_rx_p, - input wire [15:0] pcie_rx_n, - output wire [15:0] pcie_tx_p, - output wire [15:0] pcie_tx_n, - input wire pcie_refclk_1_p, - input wire pcie_refclk_1_n, - input wire pcie_reset_n, - - /* - * Ethernet: QSFP28 - */ - output wire [3:0] qsfp_tx_p, - output wire [3:0] qsfp_tx_n, - input wire [3:0] qsfp_rx_p, - input wire [3:0] qsfp_rx_n, - input wire qsfp_mgt_refclk_0_p, - input wire qsfp_mgt_refclk_0_n - // input wire qsfp_mgt_refclk_1_p, - // input wire qsfp_mgt_refclk_1_n -); - -// PTP configuration -parameter PTP_CLK_PERIOD_NS_NUM = 1024; -parameter PTP_CLK_PERIOD_NS_DENOM = 165; -parameter PTP_TS_WIDTH = 96; - -// Interface configuration -parameter TX_TAG_WIDTH = 16; - -// RAM configuration -parameter HBM_CH_INT = 32; -parameter AXI_HBM_DATA_WIDTH = 256; -parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8); -parameter AXI_HBM_ID_WIDTH = 6; - -parameter HBM_CH_STRIDE = HBM_CH_INT / 2**$clog2(HBM_CH); - -// PCIe interface configuration -parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); -parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; -parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; -parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; -parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; -parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; -parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter RQ_SEQ_NUM_WIDTH = 6; -parameter PCIE_TAG_COUNT = 256; - -// Ethernet interface configuration -parameter AXIS_ETH_DATA_WIDTH = 512; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; -parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire pcie_user_clk; -wire pcie_user_reset; - -wire clk_161mhz_ref_int; - -wire clk_50mhz_mmcm_out; -wire clk_125mhz_mmcm_out; - -// Internal 50 MHz clock -wire clk_50mhz_int; -wire rst_50mhz_int; - -// Internal 125 MHz clock -wire clk_125mhz_int; -wire rst_125mhz_int; - -wire mmcm_rst = pcie_user_reset; -wire mmcm_locked; -wire mmcm_clkfb; - -// MMCM instance -// 161.13 MHz in, 50 MHz + 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 128, D = 15 sets Fvco = 1375 MHz (in range) -// Divide by 27.5 to get output frequency of 50 MHz -// Divide by 11 to get output frequency of 125 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(27.5), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(11), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(128), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(15), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_161mhz_ref_int), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_50mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(clk_125mhz_mmcm_out), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_50mhz_bufg_inst ( - .I(clk_50mhz_mmcm_out), - .O(clk_50mhz_int) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_50mhz_inst ( - .clk(clk_50mhz_int), - .rst(~mmcm_locked), - .out(rst_50mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// Flash -wire qspi_clk_int; -wire [3:0] qspi_dq_int; -wire [3:0] qspi_dq_i_int; -wire [3:0] qspi_dq_o_int; -wire [3:0] qspi_dq_oe_int; -wire qspi_cs_int; - -reg qspi_clk_reg; -reg [3:0] qspi_dq_o_reg; -reg [3:0] qspi_dq_oe_reg; -reg qspi_cs_reg; - -always @(posedge pcie_user_clk) begin - qspi_clk_reg <= qspi_clk_int; - qspi_dq_o_reg <= qspi_dq_o_int; - qspi_dq_oe_reg <= qspi_dq_oe_int; - qspi_cs_reg <= qspi_cs_int; -end - -sync_signal #( - .WIDTH(4), - .N(2) -) -flash_sync_signal_inst ( - .clk(pcie_user_clk), - .in({qspi_dq_int}), - .out({qspi_dq_i_int}) -); - -STARTUPE3 -startupe3_inst ( - .CFGCLK(), - .CFGMCLK(), - .DI(qspi_dq_int), - .DO(qspi_dq_o_reg), - .DTS(~qspi_dq_oe_reg), - .EOS(), - .FCSBO(qspi_cs_reg), - .FCSBTS(1'b0), - .GSR(1'b0), - .GTS(1'b0), - .KEYCLEARB(1'b1), - .PACK(1'b0), - .PREQ(), - .USRCCLKO(qspi_clk_reg), - .USRCCLKTS(1'b0), - .USRDONEO(1'b0), - .USRDONETS(1'b1) -); - -// FPGA boot -wire fpga_boot; - -reg fpga_boot_sync_reg_0 = 1'b0; -reg fpga_boot_sync_reg_1 = 1'b0; -reg fpga_boot_sync_reg_2 = 1'b0; - -wire icap_avail; -reg [2:0] icap_state = 0; -reg icap_csib_reg = 1'b1; -reg icap_rdwrb_reg = 1'b0; -reg [31:0] icap_di_reg = 32'hffffffff; - -wire [31:0] icap_di_rev; - -assign icap_di_rev[ 7] = icap_di_reg[ 0]; -assign icap_di_rev[ 6] = icap_di_reg[ 1]; -assign icap_di_rev[ 5] = icap_di_reg[ 2]; -assign icap_di_rev[ 4] = icap_di_reg[ 3]; -assign icap_di_rev[ 3] = icap_di_reg[ 4]; -assign icap_di_rev[ 2] = icap_di_reg[ 5]; -assign icap_di_rev[ 1] = icap_di_reg[ 6]; -assign icap_di_rev[ 0] = icap_di_reg[ 7]; - -assign icap_di_rev[15] = icap_di_reg[ 8]; -assign icap_di_rev[14] = icap_di_reg[ 9]; -assign icap_di_rev[13] = icap_di_reg[10]; -assign icap_di_rev[12] = icap_di_reg[11]; -assign icap_di_rev[11] = icap_di_reg[12]; -assign icap_di_rev[10] = icap_di_reg[13]; -assign icap_di_rev[ 9] = icap_di_reg[14]; -assign icap_di_rev[ 8] = icap_di_reg[15]; - -assign icap_di_rev[23] = icap_di_reg[16]; -assign icap_di_rev[22] = icap_di_reg[17]; -assign icap_di_rev[21] = icap_di_reg[18]; -assign icap_di_rev[20] = icap_di_reg[19]; -assign icap_di_rev[19] = icap_di_reg[20]; -assign icap_di_rev[18] = icap_di_reg[21]; -assign icap_di_rev[17] = icap_di_reg[22]; -assign icap_di_rev[16] = icap_di_reg[23]; - -assign icap_di_rev[31] = icap_di_reg[24]; -assign icap_di_rev[30] = icap_di_reg[25]; -assign icap_di_rev[29] = icap_di_reg[26]; -assign icap_di_rev[28] = icap_di_reg[27]; -assign icap_di_rev[27] = icap_di_reg[28]; -assign icap_di_rev[26] = icap_di_reg[29]; -assign icap_di_rev[25] = icap_di_reg[30]; -assign icap_di_rev[24] = icap_di_reg[31]; - -always @(posedge clk_125mhz_int) begin - case (icap_state) - 0: begin - icap_state <= 0; - icap_csib_reg <= 1'b1; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - - if (fpga_boot_sync_reg_2 && icap_avail) begin - icap_state <= 1; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - end - end - 1: begin - icap_state <= 2; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hAA995566; // sync word - end - 2: begin - icap_state <= 3; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - 3: begin - icap_state <= 4; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h30008001; // write 1 word to CMD - end - 4: begin - icap_state <= 5; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h0000000F; // IPROG - end - 5: begin - icap_state <= 0; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - endcase - - fpga_boot_sync_reg_0 <= fpga_boot; - fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; - fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; -end - -ICAPE3 -icape3_inst ( - .AVAIL(icap_avail), - .CLK(clk_125mhz_int), - .CSIB(icap_csib_reg), - .I(icap_di_rev), - .O(), - .PRDONE(), - .PRERROR(), - .RDWRB(icap_rdwrb_reg) -); - -// BMC -wire axil_cms_clk; -wire axil_cms_rst; -wire [17:0] axil_cms_awaddr; -wire [2:0] axil_cms_awprot; -wire axil_cms_awvalid; -wire axil_cms_awready; -wire [31:0] axil_cms_wdata; -wire [3:0] axil_cms_wstrb; -wire axil_cms_wvalid; -wire axil_cms_wready; -wire [1:0] axil_cms_bresp; -wire axil_cms_bvalid; -wire axil_cms_bready; -wire [17:0] axil_cms_araddr; -wire [2:0] axil_cms_arprot; -wire axil_cms_arvalid; -wire axil_cms_arready; -wire [31:0] axil_cms_rdata; -wire [1:0] axil_cms_rresp; -wire axil_cms_rvalid; -wire axil_cms_rready; - -wire [17:0] axil_cms_awaddr_int; -wire [2:0] axil_cms_awprot_int; -wire axil_cms_awvalid_int; -wire axil_cms_awready_int; -wire [31:0] axil_cms_wdata_int; -wire [3:0] axil_cms_wstrb_int; -wire axil_cms_wvalid_int; -wire axil_cms_wready_int; -wire [1:0] axil_cms_bresp_int; -wire axil_cms_bvalid_int; -wire axil_cms_bready_int; -wire [17:0] axil_cms_araddr_int; -wire [2:0] axil_cms_arprot_int; -wire axil_cms_arvalid_int; -wire axil_cms_arready_int; -wire [31:0] axil_cms_rdata_int; -wire [1:0] axil_cms_rresp_int; -wire axil_cms_rvalid_int; -wire axil_cms_rready_int; - -wire [6:0] hbm_temp_1; -wire [6:0] hbm_temp_2; - -axil_cdc #( - .DATA_WIDTH(32), - .ADDR_WIDTH(18) -) -cms_axil_cdc_inst ( - .s_clk(axil_cms_clk), - .s_rst(axil_cms_rst), - .s_axil_awaddr(axil_cms_awaddr), - .s_axil_awprot(axil_cms_awprot), - .s_axil_awvalid(axil_cms_awvalid), - .s_axil_awready(axil_cms_awready), - .s_axil_wdata(axil_cms_wdata), - .s_axil_wstrb(axil_cms_wstrb), - .s_axil_wvalid(axil_cms_wvalid), - .s_axil_wready(axil_cms_wready), - .s_axil_bresp(axil_cms_bresp), - .s_axil_bvalid(axil_cms_bvalid), - .s_axil_bready(axil_cms_bready), - .s_axil_araddr(axil_cms_araddr), - .s_axil_arprot(axil_cms_arprot), - .s_axil_arvalid(axil_cms_arvalid), - .s_axil_arready(axil_cms_arready), - .s_axil_rdata(axil_cms_rdata), - .s_axil_rresp(axil_cms_rresp), - .s_axil_rvalid(axil_cms_rvalid), - .s_axil_rready(axil_cms_rready), - .m_clk(clk_50mhz_int), - .m_rst(rst_50mhz_int), - .m_axil_awaddr(axil_cms_awaddr_int), - .m_axil_awprot(axil_cms_awprot_int), - .m_axil_awvalid(axil_cms_awvalid_int), - .m_axil_awready(axil_cms_awready_int), - .m_axil_wdata(axil_cms_wdata_int), - .m_axil_wstrb(axil_cms_wstrb_int), - .m_axil_wvalid(axil_cms_wvalid_int), - .m_axil_wready(axil_cms_wready_int), - .m_axil_bresp(axil_cms_bresp_int), - .m_axil_bvalid(axil_cms_bvalid_int), - .m_axil_bready(axil_cms_bready_int), - .m_axil_araddr(axil_cms_araddr_int), - .m_axil_arprot(axil_cms_arprot_int), - .m_axil_arvalid(axil_cms_arvalid_int), - .m_axil_arready(axil_cms_arready_int), - .m_axil_rdata(axil_cms_rdata_int), - .m_axil_rresp(axil_cms_rresp_int), - .m_axil_rvalid(axil_cms_rvalid_int), - .m_axil_rready(axil_cms_rready_int) -); - -cms_wrapper -cms_inst ( - .aclk_ctrl_0(clk_50mhz_int), - .aresetn_ctrl_0(~rst_50mhz_int), - .hbm_temp_1_0(hbm_temp_1), - .hbm_temp_2_0(hbm_temp_2), - .interrupt_hbm_cattrip_0(hbm_cattrip), - .interrupt_host_0(), - .s_axi_ctrl_0_araddr(axil_cms_araddr_int), - .s_axi_ctrl_0_arprot(axil_cms_arprot_int), - .s_axi_ctrl_0_arready(axil_cms_arready_int), - .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), - .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), - .s_axi_ctrl_0_awprot(axil_cms_awprot_int), - .s_axi_ctrl_0_awready(axil_cms_awready_int), - .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), - .s_axi_ctrl_0_bready(axil_cms_bready_int), - .s_axi_ctrl_0_bresp(axil_cms_bresp_int), - .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), - .s_axi_ctrl_0_rdata(axil_cms_rdata_int), - .s_axi_ctrl_0_rready(axil_cms_rready_int), - .s_axi_ctrl_0_rresp(axil_cms_rresp_int), - .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), - .s_axi_ctrl_0_wdata(axil_cms_wdata_int), - .s_axi_ctrl_0_wready(axil_cms_wready_int), - .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), - .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), - .satellite_gpio_0(msp_gpio), - .satellite_uart_0_rxd(msp_uart_rxd), - .satellite_uart_0_txd(msp_uart_txd) -); - -// PCIe -wire pcie_sys_clk; -wire pcie_sys_clk_gt; - -IBUFDS_GTE4 #( - .REFCLK_HROW_CK_SEL(2'b00) -) -ibufds_gte4_pcie_mgt_refclk_inst ( - .I (pcie_refclk_1_p), - .IB (pcie_refclk_1_n), - .CEB (1'b0), - .O (pcie_sys_clk_gt), - .ODIV2 (pcie_sys_clk) -); - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; -wire axis_rq_tlast; -wire axis_rq_tready; -wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; -wire axis_rq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; -wire axis_rc_tlast; -wire axis_rc_tready; -wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; -wire axis_rc_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; -wire axis_cq_tlast; -wire axis_cq_tready; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; -wire axis_cq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; -wire axis_cc_tlast; -wire axis_cc_tready; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; -wire axis_cc_tvalid; - -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; -wire pcie_rq_seq_num_vld0; -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; -wire pcie_rq_seq_num_vld1; - -wire [3:0] pcie_tfc_nph_av; -wire [3:0] pcie_tfc_npd_av; - -wire [2:0] cfg_max_payload; -wire [2:0] cfg_max_read_req; -wire [3:0] cfg_rcb_status; - -wire [9:0] cfg_mgmt_addr; -wire [7:0] cfg_mgmt_function_number; -wire cfg_mgmt_write; -wire [31:0] cfg_mgmt_write_data; -wire [3:0] cfg_mgmt_byte_enable; -wire cfg_mgmt_read; -wire [31:0] cfg_mgmt_read_data; -wire cfg_mgmt_read_write_done; - -wire [7:0] cfg_fc_ph; -wire [11:0] cfg_fc_pd; -wire [7:0] cfg_fc_nph; -wire [11:0] cfg_fc_npd; -wire [7:0] cfg_fc_cplh; -wire [11:0] cfg_fc_cpld; -wire [2:0] cfg_fc_sel; - -wire [3:0] cfg_interrupt_msix_enable; -wire [3:0] cfg_interrupt_msix_mask; -wire [251:0] cfg_interrupt_msix_vf_enable; -wire [251:0] cfg_interrupt_msix_vf_mask; -wire [63:0] cfg_interrupt_msix_address; -wire [31:0] cfg_interrupt_msix_data; -wire cfg_interrupt_msix_int; -wire [1:0] cfg_interrupt_msix_vec_pending; -wire cfg_interrupt_msix_vec_pending_status; -wire cfg_interrupt_msix_sent; -wire cfg_interrupt_msix_fail; -wire [7:0] cfg_interrupt_msi_function_number; - -wire status_error_cor; -wire status_error_uncor; - -// extra register for pcie_user_reset signal -wire pcie_user_reset_int; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_2 = 1'b1; - -always @(posedge pcie_user_clk) begin - pcie_user_reset_reg_1 <= pcie_user_reset_int; - pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; -end - -BUFG -pcie_user_reset_bufg_inst ( - .I(pcie_user_reset_reg_2), - .O(pcie_user_reset) -); - -pcie4c_uscale_plus_0 -pcie4c_uscale_plus_inst ( - .pci_exp_txn(pcie_tx_n), - .pci_exp_txp(pcie_tx_p), - .pci_exp_rxn(pcie_rx_n), - .pci_exp_rxp(pcie_rx_p), - .user_clk(pcie_user_clk), - .user_reset(pcie_user_reset_int), - .user_lnk_up(), - - .s_axis_rq_tdata(axis_rq_tdata), - .s_axis_rq_tkeep(axis_rq_tkeep), - .s_axis_rq_tlast(axis_rq_tlast), - .s_axis_rq_tready(axis_rq_tready), - .s_axis_rq_tuser(axis_rq_tuser), - .s_axis_rq_tvalid(axis_rq_tvalid), - - .m_axis_rc_tdata(axis_rc_tdata), - .m_axis_rc_tkeep(axis_rc_tkeep), - .m_axis_rc_tlast(axis_rc_tlast), - .m_axis_rc_tready(axis_rc_tready), - .m_axis_rc_tuser(axis_rc_tuser), - .m_axis_rc_tvalid(axis_rc_tvalid), - - .m_axis_cq_tdata(axis_cq_tdata), - .m_axis_cq_tkeep(axis_cq_tkeep), - .m_axis_cq_tlast(axis_cq_tlast), - .m_axis_cq_tready(axis_cq_tready), - .m_axis_cq_tuser(axis_cq_tuser), - .m_axis_cq_tvalid(axis_cq_tvalid), - - .s_axis_cc_tdata(axis_cc_tdata), - .s_axis_cc_tkeep(axis_cc_tkeep), - .s_axis_cc_tlast(axis_cc_tlast), - .s_axis_cc_tready(axis_cc_tready), - .s_axis_cc_tuser(axis_cc_tuser), - .s_axis_cc_tvalid(axis_cc_tvalid), - - .pcie_rq_seq_num0(pcie_rq_seq_num0), - .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), - .pcie_rq_seq_num1(pcie_rq_seq_num1), - .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), - .pcie_rq_tag0(), - .pcie_rq_tag1(), - .pcie_rq_tag_av(), - .pcie_rq_tag_vld0(), - .pcie_rq_tag_vld1(), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .pcie_cq_np_req(1'b1), - .pcie_cq_np_req_count(), - - .cfg_phy_link_down(), - .cfg_phy_link_status(), - .cfg_negotiated_width(), - .cfg_current_speed(), - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_function_status(), - .cfg_function_power_state(), - .cfg_vf_status(), - .cfg_vf_power_state(), - .cfg_link_power_state(), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - .cfg_mgmt_debug_access(1'b0), - - .cfg_err_cor_out(), - .cfg_err_nonfatal_out(), - .cfg_err_fatal_out(), - .cfg_local_error_valid(), - .cfg_local_error_out(), - .cfg_ltssm_state(), - .cfg_rx_pm_state(), - .cfg_tx_pm_state(), - .cfg_rcb_status(cfg_rcb_status), - .cfg_obff_enable(), - .cfg_pl_status_change(), - .cfg_tph_requester_enable(), - .cfg_tph_st_mode(), - .cfg_vf_tph_requester_enable(), - .cfg_vf_tph_st_mode(), - - .cfg_msg_received(), - .cfg_msg_received_data(), - .cfg_msg_received_type(), - .cfg_msg_transmit(1'b0), - .cfg_msg_transmit_type(3'd0), - .cfg_msg_transmit_data(32'd0), - .cfg_msg_transmit_done(), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_dsn(64'd0), - - .cfg_power_state_change_ack(1'b1), - .cfg_power_state_change_interrupt(), - - .cfg_err_cor_in(status_error_cor), - .cfg_err_uncor_in(status_error_uncor), - .cfg_flr_in_process(), - .cfg_flr_done(4'd0), - .cfg_vf_flr_in_process(), - .cfg_vf_flr_func_num(8'd0), - .cfg_vf_flr_done(8'd0), - - .cfg_link_training_enable(1'b1), - - .cfg_interrupt_int(4'd0), - .cfg_interrupt_pending(4'd0), - .cfg_interrupt_sent(), - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .cfg_pm_aspm_l1_entry_reject(1'b0), - .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), - - .cfg_hot_reset_out(), - - .cfg_config_space_enable(1'b1), - .cfg_req_pm_transition_l23_ready(1'b0), - .cfg_hot_reset_in(1'b0), - - .cfg_ds_port_number(8'd0), - .cfg_ds_bus_number(8'd0), - .cfg_ds_device_number(5'd0), - - .sys_clk(pcie_sys_clk), - .sys_clk_gt(pcie_sys_clk_gt), - .sys_reset(pcie_reset_n), - - .phy_rdy_out() -); - -reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0_reg; -reg pcie_rq_seq_num_vld0_reg; -reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1_reg; -reg pcie_rq_seq_num_vld1_reg; - -always @(posedge pcie_user_clk) begin - pcie_rq_seq_num0_reg <= pcie_rq_seq_num0; - pcie_rq_seq_num_vld0_reg <= pcie_rq_seq_num_vld0; - pcie_rq_seq_num1_reg <= pcie_rq_seq_num1; - pcie_rq_seq_num_vld1_reg <= pcie_rq_seq_num_vld1; - - if (pcie_user_reset) begin - pcie_rq_seq_num_vld0_reg <= 1'b0; - pcie_rq_seq_num_vld1_reg <= 1'b0; - end -end - -// CMAC -wire qsfp_tx_clk_int; -wire qsfp_tx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp_tx_axis_tkeep_int; -wire qsfp_tx_axis_tvalid_int; -wire qsfp_tx_axis_tready_int; -wire qsfp_tx_axis_tlast_int; -wire [16+1-1:0] qsfp_tx_axis_tuser_int; - -wire [79:0] qsfp_tx_ptp_time_int; -wire [79:0] qsfp_tx_ptp_ts_int; -wire [15:0] qsfp_tx_ptp_ts_tag_int; -wire qsfp_tx_ptp_ts_valid_int; - -wire qsfp_rx_clk_int; -wire qsfp_rx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp_rx_axis_tkeep_int; -wire qsfp_rx_axis_tvalid_int; -wire qsfp_rx_axis_tlast_int; -wire [80+1-1:0] qsfp_rx_axis_tuser_int; - -wire [79:0] qsfp_rx_ptp_time_int; - -wire qsfp_drp_clk = clk_125mhz_int; -wire qsfp_drp_rst = rst_125mhz_int; -wire [23:0] qsfp_drp_addr; -wire [15:0] qsfp_drp_di; -wire qsfp_drp_en; -wire qsfp_drp_we; -wire [15:0] qsfp_drp_do; -wire qsfp_drp_rdy; - -wire qsfp_tx_enable; -wire qsfp_tx_lfc_en; -wire qsfp_tx_lfc_req; -wire [7:0] qsfp_tx_pfc_en; -wire [7:0] qsfp_tx_pfc_req; - -wire qsfp_rx_enable; -wire qsfp_rx_status; -wire qsfp_rx_lfc_en; -wire qsfp_rx_lfc_req; -wire qsfp_rx_lfc_ack; -wire [7:0] qsfp_rx_pfc_en; -wire [7:0] qsfp_rx_pfc_req; -wire [7:0] qsfp_rx_pfc_ack; - -wire qsfp_gtpowergood; - -wire qsfp_mgt_refclk_0; -wire qsfp_mgt_refclk_0_int; -wire qsfp_mgt_refclk_0_bufg; - -assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst ( - .I (qsfp_mgt_refclk_0_p), - .IB (qsfp_mgt_refclk_0_n), - .CEB (1'b0), - .O (qsfp_mgt_refclk_0), - .ODIV2 (qsfp_mgt_refclk_0_int) -); - -BUFG_GT bufg_gt_qsfp_mgt_refclk_0_inst ( - .CE (qsfp_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp_mgt_refclk_0_int), - .O (qsfp_mgt_refclk_0_bufg) -); - -wire qsfp_rst; - -sync_reset #( - .N(4) -) -qsfp_sync_reset_inst ( - .clk(qsfp_mgt_refclk_0_bufg), - .rst(rst_125mhz_int), - .out(qsfp_rst) -); - -cmac_gty_wrapper #( - .DRP_CLK_FREQ_HZ(125000000), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_SERDES_PIPELINE(0), - .RX_SERDES_PIPELINE(0), - .RS_FEC_ENABLE(1) -) -qsfp_cmac_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp_gtpowergood), - .xcvr_ref_clk(qsfp_mgt_refclk_0), - - /* - * DRP - */ - .drp_clk(qsfp_drp_clk), - .drp_rst(qsfp_drp_rst), - .drp_addr(qsfp_drp_addr), - .drp_di(qsfp_drp_di), - .drp_en(qsfp_drp_en), - .drp_we(qsfp_drp_we), - .drp_do(qsfp_drp_do), - .drp_rdy(qsfp_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp_tx_p), - .xcvr_txn(qsfp_tx_n), - .xcvr_rxp(qsfp_rx_p), - .xcvr_rxn(qsfp_rx_n), - - /* - * CMAC connections - */ - .tx_clk(qsfp_tx_clk_int), - .tx_rst(qsfp_tx_rst_int), - - .tx_axis_tdata(qsfp_tx_axis_tdata_int), - .tx_axis_tkeep(qsfp_tx_axis_tkeep_int), - .tx_axis_tvalid(qsfp_tx_axis_tvalid_int), - .tx_axis_tready(qsfp_tx_axis_tready_int), - .tx_axis_tlast(qsfp_tx_axis_tlast_int), - .tx_axis_tuser(qsfp_tx_axis_tuser_int), - - .tx_ptp_time(qsfp_tx_ptp_time_int), - .tx_ptp_ts(qsfp_tx_ptp_ts_int), - .tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag_int), - .tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid_int), - - .tx_enable(qsfp_tx_enable), - .tx_lfc_en(qsfp_tx_lfc_en), - .tx_lfc_req(qsfp_tx_lfc_req), - .tx_pfc_en(qsfp_tx_pfc_en), - .tx_pfc_req(qsfp_tx_pfc_req), - - .rx_clk(qsfp_rx_clk_int), - .rx_rst(qsfp_rx_rst_int), - - .rx_axis_tdata(qsfp_rx_axis_tdata_int), - .rx_axis_tkeep(qsfp_rx_axis_tkeep_int), - .rx_axis_tvalid(qsfp_rx_axis_tvalid_int), - .rx_axis_tlast(qsfp_rx_axis_tlast_int), - .rx_axis_tuser(qsfp_rx_axis_tuser_int), - - .rx_ptp_time(qsfp_rx_ptp_time_int), - - .rx_enable(qsfp_rx_enable), - .rx_status(qsfp_rx_status), - .rx_lfc_en(qsfp_rx_lfc_en), - .rx_lfc_req(qsfp_rx_lfc_req), - .rx_lfc_ack(qsfp_rx_lfc_ack), - .rx_pfc_en(qsfp_rx_pfc_en), - .rx_pfc_req(qsfp_rx_pfc_req), - .rx_pfc_ack(qsfp_rx_pfc_ack) -); - -wire ptp_clk; -wire ptp_rst; -wire ptp_sample_clk; - -assign ptp_clk = qsfp_mgt_refclk_0_bufg; -assign ptp_rst = qsfp_rst; -assign ptp_sample_clk = clk_125mhz_int; - -assign qsfp_led_stat_g = qsfp_rx_status; - -// HBM -wire [HBM_CH-1:0] hbm_clk; -wire [HBM_CH-1:0] hbm_rst; - -wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid; -wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr; -wire [HBM_CH*8-1:0] m_axi_hbm_awlen; -wire [HBM_CH*3-1:0] m_axi_hbm_awsize; -wire [HBM_CH*2-1:0] m_axi_hbm_awburst; -wire [HBM_CH-1:0] m_axi_hbm_awlock; -wire [HBM_CH*4-1:0] m_axi_hbm_awcache; -wire [HBM_CH*3-1:0] m_axi_hbm_awprot; -wire [HBM_CH*4-1:0] m_axi_hbm_awqos; -wire [HBM_CH-1:0] m_axi_hbm_awvalid; -wire [HBM_CH-1:0] m_axi_hbm_awready; -wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata; -wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb; -wire [HBM_CH-1:0] m_axi_hbm_wlast; -wire [HBM_CH-1:0] m_axi_hbm_wvalid; -wire [HBM_CH-1:0] m_axi_hbm_wready; -wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid; -wire [HBM_CH*2-1:0] m_axi_hbm_bresp; -wire [HBM_CH-1:0] m_axi_hbm_bvalid; -wire [HBM_CH-1:0] m_axi_hbm_bready; -wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid; -wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr; -wire [HBM_CH*8-1:0] m_axi_hbm_arlen; -wire [HBM_CH*3-1:0] m_axi_hbm_arsize; -wire [HBM_CH*2-1:0] m_axi_hbm_arburst; -wire [HBM_CH-1:0] m_axi_hbm_arlock; -wire [HBM_CH*4-1:0] m_axi_hbm_arcache; -wire [HBM_CH*3-1:0] m_axi_hbm_arprot; -wire [HBM_CH*4-1:0] m_axi_hbm_arqos; -wire [HBM_CH-1:0] m_axi_hbm_arvalid; -wire [HBM_CH-1:0] m_axi_hbm_arready; -wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid; -wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata; -wire [HBM_CH*2-1:0] m_axi_hbm_rresp; -wire [HBM_CH-1:0] m_axi_hbm_rlast; -wire [HBM_CH-1:0] m_axi_hbm_rvalid; -wire [HBM_CH-1:0] m_axi_hbm_rready; - -wire [HBM_CH-1:0] hbm_status; - -wire [HBM_CH_INT-1:0] hbm_clk_int; -wire [HBM_CH_INT-1:0] hbm_rst_int; - -wire [HBM_CH_INT*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_int_awid; -wire [HBM_CH_INT*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_int_awaddr; -wire [HBM_CH_INT*8-1:0] m_axi_hbm_int_awlen; -wire [HBM_CH_INT*3-1:0] m_axi_hbm_int_awsize; -wire [HBM_CH_INT*2-1:0] m_axi_hbm_int_awburst; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_awlock; -wire [HBM_CH_INT*4-1:0] m_axi_hbm_int_awcache; -wire [HBM_CH_INT*3-1:0] m_axi_hbm_int_awprot; -wire [HBM_CH_INT*4-1:0] m_axi_hbm_int_awqos; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_awvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_awready; -wire [HBM_CH_INT*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_int_wdata; -wire [HBM_CH_INT*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_int_wstrb; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_wlast; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_wvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_wready; -wire [HBM_CH_INT*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_int_bid; -wire [HBM_CH_INT*2-1:0] m_axi_hbm_int_bresp; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_bvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_bready; -wire [HBM_CH_INT*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_int_arid; -wire [HBM_CH_INT*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_int_araddr; -wire [HBM_CH_INT*8-1:0] m_axi_hbm_int_arlen; -wire [HBM_CH_INT*3-1:0] m_axi_hbm_int_arsize; -wire [HBM_CH_INT*2-1:0] m_axi_hbm_int_arburst; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_arlock; -wire [HBM_CH_INT*4-1:0] m_axi_hbm_int_arcache; -wire [HBM_CH_INT*3-1:0] m_axi_hbm_int_arprot; -wire [HBM_CH_INT*4-1:0] m_axi_hbm_int_arqos; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_arvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_arready; -wire [HBM_CH_INT*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_int_rid; -wire [HBM_CH_INT*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_int_rdata; -wire [HBM_CH_INT*2-1:0] m_axi_hbm_int_rresp; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_rlast; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_rvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_rready; - -wire clk_100mhz_1_ibufg; - -IBUFGDS #( - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") -) -clk_100mhz_1_ibufg_inst ( - .O (clk_100mhz_1_ibufg), - .I (clk_100mhz_1_p), - .IB (clk_100mhz_1_n) -); - -generate - -genvar n; - -if (HBM_ENABLE) begin - -wire hbm_ref_clk; - -wire hbm_mmcm_rst = rst_125mhz_int; -wire hbm_mmcm_locked; -wire hbm_mmcm_clkfb; - -wire hbm_axi_clk_mmcm; -wire hbm_axi_clk; -wire hbm_axi_rst_int; -wire hbm_axi_rst; - -BUFG -hbm_ref_clk_bufg_inst ( - .I(clk_100mhz_1_ibufg), - .O(hbm_ref_clk) -); - -// HBM MMCM instance -// 100 MHz in, 450 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 9, D = 1 sets Fvco = 900 MHz -// Divide by 2 to get output frequency of 450 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(2), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(1), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(9), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(1), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(10.000), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -hbm_mmcm_inst ( - .CLKIN1(clk_100mhz_1_ibufg), - .CLKFBIN(hbm_mmcm_clkfb), - .RST(hbm_mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(hbm_axi_clk_mmcm), - .CLKOUT0B(), - .CLKOUT1(), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(hbm_mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(hbm_mmcm_locked) -); - -BUFG -hbm_axi_clk_bufg_inst ( - .I(hbm_axi_clk_mmcm), - .O(hbm_axi_clk) -); - -sync_reset #( - .N(4) -) -sync_reset_hbm_axi_inst ( - .clk(hbm_axi_clk), - .rst(~hbm_mmcm_locked), - .out(hbm_axi_rst_int) -); - -// extra register for hbm_axi_rst signal -(* shreg_extract = "no" *) -reg hbm_axi_rst_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg hbm_axi_rst_reg_2 = 1'b1; - -always @(posedge hbm_axi_clk) begin - hbm_axi_rst_reg_1 <= hbm_axi_rst_int; - hbm_axi_rst_reg_2 <= hbm_axi_rst_reg_1; -end - -BUFG -hbm_axi_rst_bufg_inst ( - .I(hbm_axi_rst_reg_2), - .O(hbm_axi_rst) -); - -wire hbm_cattrip_1; -wire hbm_cattrip_2; - -assign hbm_cattrip = hbm_cattrip_1 | hbm_cattrip_2; - -assign hbm_clk_int = {HBM_CH_INT{hbm_axi_clk}}; -assign hbm_rst_int = {HBM_CH_INT{hbm_axi_rst}}; - -hbm_0 hbm_inst ( - .HBM_REF_CLK_0(hbm_ref_clk), - .HBM_REF_CLK_1(hbm_ref_clk), - - .APB_0_PWDATA(32'd0), - .APB_0_PADDR(22'd0), - .APB_0_PCLK(hbm_ref_clk), - .APB_0_PENABLE(1'b0), - .APB_0_PRESET_N(1'b1), - .APB_0_PSEL(1'b0), - .APB_0_PWRITE(1'b0), - .APB_0_PRDATA(), - .APB_0_PREADY(), - .APB_0_PSLVERR(), - .apb_complete_0(), - - .APB_1_PWDATA(32'd0), - .APB_1_PADDR(22'd0), - .APB_1_PCLK(hbm_ref_clk), - .APB_1_PENABLE(1'b0), - .APB_1_PRESET_N(1'b1), - .APB_1_PSEL(1'b0), - .APB_1_PWRITE(1'b0), - .APB_1_PRDATA(), - .APB_1_PREADY(), - .APB_1_PSLVERR(), - .apb_complete_1(), - - .AXI_00_ACLK(hbm_clk_int[0 +: 1]), - .AXI_00_ARESET_N(!hbm_rst_int[0 +: 1]), - - .AXI_00_ARADDR(m_axi_hbm_int_araddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_00_ARBURST(m_axi_hbm_int_arburst[0*2 +: 2]), - .AXI_00_ARID(m_axi_hbm_int_arid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_00_ARLEN(m_axi_hbm_int_arlen[0*8 +: 4]), - .AXI_00_ARSIZE(m_axi_hbm_int_arsize[0*3 +: 3]), - .AXI_00_ARVALID(m_axi_hbm_int_arvalid[0 +: 1]), - .AXI_00_ARREADY(m_axi_hbm_int_arready[0 +: 1]), - .AXI_00_RDATA_PARITY(), - .AXI_00_RDATA(m_axi_hbm_int_rdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_00_RID(m_axi_hbm_int_rid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_00_RLAST(m_axi_hbm_int_rlast[0 +: 1]), - .AXI_00_RRESP(m_axi_hbm_int_rresp[0*2 +: 2]), - .AXI_00_RVALID(m_axi_hbm_int_rvalid[0 +: 1]), - .AXI_00_RREADY(m_axi_hbm_int_rready[0 +: 1]), - .AXI_00_AWADDR(m_axi_hbm_int_awaddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_00_AWBURST(m_axi_hbm_int_awburst[0*2 +: 2]), - .AXI_00_AWID(m_axi_hbm_int_awid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_00_AWLEN(m_axi_hbm_int_awlen[0*8 +: 4]), - .AXI_00_AWSIZE(m_axi_hbm_int_awsize[0*3 +: 3]), - .AXI_00_AWVALID(m_axi_hbm_int_awvalid[0 +: 1]), - .AXI_00_AWREADY(m_axi_hbm_int_awready[0 +: 1]), - .AXI_00_WDATA(m_axi_hbm_int_wdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_00_WLAST(m_axi_hbm_int_wlast[0 +: 1]), - .AXI_00_WSTRB(m_axi_hbm_int_wstrb[0*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_00_WDATA_PARITY(32'd0), - .AXI_00_WVALID(m_axi_hbm_int_wvalid[0 +: 1]), - .AXI_00_WREADY(m_axi_hbm_int_wready[0 +: 1]), - .AXI_00_BID(m_axi_hbm_int_bid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_00_BRESP(m_axi_hbm_int_bresp[0*2 +: 2]), - .AXI_00_BVALID(m_axi_hbm_int_bvalid[0 +: 1]), - .AXI_00_BREADY(m_axi_hbm_int_bready[0 +: 1]), - - .AXI_01_ACLK(hbm_clk_int[1 +: 1]), - .AXI_01_ARESET_N(!hbm_rst_int[1 +: 1]), - - .AXI_01_ARADDR(m_axi_hbm_int_araddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_01_ARBURST(m_axi_hbm_int_arburst[1*2 +: 2]), - .AXI_01_ARID(m_axi_hbm_int_arid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_01_ARLEN(m_axi_hbm_int_arlen[1*8 +: 4]), - .AXI_01_ARSIZE(m_axi_hbm_int_arsize[1*3 +: 3]), - .AXI_01_ARVALID(m_axi_hbm_int_arvalid[1 +: 1]), - .AXI_01_ARREADY(m_axi_hbm_int_arready[1 +: 1]), - .AXI_01_RDATA_PARITY(), - .AXI_01_RDATA(m_axi_hbm_int_rdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_01_RID(m_axi_hbm_int_rid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_01_RLAST(m_axi_hbm_int_rlast[1 +: 1]), - .AXI_01_RRESP(m_axi_hbm_int_rresp[1*2 +: 2]), - .AXI_01_RVALID(m_axi_hbm_int_rvalid[1 +: 1]), - .AXI_01_RREADY(m_axi_hbm_int_rready[1 +: 1]), - .AXI_01_AWADDR(m_axi_hbm_int_awaddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_01_AWBURST(m_axi_hbm_int_awburst[1*2 +: 2]), - .AXI_01_AWID(m_axi_hbm_int_awid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_01_AWLEN(m_axi_hbm_int_awlen[1*8 +: 4]), - .AXI_01_AWSIZE(m_axi_hbm_int_awsize[1*3 +: 3]), - .AXI_01_AWVALID(m_axi_hbm_int_awvalid[1 +: 1]), - .AXI_01_AWREADY(m_axi_hbm_int_awready[1 +: 1]), - .AXI_01_WDATA(m_axi_hbm_int_wdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_01_WLAST(m_axi_hbm_int_wlast[1 +: 1]), - .AXI_01_WSTRB(m_axi_hbm_int_wstrb[1*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_01_WDATA_PARITY(32'd0), - .AXI_01_WVALID(m_axi_hbm_int_wvalid[1 +: 1]), - .AXI_01_WREADY(m_axi_hbm_int_wready[1 +: 1]), - .AXI_01_BID(m_axi_hbm_int_bid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_01_BRESP(m_axi_hbm_int_bresp[1*2 +: 2]), - .AXI_01_BVALID(m_axi_hbm_int_bvalid[1 +: 1]), - .AXI_01_BREADY(m_axi_hbm_int_bready[1 +: 1]), - - .AXI_02_ACLK(hbm_clk_int[2 +: 1]), - .AXI_02_ARESET_N(!hbm_rst_int[2 +: 1]), - - .AXI_02_ARADDR(m_axi_hbm_int_araddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_02_ARBURST(m_axi_hbm_int_arburst[2*2 +: 2]), - .AXI_02_ARID(m_axi_hbm_int_arid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_02_ARLEN(m_axi_hbm_int_arlen[2*8 +: 4]), - .AXI_02_ARSIZE(m_axi_hbm_int_arsize[2*3 +: 3]), - .AXI_02_ARVALID(m_axi_hbm_int_arvalid[2 +: 1]), - .AXI_02_ARREADY(m_axi_hbm_int_arready[2 +: 1]), - .AXI_02_RDATA_PARITY(), - .AXI_02_RDATA(m_axi_hbm_int_rdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_02_RID(m_axi_hbm_int_rid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_02_RLAST(m_axi_hbm_int_rlast[2 +: 1]), - .AXI_02_RRESP(m_axi_hbm_int_rresp[2*2 +: 2]), - .AXI_02_RVALID(m_axi_hbm_int_rvalid[2 +: 1]), - .AXI_02_RREADY(m_axi_hbm_int_rready[2 +: 1]), - .AXI_02_AWADDR(m_axi_hbm_int_awaddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_02_AWBURST(m_axi_hbm_int_awburst[2*2 +: 2]), - .AXI_02_AWID(m_axi_hbm_int_awid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_02_AWLEN(m_axi_hbm_int_awlen[2*8 +: 4]), - .AXI_02_AWSIZE(m_axi_hbm_int_awsize[2*3 +: 3]), - .AXI_02_AWVALID(m_axi_hbm_int_awvalid[2 +: 1]), - .AXI_02_AWREADY(m_axi_hbm_int_awready[2 +: 1]), - .AXI_02_WDATA(m_axi_hbm_int_wdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_02_WLAST(m_axi_hbm_int_wlast[2 +: 1]), - .AXI_02_WSTRB(m_axi_hbm_int_wstrb[2*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_02_WDATA_PARITY(32'd0), - .AXI_02_WVALID(m_axi_hbm_int_wvalid[2 +: 1]), - .AXI_02_WREADY(m_axi_hbm_int_wready[2 +: 1]), - .AXI_02_BID(m_axi_hbm_int_bid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_02_BRESP(m_axi_hbm_int_bresp[2*2 +: 2]), - .AXI_02_BVALID(m_axi_hbm_int_bvalid[2 +: 1]), - .AXI_02_BREADY(m_axi_hbm_int_bready[2 +: 1]), - - .AXI_03_ACLK(hbm_clk_int[3 +: 1]), - .AXI_03_ARESET_N(!hbm_rst_int[3 +: 1]), - - .AXI_03_ARADDR(m_axi_hbm_int_araddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_03_ARBURST(m_axi_hbm_int_arburst[3*2 +: 2]), - .AXI_03_ARID(m_axi_hbm_int_arid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_03_ARLEN(m_axi_hbm_int_arlen[3*8 +: 4]), - .AXI_03_ARSIZE(m_axi_hbm_int_arsize[3*3 +: 3]), - .AXI_03_ARVALID(m_axi_hbm_int_arvalid[3 +: 1]), - .AXI_03_ARREADY(m_axi_hbm_int_arready[3 +: 1]), - .AXI_03_RDATA_PARITY(), - .AXI_03_RDATA(m_axi_hbm_int_rdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_03_RID(m_axi_hbm_int_rid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_03_RLAST(m_axi_hbm_int_rlast[3 +: 1]), - .AXI_03_RRESP(m_axi_hbm_int_rresp[3*2 +: 2]), - .AXI_03_RVALID(m_axi_hbm_int_rvalid[3 +: 1]), - .AXI_03_RREADY(m_axi_hbm_int_rready[3 +: 1]), - .AXI_03_AWADDR(m_axi_hbm_int_awaddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_03_AWBURST(m_axi_hbm_int_awburst[3*2 +: 2]), - .AXI_03_AWID(m_axi_hbm_int_awid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_03_AWLEN(m_axi_hbm_int_awlen[3*8 +: 4]), - .AXI_03_AWSIZE(m_axi_hbm_int_awsize[3*3 +: 3]), - .AXI_03_AWVALID(m_axi_hbm_int_awvalid[3 +: 1]), - .AXI_03_AWREADY(m_axi_hbm_int_awready[3 +: 1]), - .AXI_03_WDATA(m_axi_hbm_int_wdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_03_WLAST(m_axi_hbm_int_wlast[3 +: 1]), - .AXI_03_WSTRB(m_axi_hbm_int_wstrb[3*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_03_WDATA_PARITY(32'd0), - .AXI_03_WVALID(m_axi_hbm_int_wvalid[3 +: 1]), - .AXI_03_WREADY(m_axi_hbm_int_wready[3 +: 1]), - .AXI_03_BID(m_axi_hbm_int_bid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_03_BRESP(m_axi_hbm_int_bresp[3*2 +: 2]), - .AXI_03_BVALID(m_axi_hbm_int_bvalid[3 +: 1]), - .AXI_03_BREADY(m_axi_hbm_int_bready[3 +: 1]), - - .AXI_04_ACLK(hbm_clk_int[4 +: 1]), - .AXI_04_ARESET_N(!hbm_rst_int[4 +: 1]), - - .AXI_04_ARADDR(m_axi_hbm_int_araddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_04_ARBURST(m_axi_hbm_int_arburst[4*2 +: 2]), - .AXI_04_ARID(m_axi_hbm_int_arid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_04_ARLEN(m_axi_hbm_int_arlen[4*8 +: 4]), - .AXI_04_ARSIZE(m_axi_hbm_int_arsize[4*3 +: 3]), - .AXI_04_ARVALID(m_axi_hbm_int_arvalid[4 +: 1]), - .AXI_04_ARREADY(m_axi_hbm_int_arready[4 +: 1]), - .AXI_04_RDATA_PARITY(), - .AXI_04_RDATA(m_axi_hbm_int_rdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_04_RID(m_axi_hbm_int_rid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_04_RLAST(m_axi_hbm_int_rlast[4 +: 1]), - .AXI_04_RRESP(m_axi_hbm_int_rresp[4*2 +: 2]), - .AXI_04_RVALID(m_axi_hbm_int_rvalid[4 +: 1]), - .AXI_04_RREADY(m_axi_hbm_int_rready[4 +: 1]), - .AXI_04_AWADDR(m_axi_hbm_int_awaddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_04_AWBURST(m_axi_hbm_int_awburst[4*2 +: 2]), - .AXI_04_AWID(m_axi_hbm_int_awid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_04_AWLEN(m_axi_hbm_int_awlen[4*8 +: 4]), - .AXI_04_AWSIZE(m_axi_hbm_int_awsize[4*3 +: 3]), - .AXI_04_AWVALID(m_axi_hbm_int_awvalid[4 +: 1]), - .AXI_04_AWREADY(m_axi_hbm_int_awready[4 +: 1]), - .AXI_04_WDATA(m_axi_hbm_int_wdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_04_WLAST(m_axi_hbm_int_wlast[4 +: 1]), - .AXI_04_WSTRB(m_axi_hbm_int_wstrb[4*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_04_WDATA_PARITY(32'd0), - .AXI_04_WVALID(m_axi_hbm_int_wvalid[4 +: 1]), - .AXI_04_WREADY(m_axi_hbm_int_wready[4 +: 1]), - .AXI_04_BID(m_axi_hbm_int_bid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_04_BRESP(m_axi_hbm_int_bresp[4*2 +: 2]), - .AXI_04_BVALID(m_axi_hbm_int_bvalid[4 +: 1]), - .AXI_04_BREADY(m_axi_hbm_int_bready[4 +: 1]), - - .AXI_05_ACLK(hbm_clk_int[5 +: 1]), - .AXI_05_ARESET_N(!hbm_rst_int[5 +: 1]), - - .AXI_05_ARADDR(m_axi_hbm_int_araddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_05_ARBURST(m_axi_hbm_int_arburst[5*2 +: 2]), - .AXI_05_ARID(m_axi_hbm_int_arid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_05_ARLEN(m_axi_hbm_int_arlen[5*8 +: 4]), - .AXI_05_ARSIZE(m_axi_hbm_int_arsize[5*3 +: 3]), - .AXI_05_ARVALID(m_axi_hbm_int_arvalid[5 +: 1]), - .AXI_05_ARREADY(m_axi_hbm_int_arready[5 +: 1]), - .AXI_05_RDATA_PARITY(), - .AXI_05_RDATA(m_axi_hbm_int_rdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_05_RID(m_axi_hbm_int_rid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_05_RLAST(m_axi_hbm_int_rlast[5 +: 1]), - .AXI_05_RRESP(m_axi_hbm_int_rresp[5*2 +: 2]), - .AXI_05_RVALID(m_axi_hbm_int_rvalid[5 +: 1]), - .AXI_05_RREADY(m_axi_hbm_int_rready[5 +: 1]), - .AXI_05_AWADDR(m_axi_hbm_int_awaddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_05_AWBURST(m_axi_hbm_int_awburst[5*2 +: 2]), - .AXI_05_AWID(m_axi_hbm_int_awid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_05_AWLEN(m_axi_hbm_int_awlen[5*8 +: 4]), - .AXI_05_AWSIZE(m_axi_hbm_int_awsize[5*3 +: 3]), - .AXI_05_AWVALID(m_axi_hbm_int_awvalid[5 +: 1]), - .AXI_05_AWREADY(m_axi_hbm_int_awready[5 +: 1]), - .AXI_05_WDATA(m_axi_hbm_int_wdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_05_WLAST(m_axi_hbm_int_wlast[5 +: 1]), - .AXI_05_WSTRB(m_axi_hbm_int_wstrb[5*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_05_WDATA_PARITY(32'd0), - .AXI_05_WVALID(m_axi_hbm_int_wvalid[5 +: 1]), - .AXI_05_WREADY(m_axi_hbm_int_wready[5 +: 1]), - .AXI_05_BID(m_axi_hbm_int_bid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_05_BRESP(m_axi_hbm_int_bresp[5*2 +: 2]), - .AXI_05_BVALID(m_axi_hbm_int_bvalid[5 +: 1]), - .AXI_05_BREADY(m_axi_hbm_int_bready[5 +: 1]), - - .AXI_06_ACLK(hbm_clk_int[6 +: 1]), - .AXI_06_ARESET_N(!hbm_rst_int[6 +: 1]), - - .AXI_06_ARADDR(m_axi_hbm_int_araddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_06_ARBURST(m_axi_hbm_int_arburst[6*2 +: 2]), - .AXI_06_ARID(m_axi_hbm_int_arid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_06_ARLEN(m_axi_hbm_int_arlen[6*8 +: 4]), - .AXI_06_ARSIZE(m_axi_hbm_int_arsize[6*3 +: 3]), - .AXI_06_ARVALID(m_axi_hbm_int_arvalid[6 +: 1]), - .AXI_06_ARREADY(m_axi_hbm_int_arready[6 +: 1]), - .AXI_06_RDATA_PARITY(), - .AXI_06_RDATA(m_axi_hbm_int_rdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_06_RID(m_axi_hbm_int_rid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_06_RLAST(m_axi_hbm_int_rlast[6 +: 1]), - .AXI_06_RRESP(m_axi_hbm_int_rresp[6*2 +: 2]), - .AXI_06_RVALID(m_axi_hbm_int_rvalid[6 +: 1]), - .AXI_06_RREADY(m_axi_hbm_int_rready[6 +: 1]), - .AXI_06_AWADDR(m_axi_hbm_int_awaddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_06_AWBURST(m_axi_hbm_int_awburst[6*2 +: 2]), - .AXI_06_AWID(m_axi_hbm_int_awid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_06_AWLEN(m_axi_hbm_int_awlen[6*8 +: 4]), - .AXI_06_AWSIZE(m_axi_hbm_int_awsize[6*3 +: 3]), - .AXI_06_AWVALID(m_axi_hbm_int_awvalid[6 +: 1]), - .AXI_06_AWREADY(m_axi_hbm_int_awready[6 +: 1]), - .AXI_06_WDATA(m_axi_hbm_int_wdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_06_WLAST(m_axi_hbm_int_wlast[6 +: 1]), - .AXI_06_WSTRB(m_axi_hbm_int_wstrb[6*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_06_WDATA_PARITY(32'd0), - .AXI_06_WVALID(m_axi_hbm_int_wvalid[6 +: 1]), - .AXI_06_WREADY(m_axi_hbm_int_wready[6 +: 1]), - .AXI_06_BID(m_axi_hbm_int_bid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_06_BRESP(m_axi_hbm_int_bresp[6*2 +: 2]), - .AXI_06_BVALID(m_axi_hbm_int_bvalid[6 +: 1]), - .AXI_06_BREADY(m_axi_hbm_int_bready[6 +: 1]), - - .AXI_07_ACLK(hbm_clk_int[7 +: 1]), - .AXI_07_ARESET_N(!hbm_rst_int[7 +: 1]), - - .AXI_07_ARADDR(m_axi_hbm_int_araddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_07_ARBURST(m_axi_hbm_int_arburst[7*2 +: 2]), - .AXI_07_ARID(m_axi_hbm_int_arid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_07_ARLEN(m_axi_hbm_int_arlen[7*8 +: 4]), - .AXI_07_ARSIZE(m_axi_hbm_int_arsize[7*3 +: 3]), - .AXI_07_ARVALID(m_axi_hbm_int_arvalid[7 +: 1]), - .AXI_07_ARREADY(m_axi_hbm_int_arready[7 +: 1]), - .AXI_07_RDATA_PARITY(), - .AXI_07_RDATA(m_axi_hbm_int_rdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_07_RID(m_axi_hbm_int_rid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_07_RLAST(m_axi_hbm_int_rlast[7 +: 1]), - .AXI_07_RRESP(m_axi_hbm_int_rresp[7*2 +: 2]), - .AXI_07_RVALID(m_axi_hbm_int_rvalid[7 +: 1]), - .AXI_07_RREADY(m_axi_hbm_int_rready[7 +: 1]), - .AXI_07_AWADDR(m_axi_hbm_int_awaddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_07_AWBURST(m_axi_hbm_int_awburst[7*2 +: 2]), - .AXI_07_AWID(m_axi_hbm_int_awid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_07_AWLEN(m_axi_hbm_int_awlen[7*8 +: 4]), - .AXI_07_AWSIZE(m_axi_hbm_int_awsize[7*3 +: 3]), - .AXI_07_AWVALID(m_axi_hbm_int_awvalid[7 +: 1]), - .AXI_07_AWREADY(m_axi_hbm_int_awready[7 +: 1]), - .AXI_07_WDATA(m_axi_hbm_int_wdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_07_WLAST(m_axi_hbm_int_wlast[7 +: 1]), - .AXI_07_WSTRB(m_axi_hbm_int_wstrb[7*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_07_WDATA_PARITY(32'd0), - .AXI_07_WVALID(m_axi_hbm_int_wvalid[7 +: 1]), - .AXI_07_WREADY(m_axi_hbm_int_wready[7 +: 1]), - .AXI_07_BID(m_axi_hbm_int_bid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_07_BRESP(m_axi_hbm_int_bresp[7*2 +: 2]), - .AXI_07_BVALID(m_axi_hbm_int_bvalid[7 +: 1]), - .AXI_07_BREADY(m_axi_hbm_int_bready[7 +: 1]), - - .AXI_08_ACLK(hbm_clk_int[8 +: 1]), - .AXI_08_ARESET_N(!hbm_rst_int[8 +: 1]), - - .AXI_08_ARADDR(m_axi_hbm_int_araddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_08_ARBURST(m_axi_hbm_int_arburst[8*2 +: 2]), - .AXI_08_ARID(m_axi_hbm_int_arid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_08_ARLEN(m_axi_hbm_int_arlen[8*8 +: 4]), - .AXI_08_ARSIZE(m_axi_hbm_int_arsize[8*3 +: 3]), - .AXI_08_ARVALID(m_axi_hbm_int_arvalid[8 +: 1]), - .AXI_08_ARREADY(m_axi_hbm_int_arready[8 +: 1]), - .AXI_08_RDATA_PARITY(), - .AXI_08_RDATA(m_axi_hbm_int_rdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_08_RID(m_axi_hbm_int_rid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_08_RLAST(m_axi_hbm_int_rlast[8 +: 1]), - .AXI_08_RRESP(m_axi_hbm_int_rresp[8*2 +: 2]), - .AXI_08_RVALID(m_axi_hbm_int_rvalid[8 +: 1]), - .AXI_08_RREADY(m_axi_hbm_int_rready[8 +: 1]), - .AXI_08_AWADDR(m_axi_hbm_int_awaddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_08_AWBURST(m_axi_hbm_int_awburst[8*2 +: 2]), - .AXI_08_AWID(m_axi_hbm_int_awid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_08_AWLEN(m_axi_hbm_int_awlen[8*8 +: 4]), - .AXI_08_AWSIZE(m_axi_hbm_int_awsize[8*3 +: 3]), - .AXI_08_AWVALID(m_axi_hbm_int_awvalid[8 +: 1]), - .AXI_08_AWREADY(m_axi_hbm_int_awready[8 +: 1]), - .AXI_08_WDATA(m_axi_hbm_int_wdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_08_WLAST(m_axi_hbm_int_wlast[8 +: 1]), - .AXI_08_WSTRB(m_axi_hbm_int_wstrb[8*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_08_WDATA_PARITY(32'd0), - .AXI_08_WVALID(m_axi_hbm_int_wvalid[8 +: 1]), - .AXI_08_WREADY(m_axi_hbm_int_wready[8 +: 1]), - .AXI_08_BID(m_axi_hbm_int_bid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_08_BRESP(m_axi_hbm_int_bresp[8*2 +: 2]), - .AXI_08_BVALID(m_axi_hbm_int_bvalid[8 +: 1]), - .AXI_08_BREADY(m_axi_hbm_int_bready[8 +: 1]), - - .AXI_09_ACLK(hbm_clk_int[9 +: 1]), - .AXI_09_ARESET_N(!hbm_rst_int[9 +: 1]), - - .AXI_09_ARADDR(m_axi_hbm_int_araddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_09_ARBURST(m_axi_hbm_int_arburst[9*2 +: 2]), - .AXI_09_ARID(m_axi_hbm_int_arid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_09_ARLEN(m_axi_hbm_int_arlen[9*8 +: 4]), - .AXI_09_ARSIZE(m_axi_hbm_int_arsize[9*3 +: 3]), - .AXI_09_ARVALID(m_axi_hbm_int_arvalid[9 +: 1]), - .AXI_09_ARREADY(m_axi_hbm_int_arready[9 +: 1]), - .AXI_09_RDATA_PARITY(), - .AXI_09_RDATA(m_axi_hbm_int_rdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_09_RID(m_axi_hbm_int_rid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_09_RLAST(m_axi_hbm_int_rlast[9 +: 1]), - .AXI_09_RRESP(m_axi_hbm_int_rresp[9*2 +: 2]), - .AXI_09_RVALID(m_axi_hbm_int_rvalid[9 +: 1]), - .AXI_09_RREADY(m_axi_hbm_int_rready[9 +: 1]), - .AXI_09_AWADDR(m_axi_hbm_int_awaddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_09_AWBURST(m_axi_hbm_int_awburst[9*2 +: 2]), - .AXI_09_AWID(m_axi_hbm_int_awid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_09_AWLEN(m_axi_hbm_int_awlen[9*8 +: 4]), - .AXI_09_AWSIZE(m_axi_hbm_int_awsize[9*3 +: 3]), - .AXI_09_AWVALID(m_axi_hbm_int_awvalid[9 +: 1]), - .AXI_09_AWREADY(m_axi_hbm_int_awready[9 +: 1]), - .AXI_09_WDATA(m_axi_hbm_int_wdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_09_WLAST(m_axi_hbm_int_wlast[9 +: 1]), - .AXI_09_WSTRB(m_axi_hbm_int_wstrb[9*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_09_WDATA_PARITY(32'd0), - .AXI_09_WVALID(m_axi_hbm_int_wvalid[9 +: 1]), - .AXI_09_WREADY(m_axi_hbm_int_wready[9 +: 1]), - .AXI_09_BID(m_axi_hbm_int_bid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_09_BRESP(m_axi_hbm_int_bresp[9*2 +: 2]), - .AXI_09_BVALID(m_axi_hbm_int_bvalid[9 +: 1]), - .AXI_09_BREADY(m_axi_hbm_int_bready[9 +: 1]), - - .AXI_10_ACLK(hbm_clk_int[10 +: 1]), - .AXI_10_ARESET_N(!hbm_rst_int[10 +: 1]), - - .AXI_10_ARADDR(m_axi_hbm_int_araddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_10_ARBURST(m_axi_hbm_int_arburst[10*2 +: 2]), - .AXI_10_ARID(m_axi_hbm_int_arid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_10_ARLEN(m_axi_hbm_int_arlen[10*8 +: 4]), - .AXI_10_ARSIZE(m_axi_hbm_int_arsize[10*3 +: 3]), - .AXI_10_ARVALID(m_axi_hbm_int_arvalid[10 +: 1]), - .AXI_10_ARREADY(m_axi_hbm_int_arready[10 +: 1]), - .AXI_10_RDATA_PARITY(), - .AXI_10_RDATA(m_axi_hbm_int_rdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_10_RID(m_axi_hbm_int_rid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_10_RLAST(m_axi_hbm_int_rlast[10 +: 1]), - .AXI_10_RRESP(m_axi_hbm_int_rresp[10*2 +: 2]), - .AXI_10_RVALID(m_axi_hbm_int_rvalid[10 +: 1]), - .AXI_10_RREADY(m_axi_hbm_int_rready[10 +: 1]), - .AXI_10_AWADDR(m_axi_hbm_int_awaddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_10_AWBURST(m_axi_hbm_int_awburst[10*2 +: 2]), - .AXI_10_AWID(m_axi_hbm_int_awid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_10_AWLEN(m_axi_hbm_int_awlen[10*8 +: 4]), - .AXI_10_AWSIZE(m_axi_hbm_int_awsize[10*3 +: 3]), - .AXI_10_AWVALID(m_axi_hbm_int_awvalid[10 +: 1]), - .AXI_10_AWREADY(m_axi_hbm_int_awready[10 +: 1]), - .AXI_10_WDATA(m_axi_hbm_int_wdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_10_WLAST(m_axi_hbm_int_wlast[10 +: 1]), - .AXI_10_WSTRB(m_axi_hbm_int_wstrb[10*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_10_WDATA_PARITY(32'd0), - .AXI_10_WVALID(m_axi_hbm_int_wvalid[10 +: 1]), - .AXI_10_WREADY(m_axi_hbm_int_wready[10 +: 1]), - .AXI_10_BID(m_axi_hbm_int_bid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_10_BRESP(m_axi_hbm_int_bresp[10*2 +: 2]), - .AXI_10_BVALID(m_axi_hbm_int_bvalid[10 +: 1]), - .AXI_10_BREADY(m_axi_hbm_int_bready[10 +: 1]), - - .AXI_11_ACLK(hbm_clk_int[11 +: 1]), - .AXI_11_ARESET_N(!hbm_rst_int[11 +: 1]), - - .AXI_11_ARADDR(m_axi_hbm_int_araddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_11_ARBURST(m_axi_hbm_int_arburst[11*2 +: 2]), - .AXI_11_ARID(m_axi_hbm_int_arid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_11_ARLEN(m_axi_hbm_int_arlen[11*8 +: 4]), - .AXI_11_ARSIZE(m_axi_hbm_int_arsize[11*3 +: 3]), - .AXI_11_ARVALID(m_axi_hbm_int_arvalid[11 +: 1]), - .AXI_11_ARREADY(m_axi_hbm_int_arready[11 +: 1]), - .AXI_11_RDATA_PARITY(), - .AXI_11_RDATA(m_axi_hbm_int_rdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_11_RID(m_axi_hbm_int_rid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_11_RLAST(m_axi_hbm_int_rlast[11 +: 1]), - .AXI_11_RRESP(m_axi_hbm_int_rresp[11*2 +: 2]), - .AXI_11_RVALID(m_axi_hbm_int_rvalid[11 +: 1]), - .AXI_11_RREADY(m_axi_hbm_int_rready[11 +: 1]), - .AXI_11_AWADDR(m_axi_hbm_int_awaddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_11_AWBURST(m_axi_hbm_int_awburst[11*2 +: 2]), - .AXI_11_AWID(m_axi_hbm_int_awid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_11_AWLEN(m_axi_hbm_int_awlen[11*8 +: 4]), - .AXI_11_AWSIZE(m_axi_hbm_int_awsize[11*3 +: 3]), - .AXI_11_AWVALID(m_axi_hbm_int_awvalid[11 +: 1]), - .AXI_11_AWREADY(m_axi_hbm_int_awready[11 +: 1]), - .AXI_11_WDATA(m_axi_hbm_int_wdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_11_WLAST(m_axi_hbm_int_wlast[11 +: 1]), - .AXI_11_WSTRB(m_axi_hbm_int_wstrb[11*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_11_WDATA_PARITY(32'd0), - .AXI_11_WVALID(m_axi_hbm_int_wvalid[11 +: 1]), - .AXI_11_WREADY(m_axi_hbm_int_wready[11 +: 1]), - .AXI_11_BID(m_axi_hbm_int_bid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_11_BRESP(m_axi_hbm_int_bresp[11*2 +: 2]), - .AXI_11_BVALID(m_axi_hbm_int_bvalid[11 +: 1]), - .AXI_11_BREADY(m_axi_hbm_int_bready[11 +: 1]), - - .AXI_12_ACLK(hbm_clk_int[12 +: 1]), - .AXI_12_ARESET_N(!hbm_rst_int[12 +: 1]), - - .AXI_12_ARADDR(m_axi_hbm_int_araddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_12_ARBURST(m_axi_hbm_int_arburst[12*2 +: 2]), - .AXI_12_ARID(m_axi_hbm_int_arid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_12_ARLEN(m_axi_hbm_int_arlen[12*8 +: 4]), - .AXI_12_ARSIZE(m_axi_hbm_int_arsize[12*3 +: 3]), - .AXI_12_ARVALID(m_axi_hbm_int_arvalid[12 +: 1]), - .AXI_12_ARREADY(m_axi_hbm_int_arready[12 +: 1]), - .AXI_12_RDATA_PARITY(), - .AXI_12_RDATA(m_axi_hbm_int_rdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_12_RID(m_axi_hbm_int_rid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_12_RLAST(m_axi_hbm_int_rlast[12 +: 1]), - .AXI_12_RRESP(m_axi_hbm_int_rresp[12*2 +: 2]), - .AXI_12_RVALID(m_axi_hbm_int_rvalid[12 +: 1]), - .AXI_12_RREADY(m_axi_hbm_int_rready[12 +: 1]), - .AXI_12_AWADDR(m_axi_hbm_int_awaddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_12_AWBURST(m_axi_hbm_int_awburst[12*2 +: 2]), - .AXI_12_AWID(m_axi_hbm_int_awid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_12_AWLEN(m_axi_hbm_int_awlen[12*8 +: 4]), - .AXI_12_AWSIZE(m_axi_hbm_int_awsize[12*3 +: 3]), - .AXI_12_AWVALID(m_axi_hbm_int_awvalid[12 +: 1]), - .AXI_12_AWREADY(m_axi_hbm_int_awready[12 +: 1]), - .AXI_12_WDATA(m_axi_hbm_int_wdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_12_WLAST(m_axi_hbm_int_wlast[12 +: 1]), - .AXI_12_WSTRB(m_axi_hbm_int_wstrb[12*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_12_WDATA_PARITY(32'd0), - .AXI_12_WVALID(m_axi_hbm_int_wvalid[12 +: 1]), - .AXI_12_WREADY(m_axi_hbm_int_wready[12 +: 1]), - .AXI_12_BID(m_axi_hbm_int_bid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_12_BRESP(m_axi_hbm_int_bresp[12*2 +: 2]), - .AXI_12_BVALID(m_axi_hbm_int_bvalid[12 +: 1]), - .AXI_12_BREADY(m_axi_hbm_int_bready[12 +: 1]), - - .AXI_13_ACLK(hbm_clk_int[13 +: 1]), - .AXI_13_ARESET_N(!hbm_rst_int[13 +: 1]), - - .AXI_13_ARADDR(m_axi_hbm_int_araddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_13_ARBURST(m_axi_hbm_int_arburst[13*2 +: 2]), - .AXI_13_ARID(m_axi_hbm_int_arid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_13_ARLEN(m_axi_hbm_int_arlen[13*8 +: 4]), - .AXI_13_ARSIZE(m_axi_hbm_int_arsize[13*3 +: 3]), - .AXI_13_ARVALID(m_axi_hbm_int_arvalid[13 +: 1]), - .AXI_13_ARREADY(m_axi_hbm_int_arready[13 +: 1]), - .AXI_13_RDATA_PARITY(), - .AXI_13_RDATA(m_axi_hbm_int_rdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_13_RID(m_axi_hbm_int_rid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_13_RLAST(m_axi_hbm_int_rlast[13 +: 1]), - .AXI_13_RRESP(m_axi_hbm_int_rresp[13*2 +: 2]), - .AXI_13_RVALID(m_axi_hbm_int_rvalid[13 +: 1]), - .AXI_13_RREADY(m_axi_hbm_int_rready[13 +: 1]), - .AXI_13_AWADDR(m_axi_hbm_int_awaddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_13_AWBURST(m_axi_hbm_int_awburst[13*2 +: 2]), - .AXI_13_AWID(m_axi_hbm_int_awid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_13_AWLEN(m_axi_hbm_int_awlen[13*8 +: 4]), - .AXI_13_AWSIZE(m_axi_hbm_int_awsize[13*3 +: 3]), - .AXI_13_AWVALID(m_axi_hbm_int_awvalid[13 +: 1]), - .AXI_13_AWREADY(m_axi_hbm_int_awready[13 +: 1]), - .AXI_13_WDATA(m_axi_hbm_int_wdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_13_WLAST(m_axi_hbm_int_wlast[13 +: 1]), - .AXI_13_WSTRB(m_axi_hbm_int_wstrb[13*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_13_WDATA_PARITY(32'd0), - .AXI_13_WVALID(m_axi_hbm_int_wvalid[13 +: 1]), - .AXI_13_WREADY(m_axi_hbm_int_wready[13 +: 1]), - .AXI_13_BID(m_axi_hbm_int_bid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_13_BRESP(m_axi_hbm_int_bresp[13*2 +: 2]), - .AXI_13_BVALID(m_axi_hbm_int_bvalid[13 +: 1]), - .AXI_13_BREADY(m_axi_hbm_int_bready[13 +: 1]), - - .AXI_14_ACLK(hbm_clk_int[14 +: 1]), - .AXI_14_ARESET_N(!hbm_rst_int[14 +: 1]), - - .AXI_14_ARADDR(m_axi_hbm_int_araddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_14_ARBURST(m_axi_hbm_int_arburst[14*2 +: 2]), - .AXI_14_ARID(m_axi_hbm_int_arid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_14_ARLEN(m_axi_hbm_int_arlen[14*8 +: 4]), - .AXI_14_ARSIZE(m_axi_hbm_int_arsize[14*3 +: 3]), - .AXI_14_ARVALID(m_axi_hbm_int_arvalid[14 +: 1]), - .AXI_14_ARREADY(m_axi_hbm_int_arready[14 +: 1]), - .AXI_14_RDATA_PARITY(), - .AXI_14_RDATA(m_axi_hbm_int_rdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_14_RID(m_axi_hbm_int_rid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_14_RLAST(m_axi_hbm_int_rlast[14 +: 1]), - .AXI_14_RRESP(m_axi_hbm_int_rresp[14*2 +: 2]), - .AXI_14_RVALID(m_axi_hbm_int_rvalid[14 +: 1]), - .AXI_14_RREADY(m_axi_hbm_int_rready[14 +: 1]), - .AXI_14_AWADDR(m_axi_hbm_int_awaddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_14_AWBURST(m_axi_hbm_int_awburst[14*2 +: 2]), - .AXI_14_AWID(m_axi_hbm_int_awid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_14_AWLEN(m_axi_hbm_int_awlen[14*8 +: 4]), - .AXI_14_AWSIZE(m_axi_hbm_int_awsize[14*3 +: 3]), - .AXI_14_AWVALID(m_axi_hbm_int_awvalid[14 +: 1]), - .AXI_14_AWREADY(m_axi_hbm_int_awready[14 +: 1]), - .AXI_14_WDATA(m_axi_hbm_int_wdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_14_WLAST(m_axi_hbm_int_wlast[14 +: 1]), - .AXI_14_WSTRB(m_axi_hbm_int_wstrb[14*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_14_WDATA_PARITY(32'd0), - .AXI_14_WVALID(m_axi_hbm_int_wvalid[14 +: 1]), - .AXI_14_WREADY(m_axi_hbm_int_wready[14 +: 1]), - .AXI_14_BID(m_axi_hbm_int_bid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_14_BRESP(m_axi_hbm_int_bresp[14*2 +: 2]), - .AXI_14_BVALID(m_axi_hbm_int_bvalid[14 +: 1]), - .AXI_14_BREADY(m_axi_hbm_int_bready[14 +: 1]), - - .AXI_15_ACLK(hbm_clk_int[15 +: 1]), - .AXI_15_ARESET_N(!hbm_rst_int[15 +: 1]), - - .AXI_15_ARADDR(m_axi_hbm_int_araddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_15_ARBURST(m_axi_hbm_int_arburst[15*2 +: 2]), - .AXI_15_ARID(m_axi_hbm_int_arid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_15_ARLEN(m_axi_hbm_int_arlen[15*8 +: 4]), - .AXI_15_ARSIZE(m_axi_hbm_int_arsize[15*3 +: 3]), - .AXI_15_ARVALID(m_axi_hbm_int_arvalid[15 +: 1]), - .AXI_15_ARREADY(m_axi_hbm_int_arready[15 +: 1]), - .AXI_15_RDATA_PARITY(), - .AXI_15_RDATA(m_axi_hbm_int_rdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_15_RID(m_axi_hbm_int_rid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_15_RLAST(m_axi_hbm_int_rlast[15 +: 1]), - .AXI_15_RRESP(m_axi_hbm_int_rresp[15*2 +: 2]), - .AXI_15_RVALID(m_axi_hbm_int_rvalid[15 +: 1]), - .AXI_15_RREADY(m_axi_hbm_int_rready[15 +: 1]), - .AXI_15_AWADDR(m_axi_hbm_int_awaddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_15_AWBURST(m_axi_hbm_int_awburst[15*2 +: 2]), - .AXI_15_AWID(m_axi_hbm_int_awid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_15_AWLEN(m_axi_hbm_int_awlen[15*8 +: 4]), - .AXI_15_AWSIZE(m_axi_hbm_int_awsize[15*3 +: 3]), - .AXI_15_AWVALID(m_axi_hbm_int_awvalid[15 +: 1]), - .AXI_15_AWREADY(m_axi_hbm_int_awready[15 +: 1]), - .AXI_15_WDATA(m_axi_hbm_int_wdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_15_WLAST(m_axi_hbm_int_wlast[15 +: 1]), - .AXI_15_WSTRB(m_axi_hbm_int_wstrb[15*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_15_WDATA_PARITY(32'd0), - .AXI_15_WVALID(m_axi_hbm_int_wvalid[15 +: 1]), - .AXI_15_WREADY(m_axi_hbm_int_wready[15 +: 1]), - .AXI_15_BID(m_axi_hbm_int_bid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_15_BRESP(m_axi_hbm_int_bresp[15*2 +: 2]), - .AXI_15_BVALID(m_axi_hbm_int_bvalid[15 +: 1]), - .AXI_15_BREADY(m_axi_hbm_int_bready[15 +: 1]), - - .AXI_16_ACLK(hbm_clk_int[16 +: 1]), - .AXI_16_ARESET_N(!hbm_rst_int[16 +: 1]), - - .AXI_16_ARADDR(m_axi_hbm_int_araddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_16_ARBURST(m_axi_hbm_int_arburst[16*2 +: 2]), - .AXI_16_ARID(m_axi_hbm_int_arid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_16_ARLEN(m_axi_hbm_int_arlen[16*8 +: 4]), - .AXI_16_ARSIZE(m_axi_hbm_int_arsize[16*3 +: 3]), - .AXI_16_ARVALID(m_axi_hbm_int_arvalid[16 +: 1]), - .AXI_16_ARREADY(m_axi_hbm_int_arready[16 +: 1]), - .AXI_16_RDATA_PARITY(), - .AXI_16_RDATA(m_axi_hbm_int_rdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_16_RID(m_axi_hbm_int_rid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_16_RLAST(m_axi_hbm_int_rlast[16 +: 1]), - .AXI_16_RRESP(m_axi_hbm_int_rresp[16*2 +: 2]), - .AXI_16_RVALID(m_axi_hbm_int_rvalid[16 +: 1]), - .AXI_16_RREADY(m_axi_hbm_int_rready[16 +: 1]), - .AXI_16_AWADDR(m_axi_hbm_int_awaddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_16_AWBURST(m_axi_hbm_int_awburst[16*2 +: 2]), - .AXI_16_AWID(m_axi_hbm_int_awid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_16_AWLEN(m_axi_hbm_int_awlen[16*8 +: 4]), - .AXI_16_AWSIZE(m_axi_hbm_int_awsize[16*3 +: 3]), - .AXI_16_AWVALID(m_axi_hbm_int_awvalid[16 +: 1]), - .AXI_16_AWREADY(m_axi_hbm_int_awready[16 +: 1]), - .AXI_16_WDATA(m_axi_hbm_int_wdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_16_WLAST(m_axi_hbm_int_wlast[16 +: 1]), - .AXI_16_WSTRB(m_axi_hbm_int_wstrb[16*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_16_WDATA_PARITY(32'd0), - .AXI_16_WVALID(m_axi_hbm_int_wvalid[16 +: 1]), - .AXI_16_WREADY(m_axi_hbm_int_wready[16 +: 1]), - .AXI_16_BID(m_axi_hbm_int_bid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_16_BRESP(m_axi_hbm_int_bresp[16*2 +: 2]), - .AXI_16_BVALID(m_axi_hbm_int_bvalid[16 +: 1]), - .AXI_16_BREADY(m_axi_hbm_int_bready[16 +: 1]), - - .AXI_17_ACLK(hbm_clk_int[17 +: 1]), - .AXI_17_ARESET_N(!hbm_rst_int[17 +: 1]), - - .AXI_17_ARADDR(m_axi_hbm_int_araddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_17_ARBURST(m_axi_hbm_int_arburst[17*2 +: 2]), - .AXI_17_ARID(m_axi_hbm_int_arid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_17_ARLEN(m_axi_hbm_int_arlen[17*8 +: 4]), - .AXI_17_ARSIZE(m_axi_hbm_int_arsize[17*3 +: 3]), - .AXI_17_ARVALID(m_axi_hbm_int_arvalid[17 +: 1]), - .AXI_17_ARREADY(m_axi_hbm_int_arready[17 +: 1]), - .AXI_17_RDATA_PARITY(), - .AXI_17_RDATA(m_axi_hbm_int_rdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_17_RID(m_axi_hbm_int_rid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_17_RLAST(m_axi_hbm_int_rlast[17 +: 1]), - .AXI_17_RRESP(m_axi_hbm_int_rresp[17*2 +: 2]), - .AXI_17_RVALID(m_axi_hbm_int_rvalid[17 +: 1]), - .AXI_17_RREADY(m_axi_hbm_int_rready[17 +: 1]), - .AXI_17_AWADDR(m_axi_hbm_int_awaddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_17_AWBURST(m_axi_hbm_int_awburst[17*2 +: 2]), - .AXI_17_AWID(m_axi_hbm_int_awid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_17_AWLEN(m_axi_hbm_int_awlen[17*8 +: 4]), - .AXI_17_AWSIZE(m_axi_hbm_int_awsize[17*3 +: 3]), - .AXI_17_AWVALID(m_axi_hbm_int_awvalid[17 +: 1]), - .AXI_17_AWREADY(m_axi_hbm_int_awready[17 +: 1]), - .AXI_17_WDATA(m_axi_hbm_int_wdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_17_WLAST(m_axi_hbm_int_wlast[17 +: 1]), - .AXI_17_WSTRB(m_axi_hbm_int_wstrb[17*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_17_WDATA_PARITY(32'd0), - .AXI_17_WVALID(m_axi_hbm_int_wvalid[17 +: 1]), - .AXI_17_WREADY(m_axi_hbm_int_wready[17 +: 1]), - .AXI_17_BID(m_axi_hbm_int_bid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_17_BRESP(m_axi_hbm_int_bresp[17*2 +: 2]), - .AXI_17_BVALID(m_axi_hbm_int_bvalid[17 +: 1]), - .AXI_17_BREADY(m_axi_hbm_int_bready[17 +: 1]), - - .AXI_18_ACLK(hbm_clk_int[18 +: 1]), - .AXI_18_ARESET_N(!hbm_rst_int[18 +: 1]), - - .AXI_18_ARADDR(m_axi_hbm_int_araddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_18_ARBURST(m_axi_hbm_int_arburst[18*2 +: 2]), - .AXI_18_ARID(m_axi_hbm_int_arid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_18_ARLEN(m_axi_hbm_int_arlen[18*8 +: 4]), - .AXI_18_ARSIZE(m_axi_hbm_int_arsize[18*3 +: 3]), - .AXI_18_ARVALID(m_axi_hbm_int_arvalid[18 +: 1]), - .AXI_18_ARREADY(m_axi_hbm_int_arready[18 +: 1]), - .AXI_18_RDATA_PARITY(), - .AXI_18_RDATA(m_axi_hbm_int_rdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_18_RID(m_axi_hbm_int_rid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_18_RLAST(m_axi_hbm_int_rlast[18 +: 1]), - .AXI_18_RRESP(m_axi_hbm_int_rresp[18*2 +: 2]), - .AXI_18_RVALID(m_axi_hbm_int_rvalid[18 +: 1]), - .AXI_18_RREADY(m_axi_hbm_int_rready[18 +: 1]), - .AXI_18_AWADDR(m_axi_hbm_int_awaddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_18_AWBURST(m_axi_hbm_int_awburst[18*2 +: 2]), - .AXI_18_AWID(m_axi_hbm_int_awid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_18_AWLEN(m_axi_hbm_int_awlen[18*8 +: 4]), - .AXI_18_AWSIZE(m_axi_hbm_int_awsize[18*3 +: 3]), - .AXI_18_AWVALID(m_axi_hbm_int_awvalid[18 +: 1]), - .AXI_18_AWREADY(m_axi_hbm_int_awready[18 +: 1]), - .AXI_18_WDATA(m_axi_hbm_int_wdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_18_WLAST(m_axi_hbm_int_wlast[18 +: 1]), - .AXI_18_WSTRB(m_axi_hbm_int_wstrb[18*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_18_WDATA_PARITY(32'd0), - .AXI_18_WVALID(m_axi_hbm_int_wvalid[18 +: 1]), - .AXI_18_WREADY(m_axi_hbm_int_wready[18 +: 1]), - .AXI_18_BID(m_axi_hbm_int_bid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_18_BRESP(m_axi_hbm_int_bresp[18*2 +: 2]), - .AXI_18_BVALID(m_axi_hbm_int_bvalid[18 +: 1]), - .AXI_18_BREADY(m_axi_hbm_int_bready[18 +: 1]), - - .AXI_19_ACLK(hbm_clk_int[19 +: 1]), - .AXI_19_ARESET_N(!hbm_rst_int[19 +: 1]), - - .AXI_19_ARADDR(m_axi_hbm_int_araddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_19_ARBURST(m_axi_hbm_int_arburst[19*2 +: 2]), - .AXI_19_ARID(m_axi_hbm_int_arid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_19_ARLEN(m_axi_hbm_int_arlen[19*8 +: 4]), - .AXI_19_ARSIZE(m_axi_hbm_int_arsize[19*3 +: 3]), - .AXI_19_ARVALID(m_axi_hbm_int_arvalid[19 +: 1]), - .AXI_19_ARREADY(m_axi_hbm_int_arready[19 +: 1]), - .AXI_19_RDATA_PARITY(), - .AXI_19_RDATA(m_axi_hbm_int_rdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_19_RID(m_axi_hbm_int_rid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_19_RLAST(m_axi_hbm_int_rlast[19 +: 1]), - .AXI_19_RRESP(m_axi_hbm_int_rresp[19*2 +: 2]), - .AXI_19_RVALID(m_axi_hbm_int_rvalid[19 +: 1]), - .AXI_19_RREADY(m_axi_hbm_int_rready[19 +: 1]), - .AXI_19_AWADDR(m_axi_hbm_int_awaddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_19_AWBURST(m_axi_hbm_int_awburst[19*2 +: 2]), - .AXI_19_AWID(m_axi_hbm_int_awid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_19_AWLEN(m_axi_hbm_int_awlen[19*8 +: 4]), - .AXI_19_AWSIZE(m_axi_hbm_int_awsize[19*3 +: 3]), - .AXI_19_AWVALID(m_axi_hbm_int_awvalid[19 +: 1]), - .AXI_19_AWREADY(m_axi_hbm_int_awready[19 +: 1]), - .AXI_19_WDATA(m_axi_hbm_int_wdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_19_WLAST(m_axi_hbm_int_wlast[19 +: 1]), - .AXI_19_WSTRB(m_axi_hbm_int_wstrb[19*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_19_WDATA_PARITY(32'd0), - .AXI_19_WVALID(m_axi_hbm_int_wvalid[19 +: 1]), - .AXI_19_WREADY(m_axi_hbm_int_wready[19 +: 1]), - .AXI_19_BID(m_axi_hbm_int_bid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_19_BRESP(m_axi_hbm_int_bresp[19*2 +: 2]), - .AXI_19_BVALID(m_axi_hbm_int_bvalid[19 +: 1]), - .AXI_19_BREADY(m_axi_hbm_int_bready[19 +: 1]), - - .AXI_20_ACLK(hbm_clk_int[20 +: 1]), - .AXI_20_ARESET_N(!hbm_rst_int[20 +: 1]), - - .AXI_20_ARADDR(m_axi_hbm_int_araddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_20_ARBURST(m_axi_hbm_int_arburst[20*2 +: 2]), - .AXI_20_ARID(m_axi_hbm_int_arid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_20_ARLEN(m_axi_hbm_int_arlen[20*8 +: 4]), - .AXI_20_ARSIZE(m_axi_hbm_int_arsize[20*3 +: 3]), - .AXI_20_ARVALID(m_axi_hbm_int_arvalid[20 +: 1]), - .AXI_20_ARREADY(m_axi_hbm_int_arready[20 +: 1]), - .AXI_20_RDATA_PARITY(), - .AXI_20_RDATA(m_axi_hbm_int_rdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_20_RID(m_axi_hbm_int_rid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_20_RLAST(m_axi_hbm_int_rlast[20 +: 1]), - .AXI_20_RRESP(m_axi_hbm_int_rresp[20*2 +: 2]), - .AXI_20_RVALID(m_axi_hbm_int_rvalid[20 +: 1]), - .AXI_20_RREADY(m_axi_hbm_int_rready[20 +: 1]), - .AXI_20_AWADDR(m_axi_hbm_int_awaddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_20_AWBURST(m_axi_hbm_int_awburst[20*2 +: 2]), - .AXI_20_AWID(m_axi_hbm_int_awid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_20_AWLEN(m_axi_hbm_int_awlen[20*8 +: 4]), - .AXI_20_AWSIZE(m_axi_hbm_int_awsize[20*3 +: 3]), - .AXI_20_AWVALID(m_axi_hbm_int_awvalid[20 +: 1]), - .AXI_20_AWREADY(m_axi_hbm_int_awready[20 +: 1]), - .AXI_20_WDATA(m_axi_hbm_int_wdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_20_WLAST(m_axi_hbm_int_wlast[20 +: 1]), - .AXI_20_WSTRB(m_axi_hbm_int_wstrb[20*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_20_WDATA_PARITY(32'd0), - .AXI_20_WVALID(m_axi_hbm_int_wvalid[20 +: 1]), - .AXI_20_WREADY(m_axi_hbm_int_wready[20 +: 1]), - .AXI_20_BID(m_axi_hbm_int_bid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_20_BRESP(m_axi_hbm_int_bresp[20*2 +: 2]), - .AXI_20_BVALID(m_axi_hbm_int_bvalid[20 +: 1]), - .AXI_20_BREADY(m_axi_hbm_int_bready[20 +: 1]), - - .AXI_21_ACLK(hbm_clk_int[21 +: 1]), - .AXI_21_ARESET_N(!hbm_rst_int[21 +: 1]), - - .AXI_21_ARADDR(m_axi_hbm_int_araddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_21_ARBURST(m_axi_hbm_int_arburst[21*2 +: 2]), - .AXI_21_ARID(m_axi_hbm_int_arid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_21_ARLEN(m_axi_hbm_int_arlen[21*8 +: 4]), - .AXI_21_ARSIZE(m_axi_hbm_int_arsize[21*3 +: 3]), - .AXI_21_ARVALID(m_axi_hbm_int_arvalid[21 +: 1]), - .AXI_21_ARREADY(m_axi_hbm_int_arready[21 +: 1]), - .AXI_21_RDATA_PARITY(), - .AXI_21_RDATA(m_axi_hbm_int_rdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_21_RID(m_axi_hbm_int_rid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_21_RLAST(m_axi_hbm_int_rlast[21 +: 1]), - .AXI_21_RRESP(m_axi_hbm_int_rresp[21*2 +: 2]), - .AXI_21_RVALID(m_axi_hbm_int_rvalid[21 +: 1]), - .AXI_21_RREADY(m_axi_hbm_int_rready[21 +: 1]), - .AXI_21_AWADDR(m_axi_hbm_int_awaddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_21_AWBURST(m_axi_hbm_int_awburst[21*2 +: 2]), - .AXI_21_AWID(m_axi_hbm_int_awid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_21_AWLEN(m_axi_hbm_int_awlen[21*8 +: 4]), - .AXI_21_AWSIZE(m_axi_hbm_int_awsize[21*3 +: 3]), - .AXI_21_AWVALID(m_axi_hbm_int_awvalid[21 +: 1]), - .AXI_21_AWREADY(m_axi_hbm_int_awready[21 +: 1]), - .AXI_21_WDATA(m_axi_hbm_int_wdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_21_WLAST(m_axi_hbm_int_wlast[21 +: 1]), - .AXI_21_WSTRB(m_axi_hbm_int_wstrb[21*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_21_WDATA_PARITY(32'd0), - .AXI_21_WVALID(m_axi_hbm_int_wvalid[21 +: 1]), - .AXI_21_WREADY(m_axi_hbm_int_wready[21 +: 1]), - .AXI_21_BID(m_axi_hbm_int_bid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_21_BRESP(m_axi_hbm_int_bresp[21*2 +: 2]), - .AXI_21_BVALID(m_axi_hbm_int_bvalid[21 +: 1]), - .AXI_21_BREADY(m_axi_hbm_int_bready[21 +: 1]), - - .AXI_22_ACLK(hbm_clk_int[22 +: 1]), - .AXI_22_ARESET_N(!hbm_rst_int[22 +: 1]), - - .AXI_22_ARADDR(m_axi_hbm_int_araddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_22_ARBURST(m_axi_hbm_int_arburst[22*2 +: 2]), - .AXI_22_ARID(m_axi_hbm_int_arid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_22_ARLEN(m_axi_hbm_int_arlen[22*8 +: 4]), - .AXI_22_ARSIZE(m_axi_hbm_int_arsize[22*3 +: 3]), - .AXI_22_ARVALID(m_axi_hbm_int_arvalid[22 +: 1]), - .AXI_22_ARREADY(m_axi_hbm_int_arready[22 +: 1]), - .AXI_22_RDATA_PARITY(), - .AXI_22_RDATA(m_axi_hbm_int_rdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_22_RID(m_axi_hbm_int_rid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_22_RLAST(m_axi_hbm_int_rlast[22 +: 1]), - .AXI_22_RRESP(m_axi_hbm_int_rresp[22*2 +: 2]), - .AXI_22_RVALID(m_axi_hbm_int_rvalid[22 +: 1]), - .AXI_22_RREADY(m_axi_hbm_int_rready[22 +: 1]), - .AXI_22_AWADDR(m_axi_hbm_int_awaddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_22_AWBURST(m_axi_hbm_int_awburst[22*2 +: 2]), - .AXI_22_AWID(m_axi_hbm_int_awid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_22_AWLEN(m_axi_hbm_int_awlen[22*8 +: 4]), - .AXI_22_AWSIZE(m_axi_hbm_int_awsize[22*3 +: 3]), - .AXI_22_AWVALID(m_axi_hbm_int_awvalid[22 +: 1]), - .AXI_22_AWREADY(m_axi_hbm_int_awready[22 +: 1]), - .AXI_22_WDATA(m_axi_hbm_int_wdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_22_WLAST(m_axi_hbm_int_wlast[22 +: 1]), - .AXI_22_WSTRB(m_axi_hbm_int_wstrb[22*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_22_WDATA_PARITY(32'd0), - .AXI_22_WVALID(m_axi_hbm_int_wvalid[22 +: 1]), - .AXI_22_WREADY(m_axi_hbm_int_wready[22 +: 1]), - .AXI_22_BID(m_axi_hbm_int_bid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_22_BRESP(m_axi_hbm_int_bresp[22*2 +: 2]), - .AXI_22_BVALID(m_axi_hbm_int_bvalid[22 +: 1]), - .AXI_22_BREADY(m_axi_hbm_int_bready[22 +: 1]), - - .AXI_23_ACLK(hbm_clk_int[23 +: 1]), - .AXI_23_ARESET_N(!hbm_rst_int[23 +: 1]), - - .AXI_23_ARADDR(m_axi_hbm_int_araddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_23_ARBURST(m_axi_hbm_int_arburst[23*2 +: 2]), - .AXI_23_ARID(m_axi_hbm_int_arid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_23_ARLEN(m_axi_hbm_int_arlen[23*8 +: 4]), - .AXI_23_ARSIZE(m_axi_hbm_int_arsize[23*3 +: 3]), - .AXI_23_ARVALID(m_axi_hbm_int_arvalid[23 +: 1]), - .AXI_23_ARREADY(m_axi_hbm_int_arready[23 +: 1]), - .AXI_23_RDATA_PARITY(), - .AXI_23_RDATA(m_axi_hbm_int_rdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_23_RID(m_axi_hbm_int_rid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_23_RLAST(m_axi_hbm_int_rlast[23 +: 1]), - .AXI_23_RRESP(m_axi_hbm_int_rresp[23*2 +: 2]), - .AXI_23_RVALID(m_axi_hbm_int_rvalid[23 +: 1]), - .AXI_23_RREADY(m_axi_hbm_int_rready[23 +: 1]), - .AXI_23_AWADDR(m_axi_hbm_int_awaddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_23_AWBURST(m_axi_hbm_int_awburst[23*2 +: 2]), - .AXI_23_AWID(m_axi_hbm_int_awid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_23_AWLEN(m_axi_hbm_int_awlen[23*8 +: 4]), - .AXI_23_AWSIZE(m_axi_hbm_int_awsize[23*3 +: 3]), - .AXI_23_AWVALID(m_axi_hbm_int_awvalid[23 +: 1]), - .AXI_23_AWREADY(m_axi_hbm_int_awready[23 +: 1]), - .AXI_23_WDATA(m_axi_hbm_int_wdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_23_WLAST(m_axi_hbm_int_wlast[23 +: 1]), - .AXI_23_WSTRB(m_axi_hbm_int_wstrb[23*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_23_WDATA_PARITY(32'd0), - .AXI_23_WVALID(m_axi_hbm_int_wvalid[23 +: 1]), - .AXI_23_WREADY(m_axi_hbm_int_wready[23 +: 1]), - .AXI_23_BID(m_axi_hbm_int_bid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_23_BRESP(m_axi_hbm_int_bresp[23*2 +: 2]), - .AXI_23_BVALID(m_axi_hbm_int_bvalid[23 +: 1]), - .AXI_23_BREADY(m_axi_hbm_int_bready[23 +: 1]), - - .AXI_24_ACLK(hbm_clk_int[24 +: 1]), - .AXI_24_ARESET_N(!hbm_rst_int[24 +: 1]), - - .AXI_24_ARADDR(m_axi_hbm_int_araddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_24_ARBURST(m_axi_hbm_int_arburst[24*2 +: 2]), - .AXI_24_ARID(m_axi_hbm_int_arid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_24_ARLEN(m_axi_hbm_int_arlen[24*8 +: 4]), - .AXI_24_ARSIZE(m_axi_hbm_int_arsize[24*3 +: 3]), - .AXI_24_ARVALID(m_axi_hbm_int_arvalid[24 +: 1]), - .AXI_24_ARREADY(m_axi_hbm_int_arready[24 +: 1]), - .AXI_24_RDATA_PARITY(), - .AXI_24_RDATA(m_axi_hbm_int_rdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_24_RID(m_axi_hbm_int_rid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_24_RLAST(m_axi_hbm_int_rlast[24 +: 1]), - .AXI_24_RRESP(m_axi_hbm_int_rresp[24*2 +: 2]), - .AXI_24_RVALID(m_axi_hbm_int_rvalid[24 +: 1]), - .AXI_24_RREADY(m_axi_hbm_int_rready[24 +: 1]), - .AXI_24_AWADDR(m_axi_hbm_int_awaddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_24_AWBURST(m_axi_hbm_int_awburst[24*2 +: 2]), - .AXI_24_AWID(m_axi_hbm_int_awid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_24_AWLEN(m_axi_hbm_int_awlen[24*8 +: 4]), - .AXI_24_AWSIZE(m_axi_hbm_int_awsize[24*3 +: 3]), - .AXI_24_AWVALID(m_axi_hbm_int_awvalid[24 +: 1]), - .AXI_24_AWREADY(m_axi_hbm_int_awready[24 +: 1]), - .AXI_24_WDATA(m_axi_hbm_int_wdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_24_WLAST(m_axi_hbm_int_wlast[24 +: 1]), - .AXI_24_WSTRB(m_axi_hbm_int_wstrb[24*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_24_WDATA_PARITY(32'd0), - .AXI_24_WVALID(m_axi_hbm_int_wvalid[24 +: 1]), - .AXI_24_WREADY(m_axi_hbm_int_wready[24 +: 1]), - .AXI_24_BID(m_axi_hbm_int_bid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_24_BRESP(m_axi_hbm_int_bresp[24*2 +: 2]), - .AXI_24_BVALID(m_axi_hbm_int_bvalid[24 +: 1]), - .AXI_24_BREADY(m_axi_hbm_int_bready[24 +: 1]), - - .AXI_25_ACLK(hbm_clk_int[25 +: 1]), - .AXI_25_ARESET_N(!hbm_rst_int[25 +: 1]), - - .AXI_25_ARADDR(m_axi_hbm_int_araddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_25_ARBURST(m_axi_hbm_int_arburst[25*2 +: 2]), - .AXI_25_ARID(m_axi_hbm_int_arid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_25_ARLEN(m_axi_hbm_int_arlen[25*8 +: 4]), - .AXI_25_ARSIZE(m_axi_hbm_int_arsize[25*3 +: 3]), - .AXI_25_ARVALID(m_axi_hbm_int_arvalid[25 +: 1]), - .AXI_25_ARREADY(m_axi_hbm_int_arready[25 +: 1]), - .AXI_25_RDATA_PARITY(), - .AXI_25_RDATA(m_axi_hbm_int_rdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_25_RID(m_axi_hbm_int_rid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_25_RLAST(m_axi_hbm_int_rlast[25 +: 1]), - .AXI_25_RRESP(m_axi_hbm_int_rresp[25*2 +: 2]), - .AXI_25_RVALID(m_axi_hbm_int_rvalid[25 +: 1]), - .AXI_25_RREADY(m_axi_hbm_int_rready[25 +: 1]), - .AXI_25_AWADDR(m_axi_hbm_int_awaddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_25_AWBURST(m_axi_hbm_int_awburst[25*2 +: 2]), - .AXI_25_AWID(m_axi_hbm_int_awid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_25_AWLEN(m_axi_hbm_int_awlen[25*8 +: 4]), - .AXI_25_AWSIZE(m_axi_hbm_int_awsize[25*3 +: 3]), - .AXI_25_AWVALID(m_axi_hbm_int_awvalid[25 +: 1]), - .AXI_25_AWREADY(m_axi_hbm_int_awready[25 +: 1]), - .AXI_25_WDATA(m_axi_hbm_int_wdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_25_WLAST(m_axi_hbm_int_wlast[25 +: 1]), - .AXI_25_WSTRB(m_axi_hbm_int_wstrb[25*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_25_WDATA_PARITY(32'd0), - .AXI_25_WVALID(m_axi_hbm_int_wvalid[25 +: 1]), - .AXI_25_WREADY(m_axi_hbm_int_wready[25 +: 1]), - .AXI_25_BID(m_axi_hbm_int_bid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_25_BRESP(m_axi_hbm_int_bresp[25*2 +: 2]), - .AXI_25_BVALID(m_axi_hbm_int_bvalid[25 +: 1]), - .AXI_25_BREADY(m_axi_hbm_int_bready[25 +: 1]), - - .AXI_26_ACLK(hbm_clk_int[26 +: 1]), - .AXI_26_ARESET_N(!hbm_rst_int[26 +: 1]), - - .AXI_26_ARADDR(m_axi_hbm_int_araddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_26_ARBURST(m_axi_hbm_int_arburst[26*2 +: 2]), - .AXI_26_ARID(m_axi_hbm_int_arid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_26_ARLEN(m_axi_hbm_int_arlen[26*8 +: 4]), - .AXI_26_ARSIZE(m_axi_hbm_int_arsize[26*3 +: 3]), - .AXI_26_ARVALID(m_axi_hbm_int_arvalid[26 +: 1]), - .AXI_26_ARREADY(m_axi_hbm_int_arready[26 +: 1]), - .AXI_26_RDATA_PARITY(), - .AXI_26_RDATA(m_axi_hbm_int_rdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_26_RID(m_axi_hbm_int_rid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_26_RLAST(m_axi_hbm_int_rlast[26 +: 1]), - .AXI_26_RRESP(m_axi_hbm_int_rresp[26*2 +: 2]), - .AXI_26_RVALID(m_axi_hbm_int_rvalid[26 +: 1]), - .AXI_26_RREADY(m_axi_hbm_int_rready[26 +: 1]), - .AXI_26_AWADDR(m_axi_hbm_int_awaddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_26_AWBURST(m_axi_hbm_int_awburst[26*2 +: 2]), - .AXI_26_AWID(m_axi_hbm_int_awid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_26_AWLEN(m_axi_hbm_int_awlen[26*8 +: 4]), - .AXI_26_AWSIZE(m_axi_hbm_int_awsize[26*3 +: 3]), - .AXI_26_AWVALID(m_axi_hbm_int_awvalid[26 +: 1]), - .AXI_26_AWREADY(m_axi_hbm_int_awready[26 +: 1]), - .AXI_26_WDATA(m_axi_hbm_int_wdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_26_WLAST(m_axi_hbm_int_wlast[26 +: 1]), - .AXI_26_WSTRB(m_axi_hbm_int_wstrb[26*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_26_WDATA_PARITY(32'd0), - .AXI_26_WVALID(m_axi_hbm_int_wvalid[26 +: 1]), - .AXI_26_WREADY(m_axi_hbm_int_wready[26 +: 1]), - .AXI_26_BID(m_axi_hbm_int_bid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_26_BRESP(m_axi_hbm_int_bresp[26*2 +: 2]), - .AXI_26_BVALID(m_axi_hbm_int_bvalid[26 +: 1]), - .AXI_26_BREADY(m_axi_hbm_int_bready[26 +: 1]), - - .AXI_27_ACLK(hbm_clk_int[27 +: 1]), - .AXI_27_ARESET_N(!hbm_rst_int[27 +: 1]), - - .AXI_27_ARADDR(m_axi_hbm_int_araddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_27_ARBURST(m_axi_hbm_int_arburst[27*2 +: 2]), - .AXI_27_ARID(m_axi_hbm_int_arid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_27_ARLEN(m_axi_hbm_int_arlen[27*8 +: 4]), - .AXI_27_ARSIZE(m_axi_hbm_int_arsize[27*3 +: 3]), - .AXI_27_ARVALID(m_axi_hbm_int_arvalid[27 +: 1]), - .AXI_27_ARREADY(m_axi_hbm_int_arready[27 +: 1]), - .AXI_27_RDATA_PARITY(), - .AXI_27_RDATA(m_axi_hbm_int_rdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_27_RID(m_axi_hbm_int_rid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_27_RLAST(m_axi_hbm_int_rlast[27 +: 1]), - .AXI_27_RRESP(m_axi_hbm_int_rresp[27*2 +: 2]), - .AXI_27_RVALID(m_axi_hbm_int_rvalid[27 +: 1]), - .AXI_27_RREADY(m_axi_hbm_int_rready[27 +: 1]), - .AXI_27_AWADDR(m_axi_hbm_int_awaddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_27_AWBURST(m_axi_hbm_int_awburst[27*2 +: 2]), - .AXI_27_AWID(m_axi_hbm_int_awid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_27_AWLEN(m_axi_hbm_int_awlen[27*8 +: 4]), - .AXI_27_AWSIZE(m_axi_hbm_int_awsize[27*3 +: 3]), - .AXI_27_AWVALID(m_axi_hbm_int_awvalid[27 +: 1]), - .AXI_27_AWREADY(m_axi_hbm_int_awready[27 +: 1]), - .AXI_27_WDATA(m_axi_hbm_int_wdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_27_WLAST(m_axi_hbm_int_wlast[27 +: 1]), - .AXI_27_WSTRB(m_axi_hbm_int_wstrb[27*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_27_WDATA_PARITY(32'd0), - .AXI_27_WVALID(m_axi_hbm_int_wvalid[27 +: 1]), - .AXI_27_WREADY(m_axi_hbm_int_wready[27 +: 1]), - .AXI_27_BID(m_axi_hbm_int_bid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_27_BRESP(m_axi_hbm_int_bresp[27*2 +: 2]), - .AXI_27_BVALID(m_axi_hbm_int_bvalid[27 +: 1]), - .AXI_27_BREADY(m_axi_hbm_int_bready[27 +: 1]), - - .AXI_28_ACLK(hbm_clk_int[28 +: 1]), - .AXI_28_ARESET_N(!hbm_rst_int[28 +: 1]), - - .AXI_28_ARADDR(m_axi_hbm_int_araddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_28_ARBURST(m_axi_hbm_int_arburst[28*2 +: 2]), - .AXI_28_ARID(m_axi_hbm_int_arid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_28_ARLEN(m_axi_hbm_int_arlen[28*8 +: 4]), - .AXI_28_ARSIZE(m_axi_hbm_int_arsize[28*3 +: 3]), - .AXI_28_ARVALID(m_axi_hbm_int_arvalid[28 +: 1]), - .AXI_28_ARREADY(m_axi_hbm_int_arready[28 +: 1]), - .AXI_28_RDATA_PARITY(), - .AXI_28_RDATA(m_axi_hbm_int_rdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_28_RID(m_axi_hbm_int_rid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_28_RLAST(m_axi_hbm_int_rlast[28 +: 1]), - .AXI_28_RRESP(m_axi_hbm_int_rresp[28*2 +: 2]), - .AXI_28_RVALID(m_axi_hbm_int_rvalid[28 +: 1]), - .AXI_28_RREADY(m_axi_hbm_int_rready[28 +: 1]), - .AXI_28_AWADDR(m_axi_hbm_int_awaddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_28_AWBURST(m_axi_hbm_int_awburst[28*2 +: 2]), - .AXI_28_AWID(m_axi_hbm_int_awid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_28_AWLEN(m_axi_hbm_int_awlen[28*8 +: 4]), - .AXI_28_AWSIZE(m_axi_hbm_int_awsize[28*3 +: 3]), - .AXI_28_AWVALID(m_axi_hbm_int_awvalid[28 +: 1]), - .AXI_28_AWREADY(m_axi_hbm_int_awready[28 +: 1]), - .AXI_28_WDATA(m_axi_hbm_int_wdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_28_WLAST(m_axi_hbm_int_wlast[28 +: 1]), - .AXI_28_WSTRB(m_axi_hbm_int_wstrb[28*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_28_WDATA_PARITY(32'd0), - .AXI_28_WVALID(m_axi_hbm_int_wvalid[28 +: 1]), - .AXI_28_WREADY(m_axi_hbm_int_wready[28 +: 1]), - .AXI_28_BID(m_axi_hbm_int_bid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_28_BRESP(m_axi_hbm_int_bresp[28*2 +: 2]), - .AXI_28_BVALID(m_axi_hbm_int_bvalid[28 +: 1]), - .AXI_28_BREADY(m_axi_hbm_int_bready[28 +: 1]), - - .AXI_29_ACLK(hbm_clk_int[29 +: 1]), - .AXI_29_ARESET_N(!hbm_rst_int[29 +: 1]), - - .AXI_29_ARADDR(m_axi_hbm_int_araddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_29_ARBURST(m_axi_hbm_int_arburst[29*2 +: 2]), - .AXI_29_ARID(m_axi_hbm_int_arid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_29_ARLEN(m_axi_hbm_int_arlen[29*8 +: 4]), - .AXI_29_ARSIZE(m_axi_hbm_int_arsize[29*3 +: 3]), - .AXI_29_ARVALID(m_axi_hbm_int_arvalid[29 +: 1]), - .AXI_29_ARREADY(m_axi_hbm_int_arready[29 +: 1]), - .AXI_29_RDATA_PARITY(), - .AXI_29_RDATA(m_axi_hbm_int_rdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_29_RID(m_axi_hbm_int_rid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_29_RLAST(m_axi_hbm_int_rlast[29 +: 1]), - .AXI_29_RRESP(m_axi_hbm_int_rresp[29*2 +: 2]), - .AXI_29_RVALID(m_axi_hbm_int_rvalid[29 +: 1]), - .AXI_29_RREADY(m_axi_hbm_int_rready[29 +: 1]), - .AXI_29_AWADDR(m_axi_hbm_int_awaddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_29_AWBURST(m_axi_hbm_int_awburst[29*2 +: 2]), - .AXI_29_AWID(m_axi_hbm_int_awid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_29_AWLEN(m_axi_hbm_int_awlen[29*8 +: 4]), - .AXI_29_AWSIZE(m_axi_hbm_int_awsize[29*3 +: 3]), - .AXI_29_AWVALID(m_axi_hbm_int_awvalid[29 +: 1]), - .AXI_29_AWREADY(m_axi_hbm_int_awready[29 +: 1]), - .AXI_29_WDATA(m_axi_hbm_int_wdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_29_WLAST(m_axi_hbm_int_wlast[29 +: 1]), - .AXI_29_WSTRB(m_axi_hbm_int_wstrb[29*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_29_WDATA_PARITY(32'd0), - .AXI_29_WVALID(m_axi_hbm_int_wvalid[29 +: 1]), - .AXI_29_WREADY(m_axi_hbm_int_wready[29 +: 1]), - .AXI_29_BID(m_axi_hbm_int_bid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_29_BRESP(m_axi_hbm_int_bresp[29*2 +: 2]), - .AXI_29_BVALID(m_axi_hbm_int_bvalid[29 +: 1]), - .AXI_29_BREADY(m_axi_hbm_int_bready[29 +: 1]), - - .AXI_30_ACLK(hbm_clk_int[30 +: 1]), - .AXI_30_ARESET_N(!hbm_rst_int[30 +: 1]), - - .AXI_30_ARADDR(m_axi_hbm_int_araddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_30_ARBURST(m_axi_hbm_int_arburst[30*2 +: 2]), - .AXI_30_ARID(m_axi_hbm_int_arid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_30_ARLEN(m_axi_hbm_int_arlen[30*8 +: 4]), - .AXI_30_ARSIZE(m_axi_hbm_int_arsize[30*3 +: 3]), - .AXI_30_ARVALID(m_axi_hbm_int_arvalid[30 +: 1]), - .AXI_30_ARREADY(m_axi_hbm_int_arready[30 +: 1]), - .AXI_30_RDATA_PARITY(), - .AXI_30_RDATA(m_axi_hbm_int_rdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_30_RID(m_axi_hbm_int_rid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_30_RLAST(m_axi_hbm_int_rlast[30 +: 1]), - .AXI_30_RRESP(m_axi_hbm_int_rresp[30*2 +: 2]), - .AXI_30_RVALID(m_axi_hbm_int_rvalid[30 +: 1]), - .AXI_30_RREADY(m_axi_hbm_int_rready[30 +: 1]), - .AXI_30_AWADDR(m_axi_hbm_int_awaddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_30_AWBURST(m_axi_hbm_int_awburst[30*2 +: 2]), - .AXI_30_AWID(m_axi_hbm_int_awid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_30_AWLEN(m_axi_hbm_int_awlen[30*8 +: 4]), - .AXI_30_AWSIZE(m_axi_hbm_int_awsize[30*3 +: 3]), - .AXI_30_AWVALID(m_axi_hbm_int_awvalid[30 +: 1]), - .AXI_30_AWREADY(m_axi_hbm_int_awready[30 +: 1]), - .AXI_30_WDATA(m_axi_hbm_int_wdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_30_WLAST(m_axi_hbm_int_wlast[30 +: 1]), - .AXI_30_WSTRB(m_axi_hbm_int_wstrb[30*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_30_WDATA_PARITY(32'd0), - .AXI_30_WVALID(m_axi_hbm_int_wvalid[30 +: 1]), - .AXI_30_WREADY(m_axi_hbm_int_wready[30 +: 1]), - .AXI_30_BID(m_axi_hbm_int_bid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_30_BRESP(m_axi_hbm_int_bresp[30*2 +: 2]), - .AXI_30_BVALID(m_axi_hbm_int_bvalid[30 +: 1]), - .AXI_30_BREADY(m_axi_hbm_int_bready[30 +: 1]), - - .AXI_31_ACLK(hbm_clk_int[31 +: 1]), - .AXI_31_ARESET_N(!hbm_rst_int[31 +: 1]), - - .AXI_31_ARADDR(m_axi_hbm_int_araddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_31_ARBURST(m_axi_hbm_int_arburst[31*2 +: 2]), - .AXI_31_ARID(m_axi_hbm_int_arid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_31_ARLEN(m_axi_hbm_int_arlen[31*8 +: 4]), - .AXI_31_ARSIZE(m_axi_hbm_int_arsize[31*3 +: 3]), - .AXI_31_ARVALID(m_axi_hbm_int_arvalid[31 +: 1]), - .AXI_31_ARREADY(m_axi_hbm_int_arready[31 +: 1]), - .AXI_31_RDATA_PARITY(), - .AXI_31_RDATA(m_axi_hbm_int_rdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_31_RID(m_axi_hbm_int_rid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_31_RLAST(m_axi_hbm_int_rlast[31 +: 1]), - .AXI_31_RRESP(m_axi_hbm_int_rresp[31*2 +: 2]), - .AXI_31_RVALID(m_axi_hbm_int_rvalid[31 +: 1]), - .AXI_31_RREADY(m_axi_hbm_int_rready[31 +: 1]), - .AXI_31_AWADDR(m_axi_hbm_int_awaddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_31_AWBURST(m_axi_hbm_int_awburst[31*2 +: 2]), - .AXI_31_AWID(m_axi_hbm_int_awid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_31_AWLEN(m_axi_hbm_int_awlen[31*8 +: 4]), - .AXI_31_AWSIZE(m_axi_hbm_int_awsize[31*3 +: 3]), - .AXI_31_AWVALID(m_axi_hbm_int_awvalid[31 +: 1]), - .AXI_31_AWREADY(m_axi_hbm_int_awready[31 +: 1]), - .AXI_31_WDATA(m_axi_hbm_int_wdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_31_WLAST(m_axi_hbm_int_wlast[31 +: 1]), - .AXI_31_WSTRB(m_axi_hbm_int_wstrb[31*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_31_WDATA_PARITY(32'd0), - .AXI_31_WVALID(m_axi_hbm_int_wvalid[31 +: 1]), - .AXI_31_WREADY(m_axi_hbm_int_wready[31 +: 1]), - .AXI_31_BID(m_axi_hbm_int_bid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_31_BRESP(m_axi_hbm_int_bresp[31*2 +: 2]), - .AXI_31_BVALID(m_axi_hbm_int_bvalid[31 +: 1]), - .AXI_31_BREADY(m_axi_hbm_int_bready[31 +: 1]), - - .DRAM_0_STAT_CATTRIP(hbm_cattrip_1), - .DRAM_0_STAT_TEMP(hbm_temp_1), - .DRAM_1_STAT_CATTRIP(hbm_cattrip_2), - .DRAM_1_STAT_TEMP(hbm_temp_2) -); - -for (n = 0; n < HBM_CH_INT; n = n + 1) begin - - localparam c = n / HBM_CH_STRIDE; - - if (c*HBM_CH_STRIDE == n) begin - - assign hbm_clk[c] = hbm_clk_int[n]; - assign hbm_rst[c] = hbm_rst_int[n]; - - assign m_axi_hbm_int_awid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = m_axi_hbm_awid[c*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]; - assign m_axi_hbm_int_awaddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH] = m_axi_hbm_awaddr[c*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]; - assign m_axi_hbm_int_awlen[n*8 +: 8] = m_axi_hbm_awlen[c*8 +: 8]; - assign m_axi_hbm_int_awsize[n*3 +: 3] = m_axi_hbm_awsize[c*3 +: 3]; - assign m_axi_hbm_int_awburst[n*2 +: 2] = m_axi_hbm_awburst[c*2 +: 2]; - assign m_axi_hbm_int_awlock[n*1 +: 1] = m_axi_hbm_awlock[c*1 +: 1]; - assign m_axi_hbm_int_awcache[n*4 +: 4] = m_axi_hbm_awcache[c*4 +: 4]; - assign m_axi_hbm_int_awprot[n*3 +: 3] = m_axi_hbm_awprot[c*3 +: 3]; - assign m_axi_hbm_int_awqos[n*4 +: 4] = m_axi_hbm_awqos[c*4 +: 4]; - assign m_axi_hbm_int_awvalid[n*1 +: 1] = m_axi_hbm_awvalid[c*1 +: 1]; - assign m_axi_hbm_awready[c*1 +: 1] = m_axi_hbm_int_awready[n*1 +: 1]; - assign m_axi_hbm_int_wdata[n*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH] = m_axi_hbm_wdata[c*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]; - assign m_axi_hbm_int_wstrb[n*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH] = m_axi_hbm_wstrb[c*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]; - assign m_axi_hbm_int_wlast[n*1 +: 1] = m_axi_hbm_wlast[c*1 +: 1]; - assign m_axi_hbm_int_wvalid[n*1 +: 1] = m_axi_hbm_wvalid[c*1 +: 1]; - assign m_axi_hbm_wready[c*1 +: 1] = m_axi_hbm_int_wready[n*1 +: 1]; - assign m_axi_hbm_bid[c*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = m_axi_hbm_int_bid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]; - assign m_axi_hbm_bresp[c*2 +: 2] = m_axi_hbm_int_bresp[n*2 +: 2]; - assign m_axi_hbm_bvalid[c*1 +: 1] = m_axi_hbm_int_bvalid[n*1 +: 1]; - assign m_axi_hbm_int_bready[n*1 +: 1] = m_axi_hbm_bready[c*1 +: 1]; - assign m_axi_hbm_int_arid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = m_axi_hbm_arid[c*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]; - assign m_axi_hbm_int_araddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH] = m_axi_hbm_araddr[c*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]; - assign m_axi_hbm_int_arlen[n*8 +: 8] = m_axi_hbm_arlen[c*8 +: 8]; - assign m_axi_hbm_int_arsize[n*3 +: 3] = m_axi_hbm_arsize[c*3 +: 3]; - assign m_axi_hbm_int_arburst[n*2 +: 2] = m_axi_hbm_arburst[c*2 +: 2]; - assign m_axi_hbm_int_arlock[n*1 +: 1] = m_axi_hbm_arlock[c*1 +: 1]; - assign m_axi_hbm_int_arcache[n*4 +: 4] = m_axi_hbm_arcache[c*4 +: 4]; - assign m_axi_hbm_int_arprot[n*3 +: 3] = m_axi_hbm_arprot[c*3 +: 3]; - assign m_axi_hbm_int_arqos[n*4 +: 4] = m_axi_hbm_arqos[c*4 +: 4]; - assign m_axi_hbm_int_arvalid[n*1 +: 1] = m_axi_hbm_arvalid[c*1 +: 1]; - assign m_axi_hbm_arready[c*1 +: 1] = m_axi_hbm_int_arready[n*1 +: 1]; - assign m_axi_hbm_rid[c*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = m_axi_hbm_int_rid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]; - assign m_axi_hbm_rdata[c*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH] = m_axi_hbm_int_rdata[n*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]; - assign m_axi_hbm_rresp[c*2 +: 2] = m_axi_hbm_int_rresp[n*2 +: 2]; - assign m_axi_hbm_rlast[c*1 +: 1] = m_axi_hbm_int_rlast[n*1 +: 1]; - assign m_axi_hbm_rvalid[c*1 +: 1] = m_axi_hbm_int_rvalid[n*1 +: 1]; - assign m_axi_hbm_int_rready[n*1 +: 1] = m_axi_hbm_rready[c*1 +: 1]; - - assign hbm_status[c] = 1'b1; - - end else begin - - assign m_axi_hbm_int_awid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = 0; - assign m_axi_hbm_int_awaddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH] = 0; - assign m_axi_hbm_int_awlen[n*8 +: 8] = 8'd0; - assign m_axi_hbm_int_awsize[n*3 +: 3] = 3'd0; - assign m_axi_hbm_int_awburst[n*2 +: 2] = 2'd0; - assign m_axi_hbm_int_awlock[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_awcache[n*4 +: 4] = 4'd0; - assign m_axi_hbm_int_awprot[n*3 +: 3] = 3'd0; - assign m_axi_hbm_int_awqos[n*4 +: 4] = 4'd0; - assign m_axi_hbm_int_awvalid[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_wdata[n*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH] = 0; - assign m_axi_hbm_int_wstrb[n*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH] = 0; - assign m_axi_hbm_int_wlast[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_wvalid[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_bready[n*1 +: 1] = 1'b1; - assign m_axi_hbm_int_arid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = 0; - assign m_axi_hbm_int_araddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH] = 0; - assign m_axi_hbm_int_arlen[n*8 +: 8] = 8'd0; - assign m_axi_hbm_int_arsize[n*3 +: 3] = 3'd0; - assign m_axi_hbm_int_arburst[n*2 +: 2] = 2'd0; - assign m_axi_hbm_int_arlock[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_arcache[n*4 +: 4] = 4'd0; - assign m_axi_hbm_int_arprot[n*3 +: 3] = 3'd0; - assign m_axi_hbm_int_arqos[n*4 +: 4] = 4'd0; - assign m_axi_hbm_int_arvalid[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_rready[n*1 +: 1] = 1'b1; - - end - -end - -end else begin - -assign hbm_clk = 0; -assign hbm_rst = 0; - -assign m_axi_hbm_awready = 0; -assign m_axi_hbm_wready = 0; -assign m_axi_hbm_bid = 0; -assign m_axi_hbm_bresp = 0; -assign m_axi_hbm_bvalid = 0; -assign m_axi_hbm_arready = 0; -assign m_axi_hbm_rid = 0; -assign m_axi_hbm_rdata = 0; -assign m_axi_hbm_rresp = 0; -assign m_axi_hbm_rlast = 0; -assign m_axi_hbm_rvalid = 0; - -assign hbm_status = 0; - -assign hbm_cattrip = 1'b0; - -assign hbm_temp_1 = 7'd0; -assign hbm_temp_2 = 7'd0; - -end - -endgenerate - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - .PORT_MASK(PORT_MASK), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .HBM_CH(HBM_CH), - .HBM_ENABLE(HBM_ENABLE), - .HBM_GROUP_SIZE(HBM_GROUP_SIZE), - .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), - .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), - .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), - .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), - .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_user_clk), - .rst_250mhz(pcie_user_reset), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - - /* - * GPIO - */ - .qsfp_led_act(qsfp_led_act), - //.qsfp_led_stat_g(qsfp_led_stat_g), - .qsfp_led_stat_y(qsfp_led_stat_y), - - /* - * PCIe - */ - .m_axis_rq_tdata(axis_rq_tdata), - .m_axis_rq_tkeep(axis_rq_tkeep), - .m_axis_rq_tlast(axis_rq_tlast), - .m_axis_rq_tready(axis_rq_tready), - .m_axis_rq_tuser(axis_rq_tuser), - .m_axis_rq_tvalid(axis_rq_tvalid), - - .s_axis_rc_tdata(axis_rc_tdata), - .s_axis_rc_tkeep(axis_rc_tkeep), - .s_axis_rc_tlast(axis_rc_tlast), - .s_axis_rc_tready(axis_rc_tready), - .s_axis_rc_tuser(axis_rc_tuser), - .s_axis_rc_tvalid(axis_rc_tvalid), - - .s_axis_cq_tdata(axis_cq_tdata), - .s_axis_cq_tkeep(axis_cq_tkeep), - .s_axis_cq_tlast(axis_cq_tlast), - .s_axis_cq_tready(axis_cq_tready), - .s_axis_cq_tuser(axis_cq_tuser), - .s_axis_cq_tvalid(axis_cq_tvalid), - - .m_axis_cc_tdata(axis_cc_tdata), - .m_axis_cc_tkeep(axis_cc_tkeep), - .m_axis_cc_tlast(axis_cc_tlast), - .m_axis_cc_tready(axis_cc_tready), - .m_axis_cc_tuser(axis_cc_tuser), - .m_axis_cc_tvalid(axis_cc_tvalid), - - .s_axis_rq_seq_num_0(pcie_rq_seq_num0_reg), - .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0_reg), - .s_axis_rq_seq_num_1(pcie_rq_seq_num1_reg), - .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1_reg), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_rcb_status(cfg_rcb_status), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * Ethernet: QSFP28 - */ - .qsfp_tx_clk(qsfp_tx_clk_int), - .qsfp_tx_rst(qsfp_tx_rst_int), - .qsfp_tx_axis_tdata(qsfp_tx_axis_tdata_int), - .qsfp_tx_axis_tkeep(qsfp_tx_axis_tkeep_int), - .qsfp_tx_axis_tvalid(qsfp_tx_axis_tvalid_int), - .qsfp_tx_axis_tready(qsfp_tx_axis_tready_int), - .qsfp_tx_axis_tlast(qsfp_tx_axis_tlast_int), - .qsfp_tx_axis_tuser(qsfp_tx_axis_tuser_int), - .qsfp_tx_ptp_time(qsfp_tx_ptp_time_int), - .qsfp_tx_ptp_ts(qsfp_tx_ptp_ts_int), - .qsfp_tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag_int), - .qsfp_tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid_int), - - .qsfp_tx_enable(qsfp_tx_enable), - .qsfp_tx_lfc_en(qsfp_tx_lfc_en), - .qsfp_tx_lfc_req(qsfp_tx_lfc_req), - .qsfp_tx_pfc_en(qsfp_tx_pfc_en), - .qsfp_tx_pfc_req(qsfp_tx_pfc_req), - - .qsfp_rx_clk(qsfp_rx_clk_int), - .qsfp_rx_rst(qsfp_rx_rst_int), - .qsfp_rx_axis_tdata(qsfp_rx_axis_tdata_int), - .qsfp_rx_axis_tkeep(qsfp_rx_axis_tkeep_int), - .qsfp_rx_axis_tvalid(qsfp_rx_axis_tvalid_int), - .qsfp_rx_axis_tlast(qsfp_rx_axis_tlast_int), - .qsfp_rx_axis_tuser(qsfp_rx_axis_tuser_int), - .qsfp_rx_ptp_time(qsfp_rx_ptp_time_int), - - .qsfp_rx_enable(qsfp_rx_enable), - .qsfp_rx_status(qsfp_rx_status), - .qsfp_rx_lfc_en(qsfp_rx_lfc_en), - .qsfp_rx_lfc_req(qsfp_rx_lfc_req), - .qsfp_rx_lfc_ack(qsfp_rx_lfc_ack), - .qsfp_rx_pfc_en(qsfp_rx_pfc_en), - .qsfp_rx_pfc_req(qsfp_rx_pfc_req), - .qsfp_rx_pfc_ack(qsfp_rx_pfc_ack), - - .qsfp_drp_clk(qsfp_drp_clk), - .qsfp_drp_rst(qsfp_drp_rst), - .qsfp_drp_addr(qsfp_drp_addr), - .qsfp_drp_di(qsfp_drp_di), - .qsfp_drp_en(qsfp_drp_en), - .qsfp_drp_we(qsfp_drp_we), - .qsfp_drp_do(qsfp_drp_do), - .qsfp_drp_rdy(qsfp_drp_rdy), - - /* - * HBM - */ - .hbm_clk(hbm_clk), - .hbm_rst(hbm_rst), - - .m_axi_hbm_awid(m_axi_hbm_awid), - .m_axi_hbm_awaddr(m_axi_hbm_awaddr), - .m_axi_hbm_awlen(m_axi_hbm_awlen), - .m_axi_hbm_awsize(m_axi_hbm_awsize), - .m_axi_hbm_awburst(m_axi_hbm_awburst), - .m_axi_hbm_awlock(m_axi_hbm_awlock), - .m_axi_hbm_awcache(m_axi_hbm_awcache), - .m_axi_hbm_awprot(m_axi_hbm_awprot), - .m_axi_hbm_awqos(m_axi_hbm_awqos), - .m_axi_hbm_awvalid(m_axi_hbm_awvalid), - .m_axi_hbm_awready(m_axi_hbm_awready), - .m_axi_hbm_wdata(m_axi_hbm_wdata), - .m_axi_hbm_wstrb(m_axi_hbm_wstrb), - .m_axi_hbm_wlast(m_axi_hbm_wlast), - .m_axi_hbm_wvalid(m_axi_hbm_wvalid), - .m_axi_hbm_wready(m_axi_hbm_wready), - .m_axi_hbm_bid(m_axi_hbm_bid), - .m_axi_hbm_bresp(m_axi_hbm_bresp), - .m_axi_hbm_bvalid(m_axi_hbm_bvalid), - .m_axi_hbm_bready(m_axi_hbm_bready), - .m_axi_hbm_arid(m_axi_hbm_arid), - .m_axi_hbm_araddr(m_axi_hbm_araddr), - .m_axi_hbm_arlen(m_axi_hbm_arlen), - .m_axi_hbm_arsize(m_axi_hbm_arsize), - .m_axi_hbm_arburst(m_axi_hbm_arburst), - .m_axi_hbm_arlock(m_axi_hbm_arlock), - .m_axi_hbm_arcache(m_axi_hbm_arcache), - .m_axi_hbm_arprot(m_axi_hbm_arprot), - .m_axi_hbm_arqos(m_axi_hbm_arqos), - .m_axi_hbm_arvalid(m_axi_hbm_arvalid), - .m_axi_hbm_arready(m_axi_hbm_arready), - .m_axi_hbm_rid(m_axi_hbm_rid), - .m_axi_hbm_rdata(m_axi_hbm_rdata), - .m_axi_hbm_rresp(m_axi_hbm_rresp), - .m_axi_hbm_rlast(m_axi_hbm_rlast), - .m_axi_hbm_rvalid(m_axi_hbm_rvalid), - .m_axi_hbm_rready(m_axi_hbm_rready), - - .hbm_status(hbm_status), - - /* - * QSPI flash - */ - .fpga_boot(fpga_boot), - .qspi_clk(qspi_clk_int), - .qspi_dq_i(qspi_dq_i_int), - .qspi_dq_o(qspi_dq_o_int), - .qspi_dq_oe(qspi_dq_oe_int), - .qspi_cs(qspi_cs_int), - - /* - * AXI-Lite interface to CMS - */ - .m_axil_cms_clk(axil_cms_clk), - .m_axil_cms_rst(axil_cms_rst), - .m_axil_cms_awaddr(axil_cms_awaddr), - .m_axil_cms_awprot(axil_cms_awprot), - .m_axil_cms_awvalid(axil_cms_awvalid), - .m_axil_cms_awready(axil_cms_awready), - .m_axil_cms_wdata(axil_cms_wdata), - .m_axil_cms_wstrb(axil_cms_wstrb), - .m_axil_cms_wvalid(axil_cms_wvalid), - .m_axil_cms_wready(axil_cms_wready), - .m_axil_cms_bresp(axil_cms_bresp), - .m_axil_cms_bvalid(axil_cms_bvalid), - .m_axil_cms_bready(axil_cms_bready), - .m_axil_cms_araddr(axil_cms_araddr), - .m_axil_cms_arprot(axil_cms_arprot), - .m_axil_cms_arvalid(axil_cms_arvalid), - .m_axil_cms_arready(axil_cms_arready), - .m_axil_cms_rdata(axil_cms_rdata), - .m_axil_cms_rresp(axil_cms_rresp), - .m_axil_cms_rvalid(axil_cms_rvalid), - .m_axil_cms_rready(axil_cms_rready) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v deleted file mode 100644 index 46846e17c..000000000 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ /dev/null @@ -1,1339 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B77093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_9032, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 1, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 1024, - parameter PTP_CLK_PERIOD_NS_DENOM = 165, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 1, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 1, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 16, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 131072, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 131072, - parameter RX_RAM_SIZE = 131072, - - // RAM configuration - parameter HBM_CH = 32, - parameter HBM_ENABLE = 0, - parameter HBM_GROUP_SIZE = HBM_CH, - parameter AXI_HBM_DATA_WIDTH = 256, - parameter AXI_HBM_ADDR_WIDTH = 33, - parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), - parameter AXI_HBM_ID_WIDTH = 6, - parameter AXI_HBM_MAX_BURST_LEN = 16, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, - parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, - parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, - parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, - parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, - parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 256, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_DATA_WIDTH = 512, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - output wire qsfp_led_act, - output wire qsfp_led_stat_g, - output wire qsfp_led_stat_y, - - /* - * PCIe - */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, - - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, - - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, - - input wire [1:0] pcie_tfc_nph_av, - input wire [1:0] pcie_tfc_npd_av, - - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, - - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, - - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - input wire [3:0] cfg_interrupt_msix_enable, - input wire [3:0] cfg_interrupt_msix_mask, - input wire [251:0] cfg_interrupt_msix_vf_enable, - input wire [251:0] cfg_interrupt_msix_vf_mask, - output wire [63:0] cfg_interrupt_msix_address, - output wire [31:0] cfg_interrupt_msix_data, - output wire cfg_interrupt_msix_int, - output wire [1:0] cfg_interrupt_msix_vec_pending, - input wire cfg_interrupt_msix_vec_pending_status, - input wire cfg_interrupt_msix_sent, - input wire cfg_interrupt_msix_fail, - output wire [7:0] cfg_interrupt_msi_function_number, - - output wire status_error_cor, - output wire status_error_uncor, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp_tx_clk, - input wire qsfp_tx_rst, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp_tx_axis_tkeep, - output wire qsfp_tx_axis_tvalid, - input wire qsfp_tx_axis_tready, - output wire qsfp_tx_axis_tlast, - output wire [16+1-1:0] qsfp_tx_axis_tuser, - - output wire [79:0] qsfp_tx_ptp_time, - input wire [79:0] qsfp_tx_ptp_ts, - input wire [15:0] qsfp_tx_ptp_ts_tag, - input wire qsfp_tx_ptp_ts_valid, - - output wire qsfp_tx_enable, - output wire qsfp_tx_lfc_en, - output wire qsfp_tx_lfc_req, - output wire [7:0] qsfp_tx_pfc_en, - output wire [7:0] qsfp_tx_pfc_req, - - input wire qsfp_rx_clk, - input wire qsfp_rx_rst, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp_rx_axis_tkeep, - input wire qsfp_rx_axis_tvalid, - input wire qsfp_rx_axis_tlast, - input wire [80+1-1:0] qsfp_rx_axis_tuser, - - output wire [79:0] qsfp_rx_ptp_time, - - output wire qsfp_rx_enable, - input wire qsfp_rx_status, - output wire qsfp_rx_lfc_en, - input wire qsfp_rx_lfc_req, - output wire qsfp_rx_lfc_ack, - output wire [7:0] qsfp_rx_pfc_en, - input wire [7:0] qsfp_rx_pfc_req, - output wire [7:0] qsfp_rx_pfc_ack, - - input wire qsfp_drp_clk, - input wire qsfp_drp_rst, - output wire [23:0] qsfp_drp_addr, - output wire [15:0] qsfp_drp_di, - output wire qsfp_drp_en, - output wire qsfp_drp_we, - input wire [15:0] qsfp_drp_do, - input wire qsfp_drp_rdy, - - /* - * HBM - */ - input wire [HBM_CH-1:0] hbm_clk, - input wire [HBM_CH-1:0] hbm_rst, - - output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, - output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, - output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, - output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, - output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, - output wire [HBM_CH-1:0] m_axi_hbm_awlock, - output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, - output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, - output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, - output wire [HBM_CH-1:0] m_axi_hbm_awvalid, - input wire [HBM_CH-1:0] m_axi_hbm_awready, - output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, - output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, - output wire [HBM_CH-1:0] m_axi_hbm_wlast, - output wire [HBM_CH-1:0] m_axi_hbm_wvalid, - input wire [HBM_CH-1:0] m_axi_hbm_wready, - input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, - input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, - input wire [HBM_CH-1:0] m_axi_hbm_bvalid, - output wire [HBM_CH-1:0] m_axi_hbm_bready, - output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, - output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, - output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, - output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, - output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, - output wire [HBM_CH-1:0] m_axi_hbm_arlock, - output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, - output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, - output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, - output wire [HBM_CH-1:0] m_axi_hbm_arvalid, - input wire [HBM_CH-1:0] m_axi_hbm_arready, - input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, - input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, - input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, - input wire [HBM_CH-1:0] m_axi_hbm_rlast, - input wire [HBM_CH-1:0] m_axi_hbm_rvalid, - output wire [HBM_CH-1:0] m_axi_hbm_rready, - - input wire [HBM_CH-1:0] hbm_status, - - /* - * QSPI flash - */ - output wire fpga_boot, - output wire qspi_clk, - input wire [3:0] qspi_dq_i, - output wire [3:0] qspi_dq_o, - output wire [3:0] qspi_dq_oe, - output wire qspi_cs, - - /* - * AXI-Lite interface to CMS - */ - output wire m_axil_cms_clk, - output wire m_axil_cms_rst, - output wire [17:0] m_axil_cms_awaddr, - output wire [2:0] m_axil_cms_awprot, - output wire m_axil_cms_awvalid, - input wire m_axil_cms_awready, - output wire [31:0] m_axil_cms_wdata, - output wire [3:0] m_axil_cms_wstrb, - output wire m_axil_cms_wvalid, - input wire m_axil_cms_wready, - input wire [1:0] m_axil_cms_bresp, - input wire m_axil_cms_bvalid, - output wire m_axil_cms_bready, - output wire [17:0] m_axil_cms_araddr, - output wire [2:0] m_axil_cms_arprot, - output wire m_axil_cms_arvalid, - input wire m_axil_cms_arready, - input wire [31:0] m_axil_cms_rdata, - input wire [1:0] m_axil_cms_rresp, - input wire m_axil_cms_rvalid, - output wire m_axil_cms_rready -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -localparam RB_DRP_QSFP_BASE = RB_BASE_ADDR + 16'h40; - -initial begin - if (PORT_COUNT > 1) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// PTP -wire ptp_td_sd; -wire ptp_pps; -wire ptp_pps_str; -wire ptp_sync_locked; -wire [63:0] ptp_sync_ts_rel; -wire ptp_sync_ts_rel_step; -wire [95:0] ptp_sync_ts_tod; -wire ptp_sync_ts_tod_step; -wire ptp_sync_pps; -wire ptp_sync_pps_str; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -wire qsfp_drp_reg_wr_wait; -wire qsfp_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_drp_reg_rd_data; -wire qsfp_drp_reg_rd_wait; -wire qsfp_drp_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg fpga_boot_reg = 1'b0; - -reg qspi_clk_reg = 1'b0; -reg qspi_cs_reg = 1'b1; -reg [3:0] qspi_dq_o_reg = 4'd0; -reg [3:0] qspi_dq_oe_reg = 4'd0; - -reg [17:0] m_axil_cms_addr_reg = 18'd0; -reg m_axil_cms_awvalid_reg = 1'b0; -reg [31:0] m_axil_cms_wdata_reg = 32'd0; -reg [3:0] m_axil_cms_wstrb_reg = 4'b0000; -reg m_axil_cms_wvalid_reg = 1'b0; -reg m_axil_cms_arvalid_reg = 1'b0; - -assign ctrl_reg_wr_wait = qsfp_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_drp_reg_rd_ack; - -assign fpga_boot = fpga_boot_reg; - -assign qspi_clk = qspi_clk_reg; -assign qspi_cs = qspi_cs_reg; -assign qspi_dq_o = qspi_dq_o_reg; -assign qspi_dq_oe = qspi_dq_oe_reg; - -assign m_axil_cms_clk = clk_250mhz; -assign m_axil_cms_rst = rst_250mhz; -assign m_axil_cms_awaddr = m_axil_cms_addr_reg; -assign m_axil_cms_awprot = 3'b000; -assign m_axil_cms_awvalid = m_axil_cms_awvalid_reg; -assign m_axil_cms_wdata = m_axil_cms_wdata_reg; -assign m_axil_cms_wstrb = m_axil_cms_wstrb_reg; -assign m_axil_cms_wvalid = m_axil_cms_wvalid_reg; -assign m_axil_cms_bready = 1'b1; -assign m_axil_cms_araddr = m_axil_cms_addr_reg; -assign m_axil_cms_arprot = 3'b000; -assign m_axil_cms_arvalid = m_axil_cms_arvalid_reg; -assign m_axil_cms_rready = 1'b1; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - m_axil_cms_awvalid_reg <= m_axil_cms_awvalid_reg && !m_axil_cms_awready; - m_axil_cms_wvalid_reg <= m_axil_cms_wvalid_reg && !m_axil_cms_wready; - m_axil_cms_arvalid_reg <= m_axil_cms_arvalid_reg && !m_axil_cms_arready; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // FW ID - 8'h0C: begin - // FW ID: FPGA JTAG ID - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - // QSPI flash - RBB+8'h0C: begin - // SPI flash ctrl: format - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - RBB+8'h10: begin - // SPI flash ctrl: control 0 - if (ctrl_reg_wr_strb[0]) begin - qspi_dq_o_reg <= ctrl_reg_wr_data[3:0]; - end - if (ctrl_reg_wr_strb[1]) begin - qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8]; - end - if (ctrl_reg_wr_strb[2]) begin - qspi_clk_reg <= ctrl_reg_wr_data[16]; - qspi_cs_reg <= ctrl_reg_wr_data[17]; - end - end - // Alveo BMC - RBB+8'h2C: begin - // BMC ctrl: Addr - if (!m_axil_cms_arvalid && !m_axil_cms_awvalid) begin - m_axil_cms_addr_reg <= ctrl_reg_wr_data; - m_axil_cms_arvalid_reg <= 1'b1; - end - end - RBB+8'h30: begin - // BMC ctrl: Data - if (!m_axil_cms_wvalid) begin - m_axil_cms_awvalid_reg <= 1'b1; - m_axil_cms_wdata_reg <= ctrl_reg_wr_data; - m_axil_cms_wstrb_reg <= ctrl_reg_wr_strb; - m_axil_cms_wvalid_reg <= 1'b1; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // QSPI flash - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // SPI flash ctrl: Next header - RBB+8'h0C: begin - // SPI flash ctrl: format - ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) - ctrl_reg_rd_data_reg[7:4] <= 1; // default segment - ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment - ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default) - end - RBB+8'h10: begin - // SPI flash ctrl: control 0 - ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i; - ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe; - ctrl_reg_rd_data_reg[16] <= qspi_clk; - ctrl_reg_rd_data_reg[17] <= qspi_cs; - end - // Alveo BMC - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C140; // BMC ctrl: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_BASE; // BMC ctrl: Next header - RBB+8'h2C: ctrl_reg_rd_data_reg <= m_axil_cms_addr_reg; // BMC ctrl: Addr - RBB+8'h30: ctrl_reg_rd_data_reg <= m_axil_cms_rdata; // BMC ctrl: Data - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - fpga_boot_reg <= 1'b0; - - qspi_clk_reg <= 1'b0; - qspi_cs_reg <= 1'b1; - qspi_dq_o_reg <= 4'd0; - qspi_dq_oe_reg <= 4'd0; - - m_axil_cms_awvalid_reg <= 1'b0; - m_axil_cms_wvalid_reg <= 1'b0; - m_axil_cms_arvalid_reg <= 1'b0; - end -end - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP_BASE), - .RB_NEXT_PTR(0) -) -qsfp_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp_drp_reg_wr_wait), - .reg_wr_ack(qsfp_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp_drp_reg_rd_data), - .reg_rd_wait(qsfp_drp_reg_rd_wait), - .reg_rd_ack(qsfp_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp_drp_clk), - .drp_rst(qsfp_drp_rst), - .drp_addr(qsfp_drp_addr), - .drp_di(qsfp_drp_di), - .drp_en(qsfp_drp_en), - .drp_we(qsfp_drp_we), - .drp_do(qsfp_drp_do), - .drp_rdy(qsfp_drp_rdy) -); - -assign qsfp_led_act = ptp_pps_str; -assign qsfp_led_stat_g = 1'b0; -assign qsfp_led_stat_y = 1'b0; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT-1:0] eth_tx_ptp_clk; -wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT-1:0] eth_rx_ptp_clk; -wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -wire [PTP_TS_WIDTH-1:0] qsfp_tx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp_rx_ptp_time_int; - -assign qsfp_tx_ptp_time = qsfp_tx_ptp_time_int >> 16; -assign qsfp_rx_ptp_time = qsfp_rx_ptp_time_int >> 16; - -mqnic_port_map_mac_axis #( - .MAC_COUNT(1), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(1), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(TX_TAG_WIDTH), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -mqnic_port_map_mac_axis_inst ( - // towards MAC - .mac_tx_clk({qsfp_tx_clk}), - .mac_tx_rst({qsfp_tx_rst}), - - .mac_tx_ptp_clk(1'b0), - .mac_tx_ptp_rst(1'b0), - .mac_tx_ptp_ts_96({qsfp_tx_ptp_time_int}), - .mac_tx_ptp_ts_step(), - - .m_axis_mac_tx_tdata({qsfp_tx_axis_tdata}), - .m_axis_mac_tx_tkeep({qsfp_tx_axis_tkeep}), - .m_axis_mac_tx_tvalid({qsfp_tx_axis_tvalid}), - .m_axis_mac_tx_tready({qsfp_tx_axis_tready}), - .m_axis_mac_tx_tlast({qsfp_tx_axis_tlast}), - .m_axis_mac_tx_tuser({qsfp_tx_axis_tuser}), - - .s_axis_mac_tx_ptp_ts({{qsfp_tx_ptp_ts, 16'd0}}), - .s_axis_mac_tx_ptp_ts_tag({qsfp_tx_ptp_ts_tag}), - .s_axis_mac_tx_ptp_ts_valid({qsfp_tx_ptp_ts_valid}), - .s_axis_mac_tx_ptp_ts_ready(), - - .mac_tx_enable({qsfp_tx_enable}), - .mac_tx_status(1'b1), - .mac_tx_lfc_en({qsfp_tx_lfc_en}), - .mac_tx_lfc_req({qsfp_tx_lfc_req}), - .mac_tx_pfc_en({qsfp_tx_pfc_en}), - .mac_tx_pfc_req({qsfp_tx_pfc_req}), - - .mac_rx_clk({qsfp_rx_clk}), - .mac_rx_rst({qsfp_rx_rst}), - - .mac_rx_ptp_clk(1'b0), - .mac_rx_ptp_rst(1'b0), - .mac_rx_ptp_ts_96({qsfp_rx_ptp_time_int}), - .mac_rx_ptp_ts_step(), - - .s_axis_mac_rx_tdata({qsfp_rx_axis_tdata}), - .s_axis_mac_rx_tkeep({qsfp_rx_axis_tkeep}), - .s_axis_mac_rx_tvalid({qsfp_rx_axis_tvalid}), - .s_axis_mac_rx_tready(), - .s_axis_mac_rx_tlast({qsfp_rx_axis_tlast}), - .s_axis_mac_rx_tuser({{qsfp_rx_axis_tuser[80:1], 16'd0, qsfp_rx_axis_tuser[0]}}), - - .mac_rx_enable({qsfp_rx_enable}), - .mac_rx_status({qsfp_rx_status}), - .mac_rx_lfc_en({qsfp_rx_lfc_en}), - .mac_rx_lfc_req({qsfp_rx_lfc_req}), - .mac_rx_lfc_ack({qsfp_rx_lfc_ack}), - .mac_rx_pfc_en({qsfp_rx_pfc_en}), - .mac_rx_pfc_req({qsfp_rx_pfc_req}), - .mac_rx_pfc_ack({qsfp_rx_pfc_ack}), - - // towards datapath - .tx_clk(eth_tx_clk), - .tx_rst(eth_tx_rst), - - .tx_ptp_clk(eth_tx_ptp_clk), - .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_tod), - .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), - - .s_axis_tx_tdata(axis_eth_tx_tdata), - .s_axis_tx_tkeep(axis_eth_tx_tkeep), - .s_axis_tx_tvalid(axis_eth_tx_tvalid), - .s_axis_tx_tready(axis_eth_tx_tready), - .s_axis_tx_tlast(axis_eth_tx_tlast), - .s_axis_tx_tuser(axis_eth_tx_tuser), - - .m_axis_tx_ptp_ts(axis_eth_tx_ptp_ts), - .m_axis_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag), - .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), - .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), - - .tx_enable(eth_tx_enable), - .tx_status(eth_tx_status), - .tx_lfc_en(eth_tx_lfc_en), - .tx_lfc_req(eth_tx_lfc_req), - .tx_pfc_en(eth_tx_pfc_en), - .tx_pfc_req(eth_tx_pfc_req), - - .rx_clk(eth_rx_clk), - .rx_rst(eth_rx_rst), - - .rx_ptp_clk(eth_rx_ptp_clk), - .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_tod), - .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), - - .m_axis_rx_tdata(axis_eth_rx_tdata), - .m_axis_rx_tkeep(axis_eth_rx_tkeep), - .m_axis_rx_tvalid(axis_eth_rx_tvalid), - .m_axis_rx_tready(axis_eth_rx_tready), - .m_axis_rx_tlast(axis_eth_rx_tlast), - .m_axis_rx_tuser(axis_eth_rx_tuser), - - .rx_enable(eth_rx_enable), - .rx_status(eth_rx_status), - .rx_lfc_en(eth_rx_lfc_en), - .rx_lfc_req(eth_rx_lfc_req), - .rx_lfc_ack(eth_rx_lfc_ack), - .rx_pfc_en(eth_rx_pfc_en), - .rx_pfc_req(eth_rx_pfc_req), - .rx_pfc_ack(eth_rx_pfc_ack) -); - -mqnic_core_pcie_us #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(0), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_ENABLE(0), - .HBM_CH(HBM_CH), - .HBM_ENABLE(HBM_ENABLE), - .HBM_GROUP_SIZE(HBM_GROUP_SIZE), - .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), - .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), - .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), - .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), - .AXI_HBM_AWUSER_ENABLE(0), - .AXI_HBM_WUSER_ENABLE(0), - .AXI_HBM_BUSER_ENABLE(0), - .AXI_HBM_ARUSER_ENABLE(0), - .AXI_HBM_RUSER_ENABLE(0), - .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), - .AXI_HBM_NARROW_BURST(0), - .AXI_HBM_FIXED_BURST(0), - .AXI_HBM_WRAP_BURST(1), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(0), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * AXI input (RC) - */ - .s_axis_rc_tdata(s_axis_rc_tdata), - .s_axis_rc_tkeep(s_axis_rc_tkeep), - .s_axis_rc_tvalid(s_axis_rc_tvalid), - .s_axis_rc_tready(s_axis_rc_tready), - .s_axis_rc_tlast(s_axis_rc_tlast), - .s_axis_rc_tuser(s_axis_rc_tuser), - - /* - * AXI output (RQ) - */ - .m_axis_rq_tdata(m_axis_rq_tdata), - .m_axis_rq_tkeep(m_axis_rq_tkeep), - .m_axis_rq_tvalid(m_axis_rq_tvalid), - .m_axis_rq_tready(m_axis_rq_tready), - .m_axis_rq_tlast(m_axis_rq_tlast), - .m_axis_rq_tuser(m_axis_rq_tuser), - - /* - * AXI input (CQ) - */ - .s_axis_cq_tdata(s_axis_cq_tdata), - .s_axis_cq_tkeep(s_axis_cq_tkeep), - .s_axis_cq_tvalid(s_axis_cq_tvalid), - .s_axis_cq_tready(s_axis_cq_tready), - .s_axis_cq_tlast(s_axis_cq_tlast), - .s_axis_cq_tuser(s_axis_cq_tuser), - - /* - * AXI output (CC) - */ - .m_axis_cc_tdata(m_axis_cc_tdata), - .m_axis_cc_tkeep(m_axis_cc_tkeep), - .m_axis_cc_tvalid(m_axis_cc_tvalid), - .m_axis_cc_tready(m_axis_cc_tready), - .m_axis_cc_tlast(m_axis_cc_tlast), - .m_axis_cc_tuser(m_axis_cc_tuser), - - /* - * Transmit sequence number input - */ - .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), - .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), - .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), - .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), - - /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration inputs - */ - .cfg_max_read_req(cfg_max_read_req), - .cfg_max_payload(cfg_max_payload), - .cfg_rcb_status(cfg_rcb_status), - - /* - * Configuration interface - */ - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - /* - * Interrupt interface - */ - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - /* - * PCIe error outputs - */ - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(), - .m_axil_csr_awprot(), - .m_axil_csr_awvalid(), - .m_axil_csr_awready(1), - .m_axil_csr_wdata(), - .m_axil_csr_wstrb(), - .m_axil_csr_wvalid(), - .m_axil_csr_wready(1), - .m_axil_csr_bresp(0), - .m_axil_csr_bvalid(0), - .m_axil_csr_bready(), - .m_axil_csr_araddr(), - .m_axil_csr_arprot(), - .m_axil_csr_arvalid(), - .m_axil_csr_arready(1), - .m_axil_csr_rdata(0), - .m_axil_csr_rresp(0), - .m_axil_csr_rvalid(0), - .m_axil_csr_rready(), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_td_sd(ptp_td_sd), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_sync_locked(ptp_sync_locked), - .ptp_sync_ts_rel(ptp_sync_ts_rel), - .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), - .ptp_sync_ts_tod(ptp_sync_ts_tod), - .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_pps_str(ptp_sync_pps_str), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(eth_tx_ptp_clk), - .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), - .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(eth_rx_ptp_clk), - .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), - .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(0), - .ddr_rst(0), - - .m_axi_ddr_awid(), - .m_axi_ddr_awaddr(), - .m_axi_ddr_awlen(), - .m_axi_ddr_awsize(), - .m_axi_ddr_awburst(), - .m_axi_ddr_awlock(), - .m_axi_ddr_awcache(), - .m_axi_ddr_awprot(), - .m_axi_ddr_awqos(), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(), - .m_axi_ddr_awready(0), - .m_axi_ddr_wdata(), - .m_axi_ddr_wstrb(), - .m_axi_ddr_wlast(), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(), - .m_axi_ddr_wready(0), - .m_axi_ddr_bid(0), - .m_axi_ddr_bresp(0), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(0), - .m_axi_ddr_bready(), - .m_axi_ddr_arid(), - .m_axi_ddr_araddr(), - .m_axi_ddr_arlen(), - .m_axi_ddr_arsize(), - .m_axi_ddr_arburst(), - .m_axi_ddr_arlock(), - .m_axi_ddr_arcache(), - .m_axi_ddr_arprot(), - .m_axi_ddr_arqos(), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(), - .m_axi_ddr_arready(0), - .m_axi_ddr_rid(0), - .m_axi_ddr_rdata(0), - .m_axi_ddr_rresp(0), - .m_axi_ddr_rlast(0), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(0), - .m_axi_ddr_rready(), - - .ddr_status(0), - - /* - * HBM - */ - .hbm_clk(hbm_clk), - .hbm_rst(hbm_rst), - - .m_axi_hbm_awid(m_axi_hbm_awid), - .m_axi_hbm_awaddr(m_axi_hbm_awaddr), - .m_axi_hbm_awlen(m_axi_hbm_awlen), - .m_axi_hbm_awsize(m_axi_hbm_awsize), - .m_axi_hbm_awburst(m_axi_hbm_awburst), - .m_axi_hbm_awlock(m_axi_hbm_awlock), - .m_axi_hbm_awcache(m_axi_hbm_awcache), - .m_axi_hbm_awprot(m_axi_hbm_awprot), - .m_axi_hbm_awqos(m_axi_hbm_awqos), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(m_axi_hbm_awvalid), - .m_axi_hbm_awready(m_axi_hbm_awready), - .m_axi_hbm_wdata(m_axi_hbm_wdata), - .m_axi_hbm_wstrb(m_axi_hbm_wstrb), - .m_axi_hbm_wlast(m_axi_hbm_wlast), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(m_axi_hbm_wvalid), - .m_axi_hbm_wready(m_axi_hbm_wready), - .m_axi_hbm_bid(m_axi_hbm_bid), - .m_axi_hbm_bresp(m_axi_hbm_bresp), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(m_axi_hbm_bvalid), - .m_axi_hbm_bready(m_axi_hbm_bready), - .m_axi_hbm_arid(m_axi_hbm_arid), - .m_axi_hbm_araddr(m_axi_hbm_araddr), - .m_axi_hbm_arlen(m_axi_hbm_arlen), - .m_axi_hbm_arsize(m_axi_hbm_arsize), - .m_axi_hbm_arburst(m_axi_hbm_arburst), - .m_axi_hbm_arlock(m_axi_hbm_arlock), - .m_axi_hbm_arcache(m_axi_hbm_arcache), - .m_axi_hbm_arprot(m_axi_hbm_arprot), - .m_axi_hbm_arqos(m_axi_hbm_arqos), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(m_axi_hbm_arvalid), - .m_axi_hbm_arready(m_axi_hbm_arready), - .m_axi_hbm_rid(m_axi_hbm_rid), - .m_axi_hbm_rdata(m_axi_hbm_rdata), - .m_axi_hbm_rresp(m_axi_hbm_rresp), - .m_axi_hbm_rlast(m_axi_hbm_rlast), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(m_axi_hbm_rvalid), - .m_axi_hbm_rready(m_axi_hbm_rready), - - .hbm_status(hbm_status), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/sync_signal.v b/fpga/mqnic/AU50/fpga_100g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/AU50/fpga_100g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile deleted file mode 100644 index ee2f891f3..000000000 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ /dev/null @@ -1,250 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rb_drp.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 1 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 -export PARAM_PTP_CLOCK_PIPELINE := 1 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 1 -export PARAM_PTP_PEROUT_ENABLE := 0 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 6 -export PARAM_TX_QUEUE_INDEX_WIDTH := 13 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 131072 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 131072 -export PARAM_RX_RAM_SIZE := 131072 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_AXIS_PCIE_DATA_WIDTH := 512 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/mqnic.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 453dc9a82..000000000 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,766 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus, AxiLiteBus, AxiLiteRam -from cocotbext.eth import EthMac -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = UltraScalePlusPcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=16, - user_clk_frequency=250e6, - alignment="dword", - cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, - cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, - rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, - pf_count=1, - max_payload_size=1024, - enable_client_tag=True, - enable_extended_tag=True, - enable_parity=False, - enable_rx_msg_interface=False, - enable_sriov=False, - enable_extended_configuration=False, - - pf0_msi_enable=False, - pf0_msi_count=32, - pf1_msi_enable=False, - pf1_msi_count=1, - pf2_msi_enable=False, - pf2_msi_count=1, - pf3_msi_enable=False, - pf3_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - pf2_msix_enable=False, - pf2_msix_table_size=0, - pf2_msix_table_bir=0, - pf2_msix_table_offset=0x00000000, - pf2_msix_pba_bir=0, - pf2_msix_pba_offset=0x00000000, - pf3_msix_enable=False, - pf3_msix_table_size=0, - pf3_msix_table_bir=0, - pf3_msix_table_offset=0x00000000, - pf3_msix_pba_bir=0, - pf3_msix_pba_offset=0x00000000, - - # signals - # Clock and Reset Interface - user_clk=dut.clk_250mhz, - user_reset=dut.rst_250mhz, - # user_lnk_up - # sys_clk - # sys_clk_gt - # sys_reset - # phy_rdy_out - - # Requester reQuest Interface - rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), - pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 - # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 - - # Requester Completion Interface - rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), - - # Completer reQuest Interface - cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - # pcie_cq_np_req - # pcie_cq_np_req_count - - # Completer Completion Interface - cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), - - # Transmit Flow Control Interface - # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, - # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, - - # Configuration Management Interface - cfg_mgmt_addr=dut.cfg_mgmt_addr, - cfg_mgmt_function_number=dut.cfg_mgmt_function_number, - cfg_mgmt_write=dut.cfg_mgmt_write, - cfg_mgmt_write_data=dut.cfg_mgmt_write_data, - cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, - cfg_mgmt_read=dut.cfg_mgmt_read, - cfg_mgmt_read_data=dut.cfg_mgmt_read_data, - cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, - # cfg_mgmt_debug_access - - # Configuration Status Interface - # cfg_phy_link_down - # cfg_phy_link_status - # cfg_negotiated_width - # cfg_current_speed - cfg_max_payload=dut.cfg_max_payload, - cfg_max_read_req=dut.cfg_max_read_req, - # cfg_function_status - # cfg_vf_status - # cfg_function_power_state - # cfg_vf_power_state - # cfg_link_power_state - # cfg_err_cor_out - # cfg_err_nonfatal_out - # cfg_err_fatal_out - # cfg_local_error_out - # cfg_local_error_valid - # cfg_rx_pm_state - # cfg_tx_pm_state - # cfg_ltssm_state - cfg_rcb_status=dut.cfg_rcb_status, - # cfg_obff_enable - # cfg_pl_status_change - # cfg_tph_requester_enable - # cfg_tph_st_mode - # cfg_vf_tph_requester_enable - # cfg_vf_tph_st_mode - - # Configuration Received Message Interface - # cfg_msg_received - # cfg_msg_received_data - # cfg_msg_received_type - - # Configuration Transmit Message Interface - # cfg_msg_transmit - # cfg_msg_transmit_type - # cfg_msg_transmit_data - # cfg_msg_transmit_done - - # Configuration Flow Control Interface - cfg_fc_ph=dut.cfg_fc_ph, - cfg_fc_pd=dut.cfg_fc_pd, - cfg_fc_nph=dut.cfg_fc_nph, - cfg_fc_npd=dut.cfg_fc_npd, - cfg_fc_cplh=dut.cfg_fc_cplh, - cfg_fc_cpld=dut.cfg_fc_cpld, - cfg_fc_sel=dut.cfg_fc_sel, - - # Configuration Control Interface - # cfg_hot_reset_in - # cfg_hot_reset_out - # cfg_config_space_enable - # cfg_dsn - # cfg_bus_number - # cfg_ds_port_number - # cfg_ds_bus_number - # cfg_ds_device_number - # cfg_ds_function_number - # cfg_power_state_change_ack - # cfg_power_state_change_interrupt - cfg_err_cor_in=dut.status_error_cor, - cfg_err_uncor_in=dut.status_error_uncor, - # cfg_flr_in_process - # cfg_flr_done - # cfg_vf_flr_in_process - # cfg_vf_flr_func_num - # cfg_vf_flr_done - # cfg_pm_aspm_l1_entry_reject - # cfg_pm_aspm_tx_l0s_entry_disable - # cfg_req_pm_transition_l23_ready - # cfg_link_training_enable - - # Configuration Interrupt Controller Interface - # cfg_interrupt_int - # cfg_interrupt_sent - # cfg_interrupt_pending - # cfg_interrupt_msi_enable - # cfg_interrupt_msi_mmenable - # cfg_interrupt_msi_mask_update - # cfg_interrupt_msi_data - # cfg_interrupt_msi_select - # cfg_interrupt_msi_int - # cfg_interrupt_msi_pending_status - # cfg_interrupt_msi_pending_status_data_enable - # cfg_interrupt_msi_pending_status_function_num - # cfg_interrupt_msi_sent - # cfg_interrupt_msi_fail - cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, - cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, - cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, - cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, - cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, - cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, - cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, - cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, - cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, - cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, - cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, - # cfg_interrupt_msi_attr - # cfg_interrupt_msi_tph_present - # cfg_interrupt_msi_tph_type - # cfg_interrupt_msi_tph_st_tag - cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, - - # Configuration Extend Interface - # cfg_ext_read_received - # cfg_ext_write_received - # cfg_ext_register_number - # cfg_ext_function_number - # cfg_ext_write_data - # cfg_ext_write_byte_enable - # cfg_ext_read_data - # cfg_ext_read_data_valid - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) - - # Ethernet - cocotb.start_soon(Clock(dut.qsfp_rx_clk, 3.102, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp_tx_clk, 3.102, units="ns").start()) - - self.qsfp_mac = EthMac( - tx_clk=dut.qsfp_tx_clk, - tx_rst=dut.qsfp_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp_tx_axis"), - tx_ptp_time=dut.qsfp_tx_ptp_time, - tx_ptp_ts=dut.qsfp_tx_ptp_ts, - tx_ptp_ts_tag=dut.qsfp_tx_ptp_ts_tag, - tx_ptp_ts_valid=dut.qsfp_tx_ptp_ts_valid, - rx_clk=dut.qsfp_rx_clk, - rx_rst=dut.qsfp_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp_rx_axis"), - rx_ptp_time=dut.qsfp_rx_ptp_time, - ifg=12, speed=100e9 - ) - - dut.qsfp_rx_status.setimmediatevalue(1) - dut.qsfp_rx_lfc_req.setimmediatevalue(1) - dut.qsfp_rx_pfc_req.setimmediatevalue(1) - - cocotb.start_soon(Clock(dut.qsfp_drp_clk, 8, units="ns").start()) - dut.qsfp_drp_rst.setimmediatevalue(0) - dut.qsfp_drp_do.setimmediatevalue(0) - dut.qsfp_drp_rdy.setimmediatevalue(0) - - dut.qspi_dq_i.setimmediatevalue(0) - - self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - self.dut.qsfp_rx_rst.setimmediatevalue(0) - self.dut.qsfp_tx_rst.setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - self.dut.qsfp_rx_rst.setimmediatevalue(1) - self.dut.qsfp_tx_rst.setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - self.dut.qsfp_rx_rst.setimmediatevalue(0) - self.dut.qsfp_tx_rst.setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - if not self.qsfp_mac.tx.empty(): - await self.qsfp_mac.rx.send(await self.qsfp_mac.tx.recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfp_mac.tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_mac.rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfp_mac.tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_mac.rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Jumbo frames") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(9014)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "rb_drp.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_td_phc.v"), - os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 1 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 - parameters['PTP_CLOCK_PIPELINE'] = 1 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 1 - parameters['PTP_PEROUT_ENABLE'] = 0 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 131072 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 131072 - parameters['RX_RAM_SIZE'] = 131072 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['AXIS_PCIE_DATA_WIDTH'] = 512 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/mqnic/AU50/fpga_25g/Makefile b/fpga/mqnic/AU50/fpga_25g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/mqnic/AU50/fpga_25g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/AU50/fpga_25g/README.md b/fpga/mqnic/AU50/fpga_25g/README.md deleted file mode 100644 index 279b2d198..000000000 --- a/fpga/mqnic/AU50/fpga_25g/README.md +++ /dev/null @@ -1,23 +0,0 @@ -# Corundum mqnic for Alveo U50 - -## Introduction - -This design targets the Xilinx Alveo U50 FPGA board. - -* FPGA: xcu50-fsvh2104-2-e -* PHY: 10G BASE-R PHY IP core and internal GTY transceivers -* RAM: 8GB HBM2 - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/AU50/fpga_25g/app b/fpga/mqnic/AU50/fpga_25g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/AU50/fpga_25g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/AU50/fpga_25g/boot.xdc b/fpga/mqnic/AU50/fpga_25g/boot.xdc deleted file mode 100644 index 5fb323e94..000000000 --- a/fpga/mqnic/AU50/fpga_25g/boot.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for FPGA boot logic - -set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] -set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/AU50/fpga_25g/common/vivado.mk b/fpga/mqnic/AU50/fpga_25g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/fpga/mqnic/AU50/fpga_25g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/AU50/fpga_25g/hbm.xdc b/fpga/mqnic/AU50/fpga_25g/hbm.xdc deleted file mode 100644 index aa147b0a5..000000000 --- a/fpga/mqnic/AU50/fpga_25g/hbm.xdc +++ /dev/null @@ -1,2 +0,0 @@ -# force debug hub to use HBM APB clock to prevent CDC issues -connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK] diff --git a/fpga/mqnic/AU50/fpga_25g/ip/cms.tcl b/fpga/mqnic/AU50/fpga_25g/ip/cms.tcl deleted file mode 100644 index 22126d4d6..000000000 --- a/fpga/mqnic/AU50/fpga_25g/ip/cms.tcl +++ /dev/null @@ -1,16 +0,0 @@ - -# create block design -create_bd_design "cms" - -# create CMS IP -set cms_block [create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem cms_subsystem_0] -make_bd_pins_external $cms_block -make_bd_intf_pins_external $cms_block - -# assign addresses -assign_bd_address -target_address_space /s_axi_ctrl_0 [get_bd_addr_segs $cms_block/s_axi_ctrl/Mem0] -force - -# save block design and create HDL wrapper -save_bd_design [current_bd_design] -add_files -norecurse [make_wrapper -files [get_files [get_property FILE_NAME [current_bd_design]]] -top] -close_bd_design [current_bd_design] diff --git a/fpga/mqnic/AU50/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/AU50/fpga_25g/ip/eth_xcvr_gty.tcl deleted file mode 100644 index e1dda063f..000000000 --- a/fpga/mqnic/AU50/fpga_25g/ip/eth_xcvr_gty.tcl +++ /dev/null @@ -1,103 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2022-2023 The Regents of the University of California - -set base_name {eth_xcvr_gty} - -set preset {GTY-10GBASE-R} - -set freerun_freq {125} -set line_rate {25.78125} -set sec_line_rate {10.3125} -set refclk_freq {161.1328125} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {64} -set int_data_width $user_data_width -set rx_eq_mode {DFE} -set extra_ports [list] -set extra_pll_ports [list] -# DRP connections -lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out -lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out -# PLL reset and power down -lappend extra_pll_ports qpll0reset_in qpll1reset_in -lappend extra_pll_ports qpll0pd_in qpll1pd_in -# PLL clocking -lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out -lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out -# channel reset -lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out -lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out -# channel power down -lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in -# channel clock selection -lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in -# channel polarity -lappend extra_ports txpolarity_in rxpolarity_in -# channel TX driver -lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in -# channel CDR -lappend extra_ports rxcdrlock_out rxcdrhold_in -# channel EQ -lappend extra_ports rxlpmen_in -# channel digital monitor -lappend extra_ports dmonitorout_out -# channel PRBS -lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out -# channel eye scan -lappend extra_ports eyescandataerror_out -# channel loopback -lappend extra_ports loopback_in - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config RX_EQ_MODE $rx_eq_mode -if {$sec_line_rate != 0} { - dict set config SECONDARY_QPLL_ENABLE true - dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn - dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq -} else { - dict set config SECONDARY_QPLL_ENABLE false -} -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} -dict set config LOCATE_TX_USER_CLOCKING {CORE} -dict set config LOCATE_RX_USER_CLOCKING {CORE} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/AU50/fpga_25g/ip/hbm_0.tcl b/fpga/mqnic/AU50/fpga_25g/ip/hbm_0.tcl deleted file mode 100644 index a8cbc2874..000000000 --- a/fpga/mqnic/AU50/fpga_25g/ip/hbm_0.tcl +++ /dev/null @@ -1,23 +0,0 @@ - -create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0 - -set_property -dict [list \ - CONFIG.USER_HBM_DENSITY {8GB} \ - CONFIG.USER_HBM_STACK {2} \ - CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \ - CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true} -] [get_ips hbm_0] diff --git a/fpga/mqnic/AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl b/fpga/mqnic/AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl deleted file mode 100644 index 936d8b1e1..000000000 --- a/fpga/mqnic/AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl +++ /dev/null @@ -1,34 +0,0 @@ - -create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0 - -set_property -dict [list \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ - CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ - CONFIG.axisten_if_enable_client_tag {true} \ - CONFIG.axisten_if_width {512_bit} \ - CONFIG.extended_tag_field {true} \ - CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ - CONFIG.axisten_freq {250} \ - CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ - CONFIG.PF0_CLASS_CODE {020000} \ - CONFIG.PF0_DEVICE_ID {1001} \ - CONFIG.PF0_SUBSYSTEM_ID {9032} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_prefetchable {true} \ - CONFIG.pf0_bar0_scale {Megabytes} \ - CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_msi_enabled {false} \ - CONFIG.pf0_msix_enabled {true} \ - CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ - CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ - CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ - CONFIG.MSI_X_OPTIONS {MSI-X_External} \ - CONFIG.vendor_id {1234} \ - CONFIG.mode_selection {Advanced} \ -] [get_ips pcie4c_uscale_plus_0] diff --git a/fpga/mqnic/AU50/fpga_25g/lib b/fpga/mqnic/AU50/fpga_25g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/AU50/fpga_25g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/common b/fpga/mqnic/AU50/fpga_25g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/AU50/fpga_25g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v deleted file mode 100644 index 44a7c7004..000000000 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ /dev/null @@ -1,3013 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B77093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_9032, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Board configuration - parameter TDMA_BER_ENABLE = 0, - - // Structural configuration - parameter IF_COUNT = 1, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLOCK_PIPELINE = 1, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 1, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter ENABLE_PADDING = 1, - parameter ENABLE_DIC = 1, - parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // RAM configuration - parameter HBM_CH = 32, - parameter HBM_ENABLE = 0, - parameter HBM_GROUP_SIZE = HBM_CH, - parameter AXI_HBM_ADDR_WIDTH = 33, - parameter AXI_HBM_MAX_BURST_LEN = 16, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock and reset - */ - // input wire clk_100mhz_0_p, - // input wire clk_100mhz_0_n, - input wire clk_100mhz_1_p, - input wire clk_100mhz_1_n, - - /* - * GPIO - */ - output wire qsfp_led_act, - output wire qsfp_led_stat_g, - output wire qsfp_led_stat_y, - output wire hbm_cattrip, - input wire [1:0] msp_gpio, - output wire msp_uart_txd, - input wire msp_uart_rxd, - - /* - * PCI express - */ - input wire [15:0] pcie_rx_p, - input wire [15:0] pcie_rx_n, - output wire [15:0] pcie_tx_p, - output wire [15:0] pcie_tx_n, - input wire pcie_refclk_1_p, - input wire pcie_refclk_1_n, - input wire pcie_reset_n, - - /* - * Ethernet: QSFP28 - */ - output wire [3:0] qsfp_tx_p, - output wire [3:0] qsfp_tx_n, - input wire [3:0] qsfp_rx_p, - input wire [3:0] qsfp_rx_n, - input wire qsfp_mgt_refclk_0_p, - input wire qsfp_mgt_refclk_0_n - // input wire qsfp_mgt_refclk_1_p, - // input wire qsfp_mgt_refclk_1_n -); - -// PTP configuration -parameter PTP_CLK_PERIOD_NS_NUM = 1024; -parameter PTP_CLK_PERIOD_NS_DENOM = 165; -parameter PTP_TS_WIDTH = 96; -parameter IF_PTP_PERIOD_NS = 6'h6; -parameter IF_PTP_PERIOD_FNS = 16'h6666; - -// Interface configuration -parameter TX_TAG_WIDTH = 16; - -// RAM configuration -parameter HBM_CH_INT = 32; -parameter AXI_HBM_DATA_WIDTH = 256; -parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8); -parameter AXI_HBM_ID_WIDTH = 6; - -parameter HBM_CH_STRIDE = HBM_CH_INT / 2**$clog2(HBM_CH); - -// PCIe interface configuration -parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); -parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; -parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; -parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; -parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; -parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; -parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter RQ_SEQ_NUM_WIDTH = 6; -parameter PCIE_TAG_COUNT = 256; - -// Ethernet interface configuration -parameter XGMII_DATA_WIDTH = 64; -parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; -parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); -parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire pcie_user_clk; -wire pcie_user_reset; - -wire clk_161mhz_ref_int; - -wire clk_50mhz_mmcm_out; -wire clk_125mhz_mmcm_out; - -// Internal 50 MHz clock -wire clk_50mhz_int; -wire rst_50mhz_int; - -// Internal 125 MHz clock -wire clk_125mhz_int; -wire rst_125mhz_int; - -wire mmcm_rst = pcie_user_reset; -wire mmcm_locked; -wire mmcm_clkfb; - -// MMCM instance -// 161.13 MHz in, 50 MHz + 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 128, D = 15 sets Fvco = 1375 MHz (in range) -// Divide by 27.5 to get output frequency of 50 MHz -// Divide by 11 to get output frequency of 125 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(27.5), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(11), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(128), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(15), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_161mhz_ref_int), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_50mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(clk_125mhz_mmcm_out), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_50mhz_bufg_inst ( - .I(clk_50mhz_mmcm_out), - .O(clk_50mhz_int) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_50mhz_inst ( - .clk(clk_50mhz_int), - .rst(~mmcm_locked), - .out(rst_50mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// Flash -wire qspi_clk_int; -wire [3:0] qspi_dq_int; -wire [3:0] qspi_dq_i_int; -wire [3:0] qspi_dq_o_int; -wire [3:0] qspi_dq_oe_int; -wire qspi_cs_int; - -reg qspi_clk_reg; -reg [3:0] qspi_dq_o_reg; -reg [3:0] qspi_dq_oe_reg; -reg qspi_cs_reg; - -always @(posedge pcie_user_clk) begin - qspi_clk_reg <= qspi_clk_int; - qspi_dq_o_reg <= qspi_dq_o_int; - qspi_dq_oe_reg <= qspi_dq_oe_int; - qspi_cs_reg <= qspi_cs_int; -end - -sync_signal #( - .WIDTH(4), - .N(2) -) -flash_sync_signal_inst ( - .clk(pcie_user_clk), - .in({qspi_dq_int}), - .out({qspi_dq_i_int}) -); - -STARTUPE3 -startupe3_inst ( - .CFGCLK(), - .CFGMCLK(), - .DI(qspi_dq_int), - .DO(qspi_dq_o_reg), - .DTS(~qspi_dq_oe_reg), - .EOS(), - .FCSBO(qspi_cs_reg), - .FCSBTS(1'b0), - .GSR(1'b0), - .GTS(1'b0), - .KEYCLEARB(1'b1), - .PACK(1'b0), - .PREQ(), - .USRCCLKO(qspi_clk_reg), - .USRCCLKTS(1'b0), - .USRDONEO(1'b0), - .USRDONETS(1'b1) -); - -// FPGA boot -wire fpga_boot; - -reg fpga_boot_sync_reg_0 = 1'b0; -reg fpga_boot_sync_reg_1 = 1'b0; -reg fpga_boot_sync_reg_2 = 1'b0; - -wire icap_avail; -reg [2:0] icap_state = 0; -reg icap_csib_reg = 1'b1; -reg icap_rdwrb_reg = 1'b0; -reg [31:0] icap_di_reg = 32'hffffffff; - -wire [31:0] icap_di_rev; - -assign icap_di_rev[ 7] = icap_di_reg[ 0]; -assign icap_di_rev[ 6] = icap_di_reg[ 1]; -assign icap_di_rev[ 5] = icap_di_reg[ 2]; -assign icap_di_rev[ 4] = icap_di_reg[ 3]; -assign icap_di_rev[ 3] = icap_di_reg[ 4]; -assign icap_di_rev[ 2] = icap_di_reg[ 5]; -assign icap_di_rev[ 1] = icap_di_reg[ 6]; -assign icap_di_rev[ 0] = icap_di_reg[ 7]; - -assign icap_di_rev[15] = icap_di_reg[ 8]; -assign icap_di_rev[14] = icap_di_reg[ 9]; -assign icap_di_rev[13] = icap_di_reg[10]; -assign icap_di_rev[12] = icap_di_reg[11]; -assign icap_di_rev[11] = icap_di_reg[12]; -assign icap_di_rev[10] = icap_di_reg[13]; -assign icap_di_rev[ 9] = icap_di_reg[14]; -assign icap_di_rev[ 8] = icap_di_reg[15]; - -assign icap_di_rev[23] = icap_di_reg[16]; -assign icap_di_rev[22] = icap_di_reg[17]; -assign icap_di_rev[21] = icap_di_reg[18]; -assign icap_di_rev[20] = icap_di_reg[19]; -assign icap_di_rev[19] = icap_di_reg[20]; -assign icap_di_rev[18] = icap_di_reg[21]; -assign icap_di_rev[17] = icap_di_reg[22]; -assign icap_di_rev[16] = icap_di_reg[23]; - -assign icap_di_rev[31] = icap_di_reg[24]; -assign icap_di_rev[30] = icap_di_reg[25]; -assign icap_di_rev[29] = icap_di_reg[26]; -assign icap_di_rev[28] = icap_di_reg[27]; -assign icap_di_rev[27] = icap_di_reg[28]; -assign icap_di_rev[26] = icap_di_reg[29]; -assign icap_di_rev[25] = icap_di_reg[30]; -assign icap_di_rev[24] = icap_di_reg[31]; - -always @(posedge clk_125mhz_int) begin - case (icap_state) - 0: begin - icap_state <= 0; - icap_csib_reg <= 1'b1; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - - if (fpga_boot_sync_reg_2 && icap_avail) begin - icap_state <= 1; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - end - end - 1: begin - icap_state <= 2; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hAA995566; // sync word - end - 2: begin - icap_state <= 3; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - 3: begin - icap_state <= 4; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h30008001; // write 1 word to CMD - end - 4: begin - icap_state <= 5; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h0000000F; // IPROG - end - 5: begin - icap_state <= 0; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - endcase - - fpga_boot_sync_reg_0 <= fpga_boot; - fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; - fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; -end - -ICAPE3 -icape3_inst ( - .AVAIL(icap_avail), - .CLK(clk_125mhz_int), - .CSIB(icap_csib_reg), - .I(icap_di_rev), - .O(), - .PRDONE(), - .PRERROR(), - .RDWRB(icap_rdwrb_reg) -); - -// BMC -wire axil_cms_clk; -wire axil_cms_rst; -wire [17:0] axil_cms_awaddr; -wire [2:0] axil_cms_awprot; -wire axil_cms_awvalid; -wire axil_cms_awready; -wire [31:0] axil_cms_wdata; -wire [3:0] axil_cms_wstrb; -wire axil_cms_wvalid; -wire axil_cms_wready; -wire [1:0] axil_cms_bresp; -wire axil_cms_bvalid; -wire axil_cms_bready; -wire [17:0] axil_cms_araddr; -wire [2:0] axil_cms_arprot; -wire axil_cms_arvalid; -wire axil_cms_arready; -wire [31:0] axil_cms_rdata; -wire [1:0] axil_cms_rresp; -wire axil_cms_rvalid; -wire axil_cms_rready; - -wire [17:0] axil_cms_awaddr_int; -wire [2:0] axil_cms_awprot_int; -wire axil_cms_awvalid_int; -wire axil_cms_awready_int; -wire [31:0] axil_cms_wdata_int; -wire [3:0] axil_cms_wstrb_int; -wire axil_cms_wvalid_int; -wire axil_cms_wready_int; -wire [1:0] axil_cms_bresp_int; -wire axil_cms_bvalid_int; -wire axil_cms_bready_int; -wire [17:0] axil_cms_araddr_int; -wire [2:0] axil_cms_arprot_int; -wire axil_cms_arvalid_int; -wire axil_cms_arready_int; -wire [31:0] axil_cms_rdata_int; -wire [1:0] axil_cms_rresp_int; -wire axil_cms_rvalid_int; -wire axil_cms_rready_int; - -wire [6:0] hbm_temp_1; -wire [6:0] hbm_temp_2; - -axil_cdc #( - .DATA_WIDTH(32), - .ADDR_WIDTH(18) -) -cms_axil_cdc_inst ( - .s_clk(axil_cms_clk), - .s_rst(axil_cms_rst), - .s_axil_awaddr(axil_cms_awaddr), - .s_axil_awprot(axil_cms_awprot), - .s_axil_awvalid(axil_cms_awvalid), - .s_axil_awready(axil_cms_awready), - .s_axil_wdata(axil_cms_wdata), - .s_axil_wstrb(axil_cms_wstrb), - .s_axil_wvalid(axil_cms_wvalid), - .s_axil_wready(axil_cms_wready), - .s_axil_bresp(axil_cms_bresp), - .s_axil_bvalid(axil_cms_bvalid), - .s_axil_bready(axil_cms_bready), - .s_axil_araddr(axil_cms_araddr), - .s_axil_arprot(axil_cms_arprot), - .s_axil_arvalid(axil_cms_arvalid), - .s_axil_arready(axil_cms_arready), - .s_axil_rdata(axil_cms_rdata), - .s_axil_rresp(axil_cms_rresp), - .s_axil_rvalid(axil_cms_rvalid), - .s_axil_rready(axil_cms_rready), - .m_clk(clk_50mhz_int), - .m_rst(rst_50mhz_int), - .m_axil_awaddr(axil_cms_awaddr_int), - .m_axil_awprot(axil_cms_awprot_int), - .m_axil_awvalid(axil_cms_awvalid_int), - .m_axil_awready(axil_cms_awready_int), - .m_axil_wdata(axil_cms_wdata_int), - .m_axil_wstrb(axil_cms_wstrb_int), - .m_axil_wvalid(axil_cms_wvalid_int), - .m_axil_wready(axil_cms_wready_int), - .m_axil_bresp(axil_cms_bresp_int), - .m_axil_bvalid(axil_cms_bvalid_int), - .m_axil_bready(axil_cms_bready_int), - .m_axil_araddr(axil_cms_araddr_int), - .m_axil_arprot(axil_cms_arprot_int), - .m_axil_arvalid(axil_cms_arvalid_int), - .m_axil_arready(axil_cms_arready_int), - .m_axil_rdata(axil_cms_rdata_int), - .m_axil_rresp(axil_cms_rresp_int), - .m_axil_rvalid(axil_cms_rvalid_int), - .m_axil_rready(axil_cms_rready_int) -); - -cms_wrapper -cms_inst ( - .aclk_ctrl_0(clk_50mhz_int), - .aresetn_ctrl_0(~rst_50mhz_int), - .hbm_temp_1_0(hbm_temp_1), - .hbm_temp_2_0(hbm_temp_2), - .interrupt_hbm_cattrip_0(hbm_cattrip), - .interrupt_host_0(), - .s_axi_ctrl_0_araddr(axil_cms_araddr_int), - .s_axi_ctrl_0_arprot(axil_cms_arprot_int), - .s_axi_ctrl_0_arready(axil_cms_arready_int), - .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), - .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), - .s_axi_ctrl_0_awprot(axil_cms_awprot_int), - .s_axi_ctrl_0_awready(axil_cms_awready_int), - .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), - .s_axi_ctrl_0_bready(axil_cms_bready_int), - .s_axi_ctrl_0_bresp(axil_cms_bresp_int), - .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), - .s_axi_ctrl_0_rdata(axil_cms_rdata_int), - .s_axi_ctrl_0_rready(axil_cms_rready_int), - .s_axi_ctrl_0_rresp(axil_cms_rresp_int), - .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), - .s_axi_ctrl_0_wdata(axil_cms_wdata_int), - .s_axi_ctrl_0_wready(axil_cms_wready_int), - .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), - .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), - .satellite_gpio_0(msp_gpio), - .satellite_uart_0_rxd(msp_uart_rxd), - .satellite_uart_0_txd(msp_uart_txd) -); - -// PCIe -wire pcie_sys_clk; -wire pcie_sys_clk_gt; - -IBUFDS_GTE4 #( - .REFCLK_HROW_CK_SEL(2'b00) -) -ibufds_gte4_pcie_mgt_refclk_inst ( - .I (pcie_refclk_1_p), - .IB (pcie_refclk_1_n), - .CEB (1'b0), - .O (pcie_sys_clk_gt), - .ODIV2 (pcie_sys_clk) -); - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; -wire axis_rq_tlast; -wire axis_rq_tready; -wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; -wire axis_rq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; -wire axis_rc_tlast; -wire axis_rc_tready; -wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; -wire axis_rc_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; -wire axis_cq_tlast; -wire axis_cq_tready; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; -wire axis_cq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; -wire axis_cc_tlast; -wire axis_cc_tready; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; -wire axis_cc_tvalid; - -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; -wire pcie_rq_seq_num_vld0; -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; -wire pcie_rq_seq_num_vld1; - -wire [3:0] pcie_tfc_nph_av; -wire [3:0] pcie_tfc_npd_av; - -wire [2:0] cfg_max_payload; -wire [2:0] cfg_max_read_req; -wire [3:0] cfg_rcb_status; - -wire [9:0] cfg_mgmt_addr; -wire [7:0] cfg_mgmt_function_number; -wire cfg_mgmt_write; -wire [31:0] cfg_mgmt_write_data; -wire [3:0] cfg_mgmt_byte_enable; -wire cfg_mgmt_read; -wire [31:0] cfg_mgmt_read_data; -wire cfg_mgmt_read_write_done; - -wire [7:0] cfg_fc_ph; -wire [11:0] cfg_fc_pd; -wire [7:0] cfg_fc_nph; -wire [11:0] cfg_fc_npd; -wire [7:0] cfg_fc_cplh; -wire [11:0] cfg_fc_cpld; -wire [2:0] cfg_fc_sel; - -wire [3:0] cfg_interrupt_msix_enable; -wire [3:0] cfg_interrupt_msix_mask; -wire [251:0] cfg_interrupt_msix_vf_enable; -wire [251:0] cfg_interrupt_msix_vf_mask; -wire [63:0] cfg_interrupt_msix_address; -wire [31:0] cfg_interrupt_msix_data; -wire cfg_interrupt_msix_int; -wire [1:0] cfg_interrupt_msix_vec_pending; -wire cfg_interrupt_msix_vec_pending_status; -wire cfg_interrupt_msix_sent; -wire cfg_interrupt_msix_fail; -wire [7:0] cfg_interrupt_msi_function_number; - -wire status_error_cor; -wire status_error_uncor; - -// extra register for pcie_user_reset signal -wire pcie_user_reset_int; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_2 = 1'b1; - -always @(posedge pcie_user_clk) begin - pcie_user_reset_reg_1 <= pcie_user_reset_int; - pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; -end - -BUFG -pcie_user_reset_bufg_inst ( - .I(pcie_user_reset_reg_2), - .O(pcie_user_reset) -); - -pcie4c_uscale_plus_0 -pcie4c_uscale_plus_inst ( - .pci_exp_txn(pcie_tx_n), - .pci_exp_txp(pcie_tx_p), - .pci_exp_rxn(pcie_rx_n), - .pci_exp_rxp(pcie_rx_p), - .user_clk(pcie_user_clk), - .user_reset(pcie_user_reset_int), - .user_lnk_up(), - - .s_axis_rq_tdata(axis_rq_tdata), - .s_axis_rq_tkeep(axis_rq_tkeep), - .s_axis_rq_tlast(axis_rq_tlast), - .s_axis_rq_tready(axis_rq_tready), - .s_axis_rq_tuser(axis_rq_tuser), - .s_axis_rq_tvalid(axis_rq_tvalid), - - .m_axis_rc_tdata(axis_rc_tdata), - .m_axis_rc_tkeep(axis_rc_tkeep), - .m_axis_rc_tlast(axis_rc_tlast), - .m_axis_rc_tready(axis_rc_tready), - .m_axis_rc_tuser(axis_rc_tuser), - .m_axis_rc_tvalid(axis_rc_tvalid), - - .m_axis_cq_tdata(axis_cq_tdata), - .m_axis_cq_tkeep(axis_cq_tkeep), - .m_axis_cq_tlast(axis_cq_tlast), - .m_axis_cq_tready(axis_cq_tready), - .m_axis_cq_tuser(axis_cq_tuser), - .m_axis_cq_tvalid(axis_cq_tvalid), - - .s_axis_cc_tdata(axis_cc_tdata), - .s_axis_cc_tkeep(axis_cc_tkeep), - .s_axis_cc_tlast(axis_cc_tlast), - .s_axis_cc_tready(axis_cc_tready), - .s_axis_cc_tuser(axis_cc_tuser), - .s_axis_cc_tvalid(axis_cc_tvalid), - - .pcie_rq_seq_num0(pcie_rq_seq_num0), - .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), - .pcie_rq_seq_num1(pcie_rq_seq_num1), - .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), - .pcie_rq_tag0(), - .pcie_rq_tag1(), - .pcie_rq_tag_av(), - .pcie_rq_tag_vld0(), - .pcie_rq_tag_vld1(), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .pcie_cq_np_req(1'b1), - .pcie_cq_np_req_count(), - - .cfg_phy_link_down(), - .cfg_phy_link_status(), - .cfg_negotiated_width(), - .cfg_current_speed(), - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_function_status(), - .cfg_function_power_state(), - .cfg_vf_status(), - .cfg_vf_power_state(), - .cfg_link_power_state(), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - .cfg_mgmt_debug_access(1'b0), - - .cfg_err_cor_out(), - .cfg_err_nonfatal_out(), - .cfg_err_fatal_out(), - .cfg_local_error_valid(), - .cfg_local_error_out(), - .cfg_ltssm_state(), - .cfg_rx_pm_state(), - .cfg_tx_pm_state(), - .cfg_rcb_status(cfg_rcb_status), - .cfg_obff_enable(), - .cfg_pl_status_change(), - .cfg_tph_requester_enable(), - .cfg_tph_st_mode(), - .cfg_vf_tph_requester_enable(), - .cfg_vf_tph_st_mode(), - - .cfg_msg_received(), - .cfg_msg_received_data(), - .cfg_msg_received_type(), - .cfg_msg_transmit(1'b0), - .cfg_msg_transmit_type(3'd0), - .cfg_msg_transmit_data(32'd0), - .cfg_msg_transmit_done(), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_dsn(64'd0), - - .cfg_power_state_change_ack(1'b1), - .cfg_power_state_change_interrupt(), - - .cfg_err_cor_in(status_error_cor), - .cfg_err_uncor_in(status_error_uncor), - .cfg_flr_in_process(), - .cfg_flr_done(4'd0), - .cfg_vf_flr_in_process(), - .cfg_vf_flr_func_num(8'd0), - .cfg_vf_flr_done(8'd0), - - .cfg_link_training_enable(1'b1), - - .cfg_interrupt_int(4'd0), - .cfg_interrupt_pending(4'd0), - .cfg_interrupt_sent(), - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .cfg_pm_aspm_l1_entry_reject(1'b0), - .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), - - .cfg_hot_reset_out(), - - .cfg_config_space_enable(1'b1), - .cfg_req_pm_transition_l23_ready(1'b0), - .cfg_hot_reset_in(1'b0), - - .cfg_ds_port_number(8'd0), - .cfg_ds_bus_number(8'd0), - .cfg_ds_device_number(5'd0), - - .sys_clk(pcie_sys_clk), - .sys_clk_gt(pcie_sys_clk_gt), - .sys_reset(pcie_reset_n), - - .phy_rdy_out() -); - -reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0_reg; -reg pcie_rq_seq_num_vld0_reg; -reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1_reg; -reg pcie_rq_seq_num_vld1_reg; - -always @(posedge pcie_user_clk) begin - pcie_rq_seq_num0_reg <= pcie_rq_seq_num0; - pcie_rq_seq_num_vld0_reg <= pcie_rq_seq_num_vld0; - pcie_rq_seq_num1_reg <= pcie_rq_seq_num1; - pcie_rq_seq_num_vld1_reg <= pcie_rq_seq_num_vld1; - - if (pcie_user_reset) begin - pcie_rq_seq_num_vld0_reg <= 1'b0; - pcie_rq_seq_num_vld1_reg <= 1'b0; - end -end - -// XGMII 10G PHY -wire qsfp_tx_clk_1_int; -wire qsfp_tx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_1_int; -wire qsfp_cfg_tx_prbs31_enable_1_int; -wire qsfp_rx_clk_1_int; -wire qsfp_rx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_1_int; -wire qsfp_cfg_rx_prbs31_enable_1_int; -wire [6:0] qsfp_rx_error_count_1_int; -wire qsfp_tx_clk_2_int; -wire qsfp_tx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_2_int; -wire qsfp_cfg_tx_prbs31_enable_2_int; -wire qsfp_rx_clk_2_int; -wire qsfp_rx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_2_int; -wire qsfp_cfg_rx_prbs31_enable_2_int; -wire [6:0] qsfp_rx_error_count_2_int; -wire qsfp_tx_clk_3_int; -wire qsfp_tx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_3_int; -wire qsfp_cfg_tx_prbs31_enable_3_int; -wire qsfp_rx_clk_3_int; -wire qsfp_rx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_3_int; -wire qsfp_cfg_rx_prbs31_enable_3_int; -wire [6:0] qsfp_rx_error_count_3_int; -wire qsfp_tx_clk_4_int; -wire qsfp_tx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_4_int; -wire qsfp_cfg_tx_prbs31_enable_4_int; -wire qsfp_rx_clk_4_int; -wire qsfp_rx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_4_int; -wire qsfp_cfg_rx_prbs31_enable_4_int; -wire [6:0] qsfp_rx_error_count_4_int; - -wire qsfp_drp_clk = clk_125mhz_int; -wire qsfp_drp_rst = rst_125mhz_int; -wire [23:0] qsfp_drp_addr; -wire [15:0] qsfp_drp_di; -wire qsfp_drp_en; -wire qsfp_drp_we; -wire [15:0] qsfp_drp_do; -wire qsfp_drp_rdy; - -wire qsfp_rx_block_lock_1; -wire qsfp_rx_status_1; -wire qsfp_rx_block_lock_2; -wire qsfp_rx_status_2; -wire qsfp_rx_block_lock_3; -wire qsfp_rx_status_3; -wire qsfp_rx_block_lock_4; -wire qsfp_rx_status_4; - -wire qsfp_gtpowergood; - -wire qsfp_mgt_refclk_0; -wire qsfp_mgt_refclk_0_int; -wire qsfp_mgt_refclk_0_bufg; - -assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst ( - .I (qsfp_mgt_refclk_0_p), - .IB (qsfp_mgt_refclk_0_n), - .CEB (1'b0), - .O (qsfp_mgt_refclk_0), - .ODIV2 (qsfp_mgt_refclk_0_int) -); - -BUFG_GT bufg_gt_qsfp_mgt_refclk_0_inst ( - .CE (qsfp_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp_mgt_refclk_0_int), - .O (qsfp_mgt_refclk_0_bufg) -); - -wire qsfp_rst; - -sync_reset #( - .N(4) -) -qsfp_sync_reset_inst ( - .clk(qsfp_mgt_refclk_0_bufg), - .rst(rst_125mhz_int), - .out(qsfp_rst) -); - -eth_xcvr_phy_10g_gty_quad_wrapper #( - .PRBS31_ENABLE(1), - .TX_SERDES_PIPELINE(1), - .RX_SERDES_PIPELINE(1), - .COUNT_125US(125000/2.56) -) -qsfp_phy_quad_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp_gtpowergood), - .xcvr_ref_clk(qsfp_mgt_refclk_0), - - /* - * DRP - */ - .drp_clk(qsfp_drp_clk), - .drp_rst(qsfp_drp_rst), - .drp_addr(qsfp_drp_addr), - .drp_di(qsfp_drp_di), - .drp_en(qsfp_drp_en), - .drp_we(qsfp_drp_we), - .drp_do(qsfp_drp_do), - .drp_rdy(qsfp_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp_tx_p), - .xcvr_txn(qsfp_tx_n), - .xcvr_rxp(qsfp_rx_p), - .xcvr_rxn(qsfp_rx_n), - - /* - * PHY connections - */ - .phy_1_tx_clk(qsfp_tx_clk_1_int), - .phy_1_tx_rst(qsfp_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp_txd_1_int), - .phy_1_xgmii_txc(qsfp_txc_1_int), - .phy_1_rx_clk(qsfp_rx_clk_1_int), - .phy_1_rx_rst(qsfp_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp_rxd_1_int), - .phy_1_xgmii_rxc(qsfp_rxc_1_int), - .phy_1_tx_bad_block(), - .phy_1_rx_error_count(qsfp_rx_error_count_1_int), - .phy_1_rx_bad_block(), - .phy_1_rx_sequence_error(), - .phy_1_rx_block_lock(qsfp_rx_block_lock_1), - .phy_1_rx_high_ber(), - .phy_1_rx_status(qsfp_rx_status_1), - .phy_1_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_1_int), - .phy_1_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_1_int), - - .phy_2_tx_clk(qsfp_tx_clk_2_int), - .phy_2_tx_rst(qsfp_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp_txd_2_int), - .phy_2_xgmii_txc(qsfp_txc_2_int), - .phy_2_rx_clk(qsfp_rx_clk_2_int), - .phy_2_rx_rst(qsfp_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp_rxd_2_int), - .phy_2_xgmii_rxc(qsfp_rxc_2_int), - .phy_2_tx_bad_block(), - .phy_2_rx_error_count(qsfp_rx_error_count_2_int), - .phy_2_rx_bad_block(), - .phy_2_rx_sequence_error(), - .phy_2_rx_block_lock(qsfp_rx_block_lock_2), - .phy_2_rx_high_ber(), - .phy_2_rx_status(qsfp_rx_status_2), - .phy_2_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_2_int), - .phy_2_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_2_int), - - .phy_3_tx_clk(qsfp_tx_clk_3_int), - .phy_3_tx_rst(qsfp_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp_txd_3_int), - .phy_3_xgmii_txc(qsfp_txc_3_int), - .phy_3_rx_clk(qsfp_rx_clk_3_int), - .phy_3_rx_rst(qsfp_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp_rxd_3_int), - .phy_3_xgmii_rxc(qsfp_rxc_3_int), - .phy_3_tx_bad_block(), - .phy_3_rx_error_count(qsfp_rx_error_count_3_int), - .phy_3_rx_bad_block(), - .phy_3_rx_sequence_error(), - .phy_3_rx_block_lock(qsfp_rx_block_lock_3), - .phy_3_rx_high_ber(), - .phy_3_rx_status(qsfp_rx_status_3), - .phy_3_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_3_int), - .phy_3_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_3_int), - - .phy_4_tx_clk(qsfp_tx_clk_4_int), - .phy_4_tx_rst(qsfp_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp_txd_4_int), - .phy_4_xgmii_txc(qsfp_txc_4_int), - .phy_4_rx_clk(qsfp_rx_clk_4_int), - .phy_4_rx_rst(qsfp_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp_rxd_4_int), - .phy_4_xgmii_rxc(qsfp_rxc_4_int), - .phy_4_tx_bad_block(), - .phy_4_rx_error_count(qsfp_rx_error_count_4_int), - .phy_4_rx_bad_block(), - .phy_4_rx_sequence_error(), - .phy_4_rx_block_lock(qsfp_rx_block_lock_4), - .phy_4_rx_high_ber(), - .phy_4_rx_status(qsfp_rx_status_4), - .phy_4_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_4_int), - .phy_4_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_4_int) -); - -wire ptp_clk; -wire ptp_rst; -wire ptp_sample_clk; - -assign ptp_clk = qsfp_mgt_refclk_0_bufg; -assign ptp_rst = qsfp_rst; -assign ptp_sample_clk = clk_125mhz_int; - -// HBM -wire [HBM_CH-1:0] hbm_clk; -wire [HBM_CH-1:0] hbm_rst; - -wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid; -wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr; -wire [HBM_CH*8-1:0] m_axi_hbm_awlen; -wire [HBM_CH*3-1:0] m_axi_hbm_awsize; -wire [HBM_CH*2-1:0] m_axi_hbm_awburst; -wire [HBM_CH-1:0] m_axi_hbm_awlock; -wire [HBM_CH*4-1:0] m_axi_hbm_awcache; -wire [HBM_CH*3-1:0] m_axi_hbm_awprot; -wire [HBM_CH*4-1:0] m_axi_hbm_awqos; -wire [HBM_CH-1:0] m_axi_hbm_awvalid; -wire [HBM_CH-1:0] m_axi_hbm_awready; -wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata; -wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb; -wire [HBM_CH-1:0] m_axi_hbm_wlast; -wire [HBM_CH-1:0] m_axi_hbm_wvalid; -wire [HBM_CH-1:0] m_axi_hbm_wready; -wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid; -wire [HBM_CH*2-1:0] m_axi_hbm_bresp; -wire [HBM_CH-1:0] m_axi_hbm_bvalid; -wire [HBM_CH-1:0] m_axi_hbm_bready; -wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid; -wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr; -wire [HBM_CH*8-1:0] m_axi_hbm_arlen; -wire [HBM_CH*3-1:0] m_axi_hbm_arsize; -wire [HBM_CH*2-1:0] m_axi_hbm_arburst; -wire [HBM_CH-1:0] m_axi_hbm_arlock; -wire [HBM_CH*4-1:0] m_axi_hbm_arcache; -wire [HBM_CH*3-1:0] m_axi_hbm_arprot; -wire [HBM_CH*4-1:0] m_axi_hbm_arqos; -wire [HBM_CH-1:0] m_axi_hbm_arvalid; -wire [HBM_CH-1:0] m_axi_hbm_arready; -wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid; -wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata; -wire [HBM_CH*2-1:0] m_axi_hbm_rresp; -wire [HBM_CH-1:0] m_axi_hbm_rlast; -wire [HBM_CH-1:0] m_axi_hbm_rvalid; -wire [HBM_CH-1:0] m_axi_hbm_rready; - -wire [HBM_CH-1:0] hbm_status; - -wire [HBM_CH_INT-1:0] hbm_clk_int; -wire [HBM_CH_INT-1:0] hbm_rst_int; - -wire [HBM_CH_INT*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_int_awid; -wire [HBM_CH_INT*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_int_awaddr; -wire [HBM_CH_INT*8-1:0] m_axi_hbm_int_awlen; -wire [HBM_CH_INT*3-1:0] m_axi_hbm_int_awsize; -wire [HBM_CH_INT*2-1:0] m_axi_hbm_int_awburst; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_awlock; -wire [HBM_CH_INT*4-1:0] m_axi_hbm_int_awcache; -wire [HBM_CH_INT*3-1:0] m_axi_hbm_int_awprot; -wire [HBM_CH_INT*4-1:0] m_axi_hbm_int_awqos; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_awvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_awready; -wire [HBM_CH_INT*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_int_wdata; -wire [HBM_CH_INT*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_int_wstrb; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_wlast; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_wvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_wready; -wire [HBM_CH_INT*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_int_bid; -wire [HBM_CH_INT*2-1:0] m_axi_hbm_int_bresp; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_bvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_bready; -wire [HBM_CH_INT*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_int_arid; -wire [HBM_CH_INT*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_int_araddr; -wire [HBM_CH_INT*8-1:0] m_axi_hbm_int_arlen; -wire [HBM_CH_INT*3-1:0] m_axi_hbm_int_arsize; -wire [HBM_CH_INT*2-1:0] m_axi_hbm_int_arburst; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_arlock; -wire [HBM_CH_INT*4-1:0] m_axi_hbm_int_arcache; -wire [HBM_CH_INT*3-1:0] m_axi_hbm_int_arprot; -wire [HBM_CH_INT*4-1:0] m_axi_hbm_int_arqos; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_arvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_arready; -wire [HBM_CH_INT*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_int_rid; -wire [HBM_CH_INT*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_int_rdata; -wire [HBM_CH_INT*2-1:0] m_axi_hbm_int_rresp; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_rlast; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_rvalid; -wire [HBM_CH_INT-1:0] m_axi_hbm_int_rready; - -wire clk_100mhz_1_ibufg; - -IBUFGDS #( - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") -) -clk_100mhz_1_ibufg_inst ( - .O (clk_100mhz_1_ibufg), - .I (clk_100mhz_1_p), - .IB (clk_100mhz_1_n) -); - -generate - -genvar n; - -if (HBM_ENABLE) begin - -wire hbm_ref_clk; - -wire hbm_mmcm_rst = rst_125mhz_int; -wire hbm_mmcm_locked; -wire hbm_mmcm_clkfb; - -wire hbm_axi_clk_mmcm; -wire hbm_axi_clk; -wire hbm_axi_rst_int; -wire hbm_axi_rst; - -BUFG -hbm_ref_clk_bufg_inst ( - .I(clk_100mhz_1_ibufg), - .O(hbm_ref_clk) -); - -// HBM MMCM instance -// 100 MHz in, 450 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 9, D = 1 sets Fvco = 900 MHz -// Divide by 2 to get output frequency of 450 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(2), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(1), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(9), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(1), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(10.000), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -hbm_mmcm_inst ( - .CLKIN1(clk_100mhz_1_ibufg), - .CLKFBIN(hbm_mmcm_clkfb), - .RST(hbm_mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(hbm_axi_clk_mmcm), - .CLKOUT0B(), - .CLKOUT1(), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(hbm_mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(hbm_mmcm_locked) -); - -BUFG -hbm_axi_clk_bufg_inst ( - .I(hbm_axi_clk_mmcm), - .O(hbm_axi_clk) -); - -sync_reset #( - .N(4) -) -sync_reset_hbm_axi_inst ( - .clk(hbm_axi_clk), - .rst(~hbm_mmcm_locked), - .out(hbm_axi_rst_int) -); - -// extra register for hbm_axi_rst signal -(* shreg_extract = "no" *) -reg hbm_axi_rst_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg hbm_axi_rst_reg_2 = 1'b1; - -always @(posedge hbm_axi_clk) begin - hbm_axi_rst_reg_1 <= hbm_axi_rst_int; - hbm_axi_rst_reg_2 <= hbm_axi_rst_reg_1; -end - -BUFG -hbm_axi_rst_bufg_inst ( - .I(hbm_axi_rst_reg_2), - .O(hbm_axi_rst) -); - -wire hbm_cattrip_1; -wire hbm_cattrip_2; - -assign hbm_cattrip = hbm_cattrip_1 | hbm_cattrip_2; - -assign hbm_clk_int = {HBM_CH_INT{hbm_axi_clk}}; -assign hbm_rst_int = {HBM_CH_INT{hbm_axi_rst}}; - -hbm_0 hbm_inst ( - .HBM_REF_CLK_0(hbm_ref_clk), - .HBM_REF_CLK_1(hbm_ref_clk), - - .APB_0_PWDATA(32'd0), - .APB_0_PADDR(22'd0), - .APB_0_PCLK(hbm_ref_clk), - .APB_0_PENABLE(1'b0), - .APB_0_PRESET_N(1'b1), - .APB_0_PSEL(1'b0), - .APB_0_PWRITE(1'b0), - .APB_0_PRDATA(), - .APB_0_PREADY(), - .APB_0_PSLVERR(), - .apb_complete_0(), - - .APB_1_PWDATA(32'd0), - .APB_1_PADDR(22'd0), - .APB_1_PCLK(hbm_ref_clk), - .APB_1_PENABLE(1'b0), - .APB_1_PRESET_N(1'b1), - .APB_1_PSEL(1'b0), - .APB_1_PWRITE(1'b0), - .APB_1_PRDATA(), - .APB_1_PREADY(), - .APB_1_PSLVERR(), - .apb_complete_1(), - - .AXI_00_ACLK(hbm_clk_int[0 +: 1]), - .AXI_00_ARESET_N(!hbm_rst_int[0 +: 1]), - - .AXI_00_ARADDR(m_axi_hbm_int_araddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_00_ARBURST(m_axi_hbm_int_arburst[0*2 +: 2]), - .AXI_00_ARID(m_axi_hbm_int_arid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_00_ARLEN(m_axi_hbm_int_arlen[0*8 +: 4]), - .AXI_00_ARSIZE(m_axi_hbm_int_arsize[0*3 +: 3]), - .AXI_00_ARVALID(m_axi_hbm_int_arvalid[0 +: 1]), - .AXI_00_ARREADY(m_axi_hbm_int_arready[0 +: 1]), - .AXI_00_RDATA_PARITY(), - .AXI_00_RDATA(m_axi_hbm_int_rdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_00_RID(m_axi_hbm_int_rid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_00_RLAST(m_axi_hbm_int_rlast[0 +: 1]), - .AXI_00_RRESP(m_axi_hbm_int_rresp[0*2 +: 2]), - .AXI_00_RVALID(m_axi_hbm_int_rvalid[0 +: 1]), - .AXI_00_RREADY(m_axi_hbm_int_rready[0 +: 1]), - .AXI_00_AWADDR(m_axi_hbm_int_awaddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_00_AWBURST(m_axi_hbm_int_awburst[0*2 +: 2]), - .AXI_00_AWID(m_axi_hbm_int_awid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_00_AWLEN(m_axi_hbm_int_awlen[0*8 +: 4]), - .AXI_00_AWSIZE(m_axi_hbm_int_awsize[0*3 +: 3]), - .AXI_00_AWVALID(m_axi_hbm_int_awvalid[0 +: 1]), - .AXI_00_AWREADY(m_axi_hbm_int_awready[0 +: 1]), - .AXI_00_WDATA(m_axi_hbm_int_wdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_00_WLAST(m_axi_hbm_int_wlast[0 +: 1]), - .AXI_00_WSTRB(m_axi_hbm_int_wstrb[0*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_00_WDATA_PARITY(32'd0), - .AXI_00_WVALID(m_axi_hbm_int_wvalid[0 +: 1]), - .AXI_00_WREADY(m_axi_hbm_int_wready[0 +: 1]), - .AXI_00_BID(m_axi_hbm_int_bid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_00_BRESP(m_axi_hbm_int_bresp[0*2 +: 2]), - .AXI_00_BVALID(m_axi_hbm_int_bvalid[0 +: 1]), - .AXI_00_BREADY(m_axi_hbm_int_bready[0 +: 1]), - - .AXI_01_ACLK(hbm_clk_int[1 +: 1]), - .AXI_01_ARESET_N(!hbm_rst_int[1 +: 1]), - - .AXI_01_ARADDR(m_axi_hbm_int_araddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_01_ARBURST(m_axi_hbm_int_arburst[1*2 +: 2]), - .AXI_01_ARID(m_axi_hbm_int_arid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_01_ARLEN(m_axi_hbm_int_arlen[1*8 +: 4]), - .AXI_01_ARSIZE(m_axi_hbm_int_arsize[1*3 +: 3]), - .AXI_01_ARVALID(m_axi_hbm_int_arvalid[1 +: 1]), - .AXI_01_ARREADY(m_axi_hbm_int_arready[1 +: 1]), - .AXI_01_RDATA_PARITY(), - .AXI_01_RDATA(m_axi_hbm_int_rdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_01_RID(m_axi_hbm_int_rid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_01_RLAST(m_axi_hbm_int_rlast[1 +: 1]), - .AXI_01_RRESP(m_axi_hbm_int_rresp[1*2 +: 2]), - .AXI_01_RVALID(m_axi_hbm_int_rvalid[1 +: 1]), - .AXI_01_RREADY(m_axi_hbm_int_rready[1 +: 1]), - .AXI_01_AWADDR(m_axi_hbm_int_awaddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_01_AWBURST(m_axi_hbm_int_awburst[1*2 +: 2]), - .AXI_01_AWID(m_axi_hbm_int_awid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_01_AWLEN(m_axi_hbm_int_awlen[1*8 +: 4]), - .AXI_01_AWSIZE(m_axi_hbm_int_awsize[1*3 +: 3]), - .AXI_01_AWVALID(m_axi_hbm_int_awvalid[1 +: 1]), - .AXI_01_AWREADY(m_axi_hbm_int_awready[1 +: 1]), - .AXI_01_WDATA(m_axi_hbm_int_wdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_01_WLAST(m_axi_hbm_int_wlast[1 +: 1]), - .AXI_01_WSTRB(m_axi_hbm_int_wstrb[1*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_01_WDATA_PARITY(32'd0), - .AXI_01_WVALID(m_axi_hbm_int_wvalid[1 +: 1]), - .AXI_01_WREADY(m_axi_hbm_int_wready[1 +: 1]), - .AXI_01_BID(m_axi_hbm_int_bid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_01_BRESP(m_axi_hbm_int_bresp[1*2 +: 2]), - .AXI_01_BVALID(m_axi_hbm_int_bvalid[1 +: 1]), - .AXI_01_BREADY(m_axi_hbm_int_bready[1 +: 1]), - - .AXI_02_ACLK(hbm_clk_int[2 +: 1]), - .AXI_02_ARESET_N(!hbm_rst_int[2 +: 1]), - - .AXI_02_ARADDR(m_axi_hbm_int_araddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_02_ARBURST(m_axi_hbm_int_arburst[2*2 +: 2]), - .AXI_02_ARID(m_axi_hbm_int_arid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_02_ARLEN(m_axi_hbm_int_arlen[2*8 +: 4]), - .AXI_02_ARSIZE(m_axi_hbm_int_arsize[2*3 +: 3]), - .AXI_02_ARVALID(m_axi_hbm_int_arvalid[2 +: 1]), - .AXI_02_ARREADY(m_axi_hbm_int_arready[2 +: 1]), - .AXI_02_RDATA_PARITY(), - .AXI_02_RDATA(m_axi_hbm_int_rdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_02_RID(m_axi_hbm_int_rid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_02_RLAST(m_axi_hbm_int_rlast[2 +: 1]), - .AXI_02_RRESP(m_axi_hbm_int_rresp[2*2 +: 2]), - .AXI_02_RVALID(m_axi_hbm_int_rvalid[2 +: 1]), - .AXI_02_RREADY(m_axi_hbm_int_rready[2 +: 1]), - .AXI_02_AWADDR(m_axi_hbm_int_awaddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_02_AWBURST(m_axi_hbm_int_awburst[2*2 +: 2]), - .AXI_02_AWID(m_axi_hbm_int_awid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_02_AWLEN(m_axi_hbm_int_awlen[2*8 +: 4]), - .AXI_02_AWSIZE(m_axi_hbm_int_awsize[2*3 +: 3]), - .AXI_02_AWVALID(m_axi_hbm_int_awvalid[2 +: 1]), - .AXI_02_AWREADY(m_axi_hbm_int_awready[2 +: 1]), - .AXI_02_WDATA(m_axi_hbm_int_wdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_02_WLAST(m_axi_hbm_int_wlast[2 +: 1]), - .AXI_02_WSTRB(m_axi_hbm_int_wstrb[2*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_02_WDATA_PARITY(32'd0), - .AXI_02_WVALID(m_axi_hbm_int_wvalid[2 +: 1]), - .AXI_02_WREADY(m_axi_hbm_int_wready[2 +: 1]), - .AXI_02_BID(m_axi_hbm_int_bid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_02_BRESP(m_axi_hbm_int_bresp[2*2 +: 2]), - .AXI_02_BVALID(m_axi_hbm_int_bvalid[2 +: 1]), - .AXI_02_BREADY(m_axi_hbm_int_bready[2 +: 1]), - - .AXI_03_ACLK(hbm_clk_int[3 +: 1]), - .AXI_03_ARESET_N(!hbm_rst_int[3 +: 1]), - - .AXI_03_ARADDR(m_axi_hbm_int_araddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_03_ARBURST(m_axi_hbm_int_arburst[3*2 +: 2]), - .AXI_03_ARID(m_axi_hbm_int_arid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_03_ARLEN(m_axi_hbm_int_arlen[3*8 +: 4]), - .AXI_03_ARSIZE(m_axi_hbm_int_arsize[3*3 +: 3]), - .AXI_03_ARVALID(m_axi_hbm_int_arvalid[3 +: 1]), - .AXI_03_ARREADY(m_axi_hbm_int_arready[3 +: 1]), - .AXI_03_RDATA_PARITY(), - .AXI_03_RDATA(m_axi_hbm_int_rdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_03_RID(m_axi_hbm_int_rid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_03_RLAST(m_axi_hbm_int_rlast[3 +: 1]), - .AXI_03_RRESP(m_axi_hbm_int_rresp[3*2 +: 2]), - .AXI_03_RVALID(m_axi_hbm_int_rvalid[3 +: 1]), - .AXI_03_RREADY(m_axi_hbm_int_rready[3 +: 1]), - .AXI_03_AWADDR(m_axi_hbm_int_awaddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_03_AWBURST(m_axi_hbm_int_awburst[3*2 +: 2]), - .AXI_03_AWID(m_axi_hbm_int_awid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_03_AWLEN(m_axi_hbm_int_awlen[3*8 +: 4]), - .AXI_03_AWSIZE(m_axi_hbm_int_awsize[3*3 +: 3]), - .AXI_03_AWVALID(m_axi_hbm_int_awvalid[3 +: 1]), - .AXI_03_AWREADY(m_axi_hbm_int_awready[3 +: 1]), - .AXI_03_WDATA(m_axi_hbm_int_wdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_03_WLAST(m_axi_hbm_int_wlast[3 +: 1]), - .AXI_03_WSTRB(m_axi_hbm_int_wstrb[3*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_03_WDATA_PARITY(32'd0), - .AXI_03_WVALID(m_axi_hbm_int_wvalid[3 +: 1]), - .AXI_03_WREADY(m_axi_hbm_int_wready[3 +: 1]), - .AXI_03_BID(m_axi_hbm_int_bid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_03_BRESP(m_axi_hbm_int_bresp[3*2 +: 2]), - .AXI_03_BVALID(m_axi_hbm_int_bvalid[3 +: 1]), - .AXI_03_BREADY(m_axi_hbm_int_bready[3 +: 1]), - - .AXI_04_ACLK(hbm_clk_int[4 +: 1]), - .AXI_04_ARESET_N(!hbm_rst_int[4 +: 1]), - - .AXI_04_ARADDR(m_axi_hbm_int_araddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_04_ARBURST(m_axi_hbm_int_arburst[4*2 +: 2]), - .AXI_04_ARID(m_axi_hbm_int_arid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_04_ARLEN(m_axi_hbm_int_arlen[4*8 +: 4]), - .AXI_04_ARSIZE(m_axi_hbm_int_arsize[4*3 +: 3]), - .AXI_04_ARVALID(m_axi_hbm_int_arvalid[4 +: 1]), - .AXI_04_ARREADY(m_axi_hbm_int_arready[4 +: 1]), - .AXI_04_RDATA_PARITY(), - .AXI_04_RDATA(m_axi_hbm_int_rdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_04_RID(m_axi_hbm_int_rid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_04_RLAST(m_axi_hbm_int_rlast[4 +: 1]), - .AXI_04_RRESP(m_axi_hbm_int_rresp[4*2 +: 2]), - .AXI_04_RVALID(m_axi_hbm_int_rvalid[4 +: 1]), - .AXI_04_RREADY(m_axi_hbm_int_rready[4 +: 1]), - .AXI_04_AWADDR(m_axi_hbm_int_awaddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_04_AWBURST(m_axi_hbm_int_awburst[4*2 +: 2]), - .AXI_04_AWID(m_axi_hbm_int_awid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_04_AWLEN(m_axi_hbm_int_awlen[4*8 +: 4]), - .AXI_04_AWSIZE(m_axi_hbm_int_awsize[4*3 +: 3]), - .AXI_04_AWVALID(m_axi_hbm_int_awvalid[4 +: 1]), - .AXI_04_AWREADY(m_axi_hbm_int_awready[4 +: 1]), - .AXI_04_WDATA(m_axi_hbm_int_wdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_04_WLAST(m_axi_hbm_int_wlast[4 +: 1]), - .AXI_04_WSTRB(m_axi_hbm_int_wstrb[4*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_04_WDATA_PARITY(32'd0), - .AXI_04_WVALID(m_axi_hbm_int_wvalid[4 +: 1]), - .AXI_04_WREADY(m_axi_hbm_int_wready[4 +: 1]), - .AXI_04_BID(m_axi_hbm_int_bid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_04_BRESP(m_axi_hbm_int_bresp[4*2 +: 2]), - .AXI_04_BVALID(m_axi_hbm_int_bvalid[4 +: 1]), - .AXI_04_BREADY(m_axi_hbm_int_bready[4 +: 1]), - - .AXI_05_ACLK(hbm_clk_int[5 +: 1]), - .AXI_05_ARESET_N(!hbm_rst_int[5 +: 1]), - - .AXI_05_ARADDR(m_axi_hbm_int_araddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_05_ARBURST(m_axi_hbm_int_arburst[5*2 +: 2]), - .AXI_05_ARID(m_axi_hbm_int_arid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_05_ARLEN(m_axi_hbm_int_arlen[5*8 +: 4]), - .AXI_05_ARSIZE(m_axi_hbm_int_arsize[5*3 +: 3]), - .AXI_05_ARVALID(m_axi_hbm_int_arvalid[5 +: 1]), - .AXI_05_ARREADY(m_axi_hbm_int_arready[5 +: 1]), - .AXI_05_RDATA_PARITY(), - .AXI_05_RDATA(m_axi_hbm_int_rdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_05_RID(m_axi_hbm_int_rid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_05_RLAST(m_axi_hbm_int_rlast[5 +: 1]), - .AXI_05_RRESP(m_axi_hbm_int_rresp[5*2 +: 2]), - .AXI_05_RVALID(m_axi_hbm_int_rvalid[5 +: 1]), - .AXI_05_RREADY(m_axi_hbm_int_rready[5 +: 1]), - .AXI_05_AWADDR(m_axi_hbm_int_awaddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_05_AWBURST(m_axi_hbm_int_awburst[5*2 +: 2]), - .AXI_05_AWID(m_axi_hbm_int_awid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_05_AWLEN(m_axi_hbm_int_awlen[5*8 +: 4]), - .AXI_05_AWSIZE(m_axi_hbm_int_awsize[5*3 +: 3]), - .AXI_05_AWVALID(m_axi_hbm_int_awvalid[5 +: 1]), - .AXI_05_AWREADY(m_axi_hbm_int_awready[5 +: 1]), - .AXI_05_WDATA(m_axi_hbm_int_wdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_05_WLAST(m_axi_hbm_int_wlast[5 +: 1]), - .AXI_05_WSTRB(m_axi_hbm_int_wstrb[5*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_05_WDATA_PARITY(32'd0), - .AXI_05_WVALID(m_axi_hbm_int_wvalid[5 +: 1]), - .AXI_05_WREADY(m_axi_hbm_int_wready[5 +: 1]), - .AXI_05_BID(m_axi_hbm_int_bid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_05_BRESP(m_axi_hbm_int_bresp[5*2 +: 2]), - .AXI_05_BVALID(m_axi_hbm_int_bvalid[5 +: 1]), - .AXI_05_BREADY(m_axi_hbm_int_bready[5 +: 1]), - - .AXI_06_ACLK(hbm_clk_int[6 +: 1]), - .AXI_06_ARESET_N(!hbm_rst_int[6 +: 1]), - - .AXI_06_ARADDR(m_axi_hbm_int_araddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_06_ARBURST(m_axi_hbm_int_arburst[6*2 +: 2]), - .AXI_06_ARID(m_axi_hbm_int_arid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_06_ARLEN(m_axi_hbm_int_arlen[6*8 +: 4]), - .AXI_06_ARSIZE(m_axi_hbm_int_arsize[6*3 +: 3]), - .AXI_06_ARVALID(m_axi_hbm_int_arvalid[6 +: 1]), - .AXI_06_ARREADY(m_axi_hbm_int_arready[6 +: 1]), - .AXI_06_RDATA_PARITY(), - .AXI_06_RDATA(m_axi_hbm_int_rdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_06_RID(m_axi_hbm_int_rid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_06_RLAST(m_axi_hbm_int_rlast[6 +: 1]), - .AXI_06_RRESP(m_axi_hbm_int_rresp[6*2 +: 2]), - .AXI_06_RVALID(m_axi_hbm_int_rvalid[6 +: 1]), - .AXI_06_RREADY(m_axi_hbm_int_rready[6 +: 1]), - .AXI_06_AWADDR(m_axi_hbm_int_awaddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_06_AWBURST(m_axi_hbm_int_awburst[6*2 +: 2]), - .AXI_06_AWID(m_axi_hbm_int_awid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_06_AWLEN(m_axi_hbm_int_awlen[6*8 +: 4]), - .AXI_06_AWSIZE(m_axi_hbm_int_awsize[6*3 +: 3]), - .AXI_06_AWVALID(m_axi_hbm_int_awvalid[6 +: 1]), - .AXI_06_AWREADY(m_axi_hbm_int_awready[6 +: 1]), - .AXI_06_WDATA(m_axi_hbm_int_wdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_06_WLAST(m_axi_hbm_int_wlast[6 +: 1]), - .AXI_06_WSTRB(m_axi_hbm_int_wstrb[6*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_06_WDATA_PARITY(32'd0), - .AXI_06_WVALID(m_axi_hbm_int_wvalid[6 +: 1]), - .AXI_06_WREADY(m_axi_hbm_int_wready[6 +: 1]), - .AXI_06_BID(m_axi_hbm_int_bid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_06_BRESP(m_axi_hbm_int_bresp[6*2 +: 2]), - .AXI_06_BVALID(m_axi_hbm_int_bvalid[6 +: 1]), - .AXI_06_BREADY(m_axi_hbm_int_bready[6 +: 1]), - - .AXI_07_ACLK(hbm_clk_int[7 +: 1]), - .AXI_07_ARESET_N(!hbm_rst_int[7 +: 1]), - - .AXI_07_ARADDR(m_axi_hbm_int_araddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_07_ARBURST(m_axi_hbm_int_arburst[7*2 +: 2]), - .AXI_07_ARID(m_axi_hbm_int_arid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_07_ARLEN(m_axi_hbm_int_arlen[7*8 +: 4]), - .AXI_07_ARSIZE(m_axi_hbm_int_arsize[7*3 +: 3]), - .AXI_07_ARVALID(m_axi_hbm_int_arvalid[7 +: 1]), - .AXI_07_ARREADY(m_axi_hbm_int_arready[7 +: 1]), - .AXI_07_RDATA_PARITY(), - .AXI_07_RDATA(m_axi_hbm_int_rdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_07_RID(m_axi_hbm_int_rid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_07_RLAST(m_axi_hbm_int_rlast[7 +: 1]), - .AXI_07_RRESP(m_axi_hbm_int_rresp[7*2 +: 2]), - .AXI_07_RVALID(m_axi_hbm_int_rvalid[7 +: 1]), - .AXI_07_RREADY(m_axi_hbm_int_rready[7 +: 1]), - .AXI_07_AWADDR(m_axi_hbm_int_awaddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_07_AWBURST(m_axi_hbm_int_awburst[7*2 +: 2]), - .AXI_07_AWID(m_axi_hbm_int_awid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_07_AWLEN(m_axi_hbm_int_awlen[7*8 +: 4]), - .AXI_07_AWSIZE(m_axi_hbm_int_awsize[7*3 +: 3]), - .AXI_07_AWVALID(m_axi_hbm_int_awvalid[7 +: 1]), - .AXI_07_AWREADY(m_axi_hbm_int_awready[7 +: 1]), - .AXI_07_WDATA(m_axi_hbm_int_wdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_07_WLAST(m_axi_hbm_int_wlast[7 +: 1]), - .AXI_07_WSTRB(m_axi_hbm_int_wstrb[7*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_07_WDATA_PARITY(32'd0), - .AXI_07_WVALID(m_axi_hbm_int_wvalid[7 +: 1]), - .AXI_07_WREADY(m_axi_hbm_int_wready[7 +: 1]), - .AXI_07_BID(m_axi_hbm_int_bid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_07_BRESP(m_axi_hbm_int_bresp[7*2 +: 2]), - .AXI_07_BVALID(m_axi_hbm_int_bvalid[7 +: 1]), - .AXI_07_BREADY(m_axi_hbm_int_bready[7 +: 1]), - - .AXI_08_ACLK(hbm_clk_int[8 +: 1]), - .AXI_08_ARESET_N(!hbm_rst_int[8 +: 1]), - - .AXI_08_ARADDR(m_axi_hbm_int_araddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_08_ARBURST(m_axi_hbm_int_arburst[8*2 +: 2]), - .AXI_08_ARID(m_axi_hbm_int_arid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_08_ARLEN(m_axi_hbm_int_arlen[8*8 +: 4]), - .AXI_08_ARSIZE(m_axi_hbm_int_arsize[8*3 +: 3]), - .AXI_08_ARVALID(m_axi_hbm_int_arvalid[8 +: 1]), - .AXI_08_ARREADY(m_axi_hbm_int_arready[8 +: 1]), - .AXI_08_RDATA_PARITY(), - .AXI_08_RDATA(m_axi_hbm_int_rdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_08_RID(m_axi_hbm_int_rid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_08_RLAST(m_axi_hbm_int_rlast[8 +: 1]), - .AXI_08_RRESP(m_axi_hbm_int_rresp[8*2 +: 2]), - .AXI_08_RVALID(m_axi_hbm_int_rvalid[8 +: 1]), - .AXI_08_RREADY(m_axi_hbm_int_rready[8 +: 1]), - .AXI_08_AWADDR(m_axi_hbm_int_awaddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_08_AWBURST(m_axi_hbm_int_awburst[8*2 +: 2]), - .AXI_08_AWID(m_axi_hbm_int_awid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_08_AWLEN(m_axi_hbm_int_awlen[8*8 +: 4]), - .AXI_08_AWSIZE(m_axi_hbm_int_awsize[8*3 +: 3]), - .AXI_08_AWVALID(m_axi_hbm_int_awvalid[8 +: 1]), - .AXI_08_AWREADY(m_axi_hbm_int_awready[8 +: 1]), - .AXI_08_WDATA(m_axi_hbm_int_wdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_08_WLAST(m_axi_hbm_int_wlast[8 +: 1]), - .AXI_08_WSTRB(m_axi_hbm_int_wstrb[8*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_08_WDATA_PARITY(32'd0), - .AXI_08_WVALID(m_axi_hbm_int_wvalid[8 +: 1]), - .AXI_08_WREADY(m_axi_hbm_int_wready[8 +: 1]), - .AXI_08_BID(m_axi_hbm_int_bid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_08_BRESP(m_axi_hbm_int_bresp[8*2 +: 2]), - .AXI_08_BVALID(m_axi_hbm_int_bvalid[8 +: 1]), - .AXI_08_BREADY(m_axi_hbm_int_bready[8 +: 1]), - - .AXI_09_ACLK(hbm_clk_int[9 +: 1]), - .AXI_09_ARESET_N(!hbm_rst_int[9 +: 1]), - - .AXI_09_ARADDR(m_axi_hbm_int_araddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_09_ARBURST(m_axi_hbm_int_arburst[9*2 +: 2]), - .AXI_09_ARID(m_axi_hbm_int_arid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_09_ARLEN(m_axi_hbm_int_arlen[9*8 +: 4]), - .AXI_09_ARSIZE(m_axi_hbm_int_arsize[9*3 +: 3]), - .AXI_09_ARVALID(m_axi_hbm_int_arvalid[9 +: 1]), - .AXI_09_ARREADY(m_axi_hbm_int_arready[9 +: 1]), - .AXI_09_RDATA_PARITY(), - .AXI_09_RDATA(m_axi_hbm_int_rdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_09_RID(m_axi_hbm_int_rid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_09_RLAST(m_axi_hbm_int_rlast[9 +: 1]), - .AXI_09_RRESP(m_axi_hbm_int_rresp[9*2 +: 2]), - .AXI_09_RVALID(m_axi_hbm_int_rvalid[9 +: 1]), - .AXI_09_RREADY(m_axi_hbm_int_rready[9 +: 1]), - .AXI_09_AWADDR(m_axi_hbm_int_awaddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_09_AWBURST(m_axi_hbm_int_awburst[9*2 +: 2]), - .AXI_09_AWID(m_axi_hbm_int_awid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_09_AWLEN(m_axi_hbm_int_awlen[9*8 +: 4]), - .AXI_09_AWSIZE(m_axi_hbm_int_awsize[9*3 +: 3]), - .AXI_09_AWVALID(m_axi_hbm_int_awvalid[9 +: 1]), - .AXI_09_AWREADY(m_axi_hbm_int_awready[9 +: 1]), - .AXI_09_WDATA(m_axi_hbm_int_wdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_09_WLAST(m_axi_hbm_int_wlast[9 +: 1]), - .AXI_09_WSTRB(m_axi_hbm_int_wstrb[9*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_09_WDATA_PARITY(32'd0), - .AXI_09_WVALID(m_axi_hbm_int_wvalid[9 +: 1]), - .AXI_09_WREADY(m_axi_hbm_int_wready[9 +: 1]), - .AXI_09_BID(m_axi_hbm_int_bid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_09_BRESP(m_axi_hbm_int_bresp[9*2 +: 2]), - .AXI_09_BVALID(m_axi_hbm_int_bvalid[9 +: 1]), - .AXI_09_BREADY(m_axi_hbm_int_bready[9 +: 1]), - - .AXI_10_ACLK(hbm_clk_int[10 +: 1]), - .AXI_10_ARESET_N(!hbm_rst_int[10 +: 1]), - - .AXI_10_ARADDR(m_axi_hbm_int_araddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_10_ARBURST(m_axi_hbm_int_arburst[10*2 +: 2]), - .AXI_10_ARID(m_axi_hbm_int_arid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_10_ARLEN(m_axi_hbm_int_arlen[10*8 +: 4]), - .AXI_10_ARSIZE(m_axi_hbm_int_arsize[10*3 +: 3]), - .AXI_10_ARVALID(m_axi_hbm_int_arvalid[10 +: 1]), - .AXI_10_ARREADY(m_axi_hbm_int_arready[10 +: 1]), - .AXI_10_RDATA_PARITY(), - .AXI_10_RDATA(m_axi_hbm_int_rdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_10_RID(m_axi_hbm_int_rid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_10_RLAST(m_axi_hbm_int_rlast[10 +: 1]), - .AXI_10_RRESP(m_axi_hbm_int_rresp[10*2 +: 2]), - .AXI_10_RVALID(m_axi_hbm_int_rvalid[10 +: 1]), - .AXI_10_RREADY(m_axi_hbm_int_rready[10 +: 1]), - .AXI_10_AWADDR(m_axi_hbm_int_awaddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_10_AWBURST(m_axi_hbm_int_awburst[10*2 +: 2]), - .AXI_10_AWID(m_axi_hbm_int_awid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_10_AWLEN(m_axi_hbm_int_awlen[10*8 +: 4]), - .AXI_10_AWSIZE(m_axi_hbm_int_awsize[10*3 +: 3]), - .AXI_10_AWVALID(m_axi_hbm_int_awvalid[10 +: 1]), - .AXI_10_AWREADY(m_axi_hbm_int_awready[10 +: 1]), - .AXI_10_WDATA(m_axi_hbm_int_wdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_10_WLAST(m_axi_hbm_int_wlast[10 +: 1]), - .AXI_10_WSTRB(m_axi_hbm_int_wstrb[10*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_10_WDATA_PARITY(32'd0), - .AXI_10_WVALID(m_axi_hbm_int_wvalid[10 +: 1]), - .AXI_10_WREADY(m_axi_hbm_int_wready[10 +: 1]), - .AXI_10_BID(m_axi_hbm_int_bid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_10_BRESP(m_axi_hbm_int_bresp[10*2 +: 2]), - .AXI_10_BVALID(m_axi_hbm_int_bvalid[10 +: 1]), - .AXI_10_BREADY(m_axi_hbm_int_bready[10 +: 1]), - - .AXI_11_ACLK(hbm_clk_int[11 +: 1]), - .AXI_11_ARESET_N(!hbm_rst_int[11 +: 1]), - - .AXI_11_ARADDR(m_axi_hbm_int_araddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_11_ARBURST(m_axi_hbm_int_arburst[11*2 +: 2]), - .AXI_11_ARID(m_axi_hbm_int_arid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_11_ARLEN(m_axi_hbm_int_arlen[11*8 +: 4]), - .AXI_11_ARSIZE(m_axi_hbm_int_arsize[11*3 +: 3]), - .AXI_11_ARVALID(m_axi_hbm_int_arvalid[11 +: 1]), - .AXI_11_ARREADY(m_axi_hbm_int_arready[11 +: 1]), - .AXI_11_RDATA_PARITY(), - .AXI_11_RDATA(m_axi_hbm_int_rdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_11_RID(m_axi_hbm_int_rid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_11_RLAST(m_axi_hbm_int_rlast[11 +: 1]), - .AXI_11_RRESP(m_axi_hbm_int_rresp[11*2 +: 2]), - .AXI_11_RVALID(m_axi_hbm_int_rvalid[11 +: 1]), - .AXI_11_RREADY(m_axi_hbm_int_rready[11 +: 1]), - .AXI_11_AWADDR(m_axi_hbm_int_awaddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_11_AWBURST(m_axi_hbm_int_awburst[11*2 +: 2]), - .AXI_11_AWID(m_axi_hbm_int_awid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_11_AWLEN(m_axi_hbm_int_awlen[11*8 +: 4]), - .AXI_11_AWSIZE(m_axi_hbm_int_awsize[11*3 +: 3]), - .AXI_11_AWVALID(m_axi_hbm_int_awvalid[11 +: 1]), - .AXI_11_AWREADY(m_axi_hbm_int_awready[11 +: 1]), - .AXI_11_WDATA(m_axi_hbm_int_wdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_11_WLAST(m_axi_hbm_int_wlast[11 +: 1]), - .AXI_11_WSTRB(m_axi_hbm_int_wstrb[11*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_11_WDATA_PARITY(32'd0), - .AXI_11_WVALID(m_axi_hbm_int_wvalid[11 +: 1]), - .AXI_11_WREADY(m_axi_hbm_int_wready[11 +: 1]), - .AXI_11_BID(m_axi_hbm_int_bid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_11_BRESP(m_axi_hbm_int_bresp[11*2 +: 2]), - .AXI_11_BVALID(m_axi_hbm_int_bvalid[11 +: 1]), - .AXI_11_BREADY(m_axi_hbm_int_bready[11 +: 1]), - - .AXI_12_ACLK(hbm_clk_int[12 +: 1]), - .AXI_12_ARESET_N(!hbm_rst_int[12 +: 1]), - - .AXI_12_ARADDR(m_axi_hbm_int_araddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_12_ARBURST(m_axi_hbm_int_arburst[12*2 +: 2]), - .AXI_12_ARID(m_axi_hbm_int_arid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_12_ARLEN(m_axi_hbm_int_arlen[12*8 +: 4]), - .AXI_12_ARSIZE(m_axi_hbm_int_arsize[12*3 +: 3]), - .AXI_12_ARVALID(m_axi_hbm_int_arvalid[12 +: 1]), - .AXI_12_ARREADY(m_axi_hbm_int_arready[12 +: 1]), - .AXI_12_RDATA_PARITY(), - .AXI_12_RDATA(m_axi_hbm_int_rdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_12_RID(m_axi_hbm_int_rid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_12_RLAST(m_axi_hbm_int_rlast[12 +: 1]), - .AXI_12_RRESP(m_axi_hbm_int_rresp[12*2 +: 2]), - .AXI_12_RVALID(m_axi_hbm_int_rvalid[12 +: 1]), - .AXI_12_RREADY(m_axi_hbm_int_rready[12 +: 1]), - .AXI_12_AWADDR(m_axi_hbm_int_awaddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_12_AWBURST(m_axi_hbm_int_awburst[12*2 +: 2]), - .AXI_12_AWID(m_axi_hbm_int_awid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_12_AWLEN(m_axi_hbm_int_awlen[12*8 +: 4]), - .AXI_12_AWSIZE(m_axi_hbm_int_awsize[12*3 +: 3]), - .AXI_12_AWVALID(m_axi_hbm_int_awvalid[12 +: 1]), - .AXI_12_AWREADY(m_axi_hbm_int_awready[12 +: 1]), - .AXI_12_WDATA(m_axi_hbm_int_wdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_12_WLAST(m_axi_hbm_int_wlast[12 +: 1]), - .AXI_12_WSTRB(m_axi_hbm_int_wstrb[12*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_12_WDATA_PARITY(32'd0), - .AXI_12_WVALID(m_axi_hbm_int_wvalid[12 +: 1]), - .AXI_12_WREADY(m_axi_hbm_int_wready[12 +: 1]), - .AXI_12_BID(m_axi_hbm_int_bid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_12_BRESP(m_axi_hbm_int_bresp[12*2 +: 2]), - .AXI_12_BVALID(m_axi_hbm_int_bvalid[12 +: 1]), - .AXI_12_BREADY(m_axi_hbm_int_bready[12 +: 1]), - - .AXI_13_ACLK(hbm_clk_int[13 +: 1]), - .AXI_13_ARESET_N(!hbm_rst_int[13 +: 1]), - - .AXI_13_ARADDR(m_axi_hbm_int_araddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_13_ARBURST(m_axi_hbm_int_arburst[13*2 +: 2]), - .AXI_13_ARID(m_axi_hbm_int_arid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_13_ARLEN(m_axi_hbm_int_arlen[13*8 +: 4]), - .AXI_13_ARSIZE(m_axi_hbm_int_arsize[13*3 +: 3]), - .AXI_13_ARVALID(m_axi_hbm_int_arvalid[13 +: 1]), - .AXI_13_ARREADY(m_axi_hbm_int_arready[13 +: 1]), - .AXI_13_RDATA_PARITY(), - .AXI_13_RDATA(m_axi_hbm_int_rdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_13_RID(m_axi_hbm_int_rid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_13_RLAST(m_axi_hbm_int_rlast[13 +: 1]), - .AXI_13_RRESP(m_axi_hbm_int_rresp[13*2 +: 2]), - .AXI_13_RVALID(m_axi_hbm_int_rvalid[13 +: 1]), - .AXI_13_RREADY(m_axi_hbm_int_rready[13 +: 1]), - .AXI_13_AWADDR(m_axi_hbm_int_awaddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_13_AWBURST(m_axi_hbm_int_awburst[13*2 +: 2]), - .AXI_13_AWID(m_axi_hbm_int_awid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_13_AWLEN(m_axi_hbm_int_awlen[13*8 +: 4]), - .AXI_13_AWSIZE(m_axi_hbm_int_awsize[13*3 +: 3]), - .AXI_13_AWVALID(m_axi_hbm_int_awvalid[13 +: 1]), - .AXI_13_AWREADY(m_axi_hbm_int_awready[13 +: 1]), - .AXI_13_WDATA(m_axi_hbm_int_wdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_13_WLAST(m_axi_hbm_int_wlast[13 +: 1]), - .AXI_13_WSTRB(m_axi_hbm_int_wstrb[13*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_13_WDATA_PARITY(32'd0), - .AXI_13_WVALID(m_axi_hbm_int_wvalid[13 +: 1]), - .AXI_13_WREADY(m_axi_hbm_int_wready[13 +: 1]), - .AXI_13_BID(m_axi_hbm_int_bid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_13_BRESP(m_axi_hbm_int_bresp[13*2 +: 2]), - .AXI_13_BVALID(m_axi_hbm_int_bvalid[13 +: 1]), - .AXI_13_BREADY(m_axi_hbm_int_bready[13 +: 1]), - - .AXI_14_ACLK(hbm_clk_int[14 +: 1]), - .AXI_14_ARESET_N(!hbm_rst_int[14 +: 1]), - - .AXI_14_ARADDR(m_axi_hbm_int_araddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_14_ARBURST(m_axi_hbm_int_arburst[14*2 +: 2]), - .AXI_14_ARID(m_axi_hbm_int_arid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_14_ARLEN(m_axi_hbm_int_arlen[14*8 +: 4]), - .AXI_14_ARSIZE(m_axi_hbm_int_arsize[14*3 +: 3]), - .AXI_14_ARVALID(m_axi_hbm_int_arvalid[14 +: 1]), - .AXI_14_ARREADY(m_axi_hbm_int_arready[14 +: 1]), - .AXI_14_RDATA_PARITY(), - .AXI_14_RDATA(m_axi_hbm_int_rdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_14_RID(m_axi_hbm_int_rid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_14_RLAST(m_axi_hbm_int_rlast[14 +: 1]), - .AXI_14_RRESP(m_axi_hbm_int_rresp[14*2 +: 2]), - .AXI_14_RVALID(m_axi_hbm_int_rvalid[14 +: 1]), - .AXI_14_RREADY(m_axi_hbm_int_rready[14 +: 1]), - .AXI_14_AWADDR(m_axi_hbm_int_awaddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_14_AWBURST(m_axi_hbm_int_awburst[14*2 +: 2]), - .AXI_14_AWID(m_axi_hbm_int_awid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_14_AWLEN(m_axi_hbm_int_awlen[14*8 +: 4]), - .AXI_14_AWSIZE(m_axi_hbm_int_awsize[14*3 +: 3]), - .AXI_14_AWVALID(m_axi_hbm_int_awvalid[14 +: 1]), - .AXI_14_AWREADY(m_axi_hbm_int_awready[14 +: 1]), - .AXI_14_WDATA(m_axi_hbm_int_wdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_14_WLAST(m_axi_hbm_int_wlast[14 +: 1]), - .AXI_14_WSTRB(m_axi_hbm_int_wstrb[14*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_14_WDATA_PARITY(32'd0), - .AXI_14_WVALID(m_axi_hbm_int_wvalid[14 +: 1]), - .AXI_14_WREADY(m_axi_hbm_int_wready[14 +: 1]), - .AXI_14_BID(m_axi_hbm_int_bid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_14_BRESP(m_axi_hbm_int_bresp[14*2 +: 2]), - .AXI_14_BVALID(m_axi_hbm_int_bvalid[14 +: 1]), - .AXI_14_BREADY(m_axi_hbm_int_bready[14 +: 1]), - - .AXI_15_ACLK(hbm_clk_int[15 +: 1]), - .AXI_15_ARESET_N(!hbm_rst_int[15 +: 1]), - - .AXI_15_ARADDR(m_axi_hbm_int_araddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_15_ARBURST(m_axi_hbm_int_arburst[15*2 +: 2]), - .AXI_15_ARID(m_axi_hbm_int_arid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_15_ARLEN(m_axi_hbm_int_arlen[15*8 +: 4]), - .AXI_15_ARSIZE(m_axi_hbm_int_arsize[15*3 +: 3]), - .AXI_15_ARVALID(m_axi_hbm_int_arvalid[15 +: 1]), - .AXI_15_ARREADY(m_axi_hbm_int_arready[15 +: 1]), - .AXI_15_RDATA_PARITY(), - .AXI_15_RDATA(m_axi_hbm_int_rdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_15_RID(m_axi_hbm_int_rid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_15_RLAST(m_axi_hbm_int_rlast[15 +: 1]), - .AXI_15_RRESP(m_axi_hbm_int_rresp[15*2 +: 2]), - .AXI_15_RVALID(m_axi_hbm_int_rvalid[15 +: 1]), - .AXI_15_RREADY(m_axi_hbm_int_rready[15 +: 1]), - .AXI_15_AWADDR(m_axi_hbm_int_awaddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_15_AWBURST(m_axi_hbm_int_awburst[15*2 +: 2]), - .AXI_15_AWID(m_axi_hbm_int_awid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_15_AWLEN(m_axi_hbm_int_awlen[15*8 +: 4]), - .AXI_15_AWSIZE(m_axi_hbm_int_awsize[15*3 +: 3]), - .AXI_15_AWVALID(m_axi_hbm_int_awvalid[15 +: 1]), - .AXI_15_AWREADY(m_axi_hbm_int_awready[15 +: 1]), - .AXI_15_WDATA(m_axi_hbm_int_wdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_15_WLAST(m_axi_hbm_int_wlast[15 +: 1]), - .AXI_15_WSTRB(m_axi_hbm_int_wstrb[15*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_15_WDATA_PARITY(32'd0), - .AXI_15_WVALID(m_axi_hbm_int_wvalid[15 +: 1]), - .AXI_15_WREADY(m_axi_hbm_int_wready[15 +: 1]), - .AXI_15_BID(m_axi_hbm_int_bid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_15_BRESP(m_axi_hbm_int_bresp[15*2 +: 2]), - .AXI_15_BVALID(m_axi_hbm_int_bvalid[15 +: 1]), - .AXI_15_BREADY(m_axi_hbm_int_bready[15 +: 1]), - - .AXI_16_ACLK(hbm_clk_int[16 +: 1]), - .AXI_16_ARESET_N(!hbm_rst_int[16 +: 1]), - - .AXI_16_ARADDR(m_axi_hbm_int_araddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_16_ARBURST(m_axi_hbm_int_arburst[16*2 +: 2]), - .AXI_16_ARID(m_axi_hbm_int_arid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_16_ARLEN(m_axi_hbm_int_arlen[16*8 +: 4]), - .AXI_16_ARSIZE(m_axi_hbm_int_arsize[16*3 +: 3]), - .AXI_16_ARVALID(m_axi_hbm_int_arvalid[16 +: 1]), - .AXI_16_ARREADY(m_axi_hbm_int_arready[16 +: 1]), - .AXI_16_RDATA_PARITY(), - .AXI_16_RDATA(m_axi_hbm_int_rdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_16_RID(m_axi_hbm_int_rid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_16_RLAST(m_axi_hbm_int_rlast[16 +: 1]), - .AXI_16_RRESP(m_axi_hbm_int_rresp[16*2 +: 2]), - .AXI_16_RVALID(m_axi_hbm_int_rvalid[16 +: 1]), - .AXI_16_RREADY(m_axi_hbm_int_rready[16 +: 1]), - .AXI_16_AWADDR(m_axi_hbm_int_awaddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_16_AWBURST(m_axi_hbm_int_awburst[16*2 +: 2]), - .AXI_16_AWID(m_axi_hbm_int_awid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_16_AWLEN(m_axi_hbm_int_awlen[16*8 +: 4]), - .AXI_16_AWSIZE(m_axi_hbm_int_awsize[16*3 +: 3]), - .AXI_16_AWVALID(m_axi_hbm_int_awvalid[16 +: 1]), - .AXI_16_AWREADY(m_axi_hbm_int_awready[16 +: 1]), - .AXI_16_WDATA(m_axi_hbm_int_wdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_16_WLAST(m_axi_hbm_int_wlast[16 +: 1]), - .AXI_16_WSTRB(m_axi_hbm_int_wstrb[16*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_16_WDATA_PARITY(32'd0), - .AXI_16_WVALID(m_axi_hbm_int_wvalid[16 +: 1]), - .AXI_16_WREADY(m_axi_hbm_int_wready[16 +: 1]), - .AXI_16_BID(m_axi_hbm_int_bid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_16_BRESP(m_axi_hbm_int_bresp[16*2 +: 2]), - .AXI_16_BVALID(m_axi_hbm_int_bvalid[16 +: 1]), - .AXI_16_BREADY(m_axi_hbm_int_bready[16 +: 1]), - - .AXI_17_ACLK(hbm_clk_int[17 +: 1]), - .AXI_17_ARESET_N(!hbm_rst_int[17 +: 1]), - - .AXI_17_ARADDR(m_axi_hbm_int_araddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_17_ARBURST(m_axi_hbm_int_arburst[17*2 +: 2]), - .AXI_17_ARID(m_axi_hbm_int_arid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_17_ARLEN(m_axi_hbm_int_arlen[17*8 +: 4]), - .AXI_17_ARSIZE(m_axi_hbm_int_arsize[17*3 +: 3]), - .AXI_17_ARVALID(m_axi_hbm_int_arvalid[17 +: 1]), - .AXI_17_ARREADY(m_axi_hbm_int_arready[17 +: 1]), - .AXI_17_RDATA_PARITY(), - .AXI_17_RDATA(m_axi_hbm_int_rdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_17_RID(m_axi_hbm_int_rid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_17_RLAST(m_axi_hbm_int_rlast[17 +: 1]), - .AXI_17_RRESP(m_axi_hbm_int_rresp[17*2 +: 2]), - .AXI_17_RVALID(m_axi_hbm_int_rvalid[17 +: 1]), - .AXI_17_RREADY(m_axi_hbm_int_rready[17 +: 1]), - .AXI_17_AWADDR(m_axi_hbm_int_awaddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_17_AWBURST(m_axi_hbm_int_awburst[17*2 +: 2]), - .AXI_17_AWID(m_axi_hbm_int_awid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_17_AWLEN(m_axi_hbm_int_awlen[17*8 +: 4]), - .AXI_17_AWSIZE(m_axi_hbm_int_awsize[17*3 +: 3]), - .AXI_17_AWVALID(m_axi_hbm_int_awvalid[17 +: 1]), - .AXI_17_AWREADY(m_axi_hbm_int_awready[17 +: 1]), - .AXI_17_WDATA(m_axi_hbm_int_wdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_17_WLAST(m_axi_hbm_int_wlast[17 +: 1]), - .AXI_17_WSTRB(m_axi_hbm_int_wstrb[17*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_17_WDATA_PARITY(32'd0), - .AXI_17_WVALID(m_axi_hbm_int_wvalid[17 +: 1]), - .AXI_17_WREADY(m_axi_hbm_int_wready[17 +: 1]), - .AXI_17_BID(m_axi_hbm_int_bid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_17_BRESP(m_axi_hbm_int_bresp[17*2 +: 2]), - .AXI_17_BVALID(m_axi_hbm_int_bvalid[17 +: 1]), - .AXI_17_BREADY(m_axi_hbm_int_bready[17 +: 1]), - - .AXI_18_ACLK(hbm_clk_int[18 +: 1]), - .AXI_18_ARESET_N(!hbm_rst_int[18 +: 1]), - - .AXI_18_ARADDR(m_axi_hbm_int_araddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_18_ARBURST(m_axi_hbm_int_arburst[18*2 +: 2]), - .AXI_18_ARID(m_axi_hbm_int_arid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_18_ARLEN(m_axi_hbm_int_arlen[18*8 +: 4]), - .AXI_18_ARSIZE(m_axi_hbm_int_arsize[18*3 +: 3]), - .AXI_18_ARVALID(m_axi_hbm_int_arvalid[18 +: 1]), - .AXI_18_ARREADY(m_axi_hbm_int_arready[18 +: 1]), - .AXI_18_RDATA_PARITY(), - .AXI_18_RDATA(m_axi_hbm_int_rdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_18_RID(m_axi_hbm_int_rid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_18_RLAST(m_axi_hbm_int_rlast[18 +: 1]), - .AXI_18_RRESP(m_axi_hbm_int_rresp[18*2 +: 2]), - .AXI_18_RVALID(m_axi_hbm_int_rvalid[18 +: 1]), - .AXI_18_RREADY(m_axi_hbm_int_rready[18 +: 1]), - .AXI_18_AWADDR(m_axi_hbm_int_awaddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_18_AWBURST(m_axi_hbm_int_awburst[18*2 +: 2]), - .AXI_18_AWID(m_axi_hbm_int_awid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_18_AWLEN(m_axi_hbm_int_awlen[18*8 +: 4]), - .AXI_18_AWSIZE(m_axi_hbm_int_awsize[18*3 +: 3]), - .AXI_18_AWVALID(m_axi_hbm_int_awvalid[18 +: 1]), - .AXI_18_AWREADY(m_axi_hbm_int_awready[18 +: 1]), - .AXI_18_WDATA(m_axi_hbm_int_wdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_18_WLAST(m_axi_hbm_int_wlast[18 +: 1]), - .AXI_18_WSTRB(m_axi_hbm_int_wstrb[18*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_18_WDATA_PARITY(32'd0), - .AXI_18_WVALID(m_axi_hbm_int_wvalid[18 +: 1]), - .AXI_18_WREADY(m_axi_hbm_int_wready[18 +: 1]), - .AXI_18_BID(m_axi_hbm_int_bid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_18_BRESP(m_axi_hbm_int_bresp[18*2 +: 2]), - .AXI_18_BVALID(m_axi_hbm_int_bvalid[18 +: 1]), - .AXI_18_BREADY(m_axi_hbm_int_bready[18 +: 1]), - - .AXI_19_ACLK(hbm_clk_int[19 +: 1]), - .AXI_19_ARESET_N(!hbm_rst_int[19 +: 1]), - - .AXI_19_ARADDR(m_axi_hbm_int_araddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_19_ARBURST(m_axi_hbm_int_arburst[19*2 +: 2]), - .AXI_19_ARID(m_axi_hbm_int_arid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_19_ARLEN(m_axi_hbm_int_arlen[19*8 +: 4]), - .AXI_19_ARSIZE(m_axi_hbm_int_arsize[19*3 +: 3]), - .AXI_19_ARVALID(m_axi_hbm_int_arvalid[19 +: 1]), - .AXI_19_ARREADY(m_axi_hbm_int_arready[19 +: 1]), - .AXI_19_RDATA_PARITY(), - .AXI_19_RDATA(m_axi_hbm_int_rdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_19_RID(m_axi_hbm_int_rid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_19_RLAST(m_axi_hbm_int_rlast[19 +: 1]), - .AXI_19_RRESP(m_axi_hbm_int_rresp[19*2 +: 2]), - .AXI_19_RVALID(m_axi_hbm_int_rvalid[19 +: 1]), - .AXI_19_RREADY(m_axi_hbm_int_rready[19 +: 1]), - .AXI_19_AWADDR(m_axi_hbm_int_awaddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_19_AWBURST(m_axi_hbm_int_awburst[19*2 +: 2]), - .AXI_19_AWID(m_axi_hbm_int_awid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_19_AWLEN(m_axi_hbm_int_awlen[19*8 +: 4]), - .AXI_19_AWSIZE(m_axi_hbm_int_awsize[19*3 +: 3]), - .AXI_19_AWVALID(m_axi_hbm_int_awvalid[19 +: 1]), - .AXI_19_AWREADY(m_axi_hbm_int_awready[19 +: 1]), - .AXI_19_WDATA(m_axi_hbm_int_wdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_19_WLAST(m_axi_hbm_int_wlast[19 +: 1]), - .AXI_19_WSTRB(m_axi_hbm_int_wstrb[19*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_19_WDATA_PARITY(32'd0), - .AXI_19_WVALID(m_axi_hbm_int_wvalid[19 +: 1]), - .AXI_19_WREADY(m_axi_hbm_int_wready[19 +: 1]), - .AXI_19_BID(m_axi_hbm_int_bid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_19_BRESP(m_axi_hbm_int_bresp[19*2 +: 2]), - .AXI_19_BVALID(m_axi_hbm_int_bvalid[19 +: 1]), - .AXI_19_BREADY(m_axi_hbm_int_bready[19 +: 1]), - - .AXI_20_ACLK(hbm_clk_int[20 +: 1]), - .AXI_20_ARESET_N(!hbm_rst_int[20 +: 1]), - - .AXI_20_ARADDR(m_axi_hbm_int_araddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_20_ARBURST(m_axi_hbm_int_arburst[20*2 +: 2]), - .AXI_20_ARID(m_axi_hbm_int_arid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_20_ARLEN(m_axi_hbm_int_arlen[20*8 +: 4]), - .AXI_20_ARSIZE(m_axi_hbm_int_arsize[20*3 +: 3]), - .AXI_20_ARVALID(m_axi_hbm_int_arvalid[20 +: 1]), - .AXI_20_ARREADY(m_axi_hbm_int_arready[20 +: 1]), - .AXI_20_RDATA_PARITY(), - .AXI_20_RDATA(m_axi_hbm_int_rdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_20_RID(m_axi_hbm_int_rid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_20_RLAST(m_axi_hbm_int_rlast[20 +: 1]), - .AXI_20_RRESP(m_axi_hbm_int_rresp[20*2 +: 2]), - .AXI_20_RVALID(m_axi_hbm_int_rvalid[20 +: 1]), - .AXI_20_RREADY(m_axi_hbm_int_rready[20 +: 1]), - .AXI_20_AWADDR(m_axi_hbm_int_awaddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_20_AWBURST(m_axi_hbm_int_awburst[20*2 +: 2]), - .AXI_20_AWID(m_axi_hbm_int_awid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_20_AWLEN(m_axi_hbm_int_awlen[20*8 +: 4]), - .AXI_20_AWSIZE(m_axi_hbm_int_awsize[20*3 +: 3]), - .AXI_20_AWVALID(m_axi_hbm_int_awvalid[20 +: 1]), - .AXI_20_AWREADY(m_axi_hbm_int_awready[20 +: 1]), - .AXI_20_WDATA(m_axi_hbm_int_wdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_20_WLAST(m_axi_hbm_int_wlast[20 +: 1]), - .AXI_20_WSTRB(m_axi_hbm_int_wstrb[20*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_20_WDATA_PARITY(32'd0), - .AXI_20_WVALID(m_axi_hbm_int_wvalid[20 +: 1]), - .AXI_20_WREADY(m_axi_hbm_int_wready[20 +: 1]), - .AXI_20_BID(m_axi_hbm_int_bid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_20_BRESP(m_axi_hbm_int_bresp[20*2 +: 2]), - .AXI_20_BVALID(m_axi_hbm_int_bvalid[20 +: 1]), - .AXI_20_BREADY(m_axi_hbm_int_bready[20 +: 1]), - - .AXI_21_ACLK(hbm_clk_int[21 +: 1]), - .AXI_21_ARESET_N(!hbm_rst_int[21 +: 1]), - - .AXI_21_ARADDR(m_axi_hbm_int_araddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_21_ARBURST(m_axi_hbm_int_arburst[21*2 +: 2]), - .AXI_21_ARID(m_axi_hbm_int_arid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_21_ARLEN(m_axi_hbm_int_arlen[21*8 +: 4]), - .AXI_21_ARSIZE(m_axi_hbm_int_arsize[21*3 +: 3]), - .AXI_21_ARVALID(m_axi_hbm_int_arvalid[21 +: 1]), - .AXI_21_ARREADY(m_axi_hbm_int_arready[21 +: 1]), - .AXI_21_RDATA_PARITY(), - .AXI_21_RDATA(m_axi_hbm_int_rdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_21_RID(m_axi_hbm_int_rid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_21_RLAST(m_axi_hbm_int_rlast[21 +: 1]), - .AXI_21_RRESP(m_axi_hbm_int_rresp[21*2 +: 2]), - .AXI_21_RVALID(m_axi_hbm_int_rvalid[21 +: 1]), - .AXI_21_RREADY(m_axi_hbm_int_rready[21 +: 1]), - .AXI_21_AWADDR(m_axi_hbm_int_awaddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_21_AWBURST(m_axi_hbm_int_awburst[21*2 +: 2]), - .AXI_21_AWID(m_axi_hbm_int_awid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_21_AWLEN(m_axi_hbm_int_awlen[21*8 +: 4]), - .AXI_21_AWSIZE(m_axi_hbm_int_awsize[21*3 +: 3]), - .AXI_21_AWVALID(m_axi_hbm_int_awvalid[21 +: 1]), - .AXI_21_AWREADY(m_axi_hbm_int_awready[21 +: 1]), - .AXI_21_WDATA(m_axi_hbm_int_wdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_21_WLAST(m_axi_hbm_int_wlast[21 +: 1]), - .AXI_21_WSTRB(m_axi_hbm_int_wstrb[21*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_21_WDATA_PARITY(32'd0), - .AXI_21_WVALID(m_axi_hbm_int_wvalid[21 +: 1]), - .AXI_21_WREADY(m_axi_hbm_int_wready[21 +: 1]), - .AXI_21_BID(m_axi_hbm_int_bid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_21_BRESP(m_axi_hbm_int_bresp[21*2 +: 2]), - .AXI_21_BVALID(m_axi_hbm_int_bvalid[21 +: 1]), - .AXI_21_BREADY(m_axi_hbm_int_bready[21 +: 1]), - - .AXI_22_ACLK(hbm_clk_int[22 +: 1]), - .AXI_22_ARESET_N(!hbm_rst_int[22 +: 1]), - - .AXI_22_ARADDR(m_axi_hbm_int_araddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_22_ARBURST(m_axi_hbm_int_arburst[22*2 +: 2]), - .AXI_22_ARID(m_axi_hbm_int_arid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_22_ARLEN(m_axi_hbm_int_arlen[22*8 +: 4]), - .AXI_22_ARSIZE(m_axi_hbm_int_arsize[22*3 +: 3]), - .AXI_22_ARVALID(m_axi_hbm_int_arvalid[22 +: 1]), - .AXI_22_ARREADY(m_axi_hbm_int_arready[22 +: 1]), - .AXI_22_RDATA_PARITY(), - .AXI_22_RDATA(m_axi_hbm_int_rdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_22_RID(m_axi_hbm_int_rid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_22_RLAST(m_axi_hbm_int_rlast[22 +: 1]), - .AXI_22_RRESP(m_axi_hbm_int_rresp[22*2 +: 2]), - .AXI_22_RVALID(m_axi_hbm_int_rvalid[22 +: 1]), - .AXI_22_RREADY(m_axi_hbm_int_rready[22 +: 1]), - .AXI_22_AWADDR(m_axi_hbm_int_awaddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_22_AWBURST(m_axi_hbm_int_awburst[22*2 +: 2]), - .AXI_22_AWID(m_axi_hbm_int_awid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_22_AWLEN(m_axi_hbm_int_awlen[22*8 +: 4]), - .AXI_22_AWSIZE(m_axi_hbm_int_awsize[22*3 +: 3]), - .AXI_22_AWVALID(m_axi_hbm_int_awvalid[22 +: 1]), - .AXI_22_AWREADY(m_axi_hbm_int_awready[22 +: 1]), - .AXI_22_WDATA(m_axi_hbm_int_wdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_22_WLAST(m_axi_hbm_int_wlast[22 +: 1]), - .AXI_22_WSTRB(m_axi_hbm_int_wstrb[22*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_22_WDATA_PARITY(32'd0), - .AXI_22_WVALID(m_axi_hbm_int_wvalid[22 +: 1]), - .AXI_22_WREADY(m_axi_hbm_int_wready[22 +: 1]), - .AXI_22_BID(m_axi_hbm_int_bid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_22_BRESP(m_axi_hbm_int_bresp[22*2 +: 2]), - .AXI_22_BVALID(m_axi_hbm_int_bvalid[22 +: 1]), - .AXI_22_BREADY(m_axi_hbm_int_bready[22 +: 1]), - - .AXI_23_ACLK(hbm_clk_int[23 +: 1]), - .AXI_23_ARESET_N(!hbm_rst_int[23 +: 1]), - - .AXI_23_ARADDR(m_axi_hbm_int_araddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_23_ARBURST(m_axi_hbm_int_arburst[23*2 +: 2]), - .AXI_23_ARID(m_axi_hbm_int_arid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_23_ARLEN(m_axi_hbm_int_arlen[23*8 +: 4]), - .AXI_23_ARSIZE(m_axi_hbm_int_arsize[23*3 +: 3]), - .AXI_23_ARVALID(m_axi_hbm_int_arvalid[23 +: 1]), - .AXI_23_ARREADY(m_axi_hbm_int_arready[23 +: 1]), - .AXI_23_RDATA_PARITY(), - .AXI_23_RDATA(m_axi_hbm_int_rdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_23_RID(m_axi_hbm_int_rid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_23_RLAST(m_axi_hbm_int_rlast[23 +: 1]), - .AXI_23_RRESP(m_axi_hbm_int_rresp[23*2 +: 2]), - .AXI_23_RVALID(m_axi_hbm_int_rvalid[23 +: 1]), - .AXI_23_RREADY(m_axi_hbm_int_rready[23 +: 1]), - .AXI_23_AWADDR(m_axi_hbm_int_awaddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_23_AWBURST(m_axi_hbm_int_awburst[23*2 +: 2]), - .AXI_23_AWID(m_axi_hbm_int_awid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_23_AWLEN(m_axi_hbm_int_awlen[23*8 +: 4]), - .AXI_23_AWSIZE(m_axi_hbm_int_awsize[23*3 +: 3]), - .AXI_23_AWVALID(m_axi_hbm_int_awvalid[23 +: 1]), - .AXI_23_AWREADY(m_axi_hbm_int_awready[23 +: 1]), - .AXI_23_WDATA(m_axi_hbm_int_wdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_23_WLAST(m_axi_hbm_int_wlast[23 +: 1]), - .AXI_23_WSTRB(m_axi_hbm_int_wstrb[23*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_23_WDATA_PARITY(32'd0), - .AXI_23_WVALID(m_axi_hbm_int_wvalid[23 +: 1]), - .AXI_23_WREADY(m_axi_hbm_int_wready[23 +: 1]), - .AXI_23_BID(m_axi_hbm_int_bid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_23_BRESP(m_axi_hbm_int_bresp[23*2 +: 2]), - .AXI_23_BVALID(m_axi_hbm_int_bvalid[23 +: 1]), - .AXI_23_BREADY(m_axi_hbm_int_bready[23 +: 1]), - - .AXI_24_ACLK(hbm_clk_int[24 +: 1]), - .AXI_24_ARESET_N(!hbm_rst_int[24 +: 1]), - - .AXI_24_ARADDR(m_axi_hbm_int_araddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_24_ARBURST(m_axi_hbm_int_arburst[24*2 +: 2]), - .AXI_24_ARID(m_axi_hbm_int_arid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_24_ARLEN(m_axi_hbm_int_arlen[24*8 +: 4]), - .AXI_24_ARSIZE(m_axi_hbm_int_arsize[24*3 +: 3]), - .AXI_24_ARVALID(m_axi_hbm_int_arvalid[24 +: 1]), - .AXI_24_ARREADY(m_axi_hbm_int_arready[24 +: 1]), - .AXI_24_RDATA_PARITY(), - .AXI_24_RDATA(m_axi_hbm_int_rdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_24_RID(m_axi_hbm_int_rid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_24_RLAST(m_axi_hbm_int_rlast[24 +: 1]), - .AXI_24_RRESP(m_axi_hbm_int_rresp[24*2 +: 2]), - .AXI_24_RVALID(m_axi_hbm_int_rvalid[24 +: 1]), - .AXI_24_RREADY(m_axi_hbm_int_rready[24 +: 1]), - .AXI_24_AWADDR(m_axi_hbm_int_awaddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_24_AWBURST(m_axi_hbm_int_awburst[24*2 +: 2]), - .AXI_24_AWID(m_axi_hbm_int_awid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_24_AWLEN(m_axi_hbm_int_awlen[24*8 +: 4]), - .AXI_24_AWSIZE(m_axi_hbm_int_awsize[24*3 +: 3]), - .AXI_24_AWVALID(m_axi_hbm_int_awvalid[24 +: 1]), - .AXI_24_AWREADY(m_axi_hbm_int_awready[24 +: 1]), - .AXI_24_WDATA(m_axi_hbm_int_wdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_24_WLAST(m_axi_hbm_int_wlast[24 +: 1]), - .AXI_24_WSTRB(m_axi_hbm_int_wstrb[24*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_24_WDATA_PARITY(32'd0), - .AXI_24_WVALID(m_axi_hbm_int_wvalid[24 +: 1]), - .AXI_24_WREADY(m_axi_hbm_int_wready[24 +: 1]), - .AXI_24_BID(m_axi_hbm_int_bid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_24_BRESP(m_axi_hbm_int_bresp[24*2 +: 2]), - .AXI_24_BVALID(m_axi_hbm_int_bvalid[24 +: 1]), - .AXI_24_BREADY(m_axi_hbm_int_bready[24 +: 1]), - - .AXI_25_ACLK(hbm_clk_int[25 +: 1]), - .AXI_25_ARESET_N(!hbm_rst_int[25 +: 1]), - - .AXI_25_ARADDR(m_axi_hbm_int_araddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_25_ARBURST(m_axi_hbm_int_arburst[25*2 +: 2]), - .AXI_25_ARID(m_axi_hbm_int_arid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_25_ARLEN(m_axi_hbm_int_arlen[25*8 +: 4]), - .AXI_25_ARSIZE(m_axi_hbm_int_arsize[25*3 +: 3]), - .AXI_25_ARVALID(m_axi_hbm_int_arvalid[25 +: 1]), - .AXI_25_ARREADY(m_axi_hbm_int_arready[25 +: 1]), - .AXI_25_RDATA_PARITY(), - .AXI_25_RDATA(m_axi_hbm_int_rdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_25_RID(m_axi_hbm_int_rid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_25_RLAST(m_axi_hbm_int_rlast[25 +: 1]), - .AXI_25_RRESP(m_axi_hbm_int_rresp[25*2 +: 2]), - .AXI_25_RVALID(m_axi_hbm_int_rvalid[25 +: 1]), - .AXI_25_RREADY(m_axi_hbm_int_rready[25 +: 1]), - .AXI_25_AWADDR(m_axi_hbm_int_awaddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_25_AWBURST(m_axi_hbm_int_awburst[25*2 +: 2]), - .AXI_25_AWID(m_axi_hbm_int_awid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_25_AWLEN(m_axi_hbm_int_awlen[25*8 +: 4]), - .AXI_25_AWSIZE(m_axi_hbm_int_awsize[25*3 +: 3]), - .AXI_25_AWVALID(m_axi_hbm_int_awvalid[25 +: 1]), - .AXI_25_AWREADY(m_axi_hbm_int_awready[25 +: 1]), - .AXI_25_WDATA(m_axi_hbm_int_wdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_25_WLAST(m_axi_hbm_int_wlast[25 +: 1]), - .AXI_25_WSTRB(m_axi_hbm_int_wstrb[25*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_25_WDATA_PARITY(32'd0), - .AXI_25_WVALID(m_axi_hbm_int_wvalid[25 +: 1]), - .AXI_25_WREADY(m_axi_hbm_int_wready[25 +: 1]), - .AXI_25_BID(m_axi_hbm_int_bid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_25_BRESP(m_axi_hbm_int_bresp[25*2 +: 2]), - .AXI_25_BVALID(m_axi_hbm_int_bvalid[25 +: 1]), - .AXI_25_BREADY(m_axi_hbm_int_bready[25 +: 1]), - - .AXI_26_ACLK(hbm_clk_int[26 +: 1]), - .AXI_26_ARESET_N(!hbm_rst_int[26 +: 1]), - - .AXI_26_ARADDR(m_axi_hbm_int_araddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_26_ARBURST(m_axi_hbm_int_arburst[26*2 +: 2]), - .AXI_26_ARID(m_axi_hbm_int_arid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_26_ARLEN(m_axi_hbm_int_arlen[26*8 +: 4]), - .AXI_26_ARSIZE(m_axi_hbm_int_arsize[26*3 +: 3]), - .AXI_26_ARVALID(m_axi_hbm_int_arvalid[26 +: 1]), - .AXI_26_ARREADY(m_axi_hbm_int_arready[26 +: 1]), - .AXI_26_RDATA_PARITY(), - .AXI_26_RDATA(m_axi_hbm_int_rdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_26_RID(m_axi_hbm_int_rid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_26_RLAST(m_axi_hbm_int_rlast[26 +: 1]), - .AXI_26_RRESP(m_axi_hbm_int_rresp[26*2 +: 2]), - .AXI_26_RVALID(m_axi_hbm_int_rvalid[26 +: 1]), - .AXI_26_RREADY(m_axi_hbm_int_rready[26 +: 1]), - .AXI_26_AWADDR(m_axi_hbm_int_awaddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_26_AWBURST(m_axi_hbm_int_awburst[26*2 +: 2]), - .AXI_26_AWID(m_axi_hbm_int_awid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_26_AWLEN(m_axi_hbm_int_awlen[26*8 +: 4]), - .AXI_26_AWSIZE(m_axi_hbm_int_awsize[26*3 +: 3]), - .AXI_26_AWVALID(m_axi_hbm_int_awvalid[26 +: 1]), - .AXI_26_AWREADY(m_axi_hbm_int_awready[26 +: 1]), - .AXI_26_WDATA(m_axi_hbm_int_wdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_26_WLAST(m_axi_hbm_int_wlast[26 +: 1]), - .AXI_26_WSTRB(m_axi_hbm_int_wstrb[26*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_26_WDATA_PARITY(32'd0), - .AXI_26_WVALID(m_axi_hbm_int_wvalid[26 +: 1]), - .AXI_26_WREADY(m_axi_hbm_int_wready[26 +: 1]), - .AXI_26_BID(m_axi_hbm_int_bid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_26_BRESP(m_axi_hbm_int_bresp[26*2 +: 2]), - .AXI_26_BVALID(m_axi_hbm_int_bvalid[26 +: 1]), - .AXI_26_BREADY(m_axi_hbm_int_bready[26 +: 1]), - - .AXI_27_ACLK(hbm_clk_int[27 +: 1]), - .AXI_27_ARESET_N(!hbm_rst_int[27 +: 1]), - - .AXI_27_ARADDR(m_axi_hbm_int_araddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_27_ARBURST(m_axi_hbm_int_arburst[27*2 +: 2]), - .AXI_27_ARID(m_axi_hbm_int_arid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_27_ARLEN(m_axi_hbm_int_arlen[27*8 +: 4]), - .AXI_27_ARSIZE(m_axi_hbm_int_arsize[27*3 +: 3]), - .AXI_27_ARVALID(m_axi_hbm_int_arvalid[27 +: 1]), - .AXI_27_ARREADY(m_axi_hbm_int_arready[27 +: 1]), - .AXI_27_RDATA_PARITY(), - .AXI_27_RDATA(m_axi_hbm_int_rdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_27_RID(m_axi_hbm_int_rid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_27_RLAST(m_axi_hbm_int_rlast[27 +: 1]), - .AXI_27_RRESP(m_axi_hbm_int_rresp[27*2 +: 2]), - .AXI_27_RVALID(m_axi_hbm_int_rvalid[27 +: 1]), - .AXI_27_RREADY(m_axi_hbm_int_rready[27 +: 1]), - .AXI_27_AWADDR(m_axi_hbm_int_awaddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_27_AWBURST(m_axi_hbm_int_awburst[27*2 +: 2]), - .AXI_27_AWID(m_axi_hbm_int_awid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_27_AWLEN(m_axi_hbm_int_awlen[27*8 +: 4]), - .AXI_27_AWSIZE(m_axi_hbm_int_awsize[27*3 +: 3]), - .AXI_27_AWVALID(m_axi_hbm_int_awvalid[27 +: 1]), - .AXI_27_AWREADY(m_axi_hbm_int_awready[27 +: 1]), - .AXI_27_WDATA(m_axi_hbm_int_wdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_27_WLAST(m_axi_hbm_int_wlast[27 +: 1]), - .AXI_27_WSTRB(m_axi_hbm_int_wstrb[27*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_27_WDATA_PARITY(32'd0), - .AXI_27_WVALID(m_axi_hbm_int_wvalid[27 +: 1]), - .AXI_27_WREADY(m_axi_hbm_int_wready[27 +: 1]), - .AXI_27_BID(m_axi_hbm_int_bid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_27_BRESP(m_axi_hbm_int_bresp[27*2 +: 2]), - .AXI_27_BVALID(m_axi_hbm_int_bvalid[27 +: 1]), - .AXI_27_BREADY(m_axi_hbm_int_bready[27 +: 1]), - - .AXI_28_ACLK(hbm_clk_int[28 +: 1]), - .AXI_28_ARESET_N(!hbm_rst_int[28 +: 1]), - - .AXI_28_ARADDR(m_axi_hbm_int_araddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_28_ARBURST(m_axi_hbm_int_arburst[28*2 +: 2]), - .AXI_28_ARID(m_axi_hbm_int_arid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_28_ARLEN(m_axi_hbm_int_arlen[28*8 +: 4]), - .AXI_28_ARSIZE(m_axi_hbm_int_arsize[28*3 +: 3]), - .AXI_28_ARVALID(m_axi_hbm_int_arvalid[28 +: 1]), - .AXI_28_ARREADY(m_axi_hbm_int_arready[28 +: 1]), - .AXI_28_RDATA_PARITY(), - .AXI_28_RDATA(m_axi_hbm_int_rdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_28_RID(m_axi_hbm_int_rid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_28_RLAST(m_axi_hbm_int_rlast[28 +: 1]), - .AXI_28_RRESP(m_axi_hbm_int_rresp[28*2 +: 2]), - .AXI_28_RVALID(m_axi_hbm_int_rvalid[28 +: 1]), - .AXI_28_RREADY(m_axi_hbm_int_rready[28 +: 1]), - .AXI_28_AWADDR(m_axi_hbm_int_awaddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_28_AWBURST(m_axi_hbm_int_awburst[28*2 +: 2]), - .AXI_28_AWID(m_axi_hbm_int_awid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_28_AWLEN(m_axi_hbm_int_awlen[28*8 +: 4]), - .AXI_28_AWSIZE(m_axi_hbm_int_awsize[28*3 +: 3]), - .AXI_28_AWVALID(m_axi_hbm_int_awvalid[28 +: 1]), - .AXI_28_AWREADY(m_axi_hbm_int_awready[28 +: 1]), - .AXI_28_WDATA(m_axi_hbm_int_wdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_28_WLAST(m_axi_hbm_int_wlast[28 +: 1]), - .AXI_28_WSTRB(m_axi_hbm_int_wstrb[28*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_28_WDATA_PARITY(32'd0), - .AXI_28_WVALID(m_axi_hbm_int_wvalid[28 +: 1]), - .AXI_28_WREADY(m_axi_hbm_int_wready[28 +: 1]), - .AXI_28_BID(m_axi_hbm_int_bid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_28_BRESP(m_axi_hbm_int_bresp[28*2 +: 2]), - .AXI_28_BVALID(m_axi_hbm_int_bvalid[28 +: 1]), - .AXI_28_BREADY(m_axi_hbm_int_bready[28 +: 1]), - - .AXI_29_ACLK(hbm_clk_int[29 +: 1]), - .AXI_29_ARESET_N(!hbm_rst_int[29 +: 1]), - - .AXI_29_ARADDR(m_axi_hbm_int_araddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_29_ARBURST(m_axi_hbm_int_arburst[29*2 +: 2]), - .AXI_29_ARID(m_axi_hbm_int_arid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_29_ARLEN(m_axi_hbm_int_arlen[29*8 +: 4]), - .AXI_29_ARSIZE(m_axi_hbm_int_arsize[29*3 +: 3]), - .AXI_29_ARVALID(m_axi_hbm_int_arvalid[29 +: 1]), - .AXI_29_ARREADY(m_axi_hbm_int_arready[29 +: 1]), - .AXI_29_RDATA_PARITY(), - .AXI_29_RDATA(m_axi_hbm_int_rdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_29_RID(m_axi_hbm_int_rid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_29_RLAST(m_axi_hbm_int_rlast[29 +: 1]), - .AXI_29_RRESP(m_axi_hbm_int_rresp[29*2 +: 2]), - .AXI_29_RVALID(m_axi_hbm_int_rvalid[29 +: 1]), - .AXI_29_RREADY(m_axi_hbm_int_rready[29 +: 1]), - .AXI_29_AWADDR(m_axi_hbm_int_awaddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_29_AWBURST(m_axi_hbm_int_awburst[29*2 +: 2]), - .AXI_29_AWID(m_axi_hbm_int_awid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_29_AWLEN(m_axi_hbm_int_awlen[29*8 +: 4]), - .AXI_29_AWSIZE(m_axi_hbm_int_awsize[29*3 +: 3]), - .AXI_29_AWVALID(m_axi_hbm_int_awvalid[29 +: 1]), - .AXI_29_AWREADY(m_axi_hbm_int_awready[29 +: 1]), - .AXI_29_WDATA(m_axi_hbm_int_wdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_29_WLAST(m_axi_hbm_int_wlast[29 +: 1]), - .AXI_29_WSTRB(m_axi_hbm_int_wstrb[29*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_29_WDATA_PARITY(32'd0), - .AXI_29_WVALID(m_axi_hbm_int_wvalid[29 +: 1]), - .AXI_29_WREADY(m_axi_hbm_int_wready[29 +: 1]), - .AXI_29_BID(m_axi_hbm_int_bid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_29_BRESP(m_axi_hbm_int_bresp[29*2 +: 2]), - .AXI_29_BVALID(m_axi_hbm_int_bvalid[29 +: 1]), - .AXI_29_BREADY(m_axi_hbm_int_bready[29 +: 1]), - - .AXI_30_ACLK(hbm_clk_int[30 +: 1]), - .AXI_30_ARESET_N(!hbm_rst_int[30 +: 1]), - - .AXI_30_ARADDR(m_axi_hbm_int_araddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_30_ARBURST(m_axi_hbm_int_arburst[30*2 +: 2]), - .AXI_30_ARID(m_axi_hbm_int_arid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_30_ARLEN(m_axi_hbm_int_arlen[30*8 +: 4]), - .AXI_30_ARSIZE(m_axi_hbm_int_arsize[30*3 +: 3]), - .AXI_30_ARVALID(m_axi_hbm_int_arvalid[30 +: 1]), - .AXI_30_ARREADY(m_axi_hbm_int_arready[30 +: 1]), - .AXI_30_RDATA_PARITY(), - .AXI_30_RDATA(m_axi_hbm_int_rdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_30_RID(m_axi_hbm_int_rid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_30_RLAST(m_axi_hbm_int_rlast[30 +: 1]), - .AXI_30_RRESP(m_axi_hbm_int_rresp[30*2 +: 2]), - .AXI_30_RVALID(m_axi_hbm_int_rvalid[30 +: 1]), - .AXI_30_RREADY(m_axi_hbm_int_rready[30 +: 1]), - .AXI_30_AWADDR(m_axi_hbm_int_awaddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_30_AWBURST(m_axi_hbm_int_awburst[30*2 +: 2]), - .AXI_30_AWID(m_axi_hbm_int_awid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_30_AWLEN(m_axi_hbm_int_awlen[30*8 +: 4]), - .AXI_30_AWSIZE(m_axi_hbm_int_awsize[30*3 +: 3]), - .AXI_30_AWVALID(m_axi_hbm_int_awvalid[30 +: 1]), - .AXI_30_AWREADY(m_axi_hbm_int_awready[30 +: 1]), - .AXI_30_WDATA(m_axi_hbm_int_wdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_30_WLAST(m_axi_hbm_int_wlast[30 +: 1]), - .AXI_30_WSTRB(m_axi_hbm_int_wstrb[30*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_30_WDATA_PARITY(32'd0), - .AXI_30_WVALID(m_axi_hbm_int_wvalid[30 +: 1]), - .AXI_30_WREADY(m_axi_hbm_int_wready[30 +: 1]), - .AXI_30_BID(m_axi_hbm_int_bid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_30_BRESP(m_axi_hbm_int_bresp[30*2 +: 2]), - .AXI_30_BVALID(m_axi_hbm_int_bvalid[30 +: 1]), - .AXI_30_BREADY(m_axi_hbm_int_bready[30 +: 1]), - - .AXI_31_ACLK(hbm_clk_int[31 +: 1]), - .AXI_31_ARESET_N(!hbm_rst_int[31 +: 1]), - - .AXI_31_ARADDR(m_axi_hbm_int_araddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_31_ARBURST(m_axi_hbm_int_arburst[31*2 +: 2]), - .AXI_31_ARID(m_axi_hbm_int_arid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_31_ARLEN(m_axi_hbm_int_arlen[31*8 +: 4]), - .AXI_31_ARSIZE(m_axi_hbm_int_arsize[31*3 +: 3]), - .AXI_31_ARVALID(m_axi_hbm_int_arvalid[31 +: 1]), - .AXI_31_ARREADY(m_axi_hbm_int_arready[31 +: 1]), - .AXI_31_RDATA_PARITY(), - .AXI_31_RDATA(m_axi_hbm_int_rdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_31_RID(m_axi_hbm_int_rid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_31_RLAST(m_axi_hbm_int_rlast[31 +: 1]), - .AXI_31_RRESP(m_axi_hbm_int_rresp[31*2 +: 2]), - .AXI_31_RVALID(m_axi_hbm_int_rvalid[31 +: 1]), - .AXI_31_RREADY(m_axi_hbm_int_rready[31 +: 1]), - .AXI_31_AWADDR(m_axi_hbm_int_awaddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), - .AXI_31_AWBURST(m_axi_hbm_int_awburst[31*2 +: 2]), - .AXI_31_AWID(m_axi_hbm_int_awid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_31_AWLEN(m_axi_hbm_int_awlen[31*8 +: 4]), - .AXI_31_AWSIZE(m_axi_hbm_int_awsize[31*3 +: 3]), - .AXI_31_AWVALID(m_axi_hbm_int_awvalid[31 +: 1]), - .AXI_31_AWREADY(m_axi_hbm_int_awready[31 +: 1]), - .AXI_31_WDATA(m_axi_hbm_int_wdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), - .AXI_31_WLAST(m_axi_hbm_int_wlast[31 +: 1]), - .AXI_31_WSTRB(m_axi_hbm_int_wstrb[31*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), - .AXI_31_WDATA_PARITY(32'd0), - .AXI_31_WVALID(m_axi_hbm_int_wvalid[31 +: 1]), - .AXI_31_WREADY(m_axi_hbm_int_wready[31 +: 1]), - .AXI_31_BID(m_axi_hbm_int_bid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), - .AXI_31_BRESP(m_axi_hbm_int_bresp[31*2 +: 2]), - .AXI_31_BVALID(m_axi_hbm_int_bvalid[31 +: 1]), - .AXI_31_BREADY(m_axi_hbm_int_bready[31 +: 1]), - - .DRAM_0_STAT_CATTRIP(hbm_cattrip_1), - .DRAM_0_STAT_TEMP(hbm_temp_1), - .DRAM_1_STAT_CATTRIP(hbm_cattrip_2), - .DRAM_1_STAT_TEMP(hbm_temp_2) -); - -for (n = 0; n < HBM_CH_INT; n = n + 1) begin - - localparam c = n / HBM_CH_STRIDE; - - if (c*HBM_CH_STRIDE == n) begin - - assign hbm_clk[c] = hbm_clk_int[n]; - assign hbm_rst[c] = hbm_rst_int[n]; - - assign m_axi_hbm_int_awid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = m_axi_hbm_awid[c*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]; - assign m_axi_hbm_int_awaddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH] = m_axi_hbm_awaddr[c*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]; - assign m_axi_hbm_int_awlen[n*8 +: 8] = m_axi_hbm_awlen[c*8 +: 8]; - assign m_axi_hbm_int_awsize[n*3 +: 3] = m_axi_hbm_awsize[c*3 +: 3]; - assign m_axi_hbm_int_awburst[n*2 +: 2] = m_axi_hbm_awburst[c*2 +: 2]; - assign m_axi_hbm_int_awlock[n*1 +: 1] = m_axi_hbm_awlock[c*1 +: 1]; - assign m_axi_hbm_int_awcache[n*4 +: 4] = m_axi_hbm_awcache[c*4 +: 4]; - assign m_axi_hbm_int_awprot[n*3 +: 3] = m_axi_hbm_awprot[c*3 +: 3]; - assign m_axi_hbm_int_awqos[n*4 +: 4] = m_axi_hbm_awqos[c*4 +: 4]; - assign m_axi_hbm_int_awvalid[n*1 +: 1] = m_axi_hbm_awvalid[c*1 +: 1]; - assign m_axi_hbm_awready[c*1 +: 1] = m_axi_hbm_int_awready[n*1 +: 1]; - assign m_axi_hbm_int_wdata[n*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH] = m_axi_hbm_wdata[c*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]; - assign m_axi_hbm_int_wstrb[n*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH] = m_axi_hbm_wstrb[c*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]; - assign m_axi_hbm_int_wlast[n*1 +: 1] = m_axi_hbm_wlast[c*1 +: 1]; - assign m_axi_hbm_int_wvalid[n*1 +: 1] = m_axi_hbm_wvalid[c*1 +: 1]; - assign m_axi_hbm_wready[c*1 +: 1] = m_axi_hbm_int_wready[n*1 +: 1]; - assign m_axi_hbm_bid[c*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = m_axi_hbm_int_bid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]; - assign m_axi_hbm_bresp[c*2 +: 2] = m_axi_hbm_int_bresp[n*2 +: 2]; - assign m_axi_hbm_bvalid[c*1 +: 1] = m_axi_hbm_int_bvalid[n*1 +: 1]; - assign m_axi_hbm_int_bready[n*1 +: 1] = m_axi_hbm_bready[c*1 +: 1]; - assign m_axi_hbm_int_arid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = m_axi_hbm_arid[c*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]; - assign m_axi_hbm_int_araddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH] = m_axi_hbm_araddr[c*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]; - assign m_axi_hbm_int_arlen[n*8 +: 8] = m_axi_hbm_arlen[c*8 +: 8]; - assign m_axi_hbm_int_arsize[n*3 +: 3] = m_axi_hbm_arsize[c*3 +: 3]; - assign m_axi_hbm_int_arburst[n*2 +: 2] = m_axi_hbm_arburst[c*2 +: 2]; - assign m_axi_hbm_int_arlock[n*1 +: 1] = m_axi_hbm_arlock[c*1 +: 1]; - assign m_axi_hbm_int_arcache[n*4 +: 4] = m_axi_hbm_arcache[c*4 +: 4]; - assign m_axi_hbm_int_arprot[n*3 +: 3] = m_axi_hbm_arprot[c*3 +: 3]; - assign m_axi_hbm_int_arqos[n*4 +: 4] = m_axi_hbm_arqos[c*4 +: 4]; - assign m_axi_hbm_int_arvalid[n*1 +: 1] = m_axi_hbm_arvalid[c*1 +: 1]; - assign m_axi_hbm_arready[c*1 +: 1] = m_axi_hbm_int_arready[n*1 +: 1]; - assign m_axi_hbm_rid[c*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = m_axi_hbm_int_rid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]; - assign m_axi_hbm_rdata[c*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH] = m_axi_hbm_int_rdata[n*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]; - assign m_axi_hbm_rresp[c*2 +: 2] = m_axi_hbm_int_rresp[n*2 +: 2]; - assign m_axi_hbm_rlast[c*1 +: 1] = m_axi_hbm_int_rlast[n*1 +: 1]; - assign m_axi_hbm_rvalid[c*1 +: 1] = m_axi_hbm_int_rvalid[n*1 +: 1]; - assign m_axi_hbm_int_rready[n*1 +: 1] = m_axi_hbm_rready[c*1 +: 1]; - - assign hbm_status[c] = 1'b1; - - end else begin - - assign m_axi_hbm_int_awid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = 0; - assign m_axi_hbm_int_awaddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH] = 0; - assign m_axi_hbm_int_awlen[n*8 +: 8] = 8'd0; - assign m_axi_hbm_int_awsize[n*3 +: 3] = 3'd0; - assign m_axi_hbm_int_awburst[n*2 +: 2] = 2'd0; - assign m_axi_hbm_int_awlock[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_awcache[n*4 +: 4] = 4'd0; - assign m_axi_hbm_int_awprot[n*3 +: 3] = 3'd0; - assign m_axi_hbm_int_awqos[n*4 +: 4] = 4'd0; - assign m_axi_hbm_int_awvalid[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_wdata[n*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH] = 0; - assign m_axi_hbm_int_wstrb[n*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH] = 0; - assign m_axi_hbm_int_wlast[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_wvalid[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_bready[n*1 +: 1] = 1'b1; - assign m_axi_hbm_int_arid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH] = 0; - assign m_axi_hbm_int_araddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH] = 0; - assign m_axi_hbm_int_arlen[n*8 +: 8] = 8'd0; - assign m_axi_hbm_int_arsize[n*3 +: 3] = 3'd0; - assign m_axi_hbm_int_arburst[n*2 +: 2] = 2'd0; - assign m_axi_hbm_int_arlock[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_arcache[n*4 +: 4] = 4'd0; - assign m_axi_hbm_int_arprot[n*3 +: 3] = 3'd0; - assign m_axi_hbm_int_arqos[n*4 +: 4] = 4'd0; - assign m_axi_hbm_int_arvalid[n*1 +: 1] = 1'b0; - assign m_axi_hbm_int_rready[n*1 +: 1] = 1'b1; - - end - -end - -end else begin - -assign hbm_clk = 0; -assign hbm_rst = 0; - -assign m_axi_hbm_awready = 0; -assign m_axi_hbm_wready = 0; -assign m_axi_hbm_bid = 0; -assign m_axi_hbm_bresp = 0; -assign m_axi_hbm_bvalid = 0; -assign m_axi_hbm_arready = 0; -assign m_axi_hbm_rid = 0; -assign m_axi_hbm_rdata = 0; -assign m_axi_hbm_rresp = 0; -assign m_axi_hbm_rlast = 0; -assign m_axi_hbm_rvalid = 0; - -assign hbm_status = 0; - -assign hbm_cattrip = 1'b0; - -assign hbm_temp_1 = 7'd0; -assign hbm_temp_2 = 7'd0; - -end - -endgenerate - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Board configuration - .TDMA_BER_ENABLE(TDMA_BER_ENABLE), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - .PORT_MASK(PORT_MASK), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .ENABLE_PADDING(ENABLE_PADDING), - .ENABLE_DIC(ENABLE_DIC), - .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .HBM_CH(HBM_CH), - .HBM_ENABLE(HBM_ENABLE), - .HBM_GROUP_SIZE(HBM_GROUP_SIZE), - .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), - .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), - .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), - .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), - .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), - .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_user_clk), - .rst_250mhz(pcie_user_reset), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - - /* - * GPIO - */ - .qsfp_led_act(qsfp_led_act), - .qsfp_led_stat_g(qsfp_led_stat_g), - .qsfp_led_stat_y(qsfp_led_stat_y), - - /* - * PCIe - */ - .m_axis_rq_tdata(axis_rq_tdata), - .m_axis_rq_tkeep(axis_rq_tkeep), - .m_axis_rq_tlast(axis_rq_tlast), - .m_axis_rq_tready(axis_rq_tready), - .m_axis_rq_tuser(axis_rq_tuser), - .m_axis_rq_tvalid(axis_rq_tvalid), - - .s_axis_rc_tdata(axis_rc_tdata), - .s_axis_rc_tkeep(axis_rc_tkeep), - .s_axis_rc_tlast(axis_rc_tlast), - .s_axis_rc_tready(axis_rc_tready), - .s_axis_rc_tuser(axis_rc_tuser), - .s_axis_rc_tvalid(axis_rc_tvalid), - - .s_axis_cq_tdata(axis_cq_tdata), - .s_axis_cq_tkeep(axis_cq_tkeep), - .s_axis_cq_tlast(axis_cq_tlast), - .s_axis_cq_tready(axis_cq_tready), - .s_axis_cq_tuser(axis_cq_tuser), - .s_axis_cq_tvalid(axis_cq_tvalid), - - .m_axis_cc_tdata(axis_cc_tdata), - .m_axis_cc_tkeep(axis_cc_tkeep), - .m_axis_cc_tlast(axis_cc_tlast), - .m_axis_cc_tready(axis_cc_tready), - .m_axis_cc_tuser(axis_cc_tuser), - .m_axis_cc_tvalid(axis_cc_tvalid), - - .s_axis_rq_seq_num_0(pcie_rq_seq_num0_reg), - .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0_reg), - .s_axis_rq_seq_num_1(pcie_rq_seq_num1_reg), - .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1_reg), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_rcb_status(cfg_rcb_status), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * Ethernet: QSFP28 - */ - .qsfp_tx_clk_1(qsfp_tx_clk_1_int), - .qsfp_tx_rst_1(qsfp_tx_rst_1_int), - .qsfp_txd_1(qsfp_txd_1_int), - .qsfp_txc_1(qsfp_txc_1_int), - .qsfp_cfg_tx_prbs31_enable_1(qsfp_cfg_tx_prbs31_enable_1_int), - .qsfp_rx_clk_1(qsfp_rx_clk_1_int), - .qsfp_rx_rst_1(qsfp_rx_rst_1_int), - .qsfp_rxd_1(qsfp_rxd_1_int), - .qsfp_rxc_1(qsfp_rxc_1_int), - .qsfp_cfg_rx_prbs31_enable_1(qsfp_cfg_rx_prbs31_enable_1_int), - .qsfp_rx_error_count_1(qsfp_rx_error_count_1_int), - .qsfp_rx_status_1(qsfp_rx_status_1), - .qsfp_tx_clk_2(qsfp_tx_clk_2_int), - .qsfp_tx_rst_2(qsfp_tx_rst_2_int), - .qsfp_txd_2(qsfp_txd_2_int), - .qsfp_txc_2(qsfp_txc_2_int), - .qsfp_cfg_tx_prbs31_enable_2(qsfp_cfg_tx_prbs31_enable_2_int), - .qsfp_rx_clk_2(qsfp_rx_clk_2_int), - .qsfp_rx_rst_2(qsfp_rx_rst_2_int), - .qsfp_rxd_2(qsfp_rxd_2_int), - .qsfp_rxc_2(qsfp_rxc_2_int), - .qsfp_cfg_rx_prbs31_enable_2(qsfp_cfg_rx_prbs31_enable_2_int), - .qsfp_rx_error_count_2(qsfp_rx_error_count_2_int), - .qsfp_rx_status_2(qsfp_rx_status_2), - .qsfp_tx_clk_3(qsfp_tx_clk_3_int), - .qsfp_tx_rst_3(qsfp_tx_rst_3_int), - .qsfp_txd_3(qsfp_txd_3_int), - .qsfp_txc_3(qsfp_txc_3_int), - .qsfp_cfg_tx_prbs31_enable_3(qsfp_cfg_tx_prbs31_enable_3_int), - .qsfp_rx_clk_3(qsfp_rx_clk_3_int), - .qsfp_rx_rst_3(qsfp_rx_rst_3_int), - .qsfp_rxd_3(qsfp_rxd_3_int), - .qsfp_rxc_3(qsfp_rxc_3_int), - .qsfp_cfg_rx_prbs31_enable_3(qsfp_cfg_rx_prbs31_enable_3_int), - .qsfp_rx_error_count_3(qsfp_rx_error_count_3_int), - .qsfp_rx_status_3(qsfp_rx_status_3), - .qsfp_tx_clk_4(qsfp_tx_clk_4_int), - .qsfp_tx_rst_4(qsfp_tx_rst_4_int), - .qsfp_txd_4(qsfp_txd_4_int), - .qsfp_txc_4(qsfp_txc_4_int), - .qsfp_cfg_tx_prbs31_enable_4(qsfp_cfg_tx_prbs31_enable_4_int), - .qsfp_rx_clk_4(qsfp_rx_clk_4_int), - .qsfp_rx_rst_4(qsfp_rx_rst_4_int), - .qsfp_rxd_4(qsfp_rxd_4_int), - .qsfp_rxc_4(qsfp_rxc_4_int), - .qsfp_cfg_rx_prbs31_enable_4(qsfp_cfg_rx_prbs31_enable_4_int), - .qsfp_rx_error_count_4(qsfp_rx_error_count_4_int), - .qsfp_rx_status_4(qsfp_rx_status_4), - - .qsfp_drp_clk(qsfp_drp_clk), - .qsfp_drp_rst(qsfp_drp_rst), - .qsfp_drp_addr(qsfp_drp_addr), - .qsfp_drp_di(qsfp_drp_di), - .qsfp_drp_en(qsfp_drp_en), - .qsfp_drp_we(qsfp_drp_we), - .qsfp_drp_do(qsfp_drp_do), - .qsfp_drp_rdy(qsfp_drp_rdy), - - /* - * HBM - */ - .hbm_clk(hbm_clk), - .hbm_rst(hbm_rst), - - .m_axi_hbm_awid(m_axi_hbm_awid), - .m_axi_hbm_awaddr(m_axi_hbm_awaddr), - .m_axi_hbm_awlen(m_axi_hbm_awlen), - .m_axi_hbm_awsize(m_axi_hbm_awsize), - .m_axi_hbm_awburst(m_axi_hbm_awburst), - .m_axi_hbm_awlock(m_axi_hbm_awlock), - .m_axi_hbm_awcache(m_axi_hbm_awcache), - .m_axi_hbm_awprot(m_axi_hbm_awprot), - .m_axi_hbm_awqos(m_axi_hbm_awqos), - .m_axi_hbm_awvalid(m_axi_hbm_awvalid), - .m_axi_hbm_awready(m_axi_hbm_awready), - .m_axi_hbm_wdata(m_axi_hbm_wdata), - .m_axi_hbm_wstrb(m_axi_hbm_wstrb), - .m_axi_hbm_wlast(m_axi_hbm_wlast), - .m_axi_hbm_wvalid(m_axi_hbm_wvalid), - .m_axi_hbm_wready(m_axi_hbm_wready), - .m_axi_hbm_bid(m_axi_hbm_bid), - .m_axi_hbm_bresp(m_axi_hbm_bresp), - .m_axi_hbm_bvalid(m_axi_hbm_bvalid), - .m_axi_hbm_bready(m_axi_hbm_bready), - .m_axi_hbm_arid(m_axi_hbm_arid), - .m_axi_hbm_araddr(m_axi_hbm_araddr), - .m_axi_hbm_arlen(m_axi_hbm_arlen), - .m_axi_hbm_arsize(m_axi_hbm_arsize), - .m_axi_hbm_arburst(m_axi_hbm_arburst), - .m_axi_hbm_arlock(m_axi_hbm_arlock), - .m_axi_hbm_arcache(m_axi_hbm_arcache), - .m_axi_hbm_arprot(m_axi_hbm_arprot), - .m_axi_hbm_arqos(m_axi_hbm_arqos), - .m_axi_hbm_arvalid(m_axi_hbm_arvalid), - .m_axi_hbm_arready(m_axi_hbm_arready), - .m_axi_hbm_rid(m_axi_hbm_rid), - .m_axi_hbm_rdata(m_axi_hbm_rdata), - .m_axi_hbm_rresp(m_axi_hbm_rresp), - .m_axi_hbm_rlast(m_axi_hbm_rlast), - .m_axi_hbm_rvalid(m_axi_hbm_rvalid), - .m_axi_hbm_rready(m_axi_hbm_rready), - - .hbm_status(hbm_status), - - /* - * QSPI flash - */ - .fpga_boot(fpga_boot), - .qspi_clk(qspi_clk_int), - .qspi_dq_i(qspi_dq_i_int), - .qspi_dq_o(qspi_dq_o_int), - .qspi_dq_oe(qspi_dq_oe_int), - .qspi_cs(qspi_cs_int), - - /* - * AXI-Lite interface to CMS - */ - .m_axil_cms_clk(axil_cms_clk), - .m_axil_cms_rst(axil_cms_rst), - .m_axil_cms_awaddr(axil_cms_awaddr), - .m_axil_cms_awprot(axil_cms_awprot), - .m_axil_cms_awvalid(axil_cms_awvalid), - .m_axil_cms_awready(axil_cms_awready), - .m_axil_cms_wdata(axil_cms_wdata), - .m_axil_cms_wstrb(axil_cms_wstrb), - .m_axil_cms_wvalid(axil_cms_wvalid), - .m_axil_cms_wready(axil_cms_wready), - .m_axil_cms_bresp(axil_cms_bresp), - .m_axil_cms_bvalid(axil_cms_bvalid), - .m_axil_cms_bready(axil_cms_bready), - .m_axil_cms_araddr(axil_cms_araddr), - .m_axil_cms_arprot(axil_cms_arprot), - .m_axil_cms_arvalid(axil_cms_arvalid), - .m_axil_cms_arready(axil_cms_arready), - .m_axil_cms_rdata(axil_cms_rdata), - .m_axil_cms_rresp(axil_cms_rresp), - .m_axil_cms_rvalid(axil_cms_rvalid), - .m_axil_cms_rready(axil_cms_rready) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v deleted file mode 100644 index 6ed0e18ee..000000000 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ /dev/null @@ -1,1531 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B77093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_9032, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Board configuration - parameter TDMA_BER_ENABLE = 0, - - // Structural configuration - parameter IF_COUNT = 1, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 1024, - parameter PTP_CLK_PERIOD_NS_DENOM = 165, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 1, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 1, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - parameter IF_PTP_PERIOD_NS = 6'h6, - parameter IF_PTP_PERIOD_FNS = 16'h6666, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 16, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter ENABLE_PADDING = 1, - parameter ENABLE_DIC = 1, - parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // RAM configuration - parameter HBM_CH = 32, - parameter HBM_ENABLE = 0, - parameter HBM_GROUP_SIZE = HBM_CH, - parameter AXI_HBM_DATA_WIDTH = 256, - parameter AXI_HBM_ADDR_WIDTH = 33, - parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), - parameter AXI_HBM_ID_WIDTH = 6, - parameter AXI_HBM_MAX_BURST_LEN = 16, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, - parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, - parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, - parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, - parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, - parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 256, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter XGMII_DATA_WIDTH = 64, - parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, - parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - output wire qsfp_led_act, - output wire qsfp_led_stat_g, - output wire qsfp_led_stat_y, - - /* - * PCIe - */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, - - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, - - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, - - input wire [1:0] pcie_tfc_nph_av, - input wire [1:0] pcie_tfc_npd_av, - - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, - - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, - - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - input wire [3:0] cfg_interrupt_msix_enable, - input wire [3:0] cfg_interrupt_msix_mask, - input wire [251:0] cfg_interrupt_msix_vf_enable, - input wire [251:0] cfg_interrupt_msix_vf_mask, - output wire [63:0] cfg_interrupt_msix_address, - output wire [31:0] cfg_interrupt_msix_data, - output wire cfg_interrupt_msix_int, - output wire [1:0] cfg_interrupt_msix_vec_pending, - input wire cfg_interrupt_msix_vec_pending_status, - input wire cfg_interrupt_msix_sent, - input wire cfg_interrupt_msix_fail, - output wire [7:0] cfg_interrupt_msi_function_number, - - output wire status_error_cor, - output wire status_error_uncor, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp_tx_clk_1, - input wire qsfp_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_1, - output wire qsfp_cfg_tx_prbs31_enable_1, - input wire qsfp_rx_clk_1, - input wire qsfp_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_1, - output wire qsfp_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp_rx_error_count_1, - input wire qsfp_rx_status_1, - input wire qsfp_tx_clk_2, - input wire qsfp_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_2, - output wire qsfp_cfg_tx_prbs31_enable_2, - input wire qsfp_rx_clk_2, - input wire qsfp_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_2, - output wire qsfp_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp_rx_error_count_2, - input wire qsfp_rx_status_2, - input wire qsfp_tx_clk_3, - input wire qsfp_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_3, - output wire qsfp_cfg_tx_prbs31_enable_3, - input wire qsfp_rx_clk_3, - input wire qsfp_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_3, - output wire qsfp_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp_rx_error_count_3, - input wire qsfp_rx_status_3, - input wire qsfp_tx_clk_4, - input wire qsfp_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_4, - output wire qsfp_cfg_tx_prbs31_enable_4, - input wire qsfp_rx_clk_4, - input wire qsfp_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_4, - output wire qsfp_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp_rx_error_count_4, - input wire qsfp_rx_status_4, - - input wire qsfp_drp_clk, - input wire qsfp_drp_rst, - output wire [23:0] qsfp_drp_addr, - output wire [15:0] qsfp_drp_di, - output wire qsfp_drp_en, - output wire qsfp_drp_we, - input wire [15:0] qsfp_drp_do, - input wire qsfp_drp_rdy, - - /* - * HBM - */ - input wire [HBM_CH-1:0] hbm_clk, - input wire [HBM_CH-1:0] hbm_rst, - - output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, - output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, - output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, - output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, - output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, - output wire [HBM_CH-1:0] m_axi_hbm_awlock, - output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, - output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, - output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, - output wire [HBM_CH-1:0] m_axi_hbm_awvalid, - input wire [HBM_CH-1:0] m_axi_hbm_awready, - output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, - output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, - output wire [HBM_CH-1:0] m_axi_hbm_wlast, - output wire [HBM_CH-1:0] m_axi_hbm_wvalid, - input wire [HBM_CH-1:0] m_axi_hbm_wready, - input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, - input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, - input wire [HBM_CH-1:0] m_axi_hbm_bvalid, - output wire [HBM_CH-1:0] m_axi_hbm_bready, - output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, - output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, - output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, - output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, - output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, - output wire [HBM_CH-1:0] m_axi_hbm_arlock, - output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, - output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, - output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, - output wire [HBM_CH-1:0] m_axi_hbm_arvalid, - input wire [HBM_CH-1:0] m_axi_hbm_arready, - input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, - input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, - input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, - input wire [HBM_CH-1:0] m_axi_hbm_rlast, - input wire [HBM_CH-1:0] m_axi_hbm_rvalid, - output wire [HBM_CH-1:0] m_axi_hbm_rready, - - input wire [HBM_CH-1:0] hbm_status, - - /* - * QSPI flash - */ - output wire fpga_boot, - output wire qspi_clk, - input wire [3:0] qspi_dq_i, - output wire [3:0] qspi_dq_o, - output wire [3:0] qspi_dq_oe, - output wire qspi_cs, - - /* - * AXI-Lite interface to CMS - */ - output wire m_axil_cms_clk, - output wire m_axil_cms_rst, - output wire [17:0] m_axil_cms_awaddr, - output wire [2:0] m_axil_cms_awprot, - output wire m_axil_cms_awvalid, - input wire m_axil_cms_awready, - output wire [31:0] m_axil_cms_wdata, - output wire [3:0] m_axil_cms_wstrb, - output wire m_axil_cms_wvalid, - input wire m_axil_cms_wready, - input wire [1:0] m_axil_cms_bresp, - input wire m_axil_cms_bvalid, - output wire m_axil_cms_bready, - output wire [17:0] m_axil_cms_araddr, - output wire [2:0] m_axil_cms_arprot, - output wire m_axil_cms_arvalid, - input wire m_axil_cms_arready, - input wire [31:0] m_axil_cms_rdata, - input wire [1:0] m_axil_cms_rresp, - input wire m_axil_cms_rvalid, - output wire m_axil_cms_rready -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -localparam RB_DRP_QSFP_BASE = RB_BASE_ADDR + 16'h40; - -initial begin - if (PORT_COUNT > 4) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// AXI lite connections -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; -wire [2:0] axil_csr_awprot; -wire axil_csr_awvalid; -wire axil_csr_awready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; -wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; -wire axil_csr_wvalid; -wire axil_csr_wready; -wire [1:0] axil_csr_bresp; -wire axil_csr_bvalid; -wire axil_csr_bready; -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; -wire [2:0] axil_csr_arprot; -wire axil_csr_arvalid; -wire axil_csr_arready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; -wire [1:0] axil_csr_rresp; -wire axil_csr_rvalid; -wire axil_csr_rready; - -// PTP -wire ptp_td_sd; -wire ptp_pps; -wire ptp_pps_str; -wire ptp_sync_locked; -wire [63:0] ptp_sync_ts_rel; -wire ptp_sync_ts_rel_step; -wire [95:0] ptp_sync_ts_tod; -wire ptp_sync_ts_tod_step; -wire ptp_sync_pps; -wire ptp_sync_pps_str; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -wire qsfp_drp_reg_wr_wait; -wire qsfp_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_drp_reg_rd_data; -wire qsfp_drp_reg_rd_wait; -wire qsfp_drp_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg fpga_boot_reg = 1'b0; - -reg qspi_clk_reg = 1'b0; -reg qspi_cs_reg = 1'b1; -reg [3:0] qspi_dq_o_reg = 4'd0; -reg [3:0] qspi_dq_oe_reg = 4'd0; - -reg [17:0] m_axil_cms_addr_reg = 18'd0; -reg m_axil_cms_awvalid_reg = 1'b0; -reg [31:0] m_axil_cms_wdata_reg = 32'd0; -reg [3:0] m_axil_cms_wstrb_reg = 4'b0000; -reg m_axil_cms_wvalid_reg = 1'b0; -reg m_axil_cms_arvalid_reg = 1'b0; - -assign ctrl_reg_wr_wait = qsfp_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_drp_reg_rd_ack; - -assign fpga_boot = fpga_boot_reg; - -assign qspi_clk = qspi_clk_reg; -assign qspi_cs = qspi_cs_reg; -assign qspi_dq_o = qspi_dq_o_reg; -assign qspi_dq_oe = qspi_dq_oe_reg; - -assign m_axil_cms_clk = clk_250mhz; -assign m_axil_cms_rst = rst_250mhz; -assign m_axil_cms_awaddr = m_axil_cms_addr_reg; -assign m_axil_cms_awprot = 3'b000; -assign m_axil_cms_awvalid = m_axil_cms_awvalid_reg; -assign m_axil_cms_wdata = m_axil_cms_wdata_reg; -assign m_axil_cms_wstrb = m_axil_cms_wstrb_reg; -assign m_axil_cms_wvalid = m_axil_cms_wvalid_reg; -assign m_axil_cms_bready = 1'b1; -assign m_axil_cms_araddr = m_axil_cms_addr_reg; -assign m_axil_cms_arprot = 3'b000; -assign m_axil_cms_arvalid = m_axil_cms_arvalid_reg; -assign m_axil_cms_rready = 1'b1; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - m_axil_cms_awvalid_reg <= m_axil_cms_awvalid_reg && !m_axil_cms_awready; - m_axil_cms_wvalid_reg <= m_axil_cms_wvalid_reg && !m_axil_cms_wready; - m_axil_cms_arvalid_reg <= m_axil_cms_arvalid_reg && !m_axil_cms_arready; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // FW ID - 8'h0C: begin - // FW ID: FPGA JTAG ID - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - // QSPI flash - RBB+8'h0C: begin - // SPI flash ctrl: format - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - RBB+8'h10: begin - // SPI flash ctrl: control 0 - if (ctrl_reg_wr_strb[0]) begin - qspi_dq_o_reg <= ctrl_reg_wr_data[3:0]; - end - if (ctrl_reg_wr_strb[1]) begin - qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8]; - end - if (ctrl_reg_wr_strb[2]) begin - qspi_clk_reg <= ctrl_reg_wr_data[16]; - qspi_cs_reg <= ctrl_reg_wr_data[17]; - end - end - // Alveo BMC - RBB+8'h2C: begin - // BMC ctrl: Addr - if (!m_axil_cms_arvalid && !m_axil_cms_awvalid) begin - m_axil_cms_addr_reg <= ctrl_reg_wr_data; - m_axil_cms_arvalid_reg <= 1'b1; - end - end - RBB+8'h30: begin - // BMC ctrl: Data - if (!m_axil_cms_wvalid) begin - m_axil_cms_awvalid_reg <= 1'b1; - m_axil_cms_wdata_reg <= ctrl_reg_wr_data; - m_axil_cms_wstrb_reg <= ctrl_reg_wr_strb; - m_axil_cms_wvalid_reg <= 1'b1; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // QSPI flash - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // SPI flash ctrl: Next header - RBB+8'h0C: begin - // SPI flash ctrl: format - ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) - ctrl_reg_rd_data_reg[7:4] <= 1; // default segment - ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment - ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default) - end - RBB+8'h10: begin - // SPI flash ctrl: control 0 - ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i; - ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe; - ctrl_reg_rd_data_reg[16] <= qspi_clk; - ctrl_reg_rd_data_reg[17] <= qspi_cs; - end - // Alveo BMC - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C140; // BMC ctrl: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_BASE; // BMC ctrl: Next header - RBB+8'h2C: ctrl_reg_rd_data_reg <= m_axil_cms_addr_reg; // BMC ctrl: Addr - RBB+8'h30: ctrl_reg_rd_data_reg <= m_axil_cms_rdata; // BMC ctrl: Data - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - fpga_boot_reg <= 1'b0; - - qspi_clk_reg <= 1'b0; - qspi_cs_reg <= 1'b1; - qspi_dq_o_reg <= 4'd0; - qspi_dq_oe_reg <= 4'd0; - - m_axil_cms_awvalid_reg <= 1'b0; - m_axil_cms_wvalid_reg <= 1'b0; - m_axil_cms_arvalid_reg <= 1'b0; - end -end - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP_BASE), - .RB_NEXT_PTR(0) -) -qsfp_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp_drp_reg_wr_wait), - .reg_wr_ack(qsfp_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp_drp_reg_rd_data), - .reg_rd_wait(qsfp_drp_reg_rd_wait), - .reg_rd_ack(qsfp_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp_drp_clk), - .drp_rst(qsfp_drp_rst), - .drp_addr(qsfp_drp_addr), - .drp_di(qsfp_drp_di), - .drp_en(qsfp_drp_en), - .drp_we(qsfp_drp_we), - .drp_do(qsfp_drp_do), - .drp_rdy(qsfp_drp_rdy) -); - -generate - -if (TDMA_BER_ENABLE) begin - - // BER tester - tdma_ber #( - .COUNT(4), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(4)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) - ) - tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}), - .phy_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}), - .phy_rx_error_count({qsfp_rx_error_count_4, qsfp_rx_error_count_3, qsfp_rx_error_count_2, qsfp_rx_error_count_1}), - .phy_cfg_tx_prbs31_enable({qsfp_cfg_tx_prbs31_enable_4, qsfp_cfg_tx_prbs31_enable_3, qsfp_cfg_tx_prbs31_enable_2, qsfp_cfg_tx_prbs31_enable_1}), - .phy_cfg_rx_prbs31_enable({qsfp_cfg_rx_prbs31_enable_4, qsfp_cfg_rx_prbs31_enable_3, qsfp_cfg_rx_prbs31_enable_2, qsfp_cfg_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_tod), - .ptp_ts_step(ptp_sync_ts_tod_step) - ); - -end else begin - - assign qsfp_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp_cfg_rx_prbs31_enable_4 = 1'b0; - -end - -endgenerate - -assign qsfp_led_act = ptp_pps_str; -assign qsfp_led_stat_g = 1'b0; -assign qsfp_led_stat_y = 1'b0; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -wire [PORT_COUNT-1:0] port_xgmii_tx_clk; -wire [PORT_COUNT-1:0] port_xgmii_tx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; - -wire [PORT_COUNT-1:0] port_xgmii_rx_clk; -wire [PORT_COUNT-1:0] port_xgmii_rx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; - -mqnic_port_map_phy_xgmii #( - .PHY_COUNT(4), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(4), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), - .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) -) -mqnic_port_map_phy_xgmii_inst ( - // towards PHY - .phy_xgmii_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}), - .phy_xgmii_tx_rst({qsfp_tx_rst_4, qsfp_tx_rst_3, qsfp_tx_rst_2, qsfp_tx_rst_1}), - .phy_xgmii_txd({qsfp_txd_4, qsfp_txd_3, qsfp_txd_2, qsfp_txd_1}), - .phy_xgmii_txc({qsfp_txc_4, qsfp_txc_3, qsfp_txc_2, qsfp_txc_1}), - .phy_tx_status(4'hf), - - .phy_xgmii_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}), - .phy_xgmii_rx_rst({qsfp_rx_rst_4, qsfp_rx_rst_3, qsfp_rx_rst_2, qsfp_rx_rst_1}), - .phy_xgmii_rxd({qsfp_rxd_4, qsfp_rxd_3, qsfp_rxd_2, qsfp_rxd_1}), - .phy_xgmii_rxc({qsfp_rxc_4, qsfp_rxc_3, qsfp_rxc_2, qsfp_rxc_1}), - .phy_rx_status({qsfp_rx_status_4, qsfp_rx_status_3, qsfp_rx_status_2, qsfp_rx_status_1}), - - // towards MAC - .port_xgmii_tx_clk(port_xgmii_tx_clk), - .port_xgmii_tx_rst(port_xgmii_tx_rst), - .port_xgmii_txd(port_xgmii_txd), - .port_xgmii_txc(port_xgmii_txc), - .port_tx_status(eth_tx_status), - - .port_xgmii_rx_clk(port_xgmii_rx_clk), - .port_xgmii_rx_rst(port_xgmii_rx_rst), - .port_xgmii_rxd(port_xgmii_rxd), - .port_xgmii_rxc(port_xgmii_rxc), - .port_rx_status(eth_rx_status) -); - -generate - genvar n; - - for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac - - assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; - assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; - assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; - assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; - - eth_mac_10g #( - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .ENABLE_PADDING(ENABLE_PADDING), - .ENABLE_DIC(ENABLE_DIC), - .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), - .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), - .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_PTP_TS_CTRL_IN_TUSER(0), - .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), - .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .PFC_ENABLE(PFC_ENABLE), - .PAUSE_ENABLE(LFC_ENABLE) - ) - eth_mac_inst ( - .tx_clk(port_xgmii_tx_clk[n]), - .tx_rst(port_xgmii_tx_rst[n]), - .rx_clk(port_xgmii_rx_clk[n]), - .rx_rst(port_xgmii_rx_rst[n]), - - /* - * AXI input - */ - .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), - .tx_axis_tready(axis_eth_tx_tready[n +: 1]), - .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), - .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), - - /* - * AXI output - */ - .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), - .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), - .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), - - /* - * XGMII interface - */ - .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - - /* - * PTP - */ - .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), - .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), - - /* - * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) - */ - .tx_lfc_req(eth_tx_lfc_req[n +: 1]), - .tx_lfc_resend(1'b0), - .rx_lfc_en(eth_rx_lfc_en[n +: 1]), - .rx_lfc_req(eth_rx_lfc_req[n +: 1]), - .rx_lfc_ack(eth_rx_lfc_ack[n +: 1]), - - /* - * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) - */ - .tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]), - .tx_pfc_resend(1'b0), - .rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]), - .rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]), - .rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]), - - /* - * Pause interface - */ - .tx_lfc_pause_en(1'b1), - .tx_pause_req(1'b0), - .tx_pause_ack(), - - /* - * Status - */ - .tx_start_packet(), - .tx_error_underflow(), - .rx_start_packet(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - .stat_tx_mcf(), - .stat_rx_mcf(), - .stat_tx_lfc_pkt(), - .stat_tx_lfc_xon(), - .stat_tx_lfc_xoff(), - .stat_tx_lfc_paused(), - .stat_tx_pfc_pkt(), - .stat_tx_pfc_xon(), - .stat_tx_pfc_xoff(), - .stat_tx_pfc_paused(), - .stat_rx_lfc_pkt(), - .stat_rx_lfc_xon(), - .stat_rx_lfc_xoff(), - .stat_rx_lfc_paused(), - .stat_rx_pfc_pkt(), - .stat_rx_pfc_xon(), - .stat_rx_pfc_xoff(), - .stat_rx_pfc_paused(), - - /* - * Configuration - */ - .cfg_ifg(8'd12), - .cfg_tx_enable(eth_tx_enable[n +: 1]), - .cfg_rx_enable(eth_rx_enable[n +: 1]), - .cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01), - .cfg_mcf_rx_check_eth_dst_mcast(1'b1), - .cfg_mcf_rx_eth_dst_ucast(48'd0), - .cfg_mcf_rx_check_eth_dst_ucast(1'b0), - .cfg_mcf_rx_eth_src(48'd0), - .cfg_mcf_rx_check_eth_src(1'b0), - .cfg_mcf_rx_eth_type(16'h8808), - .cfg_mcf_rx_opcode_lfc(16'h0001), - .cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]), - .cfg_mcf_rx_opcode_pfc(16'h0101), - .cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0), - .cfg_mcf_rx_forward(1'b0), - .cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]), - .cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01), - .cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C), - .cfg_tx_lfc_eth_type(16'h8808), - .cfg_tx_lfc_opcode(16'h0001), - .cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]), - .cfg_tx_lfc_quanta(16'hffff), - .cfg_tx_lfc_refresh(16'h7fff), - .cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01), - .cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C), - .cfg_tx_pfc_eth_type(16'h8808), - .cfg_tx_pfc_opcode(16'h0101), - .cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0), - .cfg_tx_pfc_quanta({8{16'hffff}}), - .cfg_tx_pfc_refresh({8{16'h7fff}}), - .cfg_rx_lfc_opcode(16'h0001), - .cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]), - .cfg_rx_pfc_opcode(16'h0101), - .cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0) - ); - - end - -endgenerate - -mqnic_core_pcie_us #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(0), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_ENABLE(0), - .HBM_CH(HBM_CH), - .HBM_ENABLE(HBM_ENABLE), - .HBM_GROUP_SIZE(HBM_GROUP_SIZE), - .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), - .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), - .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), - .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), - .AXI_HBM_AWUSER_ENABLE(0), - .AXI_HBM_WUSER_ENABLE(0), - .AXI_HBM_BUSER_ENABLE(0), - .AXI_HBM_ARUSER_ENABLE(0), - .AXI_HBM_RUSER_ENABLE(0), - .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), - .AXI_HBM_NARROW_BURST(0), - .AXI_HBM_FIXED_BURST(0), - .AXI_HBM_WRAP_BURST(1), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * AXI input (RC) - */ - .s_axis_rc_tdata(s_axis_rc_tdata), - .s_axis_rc_tkeep(s_axis_rc_tkeep), - .s_axis_rc_tvalid(s_axis_rc_tvalid), - .s_axis_rc_tready(s_axis_rc_tready), - .s_axis_rc_tlast(s_axis_rc_tlast), - .s_axis_rc_tuser(s_axis_rc_tuser), - - /* - * AXI output (RQ) - */ - .m_axis_rq_tdata(m_axis_rq_tdata), - .m_axis_rq_tkeep(m_axis_rq_tkeep), - .m_axis_rq_tvalid(m_axis_rq_tvalid), - .m_axis_rq_tready(m_axis_rq_tready), - .m_axis_rq_tlast(m_axis_rq_tlast), - .m_axis_rq_tuser(m_axis_rq_tuser), - - /* - * AXI input (CQ) - */ - .s_axis_cq_tdata(s_axis_cq_tdata), - .s_axis_cq_tkeep(s_axis_cq_tkeep), - .s_axis_cq_tvalid(s_axis_cq_tvalid), - .s_axis_cq_tready(s_axis_cq_tready), - .s_axis_cq_tlast(s_axis_cq_tlast), - .s_axis_cq_tuser(s_axis_cq_tuser), - - /* - * AXI output (CC) - */ - .m_axis_cc_tdata(m_axis_cc_tdata), - .m_axis_cc_tkeep(m_axis_cc_tkeep), - .m_axis_cc_tvalid(m_axis_cc_tvalid), - .m_axis_cc_tready(m_axis_cc_tready), - .m_axis_cc_tlast(m_axis_cc_tlast), - .m_axis_cc_tuser(m_axis_cc_tuser), - - /* - * Transmit sequence number input - */ - .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), - .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), - .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), - .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), - - /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration inputs - */ - .cfg_max_read_req(cfg_max_read_req), - .cfg_max_payload(cfg_max_payload), - .cfg_rcb_status(cfg_rcb_status), - - /* - * Configuration interface - */ - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - /* - * Interrupt interface - */ - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - /* - * PCIe error outputs - */ - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(axil_csr_awaddr), - .m_axil_csr_awprot(axil_csr_awprot), - .m_axil_csr_awvalid(axil_csr_awvalid), - .m_axil_csr_awready(axil_csr_awready), - .m_axil_csr_wdata(axil_csr_wdata), - .m_axil_csr_wstrb(axil_csr_wstrb), - .m_axil_csr_wvalid(axil_csr_wvalid), - .m_axil_csr_wready(axil_csr_wready), - .m_axil_csr_bresp(axil_csr_bresp), - .m_axil_csr_bvalid(axil_csr_bvalid), - .m_axil_csr_bready(axil_csr_bready), - .m_axil_csr_araddr(axil_csr_araddr), - .m_axil_csr_arprot(axil_csr_arprot), - .m_axil_csr_arvalid(axil_csr_arvalid), - .m_axil_csr_arready(axil_csr_arready), - .m_axil_csr_rdata(axil_csr_rdata), - .m_axil_csr_rresp(axil_csr_rresp), - .m_axil_csr_rvalid(axil_csr_rvalid), - .m_axil_csr_rready(axil_csr_rready), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_td_sd(ptp_td_sd), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_sync_locked(ptp_sync_locked), - .ptp_sync_ts_rel(ptp_sync_ts_rel), - .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), - .ptp_sync_ts_tod(ptp_sync_ts_tod), - .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_pps_str(ptp_sync_pps_str), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(0), - .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), - .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(0), - .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), - .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(0), - .ddr_rst(0), - - .m_axi_ddr_awid(), - .m_axi_ddr_awaddr(), - .m_axi_ddr_awlen(), - .m_axi_ddr_awsize(), - .m_axi_ddr_awburst(), - .m_axi_ddr_awlock(), - .m_axi_ddr_awcache(), - .m_axi_ddr_awprot(), - .m_axi_ddr_awqos(), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(), - .m_axi_ddr_awready(0), - .m_axi_ddr_wdata(), - .m_axi_ddr_wstrb(), - .m_axi_ddr_wlast(), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(), - .m_axi_ddr_wready(0), - .m_axi_ddr_bid(0), - .m_axi_ddr_bresp(0), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(0), - .m_axi_ddr_bready(), - .m_axi_ddr_arid(), - .m_axi_ddr_araddr(), - .m_axi_ddr_arlen(), - .m_axi_ddr_arsize(), - .m_axi_ddr_arburst(), - .m_axi_ddr_arlock(), - .m_axi_ddr_arcache(), - .m_axi_ddr_arprot(), - .m_axi_ddr_arqos(), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(), - .m_axi_ddr_arready(0), - .m_axi_ddr_rid(0), - .m_axi_ddr_rdata(0), - .m_axi_ddr_rresp(0), - .m_axi_ddr_rlast(0), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(0), - .m_axi_ddr_rready(), - - .ddr_status(0), - - /* - * HBM - */ - .hbm_clk(hbm_clk), - .hbm_rst(hbm_rst), - - .m_axi_hbm_awid(m_axi_hbm_awid), - .m_axi_hbm_awaddr(m_axi_hbm_awaddr), - .m_axi_hbm_awlen(m_axi_hbm_awlen), - .m_axi_hbm_awsize(m_axi_hbm_awsize), - .m_axi_hbm_awburst(m_axi_hbm_awburst), - .m_axi_hbm_awlock(m_axi_hbm_awlock), - .m_axi_hbm_awcache(m_axi_hbm_awcache), - .m_axi_hbm_awprot(m_axi_hbm_awprot), - .m_axi_hbm_awqos(m_axi_hbm_awqos), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(m_axi_hbm_awvalid), - .m_axi_hbm_awready(m_axi_hbm_awready), - .m_axi_hbm_wdata(m_axi_hbm_wdata), - .m_axi_hbm_wstrb(m_axi_hbm_wstrb), - .m_axi_hbm_wlast(m_axi_hbm_wlast), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(m_axi_hbm_wvalid), - .m_axi_hbm_wready(m_axi_hbm_wready), - .m_axi_hbm_bid(m_axi_hbm_bid), - .m_axi_hbm_bresp(m_axi_hbm_bresp), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(m_axi_hbm_bvalid), - .m_axi_hbm_bready(m_axi_hbm_bready), - .m_axi_hbm_arid(m_axi_hbm_arid), - .m_axi_hbm_araddr(m_axi_hbm_araddr), - .m_axi_hbm_arlen(m_axi_hbm_arlen), - .m_axi_hbm_arsize(m_axi_hbm_arsize), - .m_axi_hbm_arburst(m_axi_hbm_arburst), - .m_axi_hbm_arlock(m_axi_hbm_arlock), - .m_axi_hbm_arcache(m_axi_hbm_arcache), - .m_axi_hbm_arprot(m_axi_hbm_arprot), - .m_axi_hbm_arqos(m_axi_hbm_arqos), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(m_axi_hbm_arvalid), - .m_axi_hbm_arready(m_axi_hbm_arready), - .m_axi_hbm_rid(m_axi_hbm_rid), - .m_axi_hbm_rdata(m_axi_hbm_rdata), - .m_axi_hbm_rresp(m_axi_hbm_rresp), - .m_axi_hbm_rlast(m_axi_hbm_rlast), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(m_axi_hbm_rvalid), - .m_axi_hbm_rready(m_axi_hbm_rready), - - .hbm_status(hbm_status), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/AU50/fpga_25g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/AU50/fpga_25g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile deleted file mode 100644 index 3148af484..000000000 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ /dev/null @@ -1,261 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rb_drp.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 1 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 -export PARAM_PTP_CLOCK_PIPELINE := 1 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 1 -export PARAM_PTP_PEROUT_ENABLE := 0 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 6 -export PARAM_TX_QUEUE_INDEX_WIDTH := 13 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 131072 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_AXIS_PCIE_DATA_WIDTH := 512 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 31fea2759..000000000 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,782 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import struct -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus, AxiLiteBus, AxiLiteRam -from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = UltraScalePlusPcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=16, - user_clk_frequency=250e6, - alignment="dword", - cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, - cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, - rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, - pf_count=1, - max_payload_size=1024, - enable_client_tag=True, - enable_extended_tag=True, - enable_parity=False, - enable_rx_msg_interface=False, - enable_sriov=False, - enable_extended_configuration=False, - - pf0_msi_enable=False, - pf0_msi_count=32, - pf1_msi_enable=False, - pf1_msi_count=1, - pf2_msi_enable=False, - pf2_msi_count=1, - pf3_msi_enable=False, - pf3_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - pf2_msix_enable=False, - pf2_msix_table_size=0, - pf2_msix_table_bir=0, - pf2_msix_table_offset=0x00000000, - pf2_msix_pba_bir=0, - pf2_msix_pba_offset=0x00000000, - pf3_msix_enable=False, - pf3_msix_table_size=0, - pf3_msix_table_bir=0, - pf3_msix_table_offset=0x00000000, - pf3_msix_pba_bir=0, - pf3_msix_pba_offset=0x00000000, - - # signals - # Clock and Reset Interface - user_clk=dut.clk_250mhz, - user_reset=dut.rst_250mhz, - # user_lnk_up - # sys_clk - # sys_clk_gt - # sys_reset - # phy_rdy_out - - # Requester reQuest Interface - rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), - pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 - # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 - - # Requester Completion Interface - rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), - - # Completer reQuest Interface - cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - # pcie_cq_np_req - # pcie_cq_np_req_count - - # Completer Completion Interface - cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), - - # Transmit Flow Control Interface - # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, - # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, - - # Configuration Management Interface - cfg_mgmt_addr=dut.cfg_mgmt_addr, - cfg_mgmt_function_number=dut.cfg_mgmt_function_number, - cfg_mgmt_write=dut.cfg_mgmt_write, - cfg_mgmt_write_data=dut.cfg_mgmt_write_data, - cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, - cfg_mgmt_read=dut.cfg_mgmt_read, - cfg_mgmt_read_data=dut.cfg_mgmt_read_data, - cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, - # cfg_mgmt_debug_access - - # Configuration Status Interface - # cfg_phy_link_down - # cfg_phy_link_status - # cfg_negotiated_width - # cfg_current_speed - cfg_max_payload=dut.cfg_max_payload, - cfg_max_read_req=dut.cfg_max_read_req, - # cfg_function_status - # cfg_vf_status - # cfg_function_power_state - # cfg_vf_power_state - # cfg_link_power_state - # cfg_err_cor_out - # cfg_err_nonfatal_out - # cfg_err_fatal_out - # cfg_local_error_out - # cfg_local_error_valid - # cfg_rx_pm_state - # cfg_tx_pm_state - # cfg_ltssm_state - cfg_rcb_status=dut.cfg_rcb_status, - # cfg_obff_enable - # cfg_pl_status_change - # cfg_tph_requester_enable - # cfg_tph_st_mode - # cfg_vf_tph_requester_enable - # cfg_vf_tph_st_mode - - # Configuration Received Message Interface - # cfg_msg_received - # cfg_msg_received_data - # cfg_msg_received_type - - # Configuration Transmit Message Interface - # cfg_msg_transmit - # cfg_msg_transmit_type - # cfg_msg_transmit_data - # cfg_msg_transmit_done - - # Configuration Flow Control Interface - cfg_fc_ph=dut.cfg_fc_ph, - cfg_fc_pd=dut.cfg_fc_pd, - cfg_fc_nph=dut.cfg_fc_nph, - cfg_fc_npd=dut.cfg_fc_npd, - cfg_fc_cplh=dut.cfg_fc_cplh, - cfg_fc_cpld=dut.cfg_fc_cpld, - cfg_fc_sel=dut.cfg_fc_sel, - - # Configuration Control Interface - # cfg_hot_reset_in - # cfg_hot_reset_out - # cfg_config_space_enable - # cfg_dsn - # cfg_bus_number - # cfg_ds_port_number - # cfg_ds_bus_number - # cfg_ds_device_number - # cfg_ds_function_number - # cfg_power_state_change_ack - # cfg_power_state_change_interrupt - cfg_err_cor_in=dut.status_error_cor, - cfg_err_uncor_in=dut.status_error_uncor, - # cfg_flr_in_process - # cfg_flr_done - # cfg_vf_flr_in_process - # cfg_vf_flr_func_num - # cfg_vf_flr_done - # cfg_pm_aspm_l1_entry_reject - # cfg_pm_aspm_tx_l0s_entry_disable - # cfg_req_pm_transition_l23_ready - # cfg_link_training_enable - - # Configuration Interrupt Controller Interface - # cfg_interrupt_int - # cfg_interrupt_sent - # cfg_interrupt_pending - # cfg_interrupt_msi_enable - # cfg_interrupt_msi_mmenable - # cfg_interrupt_msi_mask_update - # cfg_interrupt_msi_data - # cfg_interrupt_msi_select - # cfg_interrupt_msi_int - # cfg_interrupt_msi_pending_status - # cfg_interrupt_msi_pending_status_data_enable - # cfg_interrupt_msi_pending_status_function_num - # cfg_interrupt_msi_sent - # cfg_interrupt_msi_fail - cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, - cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, - cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, - cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, - cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, - cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, - cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, - cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, - cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, - cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, - cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, - # cfg_interrupt_msi_attr - # cfg_interrupt_msi_tph_present - # cfg_interrupt_msi_tph_type - # cfg_interrupt_msi_tph_st_tag - cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, - - # Configuration Extend Interface - # cfg_ext_read_received - # cfg_ext_write_received - # cfg_ext_register_number - # cfg_ext_function_number - # cfg_ext_write_data - # cfg_ext_write_byte_enable - # cfg_ext_read_data - # cfg_ext_read_data_valid - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) - - # Ethernet - self.qsfp_source = [] - self.qsfp_sink = [] - - for y in range(1, 5): - cocotb.start_soon(Clock(getattr(dut, f"qsfp_rx_clk_{y}"), 2.56, units="ns").start()) - source = XgmiiSource(getattr(dut, f"qsfp_rxd_{y}"), getattr(dut, f"qsfp_rxc_{y}"), getattr(dut, f"qsfp_rx_clk_{y}"), getattr(dut, f"qsfp_rx_rst_{y}")) - self.qsfp_source.append(source) - cocotb.start_soon(Clock(getattr(dut, f"qsfp_tx_clk_{y}"), 2.56, units="ns").start()) - sink = XgmiiSink(getattr(dut, f"qsfp_txd_{y}"), getattr(dut, f"qsfp_txc_{y}"), getattr(dut, f"qsfp_tx_clk_{y}"), getattr(dut, f"qsfp_tx_rst_{y}")) - self.qsfp_sink.append(sink) - getattr(dut, f"qsfp_rx_status_{y}").setimmediatevalue(1) - getattr(dut, f"qsfp_rx_error_count_{y}").setimmediatevalue(0) - - cocotb.start_soon(Clock(dut.qsfp_drp_clk, 8, units="ns").start()) - dut.qsfp_drp_rst.setimmediatevalue(0) - dut.qsfp_drp_do.setimmediatevalue(0) - dut.qsfp_drp_rdy.setimmediatevalue(0) - - dut.qspi_dq_i.setimmediatevalue(0) - - self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - for y in range(1, 5): - getattr(self.dut, f"qsfp_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp_tx_rst_{y}").setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - for y in range(1, 5): - getattr(self.dut, f"qsfp_rx_rst_{y}").setimmediatevalue(1) - getattr(self.dut, f"qsfp_tx_rst_{y}").setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - for y in range(1, 5): - getattr(self.dut, f"qsfp_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp_tx_rst_{y}").setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - for x in range(len(self.qsfp_sink)): - if not self.qsfp_sink[x].empty(): - await self.qsfp_source[x].send(await self.qsfp_sink[x].recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfp_sink[0].recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_source[0].send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfp_sink[0].recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_source[0].send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - if tb.driver.interfaces[0].if_feature_lfc: - tb.log.info("Test LFC pause frame RX") - - await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN) - await tb.driver.hw_regs.read_dword(0) - - lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000) - - await tb.qsfp_source[0].send(XgmiiFrame.from_payload(bytes(lfc_xoff))) - - count = 16 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - if tb.driver.interfaces[0].if_feature_rx_csum: - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "rb_drp.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "tdma_scheduler.v"), - os.path.join(rtl_dir, "common", "tdma_ber.v"), - os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"), - os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), - os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_td_phc.v"), - os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 1 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 - parameters['PTP_CLOCK_PIPELINE'] = 1 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 1 - parameters['PTP_PEROUT_ENABLE'] = 0 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 131072 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['AXIS_PCIE_DATA_WIDTH'] = 512 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/mqnic/Alveo/fpga_100g/README.md b/fpga/mqnic/Alveo/fpga_100g/README.md index 9e64cbbee..8e7a8f686 100644 --- a/fpga/mqnic/Alveo/fpga_100g/README.md +++ b/fpga/mqnic/Alveo/fpga_100g/README.md @@ -5,6 +5,7 @@ This design targets multiple FPGA boards, including most of the Xilinx Alveo line. * FPGA + * AU50: xcu50-fsvh2104-2-e * AU200: xcu200-fsgd2104-2-e * AU250: xcu250-fsgd2104-2-e * AU280: xcu280-fsvh2892-2L-e @@ -12,6 +13,7 @@ This design targets multiple FPGA boards, including most of the Xilinx Alveo lin * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers * RAM + * AU50: 8 GB HBM2 * AU200: 64 GB DDR4 2400 (4x 2G x72 DIMM) * AU250: 64 GB DDR4 2400 (4x 2G x72 DIMM) * AU280: 32 GB DDR4 2400 (2x 2G x72 DIMM) + 8 GB HBM2 diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/Makefile similarity index 98% rename from fpga/mqnic/AU50/fpga_100g/fpga/Makefile rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU50/Makefile index 8ae9e12af..b3d65a1bc 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/Makefile @@ -7,7 +7,8 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au50.v +SYN_FILES += rtl/fpga_hbm.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -114,8 +115,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_au50.xdc +XDC_FILES += placement_au50.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl similarity index 99% rename from fpga/mqnic/AU50/fpga_100g/fpga/config.tcl rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl index de975787d..3853c6e89 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl @@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params CMS_ENABLE "1" + # Structural configuration dict set params IF_COUNT "1" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/Makefile similarity index 98% rename from fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/Makefile index 266db2e1a..2fa42a90f 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/Makefile @@ -7,7 +7,8 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au50.v +SYN_FILES += rtl/fpga_hbm.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -121,8 +122,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_au50.xdc +XDC_FILES += placement_au50.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl similarity index 99% rename from fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl index 930d45d2b..476022298 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl @@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params CMS_ENABLE "1" + # Structural configuration dict set params IF_COUNT "1" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/AU50/fpga_100g/fpga.xdc b/fpga/mqnic/Alveo/fpga_100g/fpga_au50.xdc similarity index 100% rename from fpga/mqnic/AU50/fpga_100g/fpga.xdc rename to fpga/mqnic/Alveo/fpga_100g/fpga_au50.xdc diff --git a/fpga/mqnic/AU50/fpga_100g/placement.xdc b/fpga/mqnic/Alveo/fpga_100g/placement_au50.xdc similarity index 100% rename from fpga/mqnic/AU50/fpga_100g/placement.xdc rename to fpga/mqnic/Alveo/fpga_100g/placement_au50.xdc diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v index 8842bd389..2a9324bd5 100644 --- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v +++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v @@ -2147,6 +2147,9 @@ core_inst ( */ .sw(sw_int), .led(led_int), + .qsfp_led_act(), + .qsfp_led_stat_g(), + .qsfp_led_stat_y(), /* * I2C diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v index d2e67ee61..f5d21ac08 100644 --- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v +++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v @@ -1952,6 +1952,9 @@ core_inst ( */ .sw(0), .led(), + .qsfp_led_act(), + .qsfp_led_stat_g(), + .qsfp_led_stat_y(), /* * I2C diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v new file mode 100644 index 000000000..0f4a12a6b --- /dev/null +++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v @@ -0,0 +1,1722 @@ +// SPDX-License-Identifier: BSD-2-Clause-Views +/* + * Copyright (c) 2019-2023 The Regents of the University of California + */ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // FW and board IDs + parameter FPGA_ID = 32'h4B77093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h10ee_9032, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter CMS_ENABLE = 1, + + // Structural configuration + parameter IF_COUNT = 1, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLOCK_PIPELINE = 1, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PORT_CDC_PIPELINE = 1, + parameter PTP_PEROUT_ENABLE = 0, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter PFC_ENABLE = 1, + parameter LFC_ENABLE = PFC_ENABLE, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 131072, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 131072, + parameter RX_RAM_SIZE = 131072, + + // RAM configuration + parameter HBM_CH = 32, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = HBM_CH, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_MAX_BURST_LEN = 16, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_WIDTH = 512, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter AXIS_ETH_TX_PIPELINE = 4, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, + parameter AXIS_ETH_TX_TS_PIPELINE = 4, + parameter AXIS_ETH_RX_PIPELINE = 4, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock and reset + */ + // input wire clk_100mhz_0_p, + // input wire clk_100mhz_0_n, + input wire clk_100mhz_1_p, + input wire clk_100mhz_1_n, + + /* + * GPIO + */ + output wire qsfp_led_act, + output wire qsfp_led_stat_g, + output wire qsfp_led_stat_y, + output wire hbm_cattrip, + input wire [1:0] msp_gpio, + output wire msp_uart_txd, + input wire msp_uart_rxd, + + /* + * PCI express + */ + input wire [15:0] pcie_rx_p, + input wire [15:0] pcie_rx_n, + output wire [15:0] pcie_tx_p, + output wire [15:0] pcie_tx_n, + input wire pcie_refclk_1_p, + input wire pcie_refclk_1_n, + input wire pcie_reset_n, + + /* + * Ethernet: QSFP28 + */ + output wire [3:0] qsfp_tx_p, + output wire [3:0] qsfp_tx_n, + input wire [3:0] qsfp_rx_p, + input wire [3:0] qsfp_rx_n, + input wire qsfp_mgt_refclk_0_p, + input wire qsfp_mgt_refclk_0_n + // input wire qsfp_mgt_refclk_1_p, + // input wire qsfp_mgt_refclk_1_n +); + +// PTP configuration +parameter PTP_CLK_PERIOD_NS_NUM = 1024; +parameter PTP_CLK_PERIOD_NS_DENOM = 165; +parameter PTP_TS_WIDTH = 96; + +// Interface configuration +parameter TX_TAG_WIDTH = 16; + +// RAM configuration +parameter AXI_HBM_DATA_WIDTH = 256; +parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8); +parameter AXI_HBM_ID_WIDTH = 6; + +// PCIe interface configuration +parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; +parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; +parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; +parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; +parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; +parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter RQ_SEQ_NUM_WIDTH = 6; +parameter PCIE_TAG_COUNT = 256; + +// Ethernet interface configuration +parameter AXIS_ETH_DATA_WIDTH = 512; +parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; +parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; +parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; + +// Clock and reset +wire pcie_user_clk; +wire pcie_user_reset; + +wire clk_161mhz_ref_int; + +wire clk_50mhz_mmcm_out; +wire clk_125mhz_mmcm_out; + +// Internal 50 MHz clock +wire clk_50mhz_int; +wire rst_50mhz_int; + +// Internal 125 MHz clock +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = pcie_user_reset; +wire mmcm_locked; +wire mmcm_clkfb; + +// MMCM instance +// 161.13 MHz in, 50 MHz + 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 128, D = 15 sets Fvco = 1375 MHz (in range) +// Divide by 27.5 to get output frequency of 50 MHz +// Divide by 11 to get output frequency of 125 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(27.5), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(11), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(128), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(15), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(6.206), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(clk_161mhz_ref_int), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_50mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(clk_125mhz_mmcm_out), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_50mhz_bufg_inst ( + .I(clk_50mhz_mmcm_out), + .O(clk_50mhz_int) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_50mhz_inst ( + .clk(clk_50mhz_int), + .rst(~mmcm_locked), + .out(rst_50mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// Flash +wire qspi_clk_int; +wire [3:0] qspi_dq_int; +wire [3:0] qspi_dq_i_int; +wire [3:0] qspi_dq_o_int; +wire [3:0] qspi_dq_oe_int; +wire qspi_cs_int; + +reg qspi_clk_reg; +reg [3:0] qspi_dq_o_reg; +reg [3:0] qspi_dq_oe_reg; +reg qspi_cs_reg; + +always @(posedge pcie_user_clk) begin + qspi_clk_reg <= qspi_clk_int; + qspi_dq_o_reg <= qspi_dq_o_int; + qspi_dq_oe_reg <= qspi_dq_oe_int; + qspi_cs_reg <= qspi_cs_int; +end + +sync_signal #( + .WIDTH(4), + .N(2) +) +flash_sync_signal_inst ( + .clk(pcie_user_clk), + .in({qspi_dq_int}), + .out({qspi_dq_i_int}) +); + +STARTUPE3 +startupe3_inst ( + .CFGCLK(), + .CFGMCLK(), + .DI(qspi_dq_int), + .DO(qspi_dq_o_reg), + .DTS(~qspi_dq_oe_reg), + .EOS(), + .FCSBO(qspi_cs_reg), + .FCSBTS(1'b0), + .GSR(1'b0), + .GTS(1'b0), + .KEYCLEARB(1'b1), + .PACK(1'b0), + .PREQ(), + .USRCCLKO(qspi_clk_reg), + .USRCCLKTS(1'b0), + .USRDONEO(1'b0), + .USRDONETS(1'b1) +); + +// FPGA boot +wire fpga_boot; + +reg fpga_boot_sync_reg_0 = 1'b0; +reg fpga_boot_sync_reg_1 = 1'b0; +reg fpga_boot_sync_reg_2 = 1'b0; + +wire icap_avail; +reg [2:0] icap_state = 0; +reg icap_csib_reg = 1'b1; +reg icap_rdwrb_reg = 1'b0; +reg [31:0] icap_di_reg = 32'hffffffff; + +wire [31:0] icap_di_rev; + +assign icap_di_rev[ 7] = icap_di_reg[ 0]; +assign icap_di_rev[ 6] = icap_di_reg[ 1]; +assign icap_di_rev[ 5] = icap_di_reg[ 2]; +assign icap_di_rev[ 4] = icap_di_reg[ 3]; +assign icap_di_rev[ 3] = icap_di_reg[ 4]; +assign icap_di_rev[ 2] = icap_di_reg[ 5]; +assign icap_di_rev[ 1] = icap_di_reg[ 6]; +assign icap_di_rev[ 0] = icap_di_reg[ 7]; + +assign icap_di_rev[15] = icap_di_reg[ 8]; +assign icap_di_rev[14] = icap_di_reg[ 9]; +assign icap_di_rev[13] = icap_di_reg[10]; +assign icap_di_rev[12] = icap_di_reg[11]; +assign icap_di_rev[11] = icap_di_reg[12]; +assign icap_di_rev[10] = icap_di_reg[13]; +assign icap_di_rev[ 9] = icap_di_reg[14]; +assign icap_di_rev[ 8] = icap_di_reg[15]; + +assign icap_di_rev[23] = icap_di_reg[16]; +assign icap_di_rev[22] = icap_di_reg[17]; +assign icap_di_rev[21] = icap_di_reg[18]; +assign icap_di_rev[20] = icap_di_reg[19]; +assign icap_di_rev[19] = icap_di_reg[20]; +assign icap_di_rev[18] = icap_di_reg[21]; +assign icap_di_rev[17] = icap_di_reg[22]; +assign icap_di_rev[16] = icap_di_reg[23]; + +assign icap_di_rev[31] = icap_di_reg[24]; +assign icap_di_rev[30] = icap_di_reg[25]; +assign icap_di_rev[29] = icap_di_reg[26]; +assign icap_di_rev[28] = icap_di_reg[27]; +assign icap_di_rev[27] = icap_di_reg[28]; +assign icap_di_rev[26] = icap_di_reg[29]; +assign icap_di_rev[25] = icap_di_reg[30]; +assign icap_di_rev[24] = icap_di_reg[31]; + +always @(posedge clk_125mhz_int) begin + case (icap_state) + 0: begin + icap_state <= 0; + icap_csib_reg <= 1'b1; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + + if (fpga_boot_sync_reg_2 && icap_avail) begin + icap_state <= 1; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + end + end + 1: begin + icap_state <= 2; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hAA995566; // sync word + end + 2: begin + icap_state <= 3; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + 3: begin + icap_state <= 4; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h30008001; // write 1 word to CMD + end + 4: begin + icap_state <= 5; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h0000000F; // IPROG + end + 5: begin + icap_state <= 0; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + endcase + + fpga_boot_sync_reg_0 <= fpga_boot; + fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; + fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; +end + +ICAPE3 +icape3_inst ( + .AVAIL(icap_avail), + .CLK(clk_125mhz_int), + .CSIB(icap_csib_reg), + .I(icap_di_rev), + .O(), + .PRDONE(), + .PRERROR(), + .RDWRB(icap_rdwrb_reg) +); + +// BMC +wire axil_cms_clk; +wire axil_cms_rst; +wire [17:0] axil_cms_awaddr; +wire [2:0] axil_cms_awprot; +wire axil_cms_awvalid; +wire axil_cms_awready; +wire [31:0] axil_cms_wdata; +wire [3:0] axil_cms_wstrb; +wire axil_cms_wvalid; +wire axil_cms_wready; +wire [1:0] axil_cms_bresp; +wire axil_cms_bvalid; +wire axil_cms_bready; +wire [17:0] axil_cms_araddr; +wire [2:0] axil_cms_arprot; +wire axil_cms_arvalid; +wire axil_cms_arready; +wire [31:0] axil_cms_rdata; +wire [1:0] axil_cms_rresp; +wire axil_cms_rvalid; +wire axil_cms_rready; + +wire [6:0] hbm_temp_1; +wire [6:0] hbm_temp_2; + +generate + +if (CMS_ENABLE) begin : cms + + wire [17:0] axil_cms_awaddr_int; + wire [2:0] axil_cms_awprot_int; + wire axil_cms_awvalid_int; + wire axil_cms_awready_int; + wire [31:0] axil_cms_wdata_int; + wire [3:0] axil_cms_wstrb_int; + wire axil_cms_wvalid_int; + wire axil_cms_wready_int; + wire [1:0] axil_cms_bresp_int; + wire axil_cms_bvalid_int; + wire axil_cms_bready_int; + wire [17:0] axil_cms_araddr_int; + wire [2:0] axil_cms_arprot_int; + wire axil_cms_arvalid_int; + wire axil_cms_arready_int; + wire [31:0] axil_cms_rdata_int; + wire [1:0] axil_cms_rresp_int; + wire axil_cms_rvalid_int; + wire axil_cms_rready_int; + + axil_cdc #( + .DATA_WIDTH(32), + .ADDR_WIDTH(18) + ) + cms_axil_cdc_inst ( + .s_clk(axil_cms_clk), + .s_rst(axil_cms_rst), + .s_axil_awaddr(axil_cms_awaddr), + .s_axil_awprot(axil_cms_awprot), + .s_axil_awvalid(axil_cms_awvalid), + .s_axil_awready(axil_cms_awready), + .s_axil_wdata(axil_cms_wdata), + .s_axil_wstrb(axil_cms_wstrb), + .s_axil_wvalid(axil_cms_wvalid), + .s_axil_wready(axil_cms_wready), + .s_axil_bresp(axil_cms_bresp), + .s_axil_bvalid(axil_cms_bvalid), + .s_axil_bready(axil_cms_bready), + .s_axil_araddr(axil_cms_araddr), + .s_axil_arprot(axil_cms_arprot), + .s_axil_arvalid(axil_cms_arvalid), + .s_axil_arready(axil_cms_arready), + .s_axil_rdata(axil_cms_rdata), + .s_axil_rresp(axil_cms_rresp), + .s_axil_rvalid(axil_cms_rvalid), + .s_axil_rready(axil_cms_rready), + .m_clk(clk_50mhz_int), + .m_rst(rst_50mhz_int), + .m_axil_awaddr(axil_cms_awaddr_int), + .m_axil_awprot(axil_cms_awprot_int), + .m_axil_awvalid(axil_cms_awvalid_int), + .m_axil_awready(axil_cms_awready_int), + .m_axil_wdata(axil_cms_wdata_int), + .m_axil_wstrb(axil_cms_wstrb_int), + .m_axil_wvalid(axil_cms_wvalid_int), + .m_axil_wready(axil_cms_wready_int), + .m_axil_bresp(axil_cms_bresp_int), + .m_axil_bvalid(axil_cms_bvalid_int), + .m_axil_bready(axil_cms_bready_int), + .m_axil_araddr(axil_cms_araddr_int), + .m_axil_arprot(axil_cms_arprot_int), + .m_axil_arvalid(axil_cms_arvalid_int), + .m_axil_arready(axil_cms_arready_int), + .m_axil_rdata(axil_cms_rdata_int), + .m_axil_rresp(axil_cms_rresp_int), + .m_axil_rvalid(axil_cms_rvalid_int), + .m_axil_rready(axil_cms_rready_int) + ); + + cms_wrapper + cms_inst ( + .aclk_ctrl_0(clk_50mhz_int), + .aresetn_ctrl_0(~rst_50mhz_int), + .hbm_temp_1_0(hbm_temp_1), + .hbm_temp_2_0(hbm_temp_2), + .interrupt_hbm_cattrip_0(hbm_cattrip), + .interrupt_host_0(), + .s_axi_ctrl_0_araddr(axil_cms_araddr_int), + .s_axi_ctrl_0_arprot(axil_cms_arprot_int), + .s_axi_ctrl_0_arready(axil_cms_arready_int), + .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), + .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), + .s_axi_ctrl_0_awprot(axil_cms_awprot_int), + .s_axi_ctrl_0_awready(axil_cms_awready_int), + .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), + .s_axi_ctrl_0_bready(axil_cms_bready_int), + .s_axi_ctrl_0_bresp(axil_cms_bresp_int), + .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), + .s_axi_ctrl_0_rdata(axil_cms_rdata_int), + .s_axi_ctrl_0_rready(axil_cms_rready_int), + .s_axi_ctrl_0_rresp(axil_cms_rresp_int), + .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), + .s_axi_ctrl_0_wdata(axil_cms_wdata_int), + .s_axi_ctrl_0_wready(axil_cms_wready_int), + .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), + .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), + .satellite_gpio_0(msp_gpio), + .satellite_uart_0_rxd(msp_uart_rxd), + .satellite_uart_0_txd(msp_uart_txd) + ); + +end else begin + + assign axil_cms_awready = 0; + assign axil_cms_wdata = 0; + assign axil_cms_wstrb = 0; + assign axil_cms_wvalid = 0; + assign axil_cms_bresp = 0; + assign axil_cms_bvalid = 0; + assign axil_cms_arready = 0; + assign axil_cms_rdata = 0; + assign axil_cms_rresp = 0; + assign axil_cms_rvalid = 0; + + assign msp_uart_txd = 1'bz; + +end + +endgenerate + +// PCIe +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE4 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte4_pcie_mgt_refclk_inst ( + .I (pcie_refclk_1_p), + .IB (pcie_refclk_1_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; +wire axis_rq_tlast; +wire axis_rq_tready; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; +wire axis_rq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; +wire axis_rc_tlast; +wire axis_rc_tready; +wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; +wire axis_rc_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; +wire axis_cq_tlast; +wire axis_cq_tready; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; +wire axis_cq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; +wire axis_cc_tlast; +wire axis_cc_tready; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; +wire axis_cc_tvalid; + +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; +wire pcie_rq_seq_num_vld0; +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; +wire pcie_rq_seq_num_vld1; + +wire [3:0] pcie_tfc_nph_av; +wire [3:0] pcie_tfc_npd_av; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; +wire [3:0] cfg_rcb_status; + +wire [9:0] cfg_mgmt_addr; +wire [7:0] cfg_mgmt_function_number; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [7:0] cfg_fc_ph; +wire [11:0] cfg_fc_pd; +wire [7:0] cfg_fc_nph; +wire [11:0] cfg_fc_npd; +wire [7:0] cfg_fc_cplh; +wire [11:0] cfg_fc_cpld; +wire [2:0] cfg_fc_sel; + +wire [3:0] cfg_interrupt_msix_enable; +wire [3:0] cfg_interrupt_msix_mask; +wire [251:0] cfg_interrupt_msix_vf_enable; +wire [251:0] cfg_interrupt_msix_vf_mask; +wire [63:0] cfg_interrupt_msix_address; +wire [31:0] cfg_interrupt_msix_data; +wire cfg_interrupt_msix_int; +wire [1:0] cfg_interrupt_msix_vec_pending; +wire cfg_interrupt_msix_vec_pending_status; +wire cfg_interrupt_msix_sent; +wire cfg_interrupt_msix_fail; +wire [7:0] cfg_interrupt_msi_function_number; + +wire status_error_cor; +wire status_error_uncor; + +// extra register for pcie_user_reset signal +wire pcie_user_reset_int; +(* shreg_extract = "no" *) +reg pcie_user_reset_reg_1 = 1'b1; +(* shreg_extract = "no" *) +reg pcie_user_reset_reg_2 = 1'b1; + +always @(posedge pcie_user_clk) begin + pcie_user_reset_reg_1 <= pcie_user_reset_int; + pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; +end + +BUFG +pcie_user_reset_bufg_inst ( + .I(pcie_user_reset_reg_2), + .O(pcie_user_reset) +); + +pcie4c_uscale_plus_0 +pcie4c_uscale_plus_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_reset_int), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_rq_tdata), + .s_axis_rq_tkeep(axis_rq_tkeep), + .s_axis_rq_tlast(axis_rq_tlast), + .s_axis_rq_tready(axis_rq_tready), + .s_axis_rq_tuser(axis_rq_tuser), + .s_axis_rq_tvalid(axis_rq_tvalid), + + .m_axis_rc_tdata(axis_rc_tdata), + .m_axis_rc_tkeep(axis_rc_tkeep), + .m_axis_rc_tlast(axis_rc_tlast), + .m_axis_rc_tready(axis_rc_tready), + .m_axis_rc_tuser(axis_rc_tuser), + .m_axis_rc_tvalid(axis_rc_tvalid), + + .m_axis_cq_tdata(axis_cq_tdata), + .m_axis_cq_tkeep(axis_cq_tkeep), + .m_axis_cq_tlast(axis_cq_tlast), + .m_axis_cq_tready(axis_cq_tready), + .m_axis_cq_tuser(axis_cq_tuser), + .m_axis_cq_tvalid(axis_cq_tvalid), + + .s_axis_cc_tdata(axis_cc_tdata), + .s_axis_cc_tkeep(axis_cc_tkeep), + .s_axis_cc_tlast(axis_cc_tlast), + .s_axis_cc_tready(axis_cc_tready), + .s_axis_cc_tuser(axis_cc_tuser), + .s_axis_cc_tvalid(axis_cc_tvalid), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + .pcie_rq_tag0(), + .pcie_rq_tag1(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld0(), + .pcie_rq_tag_vld1(), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_debug_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error_valid(), + .cfg_local_error_out(), + .cfg_ltssm_state(), + .cfg_rx_pm_state(), + .cfg_tx_pm_state(), + .cfg_rcb_status(cfg_rcb_status), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_dsn(64'd0), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(status_error_cor), + .cfg_err_uncor_in(status_error_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_func_num(8'd0), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_pm_aspm_l1_entry_reject(1'b0), + .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_reset_n), + + .phy_rdy_out() +); + +reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0_reg; +reg pcie_rq_seq_num_vld0_reg; +reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1_reg; +reg pcie_rq_seq_num_vld1_reg; + +always @(posedge pcie_user_clk) begin + pcie_rq_seq_num0_reg <= pcie_rq_seq_num0; + pcie_rq_seq_num_vld0_reg <= pcie_rq_seq_num_vld0; + pcie_rq_seq_num1_reg <= pcie_rq_seq_num1; + pcie_rq_seq_num_vld1_reg <= pcie_rq_seq_num_vld1; + + if (pcie_user_reset) begin + pcie_rq_seq_num_vld0_reg <= 1'b0; + pcie_rq_seq_num_vld1_reg <= 1'b0; + end +end + +// Ethernet +localparam QSFP_CNT = 1; + +wire [QSFP_CNT-1:0] qsfp_tx_clk; +wire [QSFP_CNT-1:0] qsfp_tx_rst; + +wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_tx_axis_tdata; +wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_tx_axis_tkeep; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tvalid; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tready; +wire [QSFP_CNT-1:0] qsfp_tx_axis_tlast; +wire [QSFP_CNT*(16+1)-1:0] qsfp_tx_axis_tuser; + +wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_time; +wire [QSFP_CNT*80-1:0] qsfp_tx_ptp_ts; +wire [QSFP_CNT*16-1:0] qsfp_tx_ptp_ts_tag; +wire [QSFP_CNT-1:0] qsfp_tx_ptp_ts_valid; + +wire [QSFP_CNT-1:0] qsfp_tx_enable; +wire [QSFP_CNT-1:0] qsfp_tx_lfc_en; +wire [QSFP_CNT-1:0] qsfp_tx_lfc_req; +wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_en; +wire [QSFP_CNT*8-1:0] qsfp_tx_pfc_req; + +wire [QSFP_CNT-1:0] qsfp_rx_clk; +wire [QSFP_CNT-1:0] qsfp_rx_rst; + +wire [QSFP_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_rx_axis_tdata; +wire [QSFP_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_rx_axis_tkeep; +wire [QSFP_CNT-1:0] qsfp_rx_axis_tvalid; +wire [QSFP_CNT-1:0] qsfp_rx_axis_tlast; +wire [QSFP_CNT*(80+1)-1:0] qsfp_rx_axis_tuser; + +wire [QSFP_CNT*80-1:0] qsfp_rx_ptp_time; + +wire [QSFP_CNT-1:0] qsfp_rx_enable; +wire [QSFP_CNT-1:0] qsfp_rx_status; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_en; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_req; +wire [QSFP_CNT-1:0] qsfp_rx_lfc_ack; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_en; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_req; +wire [QSFP_CNT*8-1:0] qsfp_rx_pfc_ack; + +wire [QSFP_CNT-1:0] qsfp_drp_clk; +wire [QSFP_CNT-1:0] qsfp_drp_rst; +wire [QSFP_CNT*24-1:0] qsfp_drp_addr; +wire [QSFP_CNT*16-1:0] qsfp_drp_di; +wire [QSFP_CNT-1:0] qsfp_drp_en; +wire [QSFP_CNT-1:0] qsfp_drp_we; +wire [QSFP_CNT*16-1:0] qsfp_drp_do; +wire [QSFP_CNT-1:0] qsfp_drp_rdy; + +// CMAC +assign qsfp_drp_clk[0 +: 1] = clk_125mhz_int; +assign qsfp_drp_rst[0 +: 1] = rst_125mhz_int; + +wire qsfp_gtpowergood; + +wire qsfp_mgt_refclk_0; +wire qsfp_mgt_refclk_0_int; +wire qsfp_mgt_refclk_0_bufg; + +assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst ( + .I (qsfp_mgt_refclk_0_p), + .IB (qsfp_mgt_refclk_0_n), + .CEB (1'b0), + .O (qsfp_mgt_refclk_0), + .ODIV2 (qsfp_mgt_refclk_0_int) +); + +BUFG_GT bufg_gt_qsfp_mgt_refclk_0_inst ( + .CE (qsfp_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_mgt_refclk_0_int), + .O (qsfp_mgt_refclk_0_bufg) +); + +wire qsfp_rst; + +sync_reset #( + .N(4) +) +qsfp_sync_reset_inst ( + .clk(qsfp_mgt_refclk_0_bufg), + .rst(rst_125mhz_int), + .out(qsfp_rst) +); + +cmac_gty_wrapper #( + .DRP_CLK_FREQ_HZ(125000000), + .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_SERDES_PIPELINE(0), + .RX_SERDES_PIPELINE(0), + .RS_FEC_ENABLE(1) +) +qsfp_cmac_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp_gtpowergood), + .xcvr_ref_clk(qsfp_mgt_refclk_0), + + /* + * DRP + */ + .drp_clk(qsfp_drp_clk[0 +: 1]), + .drp_rst(qsfp_drp_rst[0 +: 1]), + .drp_addr(qsfp_drp_addr[0*24 +: 24]), + .drp_di(qsfp_drp_di[0*16 +: 16]), + .drp_en(qsfp_drp_en[0 +: 1]), + .drp_we(qsfp_drp_we[0 +: 1]), + .drp_do(qsfp_drp_do[0*16 +: 16]), + .drp_rdy(qsfp_drp_rdy[0 +: 1]), + + /* + * Serial data + */ + .xcvr_txp(qsfp_tx_p), + .xcvr_txn(qsfp_tx_n), + .xcvr_rxp(qsfp_rx_p), + .xcvr_rxn(qsfp_rx_n), + + /* + * CMAC connections + */ + .tx_clk(qsfp_tx_clk[0 +: 1]), + .tx_rst(qsfp_tx_rst[0 +: 1]), + + .tx_axis_tdata(qsfp_tx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .tx_axis_tkeep(qsfp_tx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .tx_axis_tvalid(qsfp_tx_axis_tvalid[0 +: 1]), + .tx_axis_tready(qsfp_tx_axis_tready[0 +: 1]), + .tx_axis_tlast(qsfp_tx_axis_tlast[0 +: 1]), + .tx_axis_tuser(qsfp_tx_axis_tuser[0*(16+1) +: (16+1)]), + + .tx_ptp_time(qsfp_tx_ptp_time[0*80 +: 80]), + .tx_ptp_ts(qsfp_tx_ptp_ts[0*80 +: 80]), + .tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag[0*16 +: 16]), + .tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid[0 +: 1]), + + .tx_enable(qsfp_tx_enable[0 +: 1]), + .tx_lfc_en(qsfp_tx_lfc_en[0 +: 1]), + .tx_lfc_req(qsfp_tx_lfc_req[0 +: 1]), + .tx_pfc_en(qsfp_tx_pfc_en[0*8 +: 8]), + .tx_pfc_req(qsfp_tx_pfc_req[0*8 +: 8]), + + .rx_clk(qsfp_rx_clk[0 +: 1]), + .rx_rst(qsfp_rx_rst[0 +: 1]), + + .rx_axis_tdata(qsfp_rx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .rx_axis_tkeep(qsfp_rx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .rx_axis_tvalid(qsfp_rx_axis_tvalid[0 +: 1]), + .rx_axis_tlast(qsfp_rx_axis_tlast[0 +: 1]), + .rx_axis_tuser(qsfp_rx_axis_tuser[0*(80+1) +: (80+1)]), + + .rx_ptp_time(qsfp_rx_ptp_time[0*80 +: 80]), + + .rx_enable(qsfp_rx_enable[0 +: 1]), + .rx_status(qsfp_rx_status[0 +: 1]), + .rx_lfc_en(qsfp_rx_lfc_en[0 +: 1]), + .rx_lfc_req(qsfp_rx_lfc_req[0 +: 1]), + .rx_lfc_ack(qsfp_rx_lfc_ack[0 +: 1]), + .rx_pfc_en(qsfp_rx_pfc_en[0*8 +: 8]), + .rx_pfc_req(qsfp_rx_pfc_req[0*8 +: 8]), + .rx_pfc_ack(qsfp_rx_pfc_ack[0*8 +: 8]) +); + +wire ptp_clk; +wire ptp_rst; +wire ptp_sample_clk; + +assign ptp_clk = qsfp_mgt_refclk_0_bufg; +assign ptp_rst = qsfp_rst; +assign ptp_sample_clk = clk_125mhz_int; + +assign qsfp_led_stat_g = qsfp_rx_status; + +// HBM +wire [HBM_CH-1:0] hbm_clk; +wire [HBM_CH-1:0] hbm_rst; + +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr; +wire [HBM_CH*8-1:0] m_axi_hbm_awlen; +wire [HBM_CH*3-1:0] m_axi_hbm_awsize; +wire [HBM_CH*2-1:0] m_axi_hbm_awburst; +wire [HBM_CH-1:0] m_axi_hbm_awlock; +wire [HBM_CH*4-1:0] m_axi_hbm_awcache; +wire [HBM_CH*3-1:0] m_axi_hbm_awprot; +wire [HBM_CH*4-1:0] m_axi_hbm_awqos; +wire [HBM_CH-1:0] m_axi_hbm_awvalid; +wire [HBM_CH-1:0] m_axi_hbm_awready; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata; +wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb; +wire [HBM_CH-1:0] m_axi_hbm_wlast; +wire [HBM_CH-1:0] m_axi_hbm_wvalid; +wire [HBM_CH-1:0] m_axi_hbm_wready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid; +wire [HBM_CH*2-1:0] m_axi_hbm_bresp; +wire [HBM_CH-1:0] m_axi_hbm_bvalid; +wire [HBM_CH-1:0] m_axi_hbm_bready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr; +wire [HBM_CH*8-1:0] m_axi_hbm_arlen; +wire [HBM_CH*3-1:0] m_axi_hbm_arsize; +wire [HBM_CH*2-1:0] m_axi_hbm_arburst; +wire [HBM_CH-1:0] m_axi_hbm_arlock; +wire [HBM_CH*4-1:0] m_axi_hbm_arcache; +wire [HBM_CH*3-1:0] m_axi_hbm_arprot; +wire [HBM_CH*4-1:0] m_axi_hbm_arqos; +wire [HBM_CH-1:0] m_axi_hbm_arvalid; +wire [HBM_CH-1:0] m_axi_hbm_arready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata; +wire [HBM_CH*2-1:0] m_axi_hbm_rresp; +wire [HBM_CH-1:0] m_axi_hbm_rlast; +wire [HBM_CH-1:0] m_axi_hbm_rvalid; +wire [HBM_CH-1:0] m_axi_hbm_rready; + +wire [HBM_CH-1:0] hbm_status; + +wire clk_100mhz_1_ibufg; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_1_ibufg_inst ( + .O (clk_100mhz_1_ibufg), + .I (clk_100mhz_1_p), + .IB (clk_100mhz_1_n) +); + +generate + +if (HBM_ENABLE) begin + + wire hbm_ref_clk; + + BUFG + hbm_ref_clk_bufg_inst ( + .I(clk_100mhz_1_ibufg), + .O(hbm_ref_clk) + ); + + wire hbm_cattrip_1; + wire hbm_cattrip_2; + + assign hbm_cattrip = hbm_cattrip_1 | hbm_cattrip_2; + + fpga_hbm #( + .HBM_CH(HBM_CH), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN) + ) + hbm_inst ( + .hbm_ref_clk(hbm_ref_clk), + .hbm_rst_in(rst_125mhz_int), + + .hbm_cattrip_1(hbm_cattrip_1), + .hbm_cattrip_2(hbm_cattrip_2), + .hbm_temp_1(hbm_temp_1), + .hbm_temp_2(hbm_temp_2), + + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .s_axi_hbm_awid(m_axi_hbm_awid), + .s_axi_hbm_awaddr(m_axi_hbm_awaddr), + .s_axi_hbm_awlen(m_axi_hbm_awlen), + .s_axi_hbm_awsize(m_axi_hbm_awsize), + .s_axi_hbm_awburst(m_axi_hbm_awburst), + .s_axi_hbm_awlock(m_axi_hbm_awlock), + .s_axi_hbm_awcache(m_axi_hbm_awcache), + .s_axi_hbm_awprot(m_axi_hbm_awprot), + .s_axi_hbm_awqos(m_axi_hbm_awqos), + .s_axi_hbm_awvalid(m_axi_hbm_awvalid), + .s_axi_hbm_awready(m_axi_hbm_awready), + .s_axi_hbm_wdata(m_axi_hbm_wdata), + .s_axi_hbm_wstrb(m_axi_hbm_wstrb), + .s_axi_hbm_wlast(m_axi_hbm_wlast), + .s_axi_hbm_wvalid(m_axi_hbm_wvalid), + .s_axi_hbm_wready(m_axi_hbm_wready), + .s_axi_hbm_bid(m_axi_hbm_bid), + .s_axi_hbm_bresp(m_axi_hbm_bresp), + .s_axi_hbm_bvalid(m_axi_hbm_bvalid), + .s_axi_hbm_bready(m_axi_hbm_bready), + .s_axi_hbm_arid(m_axi_hbm_arid), + .s_axi_hbm_araddr(m_axi_hbm_araddr), + .s_axi_hbm_arlen(m_axi_hbm_arlen), + .s_axi_hbm_arsize(m_axi_hbm_arsize), + .s_axi_hbm_arburst(m_axi_hbm_arburst), + .s_axi_hbm_arlock(m_axi_hbm_arlock), + .s_axi_hbm_arcache(m_axi_hbm_arcache), + .s_axi_hbm_arprot(m_axi_hbm_arprot), + .s_axi_hbm_arqos(m_axi_hbm_arqos), + .s_axi_hbm_arvalid(m_axi_hbm_arvalid), + .s_axi_hbm_arready(m_axi_hbm_arready), + .s_axi_hbm_rid(m_axi_hbm_rid), + .s_axi_hbm_rdata(m_axi_hbm_rdata), + .s_axi_hbm_rresp(m_axi_hbm_rresp), + .s_axi_hbm_rlast(m_axi_hbm_rlast), + .s_axi_hbm_rvalid(m_axi_hbm_rvalid), + .s_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status) + ); + +end else begin + + assign hbm_clk = 0; + assign hbm_rst = 0; + + assign m_axi_hbm_awready = 0; + assign m_axi_hbm_wready = 0; + assign m_axi_hbm_bid = 0; + assign m_axi_hbm_bresp = 0; + assign m_axi_hbm_bvalid = 0; + assign m_axi_hbm_arready = 0; + assign m_axi_hbm_rid = 0; + assign m_axi_hbm_rdata = 0; + assign m_axi_hbm_rresp = 0; + assign m_axi_hbm_rlast = 0; + assign m_axi_hbm_rvalid = 0; + + assign hbm_status = 0; + + assign hbm_cattrip = 1'b0; + + assign hbm_temp_1 = 7'd0; + assign hbm_temp_2 = 7'd0; + +end + +endgenerate + +fpga_core #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Board configuration + .QSFP_CNT(QSFP_CNT), + .CH_CNT(QSFP_CNT*4), + .CMS_ENABLE(CMS_ENABLE), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + .PORT_MASK(PORT_MASK), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .PFC_ENABLE(PFC_ENABLE), + .LFC_ENABLE(LFC_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // RAM configuration + .DDR_ENABLE(0), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RC_STRADDLE(RC_STRADDLE), + .RQ_STRADDLE(RQ_STRADDLE), + .CQ_STRADDLE(CQ_STRADDLE), + .CC_STRADDLE(CC_STRADDLE), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + /* + * Clock: 250 MHz + * Synchronous reset + */ + .clk_250mhz(pcie_user_clk), + .rst_250mhz(pcie_user_reset), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + + /* + * GPIO + */ + .sw(0), + .led(), + .qsfp_led_act(qsfp_led_act), + //.qsfp_led_stat_g(qsfp_led_stat_g), + .qsfp_led_stat_y(qsfp_led_stat_y), + + /* + * I2C + */ + .i2c_scl_i(1'b1), + .i2c_scl_o(), + .i2c_scl_t(), + .i2c_sda_i(1'b1), + .i2c_sda_o(), + .i2c_sda_t(), + + /* + * PCIe + */ + .m_axis_rq_tdata(axis_rq_tdata), + .m_axis_rq_tkeep(axis_rq_tkeep), + .m_axis_rq_tlast(axis_rq_tlast), + .m_axis_rq_tready(axis_rq_tready), + .m_axis_rq_tuser(axis_rq_tuser), + .m_axis_rq_tvalid(axis_rq_tvalid), + + .s_axis_rc_tdata(axis_rc_tdata), + .s_axis_rc_tkeep(axis_rc_tkeep), + .s_axis_rc_tlast(axis_rc_tlast), + .s_axis_rc_tready(axis_rc_tready), + .s_axis_rc_tuser(axis_rc_tuser), + .s_axis_rc_tvalid(axis_rc_tvalid), + + .s_axis_cq_tdata(axis_cq_tdata), + .s_axis_cq_tkeep(axis_cq_tkeep), + .s_axis_cq_tlast(axis_cq_tlast), + .s_axis_cq_tready(axis_cq_tready), + .s_axis_cq_tuser(axis_cq_tuser), + .s_axis_cq_tvalid(axis_cq_tvalid), + + .m_axis_cc_tdata(axis_cc_tdata), + .m_axis_cc_tkeep(axis_cc_tkeep), + .m_axis_cc_tlast(axis_cc_tlast), + .m_axis_cc_tready(axis_cc_tready), + .m_axis_cc_tuser(axis_cc_tuser), + .m_axis_cc_tvalid(axis_cc_tvalid), + + .s_axis_rq_seq_num_0(pcie_rq_seq_num0_reg), + .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0_reg), + .s_axis_rq_seq_num_1(pcie_rq_seq_num1_reg), + .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1_reg), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * Ethernet: QSFP28 + */ + .qsfp_tx_clk(qsfp_tx_clk), + .qsfp_tx_rst(qsfp_tx_rst), + .qsfp_tx_axis_tdata(qsfp_tx_axis_tdata), + .qsfp_tx_axis_tkeep(qsfp_tx_axis_tkeep), + .qsfp_tx_axis_tvalid(qsfp_tx_axis_tvalid), + .qsfp_tx_axis_tready(qsfp_tx_axis_tready), + .qsfp_tx_axis_tlast(qsfp_tx_axis_tlast), + .qsfp_tx_axis_tuser(qsfp_tx_axis_tuser), + .qsfp_tx_ptp_time(qsfp_tx_ptp_time), + .qsfp_tx_ptp_ts(qsfp_tx_ptp_ts), + .qsfp_tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag), + .qsfp_tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid), + + .qsfp_tx_enable(qsfp_tx_enable), + .qsfp_tx_lfc_en(qsfp_tx_lfc_en), + .qsfp_tx_lfc_req(qsfp_tx_lfc_req), + .qsfp_tx_pfc_en(qsfp_tx_pfc_en), + .qsfp_tx_pfc_req(qsfp_tx_pfc_req), + + .qsfp_rx_clk(qsfp_rx_clk), + .qsfp_rx_rst(qsfp_rx_rst), + .qsfp_rx_axis_tdata(qsfp_rx_axis_tdata), + .qsfp_rx_axis_tkeep(qsfp_rx_axis_tkeep), + .qsfp_rx_axis_tvalid(qsfp_rx_axis_tvalid), + .qsfp_rx_axis_tlast(qsfp_rx_axis_tlast), + .qsfp_rx_axis_tuser(qsfp_rx_axis_tuser), + .qsfp_rx_ptp_time(qsfp_rx_ptp_time), + + .qsfp_rx_enable(qsfp_rx_enable), + .qsfp_rx_status(qsfp_rx_status), + .qsfp_rx_lfc_en(qsfp_rx_lfc_en), + .qsfp_rx_lfc_req(qsfp_rx_lfc_req), + .qsfp_rx_lfc_ack(qsfp_rx_lfc_ack), + .qsfp_rx_pfc_en(qsfp_rx_pfc_en), + .qsfp_rx_pfc_req(qsfp_rx_pfc_req), + .qsfp_rx_pfc_ack(qsfp_rx_pfc_ack), + + .qsfp_drp_clk(qsfp_drp_clk), + .qsfp_drp_rst(qsfp_drp_rst), + .qsfp_drp_addr(qsfp_drp_addr), + .qsfp_drp_di(qsfp_drp_di), + .qsfp_drp_en(qsfp_drp_en), + .qsfp_drp_we(qsfp_drp_we), + .qsfp_drp_do(qsfp_drp_do), + .qsfp_drp_rdy(qsfp_drp_rdy), + + .qsfp_modprsl(1'b0), + .qsfp_modsell(), + .qsfp_resetl(), + .qsfp_intl(1'b1), + .qsfp_lpmode(), + + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk_int), + .qspi_dq_i(qspi_dq_i_int), + .qspi_dq_o(qspi_dq_o_int), + .qspi_dq_oe(qspi_dq_oe_int), + .qspi_cs(qspi_cs_int), + + /* + * AXI-Lite interface to CMS + */ + .m_axil_cms_clk(axil_cms_clk), + .m_axil_cms_rst(axil_cms_rst), + .m_axil_cms_awaddr(axil_cms_awaddr), + .m_axil_cms_awprot(axil_cms_awprot), + .m_axil_cms_awvalid(axil_cms_awvalid), + .m_axil_cms_awready(axil_cms_awready), + .m_axil_cms_wdata(axil_cms_wdata), + .m_axil_cms_wstrb(axil_cms_wstrb), + .m_axil_cms_wvalid(axil_cms_wvalid), + .m_axil_cms_wready(axil_cms_wready), + .m_axil_cms_bresp(axil_cms_bresp), + .m_axil_cms_bvalid(axil_cms_bvalid), + .m_axil_cms_bready(axil_cms_bready), + .m_axil_cms_araddr(axil_cms_araddr), + .m_axil_cms_arprot(axil_cms_arprot), + .m_axil_cms_arvalid(axil_cms_arvalid), + .m_axil_cms_arready(axil_cms_arready), + .m_axil_cms_rdata(axil_cms_rdata), + .m_axil_cms_rresp(axil_cms_rresp), + .m_axil_cms_rvalid(axil_cms_rvalid), + .m_axil_cms_rready(axil_cms_rready) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v index 4adb4f839..b4bcb2584 100644 --- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v @@ -191,6 +191,9 @@ module fpga_core # */ input wire [3:0] sw, output wire [2:0] led, + output wire [QSFP_CNT-1:0] qsfp_led_act, + output wire [QSFP_CNT-1:0] qsfp_led_stat_g, + output wire [QSFP_CNT-1:0] qsfp_led_stat_y, /* * I2C @@ -817,6 +820,10 @@ endgenerate assign led[0] = ptp_pps_str; assign led[2:1] = 0; +assign qsfp_led_act = ptp_pps_str; +assign qsfp_led_stat_g = 0; +assign qsfp_led_stat_y = 0; + wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; diff --git a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v index 6d57d6462..a095dde1f 100644 --- a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v +++ b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v @@ -210,6 +210,9 @@ module test_fpga_core # */ input wire [3:0] sw, output wire [2:0] led, + output wire [QSFP_CNT-1:0] qsfp_led_act, + output wire [QSFP_CNT-1:0] qsfp_led_stat_g, + output wire [QSFP_CNT-1:0] qsfp_led_stat_y, /* * I2C @@ -795,6 +798,9 @@ uut ( */ .sw(sw), .led(led), + .qsfp_led_act(qsfp_led_act), + .qsfp_led_stat_g(qsfp_led_stat_g), + .qsfp_led_stat_y(qsfp_led_stat_y), /* * I2C diff --git a/fpga/mqnic/Alveo/fpga_25g/README.md b/fpga/mqnic/Alveo/fpga_25g/README.md index 6c68a607c..9aaa6fd04 100644 --- a/fpga/mqnic/Alveo/fpga_25g/README.md +++ b/fpga/mqnic/Alveo/fpga_25g/README.md @@ -5,12 +5,14 @@ This design targets multiple FPGA boards, including most of the Xilinx Alveo line. * FPGA + * AU50: xcu50-fsvh2104-2-e * AU200: xcu200-fsgd2104-2-e * AU250: xcu250-fsgd2104-2-e * AU280: xcu280-fsvh2892-2L-e * VCU1525: xcvu9p-fsgd2104-2L-e * PHY: 10G BASE-R PHY IP core and internal GTY transceiver * RAM + * AU50: 8 GB HBM2 * AU200: 64 GB DDR4 2400 (4x 2G x72 DIMM) * AU250: 64 GB DDR4 2400 (4x 2G x72 DIMM) * AU280: 32 GB DDR4 2400 (2x 2G x72 DIMM) + 8 GB HBM2 diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/Makefile similarity index 98% rename from fpga/mqnic/AU50/fpga_25g/fpga/Makefile rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU50/Makefile index 7564ec95e..57c800d0a 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/Makefile @@ -7,7 +7,8 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au50.v +SYN_FILES += rtl/fpga_hbm.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -133,8 +134,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_au50.xdc +XDC_FILES += placement_au50.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl similarity index 99% rename from fpga/mqnic/AU50/fpga_25g/fpga/config.tcl rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl index fe59f6521..644346861 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl @@ -55,6 +55,7 @@ dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] # Board configuration +dict set params CMS_ENABLE "1" dict set params TDMA_BER_ENABLE "0" # Transceiver configuration diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/Makefile similarity index 98% rename from fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/Makefile index 7564ec95e..57c800d0a 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/Makefile @@ -7,7 +7,8 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au50.v +SYN_FILES += rtl/fpga_hbm.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -133,8 +134,8 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES = fpga_au50.xdc +XDC_FILES += placement_au50.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/config.tcl similarity index 99% rename from fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/config.tcl index 5a9f96baa..539dbf43f 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/config.tcl @@ -55,6 +55,7 @@ dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] # Board configuration +dict set params CMS_ENABLE "1" dict set params TDMA_BER_ENABLE "0" # Transceiver configuration diff --git a/fpga/mqnic/AU50/fpga_25g/fpga.xdc b/fpga/mqnic/Alveo/fpga_25g/fpga_au50.xdc similarity index 100% rename from fpga/mqnic/AU50/fpga_25g/fpga.xdc rename to fpga/mqnic/Alveo/fpga_25g/fpga_au50.xdc diff --git a/fpga/mqnic/AU50/fpga_25g/placement.xdc b/fpga/mqnic/Alveo/fpga_25g/placement_au50.xdc similarity index 100% rename from fpga/mqnic/AU50/fpga_25g/placement.xdc rename to fpga/mqnic/Alveo/fpga_25g/placement_au50.xdc diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v index b98996ea9..31bca4850 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v @@ -2187,6 +2187,9 @@ core_inst ( */ .sw(sw_int), .led(led), + .qsfp_led_act(), + .qsfp_led_stat_g(), + .qsfp_led_stat_y(), /* * I2C diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v index ebdb6a0c3..0af7c171f 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v @@ -1996,6 +1996,9 @@ core_inst ( */ .sw(0), .led(), + .qsfp_led_act(), + .qsfp_led_stat_g(), + .qsfp_led_stat_y(), /* * I2C diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v new file mode 100644 index 000000000..4a7f6f304 --- /dev/null +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v @@ -0,0 +1,1711 @@ +// SPDX-License-Identifier: BSD-2-Clause-Views +/* + * Copyright (c) 2019-2023 The Regents of the University of California + */ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // FW and board IDs + parameter FPGA_ID = 32'h4B77093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h10ee_9032, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter CMS_ENABLE = 1, + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 1, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLOCK_PIPELINE = 1, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PORT_CDC_PIPELINE = 1, + parameter PTP_PEROUT_ENABLE = 0, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter PFC_ENABLE = 1, + parameter LFC_ENABLE = PFC_ENABLE, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // RAM configuration + parameter HBM_CH = 32, + parameter HBM_ENABLE = 0, + parameter HBM_GROUP_SIZE = HBM_CH, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_MAX_BURST_LEN = 16, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_WIDTH = 512, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, + parameter AXIS_ETH_TX_PIPELINE = 4, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, + parameter AXIS_ETH_TX_TS_PIPELINE = 4, + parameter AXIS_ETH_RX_PIPELINE = 4, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock and reset + */ + // input wire clk_100mhz_0_p, + // input wire clk_100mhz_0_n, + input wire clk_100mhz_1_p, + input wire clk_100mhz_1_n, + + /* + * GPIO + */ + output wire qsfp_led_act, + output wire qsfp_led_stat_g, + output wire qsfp_led_stat_y, + output wire hbm_cattrip, + input wire [1:0] msp_gpio, + output wire msp_uart_txd, + input wire msp_uart_rxd, + + /* + * PCI express + */ + input wire [15:0] pcie_rx_p, + input wire [15:0] pcie_rx_n, + output wire [15:0] pcie_tx_p, + output wire [15:0] pcie_tx_n, + input wire pcie_refclk_1_p, + input wire pcie_refclk_1_n, + input wire pcie_reset_n, + + /* + * Ethernet: QSFP28 + */ + output wire [3:0] qsfp_tx_p, + output wire [3:0] qsfp_tx_n, + input wire [3:0] qsfp_rx_p, + input wire [3:0] qsfp_rx_n, + input wire qsfp_mgt_refclk_0_p, + input wire qsfp_mgt_refclk_0_n + // input wire qsfp_mgt_refclk_1_p, + // input wire qsfp_mgt_refclk_1_n +); + +// PTP configuration +parameter PTP_CLK_PERIOD_NS_NUM = 1024; +parameter PTP_CLK_PERIOD_NS_DENOM = 165; +parameter PTP_TS_WIDTH = 96; +parameter IF_PTP_PERIOD_NS = 6'h6; +parameter IF_PTP_PERIOD_FNS = 16'h6666; + +// Interface configuration +parameter TX_TAG_WIDTH = 16; + +// RAM configuration +parameter AXI_HBM_DATA_WIDTH = 256; +parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8); +parameter AXI_HBM_ID_WIDTH = 6; + +// PCIe interface configuration +parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; +parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; +parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; +parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; +parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; +parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter RQ_SEQ_NUM_WIDTH = 6; +parameter PCIE_TAG_COUNT = 256; + +// Ethernet interface configuration +parameter XGMII_DATA_WIDTH = 64; +parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; +parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; +parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); +parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; +parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; + +// Clock and reset +wire pcie_user_clk; +wire pcie_user_reset; + +wire clk_161mhz_ref_int; + +wire clk_50mhz_mmcm_out; +wire clk_125mhz_mmcm_out; + +// Internal 50 MHz clock +wire clk_50mhz_int; +wire rst_50mhz_int; + +// Internal 125 MHz clock +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = pcie_user_reset; +wire mmcm_locked; +wire mmcm_clkfb; + +// MMCM instance +// 161.13 MHz in, 50 MHz + 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 128, D = 15 sets Fvco = 1375 MHz (in range) +// Divide by 27.5 to get output frequency of 50 MHz +// Divide by 11 to get output frequency of 125 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(27.5), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(11), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(128), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(15), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(6.206), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(clk_161mhz_ref_int), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_50mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(clk_125mhz_mmcm_out), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_50mhz_bufg_inst ( + .I(clk_50mhz_mmcm_out), + .O(clk_50mhz_int) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_50mhz_inst ( + .clk(clk_50mhz_int), + .rst(~mmcm_locked), + .out(rst_50mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// Flash +wire qspi_clk_int; +wire [3:0] qspi_dq_int; +wire [3:0] qspi_dq_i_int; +wire [3:0] qspi_dq_o_int; +wire [3:0] qspi_dq_oe_int; +wire qspi_cs_int; + +reg qspi_clk_reg; +reg [3:0] qspi_dq_o_reg; +reg [3:0] qspi_dq_oe_reg; +reg qspi_cs_reg; + +always @(posedge pcie_user_clk) begin + qspi_clk_reg <= qspi_clk_int; + qspi_dq_o_reg <= qspi_dq_o_int; + qspi_dq_oe_reg <= qspi_dq_oe_int; + qspi_cs_reg <= qspi_cs_int; +end + +sync_signal #( + .WIDTH(4), + .N(2) +) +flash_sync_signal_inst ( + .clk(pcie_user_clk), + .in({qspi_dq_int}), + .out({qspi_dq_i_int}) +); + +STARTUPE3 +startupe3_inst ( + .CFGCLK(), + .CFGMCLK(), + .DI(qspi_dq_int), + .DO(qspi_dq_o_reg), + .DTS(~qspi_dq_oe_reg), + .EOS(), + .FCSBO(qspi_cs_reg), + .FCSBTS(1'b0), + .GSR(1'b0), + .GTS(1'b0), + .KEYCLEARB(1'b1), + .PACK(1'b0), + .PREQ(), + .USRCCLKO(qspi_clk_reg), + .USRCCLKTS(1'b0), + .USRDONEO(1'b0), + .USRDONETS(1'b1) +); + +// FPGA boot +wire fpga_boot; + +reg fpga_boot_sync_reg_0 = 1'b0; +reg fpga_boot_sync_reg_1 = 1'b0; +reg fpga_boot_sync_reg_2 = 1'b0; + +wire icap_avail; +reg [2:0] icap_state = 0; +reg icap_csib_reg = 1'b1; +reg icap_rdwrb_reg = 1'b0; +reg [31:0] icap_di_reg = 32'hffffffff; + +wire [31:0] icap_di_rev; + +assign icap_di_rev[ 7] = icap_di_reg[ 0]; +assign icap_di_rev[ 6] = icap_di_reg[ 1]; +assign icap_di_rev[ 5] = icap_di_reg[ 2]; +assign icap_di_rev[ 4] = icap_di_reg[ 3]; +assign icap_di_rev[ 3] = icap_di_reg[ 4]; +assign icap_di_rev[ 2] = icap_di_reg[ 5]; +assign icap_di_rev[ 1] = icap_di_reg[ 6]; +assign icap_di_rev[ 0] = icap_di_reg[ 7]; + +assign icap_di_rev[15] = icap_di_reg[ 8]; +assign icap_di_rev[14] = icap_di_reg[ 9]; +assign icap_di_rev[13] = icap_di_reg[10]; +assign icap_di_rev[12] = icap_di_reg[11]; +assign icap_di_rev[11] = icap_di_reg[12]; +assign icap_di_rev[10] = icap_di_reg[13]; +assign icap_di_rev[ 9] = icap_di_reg[14]; +assign icap_di_rev[ 8] = icap_di_reg[15]; + +assign icap_di_rev[23] = icap_di_reg[16]; +assign icap_di_rev[22] = icap_di_reg[17]; +assign icap_di_rev[21] = icap_di_reg[18]; +assign icap_di_rev[20] = icap_di_reg[19]; +assign icap_di_rev[19] = icap_di_reg[20]; +assign icap_di_rev[18] = icap_di_reg[21]; +assign icap_di_rev[17] = icap_di_reg[22]; +assign icap_di_rev[16] = icap_di_reg[23]; + +assign icap_di_rev[31] = icap_di_reg[24]; +assign icap_di_rev[30] = icap_di_reg[25]; +assign icap_di_rev[29] = icap_di_reg[26]; +assign icap_di_rev[28] = icap_di_reg[27]; +assign icap_di_rev[27] = icap_di_reg[28]; +assign icap_di_rev[26] = icap_di_reg[29]; +assign icap_di_rev[25] = icap_di_reg[30]; +assign icap_di_rev[24] = icap_di_reg[31]; + +always @(posedge clk_125mhz_int) begin + case (icap_state) + 0: begin + icap_state <= 0; + icap_csib_reg <= 1'b1; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + + if (fpga_boot_sync_reg_2 && icap_avail) begin + icap_state <= 1; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + end + end + 1: begin + icap_state <= 2; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hAA995566; // sync word + end + 2: begin + icap_state <= 3; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + 3: begin + icap_state <= 4; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h30008001; // write 1 word to CMD + end + 4: begin + icap_state <= 5; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h0000000F; // IPROG + end + 5: begin + icap_state <= 0; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + endcase + + fpga_boot_sync_reg_0 <= fpga_boot; + fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; + fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; +end + +ICAPE3 +icape3_inst ( + .AVAIL(icap_avail), + .CLK(clk_125mhz_int), + .CSIB(icap_csib_reg), + .I(icap_di_rev), + .O(), + .PRDONE(), + .PRERROR(), + .RDWRB(icap_rdwrb_reg) +); + +// BMC +wire axil_cms_clk; +wire axil_cms_rst; +wire [17:0] axil_cms_awaddr; +wire [2:0] axil_cms_awprot; +wire axil_cms_awvalid; +wire axil_cms_awready; +wire [31:0] axil_cms_wdata; +wire [3:0] axil_cms_wstrb; +wire axil_cms_wvalid; +wire axil_cms_wready; +wire [1:0] axil_cms_bresp; +wire axil_cms_bvalid; +wire axil_cms_bready; +wire [17:0] axil_cms_araddr; +wire [2:0] axil_cms_arprot; +wire axil_cms_arvalid; +wire axil_cms_arready; +wire [31:0] axil_cms_rdata; +wire [1:0] axil_cms_rresp; +wire axil_cms_rvalid; +wire axil_cms_rready; + +wire [6:0] hbm_temp_1; +wire [6:0] hbm_temp_2; + +generate + +if (CMS_ENABLE) begin : cms + + wire [17:0] axil_cms_awaddr_int; + wire [2:0] axil_cms_awprot_int; + wire axil_cms_awvalid_int; + wire axil_cms_awready_int; + wire [31:0] axil_cms_wdata_int; + wire [3:0] axil_cms_wstrb_int; + wire axil_cms_wvalid_int; + wire axil_cms_wready_int; + wire [1:0] axil_cms_bresp_int; + wire axil_cms_bvalid_int; + wire axil_cms_bready_int; + wire [17:0] axil_cms_araddr_int; + wire [2:0] axil_cms_arprot_int; + wire axil_cms_arvalid_int; + wire axil_cms_arready_int; + wire [31:0] axil_cms_rdata_int; + wire [1:0] axil_cms_rresp_int; + wire axil_cms_rvalid_int; + wire axil_cms_rready_int; + + axil_cdc #( + .DATA_WIDTH(32), + .ADDR_WIDTH(18) + ) + cms_axil_cdc_inst ( + .s_clk(axil_cms_clk), + .s_rst(axil_cms_rst), + .s_axil_awaddr(axil_cms_awaddr), + .s_axil_awprot(axil_cms_awprot), + .s_axil_awvalid(axil_cms_awvalid), + .s_axil_awready(axil_cms_awready), + .s_axil_wdata(axil_cms_wdata), + .s_axil_wstrb(axil_cms_wstrb), + .s_axil_wvalid(axil_cms_wvalid), + .s_axil_wready(axil_cms_wready), + .s_axil_bresp(axil_cms_bresp), + .s_axil_bvalid(axil_cms_bvalid), + .s_axil_bready(axil_cms_bready), + .s_axil_araddr(axil_cms_araddr), + .s_axil_arprot(axil_cms_arprot), + .s_axil_arvalid(axil_cms_arvalid), + .s_axil_arready(axil_cms_arready), + .s_axil_rdata(axil_cms_rdata), + .s_axil_rresp(axil_cms_rresp), + .s_axil_rvalid(axil_cms_rvalid), + .s_axil_rready(axil_cms_rready), + .m_clk(clk_50mhz_int), + .m_rst(rst_50mhz_int), + .m_axil_awaddr(axil_cms_awaddr_int), + .m_axil_awprot(axil_cms_awprot_int), + .m_axil_awvalid(axil_cms_awvalid_int), + .m_axil_awready(axil_cms_awready_int), + .m_axil_wdata(axil_cms_wdata_int), + .m_axil_wstrb(axil_cms_wstrb_int), + .m_axil_wvalid(axil_cms_wvalid_int), + .m_axil_wready(axil_cms_wready_int), + .m_axil_bresp(axil_cms_bresp_int), + .m_axil_bvalid(axil_cms_bvalid_int), + .m_axil_bready(axil_cms_bready_int), + .m_axil_araddr(axil_cms_araddr_int), + .m_axil_arprot(axil_cms_arprot_int), + .m_axil_arvalid(axil_cms_arvalid_int), + .m_axil_arready(axil_cms_arready_int), + .m_axil_rdata(axil_cms_rdata_int), + .m_axil_rresp(axil_cms_rresp_int), + .m_axil_rvalid(axil_cms_rvalid_int), + .m_axil_rready(axil_cms_rready_int) + ); + + cms_wrapper + cms_inst ( + .aclk_ctrl_0(clk_50mhz_int), + .aresetn_ctrl_0(~rst_50mhz_int), + .hbm_temp_1_0(hbm_temp_1), + .hbm_temp_2_0(hbm_temp_2), + .interrupt_hbm_cattrip_0(hbm_cattrip), + .interrupt_host_0(), + .s_axi_ctrl_0_araddr(axil_cms_araddr_int), + .s_axi_ctrl_0_arprot(axil_cms_arprot_int), + .s_axi_ctrl_0_arready(axil_cms_arready_int), + .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), + .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), + .s_axi_ctrl_0_awprot(axil_cms_awprot_int), + .s_axi_ctrl_0_awready(axil_cms_awready_int), + .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), + .s_axi_ctrl_0_bready(axil_cms_bready_int), + .s_axi_ctrl_0_bresp(axil_cms_bresp_int), + .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), + .s_axi_ctrl_0_rdata(axil_cms_rdata_int), + .s_axi_ctrl_0_rready(axil_cms_rready_int), + .s_axi_ctrl_0_rresp(axil_cms_rresp_int), + .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), + .s_axi_ctrl_0_wdata(axil_cms_wdata_int), + .s_axi_ctrl_0_wready(axil_cms_wready_int), + .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), + .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), + .satellite_gpio_0(msp_gpio), + .satellite_uart_0_rxd(msp_uart_rxd), + .satellite_uart_0_txd(msp_uart_txd) + ); + +end else begin + + assign axil_cms_awready = 0; + assign axil_cms_wdata = 0; + assign axil_cms_wstrb = 0; + assign axil_cms_wvalid = 0; + assign axil_cms_bresp = 0; + assign axil_cms_bvalid = 0; + assign axil_cms_arready = 0; + assign axil_cms_rdata = 0; + assign axil_cms_rresp = 0; + assign axil_cms_rvalid = 0; + + assign msp_uart_txd = 1'bz; + +end + +endgenerate + +// PCIe +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE4 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte4_pcie_mgt_refclk_inst ( + .I (pcie_refclk_1_p), + .IB (pcie_refclk_1_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; +wire axis_rq_tlast; +wire axis_rq_tready; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; +wire axis_rq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; +wire axis_rc_tlast; +wire axis_rc_tready; +wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; +wire axis_rc_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; +wire axis_cq_tlast; +wire axis_cq_tready; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; +wire axis_cq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; +wire axis_cc_tlast; +wire axis_cc_tready; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; +wire axis_cc_tvalid; + +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; +wire pcie_rq_seq_num_vld0; +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; +wire pcie_rq_seq_num_vld1; + +wire [3:0] pcie_tfc_nph_av; +wire [3:0] pcie_tfc_npd_av; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; +wire [3:0] cfg_rcb_status; + +wire [9:0] cfg_mgmt_addr; +wire [7:0] cfg_mgmt_function_number; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [7:0] cfg_fc_ph; +wire [11:0] cfg_fc_pd; +wire [7:0] cfg_fc_nph; +wire [11:0] cfg_fc_npd; +wire [7:0] cfg_fc_cplh; +wire [11:0] cfg_fc_cpld; +wire [2:0] cfg_fc_sel; + +wire [3:0] cfg_interrupt_msix_enable; +wire [3:0] cfg_interrupt_msix_mask; +wire [251:0] cfg_interrupt_msix_vf_enable; +wire [251:0] cfg_interrupt_msix_vf_mask; +wire [63:0] cfg_interrupt_msix_address; +wire [31:0] cfg_interrupt_msix_data; +wire cfg_interrupt_msix_int; +wire [1:0] cfg_interrupt_msix_vec_pending; +wire cfg_interrupt_msix_vec_pending_status; +wire cfg_interrupt_msix_sent; +wire cfg_interrupt_msix_fail; +wire [7:0] cfg_interrupt_msi_function_number; + +wire status_error_cor; +wire status_error_uncor; + +// extra register for pcie_user_reset signal +wire pcie_user_reset_int; +(* shreg_extract = "no" *) +reg pcie_user_reset_reg_1 = 1'b1; +(* shreg_extract = "no" *) +reg pcie_user_reset_reg_2 = 1'b1; + +always @(posedge pcie_user_clk) begin + pcie_user_reset_reg_1 <= pcie_user_reset_int; + pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; +end + +BUFG +pcie_user_reset_bufg_inst ( + .I(pcie_user_reset_reg_2), + .O(pcie_user_reset) +); + +pcie4c_uscale_plus_0 +pcie4c_uscale_plus_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_reset_int), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_rq_tdata), + .s_axis_rq_tkeep(axis_rq_tkeep), + .s_axis_rq_tlast(axis_rq_tlast), + .s_axis_rq_tready(axis_rq_tready), + .s_axis_rq_tuser(axis_rq_tuser), + .s_axis_rq_tvalid(axis_rq_tvalid), + + .m_axis_rc_tdata(axis_rc_tdata), + .m_axis_rc_tkeep(axis_rc_tkeep), + .m_axis_rc_tlast(axis_rc_tlast), + .m_axis_rc_tready(axis_rc_tready), + .m_axis_rc_tuser(axis_rc_tuser), + .m_axis_rc_tvalid(axis_rc_tvalid), + + .m_axis_cq_tdata(axis_cq_tdata), + .m_axis_cq_tkeep(axis_cq_tkeep), + .m_axis_cq_tlast(axis_cq_tlast), + .m_axis_cq_tready(axis_cq_tready), + .m_axis_cq_tuser(axis_cq_tuser), + .m_axis_cq_tvalid(axis_cq_tvalid), + + .s_axis_cc_tdata(axis_cc_tdata), + .s_axis_cc_tkeep(axis_cc_tkeep), + .s_axis_cc_tlast(axis_cc_tlast), + .s_axis_cc_tready(axis_cc_tready), + .s_axis_cc_tuser(axis_cc_tuser), + .s_axis_cc_tvalid(axis_cc_tvalid), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + .pcie_rq_tag0(), + .pcie_rq_tag1(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld0(), + .pcie_rq_tag_vld1(), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_debug_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error_valid(), + .cfg_local_error_out(), + .cfg_ltssm_state(), + .cfg_rx_pm_state(), + .cfg_tx_pm_state(), + .cfg_rcb_status(cfg_rcb_status), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_dsn(64'd0), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(status_error_cor), + .cfg_err_uncor_in(status_error_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_func_num(8'd0), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_pm_aspm_l1_entry_reject(1'b0), + .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_reset_n), + + .phy_rdy_out() +); + +reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0_reg; +reg pcie_rq_seq_num_vld0_reg; +reg [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1_reg; +reg pcie_rq_seq_num_vld1_reg; + +always @(posedge pcie_user_clk) begin + pcie_rq_seq_num0_reg <= pcie_rq_seq_num0; + pcie_rq_seq_num_vld0_reg <= pcie_rq_seq_num_vld0; + pcie_rq_seq_num1_reg <= pcie_rq_seq_num1; + pcie_rq_seq_num_vld1_reg <= pcie_rq_seq_num_vld1; + + if (pcie_user_reset) begin + pcie_rq_seq_num_vld0_reg <= 1'b0; + pcie_rq_seq_num_vld1_reg <= 1'b0; + end +end + +// XGMII 25G PHY +localparam QSFP_CNT = 1; +localparam CH_CNT = QSFP_CNT*4; + +wire [CH_CNT-1:0] qsfp_tx_clk; +wire [CH_CNT-1:0] qsfp_tx_rst; +wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_txd; +wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_txc; +wire [CH_CNT-1:0] qsfp_cfg_tx_prbs31_enable; +wire [CH_CNT-1:0] qsfp_rx_clk; +wire [CH_CNT-1:0] qsfp_rx_rst; +wire [CH_CNT*XGMII_DATA_WIDTH-1:0] qsfp_rxd; +wire [CH_CNT*XGMII_CTRL_WIDTH-1:0] qsfp_rxc; +wire [CH_CNT-1:0] qsfp_cfg_rx_prbs31_enable; +wire [CH_CNT*7-1:0] qsfp_rx_error_count; +wire [CH_CNT-1:0] qsfp_rx_status; + +wire [QSFP_CNT-1:0] qsfp_drp_clk; +wire [QSFP_CNT-1:0] qsfp_drp_rst; +wire [QSFP_CNT*24-1:0] qsfp_drp_addr; +wire [QSFP_CNT*16-1:0] qsfp_drp_di; +wire [QSFP_CNT-1:0] qsfp_drp_en; +wire [QSFP_CNT-1:0] qsfp_drp_we; +wire [QSFP_CNT*16-1:0] qsfp_drp_do; +wire [QSFP_CNT-1:0] qsfp_drp_rdy; + +assign qsfp_drp_clk[0 +: 1] = clk_125mhz_int; +assign qsfp_drp_rst[0 +: 1] = rst_125mhz_int; + +wire qsfp_gtpowergood; + +wire qsfp_mgt_refclk_0; +wire qsfp_mgt_refclk_0_int; +wire qsfp_mgt_refclk_0_bufg; + +assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst ( + .I (qsfp_mgt_refclk_0_p), + .IB (qsfp_mgt_refclk_0_n), + .CEB (1'b0), + .O (qsfp_mgt_refclk_0), + .ODIV2 (qsfp_mgt_refclk_0_int) +); + +BUFG_GT bufg_gt_qsfp_mgt_refclk_0_inst ( + .CE (qsfp_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_mgt_refclk_0_int), + .O (qsfp_mgt_refclk_0_bufg) +); + +wire qsfp_rst; + +sync_reset #( + .N(4) +) +qsfp_sync_reset_inst ( + .clk(qsfp_mgt_refclk_0_bufg), + .rst(rst_125mhz_int), + .out(qsfp_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp_gtpowergood), + .xcvr_ref_clk(qsfp_mgt_refclk_0), + + /* + * DRP + */ + .drp_clk(qsfp_drp_clk[0 +: 1]), + .drp_rst(qsfp_drp_rst[0 +: 1]), + .drp_addr(qsfp_drp_addr[0*24 +: 24]), + .drp_di(qsfp_drp_di[0*16 +: 16]), + .drp_en(qsfp_drp_en[0 +: 1]), + .drp_we(qsfp_drp_we[0 +: 1]), + .drp_do(qsfp_drp_do[0*16 +: 16]), + .drp_rdy(qsfp_drp_rdy[0 +: 1]), + + /* + * Serial data + */ + .xcvr_txp(qsfp_tx_p), + .xcvr_txn(qsfp_tx_n), + .xcvr_rxp(qsfp_rx_p), + .xcvr_rxn(qsfp_rx_n), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_tx_clk[0*4+0 +: 1]), + .phy_1_tx_rst(qsfp_tx_rst[0*4+0 +: 1]), + .phy_1_xgmii_txd(qsfp_txd[(0*4+0)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_1_xgmii_txc(qsfp_txc[(0*4+0)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_1_rx_clk(qsfp_rx_clk[0*4+0 +: 1]), + .phy_1_rx_rst(qsfp_rx_rst[0*4+0 +: 1]), + .phy_1_xgmii_rxd(qsfp_rxd[(0*4+0)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_1_xgmii_rxc(qsfp_rxc[(0*4+0)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp_rx_error_count[(0*4+0)*7 +: 7]), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp_rx_status[0*4+0 +: 1]), + .phy_1_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[0*4+0 +: 1]), + .phy_1_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[0*4+0 +: 1]), + + .phy_2_tx_clk(qsfp_tx_clk[0*4+1 +: 1]), + .phy_2_tx_rst(qsfp_tx_rst[0*4+1 +: 1]), + .phy_2_xgmii_txd(qsfp_txd[(0*4+1)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_2_xgmii_txc(qsfp_txc[(0*4+1)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_2_rx_clk(qsfp_rx_clk[0*4+1 +: 1]), + .phy_2_rx_rst(qsfp_rx_rst[0*4+1 +: 1]), + .phy_2_xgmii_rxd(qsfp_rxd[(0*4+1)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_2_xgmii_rxc(qsfp_rxc[(0*4+1)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp_rx_error_count[(0*4+1)*7 +: 7]), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp_rx_status[0*4+1 +: 1]), + .phy_2_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[0*4+1 +: 1]), + .phy_2_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[0*4+1 +: 1]), + + .phy_3_tx_clk(qsfp_tx_clk[0*4+2 +: 1]), + .phy_3_tx_rst(qsfp_tx_rst[0*4+2 +: 1]), + .phy_3_xgmii_txd(qsfp_txd[(0*4+2)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_3_xgmii_txc(qsfp_txc[(0*4+2)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_3_rx_clk(qsfp_rx_clk[0*4+2 +: 1]), + .phy_3_rx_rst(qsfp_rx_rst[0*4+2 +: 1]), + .phy_3_xgmii_rxd(qsfp_rxd[(0*4+2)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_3_xgmii_rxc(qsfp_rxc[(0*4+2)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp_rx_error_count[(0*4+2)*7 +: 7]), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp_rx_status[0*4+2 +: 1]), + .phy_3_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[0*4+2 +: 1]), + .phy_3_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[0*4+2 +: 1]), + + .phy_4_tx_clk(qsfp_tx_clk[0*4+3 +: 1]), + .phy_4_tx_rst(qsfp_tx_rst[0*4+3 +: 1]), + .phy_4_xgmii_txd(qsfp_txd[(0*4+3)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_4_xgmii_txc(qsfp_txc[(0*4+3)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_4_rx_clk(qsfp_rx_clk[0*4+3 +: 1]), + .phy_4_rx_rst(qsfp_rx_rst[0*4+3 +: 1]), + .phy_4_xgmii_rxd(qsfp_rxd[(0*4+3)*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .phy_4_xgmii_rxc(qsfp_rxc[(0*4+3)*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp_rx_error_count[(0*4+3)*7 +: 7]), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp_rx_status[0*4+3 +: 1]), + .phy_4_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable[0*4+3 +: 1]), + .phy_4_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable[0*4+3 +: 1]) +); + +wire ptp_clk; +wire ptp_rst; +wire ptp_sample_clk; + +assign ptp_clk = qsfp_mgt_refclk_0_bufg; +assign ptp_rst = qsfp_rst; +assign ptp_sample_clk = clk_125mhz_int; + +// HBM +wire [HBM_CH-1:0] hbm_clk; +wire [HBM_CH-1:0] hbm_rst; + +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr; +wire [HBM_CH*8-1:0] m_axi_hbm_awlen; +wire [HBM_CH*3-1:0] m_axi_hbm_awsize; +wire [HBM_CH*2-1:0] m_axi_hbm_awburst; +wire [HBM_CH-1:0] m_axi_hbm_awlock; +wire [HBM_CH*4-1:0] m_axi_hbm_awcache; +wire [HBM_CH*3-1:0] m_axi_hbm_awprot; +wire [HBM_CH*4-1:0] m_axi_hbm_awqos; +wire [HBM_CH-1:0] m_axi_hbm_awvalid; +wire [HBM_CH-1:0] m_axi_hbm_awready; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata; +wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb; +wire [HBM_CH-1:0] m_axi_hbm_wlast; +wire [HBM_CH-1:0] m_axi_hbm_wvalid; +wire [HBM_CH-1:0] m_axi_hbm_wready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid; +wire [HBM_CH*2-1:0] m_axi_hbm_bresp; +wire [HBM_CH-1:0] m_axi_hbm_bvalid; +wire [HBM_CH-1:0] m_axi_hbm_bready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr; +wire [HBM_CH*8-1:0] m_axi_hbm_arlen; +wire [HBM_CH*3-1:0] m_axi_hbm_arsize; +wire [HBM_CH*2-1:0] m_axi_hbm_arburst; +wire [HBM_CH-1:0] m_axi_hbm_arlock; +wire [HBM_CH*4-1:0] m_axi_hbm_arcache; +wire [HBM_CH*3-1:0] m_axi_hbm_arprot; +wire [HBM_CH*4-1:0] m_axi_hbm_arqos; +wire [HBM_CH-1:0] m_axi_hbm_arvalid; +wire [HBM_CH-1:0] m_axi_hbm_arready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata; +wire [HBM_CH*2-1:0] m_axi_hbm_rresp; +wire [HBM_CH-1:0] m_axi_hbm_rlast; +wire [HBM_CH-1:0] m_axi_hbm_rvalid; +wire [HBM_CH-1:0] m_axi_hbm_rready; + +wire [HBM_CH-1:0] hbm_status; + +wire clk_100mhz_1_ibufg; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_1_ibufg_inst ( + .O (clk_100mhz_1_ibufg), + .I (clk_100mhz_1_p), + .IB (clk_100mhz_1_n) +); + +generate + +if (HBM_ENABLE) begin + + wire hbm_ref_clk; + + BUFG + hbm_ref_clk_bufg_inst ( + .I(clk_100mhz_1_ibufg), + .O(hbm_ref_clk) + ); + + wire hbm_cattrip_1; + wire hbm_cattrip_2; + + assign hbm_cattrip = hbm_cattrip_1 | hbm_cattrip_2; + + fpga_hbm #( + .HBM_CH(HBM_CH), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN) + ) + hbm_inst ( + .hbm_ref_clk(hbm_ref_clk), + .hbm_rst_in(rst_125mhz_int), + + .hbm_cattrip_1(hbm_cattrip_1), + .hbm_cattrip_2(hbm_cattrip_2), + .hbm_temp_1(hbm_temp_1), + .hbm_temp_2(hbm_temp_2), + + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .s_axi_hbm_awid(m_axi_hbm_awid), + .s_axi_hbm_awaddr(m_axi_hbm_awaddr), + .s_axi_hbm_awlen(m_axi_hbm_awlen), + .s_axi_hbm_awsize(m_axi_hbm_awsize), + .s_axi_hbm_awburst(m_axi_hbm_awburst), + .s_axi_hbm_awlock(m_axi_hbm_awlock), + .s_axi_hbm_awcache(m_axi_hbm_awcache), + .s_axi_hbm_awprot(m_axi_hbm_awprot), + .s_axi_hbm_awqos(m_axi_hbm_awqos), + .s_axi_hbm_awvalid(m_axi_hbm_awvalid), + .s_axi_hbm_awready(m_axi_hbm_awready), + .s_axi_hbm_wdata(m_axi_hbm_wdata), + .s_axi_hbm_wstrb(m_axi_hbm_wstrb), + .s_axi_hbm_wlast(m_axi_hbm_wlast), + .s_axi_hbm_wvalid(m_axi_hbm_wvalid), + .s_axi_hbm_wready(m_axi_hbm_wready), + .s_axi_hbm_bid(m_axi_hbm_bid), + .s_axi_hbm_bresp(m_axi_hbm_bresp), + .s_axi_hbm_bvalid(m_axi_hbm_bvalid), + .s_axi_hbm_bready(m_axi_hbm_bready), + .s_axi_hbm_arid(m_axi_hbm_arid), + .s_axi_hbm_araddr(m_axi_hbm_araddr), + .s_axi_hbm_arlen(m_axi_hbm_arlen), + .s_axi_hbm_arsize(m_axi_hbm_arsize), + .s_axi_hbm_arburst(m_axi_hbm_arburst), + .s_axi_hbm_arlock(m_axi_hbm_arlock), + .s_axi_hbm_arcache(m_axi_hbm_arcache), + .s_axi_hbm_arprot(m_axi_hbm_arprot), + .s_axi_hbm_arqos(m_axi_hbm_arqos), + .s_axi_hbm_arvalid(m_axi_hbm_arvalid), + .s_axi_hbm_arready(m_axi_hbm_arready), + .s_axi_hbm_rid(m_axi_hbm_rid), + .s_axi_hbm_rdata(m_axi_hbm_rdata), + .s_axi_hbm_rresp(m_axi_hbm_rresp), + .s_axi_hbm_rlast(m_axi_hbm_rlast), + .s_axi_hbm_rvalid(m_axi_hbm_rvalid), + .s_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status) + ); + +end else begin + + assign hbm_clk = 0; + assign hbm_rst = 0; + + assign m_axi_hbm_awready = 0; + assign m_axi_hbm_wready = 0; + assign m_axi_hbm_bid = 0; + assign m_axi_hbm_bresp = 0; + assign m_axi_hbm_bvalid = 0; + assign m_axi_hbm_arready = 0; + assign m_axi_hbm_rid = 0; + assign m_axi_hbm_rdata = 0; + assign m_axi_hbm_rresp = 0; + assign m_axi_hbm_rlast = 0; + assign m_axi_hbm_rvalid = 0; + + assign hbm_status = 0; + + assign hbm_cattrip = 1'b0; + + assign hbm_temp_1 = 7'd0; + assign hbm_temp_2 = 7'd0; + +end + +endgenerate + +fpga_core #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Board configuration + .QSFP_CNT(QSFP_CNT), + .CH_CNT(CH_CNT), + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + .PORT_MASK(PORT_MASK), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .PFC_ENABLE(PFC_ENABLE), + .LFC_ENABLE(LFC_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // RAM configuration + .DDR_ENABLE(0), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RC_STRADDLE(RC_STRADDLE), + .RQ_STRADDLE(RQ_STRADDLE), + .CQ_STRADDLE(CQ_STRADDLE), + .CC_STRADDLE(CC_STRADDLE), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + /* + * Clock: 250 MHz + * Synchronous reset + */ + .clk_250mhz(pcie_user_clk), + .rst_250mhz(pcie_user_reset), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + + /* + * GPIO + */ + .sw(0), + .led(), + .qsfp_led_act(qsfp_led_act), + //.qsfp_led_stat_g(qsfp_led_stat_g), + .qsfp_led_stat_y(qsfp_led_stat_y), + + /* + * I2C + */ + .i2c_scl_i(1'b1), + .i2c_scl_o(), + .i2c_scl_t(), + .i2c_sda_i(1'b1), + .i2c_sda_o(), + .i2c_sda_t(), + + /* + * PCIe + */ + .m_axis_rq_tdata(axis_rq_tdata), + .m_axis_rq_tkeep(axis_rq_tkeep), + .m_axis_rq_tlast(axis_rq_tlast), + .m_axis_rq_tready(axis_rq_tready), + .m_axis_rq_tuser(axis_rq_tuser), + .m_axis_rq_tvalid(axis_rq_tvalid), + + .s_axis_rc_tdata(axis_rc_tdata), + .s_axis_rc_tkeep(axis_rc_tkeep), + .s_axis_rc_tlast(axis_rc_tlast), + .s_axis_rc_tready(axis_rc_tready), + .s_axis_rc_tuser(axis_rc_tuser), + .s_axis_rc_tvalid(axis_rc_tvalid), + + .s_axis_cq_tdata(axis_cq_tdata), + .s_axis_cq_tkeep(axis_cq_tkeep), + .s_axis_cq_tlast(axis_cq_tlast), + .s_axis_cq_tready(axis_cq_tready), + .s_axis_cq_tuser(axis_cq_tuser), + .s_axis_cq_tvalid(axis_cq_tvalid), + + .m_axis_cc_tdata(axis_cc_tdata), + .m_axis_cc_tkeep(axis_cc_tkeep), + .m_axis_cc_tlast(axis_cc_tlast), + .m_axis_cc_tready(axis_cc_tready), + .m_axis_cc_tuser(axis_cc_tuser), + .m_axis_cc_tvalid(axis_cc_tvalid), + + .s_axis_rq_seq_num_0(pcie_rq_seq_num0_reg), + .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0_reg), + .s_axis_rq_seq_num_1(pcie_rq_seq_num1_reg), + .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1_reg), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * Ethernet: QSFP28 + */ + .qsfp_tx_clk(qsfp_tx_clk), + .qsfp_tx_rst(qsfp_tx_rst), + .qsfp_txd(qsfp_txd), + .qsfp_txc(qsfp_txc), + .qsfp_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable), + .qsfp_rx_clk(qsfp_rx_clk), + .qsfp_rx_rst(qsfp_rx_rst), + .qsfp_rxd(qsfp_rxd), + .qsfp_rxc(qsfp_rxc), + .qsfp_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable), + .qsfp_rx_error_count(qsfp_rx_error_count), + .qsfp_rx_status(qsfp_rx_status), + + .qsfp_drp_clk(qsfp_drp_clk), + .qsfp_drp_rst(qsfp_drp_rst), + .qsfp_drp_addr(qsfp_drp_addr), + .qsfp_drp_di(qsfp_drp_di), + .qsfp_drp_en(qsfp_drp_en), + .qsfp_drp_we(qsfp_drp_we), + .qsfp_drp_do(qsfp_drp_do), + .qsfp_drp_rdy(qsfp_drp_rdy), + + .qsfp_modprsl(1'b0), + .qsfp_modsell(), + .qsfp_resetl(), + .qsfp_intl(1'b1), + .qsfp_lpmode(), + + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk_int), + .qspi_dq_i(qspi_dq_i_int), + .qspi_dq_o(qspi_dq_o_int), + .qspi_dq_oe(qspi_dq_oe_int), + .qspi_cs(qspi_cs_int), + + /* + * AXI-Lite interface to CMS + */ + .m_axil_cms_clk(axil_cms_clk), + .m_axil_cms_rst(axil_cms_rst), + .m_axil_cms_awaddr(axil_cms_awaddr), + .m_axil_cms_awprot(axil_cms_awprot), + .m_axil_cms_awvalid(axil_cms_awvalid), + .m_axil_cms_awready(axil_cms_awready), + .m_axil_cms_wdata(axil_cms_wdata), + .m_axil_cms_wstrb(axil_cms_wstrb), + .m_axil_cms_wvalid(axil_cms_wvalid), + .m_axil_cms_wready(axil_cms_wready), + .m_axil_cms_bresp(axil_cms_bresp), + .m_axil_cms_bvalid(axil_cms_bvalid), + .m_axil_cms_bready(axil_cms_bready), + .m_axil_cms_araddr(axil_cms_araddr), + .m_axil_cms_arprot(axil_cms_arprot), + .m_axil_cms_arvalid(axil_cms_arvalid), + .m_axil_cms_arready(axil_cms_arready), + .m_axil_cms_rdata(axil_cms_rdata), + .m_axil_cms_rresp(axil_cms_rresp), + .m_axil_cms_rvalid(axil_cms_rvalid), + .m_axil_cms_rready(axil_cms_rready) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v index 2f28e54ef..1ebb480cb 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v @@ -199,6 +199,9 @@ module fpga_core # */ input wire [3:0] sw, output wire [2:0] led, + output wire [QSFP_CNT-1:0] qsfp_led_act, + output wire [QSFP_CNT-1:0] qsfp_led_stat_g, + output wire [QSFP_CNT-1:0] qsfp_led_stat_y, /* * I2C @@ -876,6 +879,10 @@ endgenerate assign led[0] = ptp_pps_str; assign led[2:1] = 0; +assign qsfp_led_act = ptp_pps_str; +assign qsfp_led_stat_g = 0; +assign qsfp_led_stat_y = 0; + wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v index 5e66f05fd..e8717db3c 100644 --- a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v +++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v @@ -218,6 +218,9 @@ module test_fpga_core # */ input wire [3:0] sw, output wire [2:0] led, + output wire [QSFP_CNT-1:0] qsfp_led_act, + output wire [QSFP_CNT-1:0] qsfp_led_stat_g, + output wire [QSFP_CNT-1:0] qsfp_led_stat_y, /* * I2C @@ -699,6 +702,9 @@ uut ( */ .sw(sw), .led(led), + .qsfp_led_act(qsfp_led_act), + .qsfp_led_stat_g(qsfp_led_stat_g), + .qsfp_led_stat_y(qsfp_led_stat_y), /* * I2C