From de3ec216a037d7d1a0b6dcd5e4c318e6241f8858 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 13 Feb 2023 13:18:24 -0800 Subject: [PATCH] Fix min address width checks in AXI lite components Signed-off-by: Alex Forencich --- rtl/axil_crossbar_addr.v | 2 +- rtl/axil_crossbar_rd.v | 2 +- rtl/axil_crossbar_wr.v | 2 +- rtl/axil_interconnect.v | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/axil_crossbar_addr.v b/rtl/axil_crossbar_addr.v index dc07e98e7..f4ebd79e5 100644 --- a/rtl/axil_crossbar_addr.v +++ b/rtl/axil_crossbar_addr.v @@ -135,7 +135,7 @@ initial begin end for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin + if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH) begin $error("Error: address width out of range (instance %m)"); $finish; end diff --git a/rtl/axil_crossbar_rd.v b/rtl/axil_crossbar_rd.v index d8bf74542..0c3e3ef66 100644 --- a/rtl/axil_crossbar_rd.v +++ b/rtl/axil_crossbar_rd.v @@ -116,7 +116,7 @@ integer i; // check configuration initial begin for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin + if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < $clog2(STRB_WIDTH) || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin $error("Error: value out of range (instance %m)"); $finish; end diff --git a/rtl/axil_crossbar_wr.v b/rtl/axil_crossbar_wr.v index 6fbbca2db..1268ee406 100644 --- a/rtl/axil_crossbar_wr.v +++ b/rtl/axil_crossbar_wr.v @@ -128,7 +128,7 @@ integer i; // check configuration initial begin for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin + if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < $clog2(STRB_WIDTH) || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin $error("Error: value out of range (instance %m)"); $finish; end diff --git a/rtl/axil_interconnect.v b/rtl/axil_interconnect.v index fb9d9bfc2..e5d55ad97 100644 --- a/rtl/axil_interconnect.v +++ b/rtl/axil_interconnect.v @@ -148,7 +148,7 @@ integer i, j; // check configuration initial begin for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 0 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin + if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < $clog2(STRB_WIDTH) || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin $error("Error: address width out of range (instance %m)"); $finish; end