From de76c82186e251643bb227a8c94c31d4277f21a7 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 13 Jan 2021 21:50:32 -0800 Subject: [PATCH] Add placement constraints for VCU118 10G mqnic_tdma design --- fpga/mqnic_tdma/VCU118/fpga_10g/fpga.xdc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/fpga.xdc b/fpga/mqnic_tdma/VCU118/fpga_10g/fpga.xdc index dbb534e6f..f77ac3a74 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/fpga.xdc +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/fpga.xdc @@ -251,3 +251,19 @@ set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}] + +# Floorplanning constraints +#create_pblock pblock_slr0 +#add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet [list ]] +#resize_pblock [get_pblocks pblock_slr0] -add {SLR0} + +create_pblock pblock_slr1 +add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list pcie4_uscale_plus_inst]] +add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]] +add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_mux_inst]] +resize_pblock [get_pblocks pblock_slr1] -add {SLR1} + +#create_pblock pblock_slr2 +#add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list ]] +#resize_pblock [get_pblocks pblock_slr2] -add {SLR2} +