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Add Stratix 10 JTAG IDs
This commit is contained in:
Alex Forencich
parent
7ab18f8602
commit
dfdf880c3a
221
utils/fpga_id.c
221
utils/fpga_id.c
@ -35,100 +35,173 @@ either expressed or implied, of The Regents of the University of California.
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struct fpga_id {
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int id;
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int mask;
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char part[16];
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};
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const struct fpga_id fpga_id_list[] =
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{
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// Xilinx
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// Artix 7
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{FPGA_ID_XC7A15T, "XC7A15T"},
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{FPGA_ID_XC7A35T, "XC7A35T"},
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{FPGA_ID_XC7A50T, "XC7A50T"},
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{FPGA_ID_XC7A75T, "XC7A75T"},
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{FPGA_ID_XC7A100T, "XC7A100T"},
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{FPGA_ID_XC7A200T, "XC7A200T"},
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{FPGA_ID_XC7A15T, FPGA_ID_MASK_NOVER, "XC7A15T"},
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{FPGA_ID_XC7A35T, FPGA_ID_MASK_NOVER, "XC7A35T"},
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{FPGA_ID_XC7A50T, FPGA_ID_MASK_NOVER, "XC7A50T"},
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{FPGA_ID_XC7A75T, FPGA_ID_MASK_NOVER, "XC7A75T"},
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{FPGA_ID_XC7A100T, FPGA_ID_MASK_NOVER, "XC7A100T"},
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{FPGA_ID_XC7A200T, FPGA_ID_MASK_NOVER, "XC7A200T"},
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// Kintex 7
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{FPGA_ID_XC7K70T, "XC7K70T"},
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{FPGA_ID_XC7K160T, "XC7K160T"},
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{FPGA_ID_XC7K325T, "XC7K325T"},
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{FPGA_ID_XC7K355T, "XC7K355T"},
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{FPGA_ID_XC7K410T, "XC7K410T"},
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{FPGA_ID_XC7K420T, "XC7K420T"},
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{FPGA_ID_XC7K480T, "XC7K480T"},
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{FPGA_ID_XC7K70T, FPGA_ID_MASK_NOVER, "XC7K70T"},
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{FPGA_ID_XC7K160T, FPGA_ID_MASK_NOVER, "XC7K160T"},
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{FPGA_ID_XC7K325T, FPGA_ID_MASK_NOVER, "XC7K325T"},
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{FPGA_ID_XC7K355T, FPGA_ID_MASK_NOVER, "XC7K355T"},
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{FPGA_ID_XC7K410T, FPGA_ID_MASK_NOVER, "XC7K410T"},
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{FPGA_ID_XC7K420T, FPGA_ID_MASK_NOVER, "XC7K420T"},
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{FPGA_ID_XC7K480T, FPGA_ID_MASK_NOVER, "XC7K480T"},
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// Virtex 7
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{FPGA_ID_XC7V585T, "XC7V585T"},
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{FPGA_ID_XC7V2000T, "XC7V2000T"},
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{FPGA_ID_XC7VX330T, "XC7VX330T"},
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{FPGA_ID_XC7VX415T, "XC7VX415T"},
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{FPGA_ID_XC7VX485T, "XC7VX485T"},
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{FPGA_ID_XC7VX550T, "XC7VX550T"},
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{FPGA_ID_XC7VX690T, "XC7VX690T"},
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{FPGA_ID_XC7VX980T, "XC7VX980T"},
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{FPGA_ID_XC7VX1140T, "XC7VX1140T"},
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{FPGA_ID_XC7VH580T, "XC7VH580T"},
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{FPGA_ID_XC7VH870T, "XC7VH870T"},
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{FPGA_ID_XC7V585T, FPGA_ID_MASK_NOVER, "XC7V585T"},
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{FPGA_ID_XC7V2000T, FPGA_ID_MASK_NOVER, "XC7V2000T"},
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{FPGA_ID_XC7VX330T, FPGA_ID_MASK_NOVER, "XC7VX330T"},
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{FPGA_ID_XC7VX415T, FPGA_ID_MASK_NOVER, "XC7VX415T"},
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{FPGA_ID_XC7VX485T, FPGA_ID_MASK_NOVER, "XC7VX485T"},
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{FPGA_ID_XC7VX550T, FPGA_ID_MASK_NOVER, "XC7VX550T"},
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{FPGA_ID_XC7VX690T, FPGA_ID_MASK_NOVER, "XC7VX690T"},
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{FPGA_ID_XC7VX980T, FPGA_ID_MASK_NOVER, "XC7VX980T"},
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{FPGA_ID_XC7VX1140T, FPGA_ID_MASK_NOVER, "XC7VX1140T"},
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{FPGA_ID_XC7VH580T, FPGA_ID_MASK_NOVER, "XC7VH580T"},
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{FPGA_ID_XC7VH870T, FPGA_ID_MASK_NOVER, "XC7VH870T"},
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// Kintex Ultrascale
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{FPGA_ID_XCKU025, "XCKU025"},
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{FPGA_ID_XCKU035, "XCKU035"},
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{FPGA_ID_XCKU040, "XCKU040"},
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{FPGA_ID_XCKU060, "XCKU060"},
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{FPGA_ID_XCKU085, "XCKU085"},
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{FPGA_ID_XCKU095, "XCKU095"},
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{FPGA_ID_XCKU115, "XCKU115"},
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{FPGA_ID_XCKU025, FPGA_ID_MASK_NOVER, "XCKU025"},
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{FPGA_ID_XCKU035, FPGA_ID_MASK_NOVER, "XCKU035"},
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{FPGA_ID_XCKU040, FPGA_ID_MASK_NOVER, "XCKU040"},
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{FPGA_ID_XCKU060, FPGA_ID_MASK_NOVER, "XCKU060"},
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{FPGA_ID_XCKU085, FPGA_ID_MASK_NOVER, "XCKU085"},
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{FPGA_ID_XCKU095, FPGA_ID_MASK_NOVER, "XCKU095"},
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{FPGA_ID_XCKU115, FPGA_ID_MASK_NOVER, "XCKU115"},
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// Virtex Ultrascale
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{FPGA_ID_XCVU065, "XCVU065"},
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{FPGA_ID_XCVU080, "XCVU080"},
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{FPGA_ID_XCVU095, "XCVU095"},
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{FPGA_ID_XCVU125, "XCVU125"},
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{FPGA_ID_XCVU160, "XCVU160"},
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{FPGA_ID_XCVU190, "XCVU190"},
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{FPGA_ID_XCVU440, "XCVU440"},
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{FPGA_ID_XCVU065, FPGA_ID_MASK_NOVER, "XCVU065"},
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{FPGA_ID_XCVU080, FPGA_ID_MASK_NOVER, "XCVU080"},
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{FPGA_ID_XCVU095, FPGA_ID_MASK_NOVER, "XCVU095"},
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{FPGA_ID_XCVU125, FPGA_ID_MASK_NOVER, "XCVU125"},
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{FPGA_ID_XCVU160, FPGA_ID_MASK_NOVER, "XCVU160"},
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{FPGA_ID_XCVU190, FPGA_ID_MASK_NOVER, "XCVU190"},
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{FPGA_ID_XCVU440, FPGA_ID_MASK_NOVER, "XCVU440"},
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// Kintex Ultrascale+
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{FPGA_ID_XCKU3P, "XCKU3P"},
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{FPGA_ID_XCKU5P, "XCKU5P"},
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{FPGA_ID_XCKU9P, "XCKU9P"},
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{FPGA_ID_XCKU11P, "XCKU11P"},
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{FPGA_ID_XCKU13P, "XCKU13P"},
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{FPGA_ID_XCKU15P, "XCKU15P"},
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{FPGA_ID_XCKU3P, FPGA_ID_MASK_NOVER, "XCKU3P"},
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{FPGA_ID_XCKU5P, FPGA_ID_MASK_NOVER, "XCKU5P"},
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{FPGA_ID_XCKU9P, FPGA_ID_MASK_NOVER, "XCKU9P"},
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{FPGA_ID_XCKU11P, FPGA_ID_MASK_NOVER, "XCKU11P"},
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{FPGA_ID_XCKU13P, FPGA_ID_MASK_NOVER, "XCKU13P"},
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{FPGA_ID_XCKU15P, FPGA_ID_MASK_NOVER, "XCKU15P"},
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// Virtex Ultrascale+
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{FPGA_ID_XCVU3P, "XCVU3P"},
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{FPGA_ID_XCVU5P, "XCVU5P"},
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{FPGA_ID_XCVU7P, "XCVU7P"},
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{FPGA_ID_XCVU9P, "XCVU9P"},
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{FPGA_ID_XCVU11P, "XCVU11P"},
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{FPGA_ID_XCVU13P, "XCVU13P"},
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{FPGA_ID_XCVU3P, FPGA_ID_MASK_NOVER, "XCVU3P"},
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{FPGA_ID_XCVU5P, FPGA_ID_MASK_NOVER, "XCVU5P"},
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{FPGA_ID_XCVU7P, FPGA_ID_MASK_NOVER, "XCVU7P"},
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{FPGA_ID_XCVU9P, FPGA_ID_MASK_NOVER, "XCVU9P"},
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{FPGA_ID_XCVU11P, FPGA_ID_MASK_NOVER, "XCVU11P"},
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{FPGA_ID_XCVU13P, FPGA_ID_MASK_NOVER, "XCVU13P"},
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// Zynq Ultrascale+
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{FPGA_ID_XCZU2, "XCZU2"},
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{FPGA_ID_XCZU3, "XCZU3"},
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{FPGA_ID_XCZU4, "XCZU4"},
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{FPGA_ID_XCZU5, "XCZU5"},
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{FPGA_ID_XCZU6, "XCZU6"},
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{FPGA_ID_XCZU7, "XCZU7"},
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{FPGA_ID_XCZU9, "XCZU9"},
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{FPGA_ID_XCZU11, "XCZU11"},
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{FPGA_ID_XCZU15, "XCZU15"},
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{FPGA_ID_XCZU17, "XCZU17"},
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{FPGA_ID_XCZU19, "XCZU19"},
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{FPGA_ID_XCZU21, "XCZU21"},
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{FPGA_ID_XCZU25, "XCZU25"},
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{FPGA_ID_XCZU27, "XCZU27"},
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{FPGA_ID_XCZU28, "XCZU28"},
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{FPGA_ID_XCZU29, "XCZU29"},
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{FPGA_ID_XCZU2, FPGA_ID_MASK_NOVER, "XCZU2"},
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{FPGA_ID_XCZU3, FPGA_ID_MASK_NOVER, "XCZU3"},
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{FPGA_ID_XCZU4, FPGA_ID_MASK_NOVER, "XCZU4"},
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{FPGA_ID_XCZU5, FPGA_ID_MASK_NOVER, "XCZU5"},
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{FPGA_ID_XCZU6, FPGA_ID_MASK_NOVER, "XCZU6"},
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{FPGA_ID_XCZU7, FPGA_ID_MASK_NOVER, "XCZU7"},
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{FPGA_ID_XCZU9, FPGA_ID_MASK_NOVER, "XCZU9"},
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{FPGA_ID_XCZU11, FPGA_ID_MASK_NOVER, "XCZU11"},
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{FPGA_ID_XCZU15, FPGA_ID_MASK_NOVER, "XCZU15"},
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{FPGA_ID_XCZU17, FPGA_ID_MASK_NOVER, "XCZU17"},
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{FPGA_ID_XCZU19, FPGA_ID_MASK_NOVER, "XCZU19"},
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{FPGA_ID_XCZU21, FPGA_ID_MASK_NOVER, "XCZU21"},
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{FPGA_ID_XCZU25, FPGA_ID_MASK_NOVER, "XCZU25"},
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{FPGA_ID_XCZU27, FPGA_ID_MASK_NOVER, "XCZU27"},
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{FPGA_ID_XCZU28, FPGA_ID_MASK_NOVER, "XCZU28"},
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{FPGA_ID_XCZU29, FPGA_ID_MASK_NOVER, "XCZU29"},
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// Alveo
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{FPGA_ID_XCU50, "XCU50"},
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{FPGA_ID_XCU200, "XCU200"},
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{FPGA_ID_XCU250, "XCU250"},
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{FPGA_ID_XCU280, "XCU280"},
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{0, ""}
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{FPGA_ID_XCU50, FPGA_ID_MASK_NOVER, "XCU50"},
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{FPGA_ID_XCU200, FPGA_ID_MASK_NOVER, "XCU200"},
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{FPGA_ID_XCU250, FPGA_ID_MASK_NOVER, "XCU250"},
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{FPGA_ID_XCU280, FPGA_ID_MASK_NOVER, "XCU280"},
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// Intel
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// Stratix 10
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{FPGA_ID_1SG10MH_U1, FPGA_ID_MASK_FULL, "1SG10MH_U1"},
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{FPGA_ID_1SG10MH_U2, FPGA_ID_MASK_FULL, "1SG10MH_U2"},
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{FPGA_ID_1SG040H, FPGA_ID_MASK_FULL, "1SG040H"},
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{FPGA_ID_1SG040H_NL, FPGA_ID_MASK_FULL, "1SG040H(NL)"},
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{FPGA_ID_1SG065H, FPGA_ID_MASK_FULL, "1SG065H"},
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{FPGA_ID_1SG065H_NL, FPGA_ID_MASK_FULL, "1SG065H(NL)"},
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{FPGA_ID_1SG085H, FPGA_ID_MASK_FULL, "1SG085H"},
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{FPGA_ID_1SG110H, FPGA_ID_MASK_FULL, "1SG110H"},
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{FPGA_ID_1SG110H_NL, FPGA_ID_MASK_FULL, "1SG110H(NL)"},
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{FPGA_ID_1SG165H, FPGA_ID_MASK_FULL, "1SG165H"},
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{FPGA_ID_1SG166H, FPGA_ID_MASK_FULL, "1SG166H"},
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{FPGA_ID_1SG166H_NL, FPGA_ID_MASK_FULL, "1SG166H(NL)"},
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{FPGA_ID_1SG210H, FPGA_ID_MASK_FULL, "1SG210H"},
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{FPGA_ID_1SG210H_ES1, FPGA_ID_MASK_FULL, "1SG210H(ES1)"},
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{FPGA_ID_1SG211H, FPGA_ID_MASK_FULL, "1SG211H"},
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{FPGA_ID_1SG250L, FPGA_ID_MASK_FULL, "1SG250L"},
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{FPGA_ID_1SG250H, FPGA_ID_MASK_FULL, "1SG250H"},
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{FPGA_ID_1SG280L, FPGA_ID_MASK_FULL, "1SG280L"},
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{FPGA_ID_1SG280L_NL, FPGA_ID_MASK_FULL, "1SG280L(NL)"},
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{FPGA_ID_1SG280L_ES1, FPGA_ID_MASK_FULL, "1SG280L(ES1)"},
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{FPGA_ID_1SG280L_ES2, FPGA_ID_MASK_FULL, "1SG280L(ES2)"},
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{FPGA_ID_1SG280L_ES3, FPGA_ID_MASK_FULL, "1SG280L(ES3)"},
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{FPGA_ID_1SG280H, FPGA_ID_MASK_FULL, "1SG280H"},
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{FPGA_ID_1SG280H_NL, FPGA_ID_MASK_FULL, "1SG280H(NL)"},
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{FPGA_ID_1SG280H_ES1, FPGA_ID_MASK_FULL, "1SG280H(ES1)"},
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{FPGA_ID_1SG280H_ES2, FPGA_ID_MASK_FULL, "1SG280H(ES2)"},
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{FPGA_ID_1SG280H_ES3, FPGA_ID_MASK_FULL, "1SG280H(ES3)"},
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{FPGA_ID_1SX040H, FPGA_ID_MASK_FULL, "1SX040H"},
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{FPGA_ID_1SX065H, FPGA_ID_MASK_FULL, "1SX065H"},
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{FPGA_ID_1SX085H, FPGA_ID_MASK_FULL, "1SX085H"},
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{FPGA_ID_1SX110H, FPGA_ID_MASK_FULL, "1SX110H"},
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{FPGA_ID_1SX165H, FPGA_ID_MASK_FULL, "1SX165H"},
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{FPGA_ID_1SX210H, FPGA_ID_MASK_FULL, "1SX210H"},
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{FPGA_ID_1SX250L, FPGA_ID_MASK_FULL, "1SX250L"},
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{FPGA_ID_1SX250H, FPGA_ID_MASK_FULL, "1SX250H"},
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{FPGA_ID_1SX280L, FPGA_ID_MASK_FULL, "1SX280L"},
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{FPGA_ID_1SX280L_ES1, FPGA_ID_MASK_FULL, "1SX280L(ES1)"},
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{FPGA_ID_1SX280L_ES2, FPGA_ID_MASK_FULL, "1SX280L(ES2)"},
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{FPGA_ID_1SX280H, FPGA_ID_MASK_FULL, "1SX280H"},
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{FPGA_ID_1SX280H_ES1, FPGA_ID_MASK_FULL, "1SX280H(ES1)"},
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{FPGA_ID_1SX280H_ES2, FPGA_ID_MASK_FULL, "1SX280H(ES2)"},
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{FPGA_ID_1ST040E, FPGA_ID_MASK_FULL, "1ST040E"},
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{FPGA_ID_1ST040E_NL, FPGA_ID_MASK_FULL, "1ST040E(NL)"},
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{FPGA_ID_1ST085E, FPGA_ID_MASK_FULL, "1ST085E"},
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{FPGA_ID_1ST110E, FPGA_ID_MASK_FULL, "1ST110E"},
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{FPGA_ID_1ST110E_NL, FPGA_ID_MASK_FULL, "1ST110E(NL)"},
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{FPGA_ID_1ST165E, FPGA_ID_MASK_FULL, "1ST165E"},
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{FPGA_ID_1ST210E, FPGA_ID_MASK_FULL, "1ST210E"},
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{FPGA_ID_1ST210E_ES1, FPGA_ID_MASK_FULL, "1ST210E(ES1)"},
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{FPGA_ID_1ST250E, FPGA_ID_MASK_FULL, "1ST250E"},
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{FPGA_ID_1ST280E, FPGA_ID_MASK_FULL, "1ST280E"},
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{FPGA_ID_1ST280E_ES1, FPGA_ID_MASK_FULL, "1ST280E(ES1)"},
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{FPGA_ID_1SM16BE, FPGA_ID_MASK_FULL, "1SM16BE"},
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{FPGA_ID_1SM16BE_ES1, FPGA_ID_MASK_FULL, "1SM16BE(ES1)"},
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{FPGA_ID_1SM16BH, FPGA_ID_MASK_FULL, "1SM16BH"},
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{FPGA_ID_1SM16BH_ES1, FPGA_ID_MASK_FULL, "1SM16BH(ES1)"},
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{FPGA_ID_1SM16CH, FPGA_ID_MASK_FULL, "1SM16CH"},
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{FPGA_ID_1SM16CH_ES1, FPGA_ID_MASK_FULL, "1SM16CH(ES1)"},
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{FPGA_ID_1SM21BE, FPGA_ID_MASK_FULL, "1SM21BE"},
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{FPGA_ID_1SM21BE_ES1, FPGA_ID_MASK_FULL, "1SM21BE(ES1)"},
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{FPGA_ID_1SM21BH, FPGA_ID_MASK_FULL, "1SM21BH"},
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{FPGA_ID_1SM21BH_ES1, FPGA_ID_MASK_FULL, "1SM21BH(ES1)"},
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{FPGA_ID_1SM21CH, FPGA_ID_MASK_FULL, "1SM21CH"},
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{FPGA_ID_1SM21CH_ES1, FPGA_ID_MASK_FULL, "1SM21CH(ES1)"},
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{FPGA_ID_1SD110P, FPGA_ID_MASK_FULL, "1SD110P"},
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{FPGA_ID_1SD110P_NL, FPGA_ID_MASK_FULL, "1SD110P(NL)"},
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{FPGA_ID_1SD21BP, FPGA_ID_MASK_FULL, "1SD21BP"},
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{FPGA_ID_1SD280P, FPGA_ID_MASK_FULL, "1SD280P"},
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// end of list
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{0, 0, ""}
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};
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const char *get_fpga_part(int id)
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{
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const struct fpga_id *ptr = fpga_id_list;
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id = id & 0x0fffffff; // mask off version
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while (ptr->id && ptr->id != id)
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while (ptr->id && ((ptr->id ^ id) & ptr->mask) != 0)
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{
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ptr++;
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}
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@ -34,6 +34,13 @@ either expressed or implied, of The Regents of the University of California.
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#ifndef FPGA_ID_H
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#define FPGA_ID_H
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#define FPGA_ID_MASK_FULL 0xFFFFFFFF
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#define FPGA_ID_MASK_VER 0xF0000000
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#define FPGA_ID_MASK_PART 0x0FFFF000
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#define FPGA_ID_MASK_MFR 0x00000FFE
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#define FPGA_ID_MASK_NOVER 0x0FFFFFFF
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// Xilinx
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// Artix 7
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#define FPGA_ID_XC7A15T 0x362D093
|
||||
#define FPGA_ID_XC7A35T 0x362D093
|
||||
@ -114,6 +121,77 @@ either expressed or implied, of The Regents of the University of California.
|
||||
#define FPGA_ID_XCU250 0x4B57093
|
||||
#define FPGA_ID_XCU280 0x4B7D093
|
||||
|
||||
// Intel
|
||||
// Stratix 10
|
||||
#define FPGA_ID_1SG10MH_U1 0x032270DD
|
||||
#define FPGA_ID_1SG10MH_U2 0x0322F0DD
|
||||
#define FPGA_ID_1SG040H 0x032200DD
|
||||
#define FPGA_ID_1SG040H_NL 0x032A00DD
|
||||
#define FPGA_ID_1SG065H 0x032210DD
|
||||
#define FPGA_ID_1SG065H_NL 0x032A10DD
|
||||
#define FPGA_ID_1SG085H 0x132220DD
|
||||
#define FPGA_ID_1SG110H 0x032220DD
|
||||
#define FPGA_ID_1SG110H_NL 0x032A20DD
|
||||
#define FPGA_ID_1SG165H 0xF32250DD
|
||||
#define FPGA_ID_1SG166H 0x532240DD
|
||||
#define FPGA_ID_1SG166H_NL 0x5322C0DD
|
||||
#define FPGA_ID_1SG210H 0xE32250DD
|
||||
#define FPGA_ID_1SG210H_ES1 0x232250DD
|
||||
#define FPGA_ID_1SG211H 0x432240DD
|
||||
#define FPGA_ID_1SG250L 0xD32150DD
|
||||
#define FPGA_ID_1SG250H 0xD32250DD
|
||||
#define FPGA_ID_1SG280L 0xC32150DD
|
||||
#define FPGA_ID_1SG280L_NL 0xC32950DD
|
||||
#define FPGA_ID_1SG280L_ES1 0x032150DD
|
||||
#define FPGA_ID_1SG280L_ES2 0x032250DD
|
||||
#define FPGA_ID_1SG280L_ES3 0xC32150DD
|
||||
#define FPGA_ID_1SG280H 0xC32250DD
|
||||
#define FPGA_ID_1SG280H_NL 0xC32A50DD
|
||||
#define FPGA_ID_1SG280H_ES1 0x032250DD
|
||||
#define FPGA_ID_1SG280H_ES2 0xC32150DD
|
||||
#define FPGA_ID_1SG280H_ES3 0xC32250DD
|
||||
#define FPGA_ID_1SX040H 0x032280DD
|
||||
#define FPGA_ID_1SX065H 0x032290DD
|
||||
#define FPGA_ID_1SX085H 0x1322A0DD
|
||||
#define FPGA_ID_1SX110H 0x0322A0DD
|
||||
#define FPGA_ID_1SX165H 0xF322D0DD
|
||||
#define FPGA_ID_1SX210H 0xE322D0DD
|
||||
#define FPGA_ID_1SX250L 0xD321D0DD
|
||||
#define FPGA_ID_1SX250H 0xD322D0DD
|
||||
#define FPGA_ID_1SX280L 0xC321D0DD
|
||||
#define FPGA_ID_1SX280L_ES1 0x4321D0DD
|
||||
#define FPGA_ID_1SX280L_ES2 0x4321D0DD
|
||||
#define FPGA_ID_1SX280H 0xC322D0DD
|
||||
#define FPGA_ID_1SX280H_ES1 0x4322D0DD
|
||||
#define FPGA_ID_1SX280H_ES2 0xC322D0DD
|
||||
#define FPGA_ID_1ST040E 0x032380DD
|
||||
#define FPGA_ID_1ST040E_NL 0x032B00DD
|
||||
#define FPGA_ID_1ST085E 0x1323A0DD
|
||||
#define FPGA_ID_1ST110E 0x0323A0DD
|
||||
#define FPGA_ID_1ST110E_NL 0x032B20DD
|
||||
#define FPGA_ID_1ST165E 0x532340DD
|
||||
#define FPGA_ID_1ST210E 0x432340DD
|
||||
#define FPGA_ID_1ST210E_ES1 0x032340DD
|
||||
#define FPGA_ID_1ST250E 0xD323D0DD
|
||||
#define FPGA_ID_1ST280E 0xC323D0DD
|
||||
#define FPGA_ID_1ST280E_ES1 0xC323D0DD
|
||||
#define FPGA_ID_1SM16BE 0x732BC0DD
|
||||
#define FPGA_ID_1SM16BE_ES1 0x732BC0DD
|
||||
#define FPGA_ID_1SM16BH 0x732AC0DD
|
||||
#define FPGA_ID_1SM16BH_ES1 0x332AC0DD
|
||||
#define FPGA_ID_1SM16CH 0x532AC0DD
|
||||
#define FPGA_ID_1SM16CH_ES1 0x132AC0DD
|
||||
#define FPGA_ID_1SM21BE 0x632BC0DD
|
||||
#define FPGA_ID_1SM21BE_ES1 0x632BC0DD
|
||||
#define FPGA_ID_1SM21BH 0x632AC0DD
|
||||
#define FPGA_ID_1SM21BH_ES1 0x232AC0DD
|
||||
#define FPGA_ID_1SM21CH 0x432AC0DD
|
||||
#define FPGA_ID_1SM21CH_ES1 0x032AC0DD
|
||||
#define FPGA_ID_1SD110P 0x0324A0DD
|
||||
#define FPGA_ID_1SD110P_NL 0x032C20DD
|
||||
#define FPGA_ID_1SD21BP 0x632CC0DD
|
||||
#define FPGA_ID_1SD280P 0xC32450DD
|
||||
|
||||
const char *get_fpga_part(int id);
|
||||
|
||||
#endif /* FPGA_ID_H */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user