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fpga/mqnic: Add MAC-related parameters

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-09-07 18:35:42 -07:00
parent 31ced63c91
commit e0b31d9b94
82 changed files with 315 additions and 0 deletions
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3
fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1373,6 +1376,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1318,6 +1321,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1737,6 +1740,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -2134,6 +2137,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -2134,6 +2137,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -3269,6 +3272,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -2679,6 +2679,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1015,6 +1018,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1579,6 +1582,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/KR260/fpga/fpga/config.tcl
View File

@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl
View File

@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/KR260/fpga/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -693,6 +696,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
View File

@ -101,6 +101,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl
View File

@ -101,6 +101,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
View File

@ -71,6 +71,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1329,6 +1332,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl
View File

@ -101,6 +101,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl
View File

@ -101,6 +101,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v
View File

@ -71,6 +71,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1044,6 +1047,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1596,6 +1599,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1172,6 +1175,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1519,6 +1522,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1688,6 +1691,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1979,6 +1982,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -2488,6 +2491,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -2507,6 +2510,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/ZCU102/fpga/fpga/config.tcl
View File

@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl
View File

@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/ZCU102/fpga/rtl/fpga.v
View File

@ -75,6 +75,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1010,6 +1013,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl
View File

@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -1063,6 +1066,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
View File

@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl
View File

@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
View File

@ -75,6 +75,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -931,6 +934,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -2067,6 +2070,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

3
fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

3
fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl
View File

@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params ENABLE_PADDING "1"
dict set params ENABLE_DIC "1"
dict set params MIN_FRAME_LENGTH "64"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"

6
fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v
View File

@ -74,6 +74,9 @@ module fpga #
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
@ -2393,6 +2396,9 @@ fpga_core #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),