From e0b31d9b949b555f3fbaf59a72eaab5f0131039a Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 7 Sep 2023 18:35:42 -0700 Subject: [PATCH] fpga/mqnic: Add MAC-related parameters Signed-off-by: Alex Forencich --- fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl | 3 +++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/AU200/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/AU200/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/AU250/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/AU250/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/AU280/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/AU280/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/AU50/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/AU50/fpga_25g/rtl/fpga.v | 3 +++ .../DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl | 3 +++ .../DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl | 3 +++ fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl | 3 +++ fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl | 3 +++ fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v | 6 ++++++ .../fpga/fpga_app_dma_bench_ku040/config.tcl | 3 +++ .../fpga/fpga_app_dma_bench_ku060/config.tcl | 3 +++ .../mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl | 3 +++ .../mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl | 3 +++ fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v | 6 ++++++ fpga/mqnic/KR260/fpga/fpga/config.tcl | 3 +++ fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/KR260/fpga/rtl/fpga.v | 6 ++++++ fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl | 3 +++ fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v | 6 ++++++ fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl | 3 +++ fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v | 6 ++++++ fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl | 3 +++ .../Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl | 3 +++ .../Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/ZCU102/fpga/fpga/config.tcl | 3 +++ fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/ZCU102/fpga/rtl/fpga.v | 6 ++++++ fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl | 3 +++ fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v | 6 ++++++ fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl | 3 +++ fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl | 3 +++ fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v | 6 ++++++ fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl | 3 +++ fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v | 6 ++++++ fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl | 3 +++ fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl | 3 +++ fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v | 6 ++++++ 82 files changed, 315 insertions(+) diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl index 759e88e1a..daced677a 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl index b98313f5d..01acc3f42 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index 4ebfc8cdb..62e493f48 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1373,6 +1376,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl b/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl index 59520d0fe..6e1e0e5a3 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl index 2cf4f4a36..519681555 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v index 7dc9582b6..623f19e50 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1318,6 +1321,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index c88f80797..0edcf84fd 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index 85767d124..55cd4605c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index f7df7e22c..e47ee50bf 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 260124152..f30f80c9a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1737,6 +1740,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl index d8cc4b5f5..e8a6e4004 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl index cfae37032..50e894601 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index 191f9e04d..95b0715de 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -2134,6 +2137,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl index aaadf8690..1cab136b4 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index f4b628363..8076cb78c 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index 8570c6708..6c2ceebd5 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -2134,6 +2137,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl index 0eb3e4a4e..c06962a61 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl index f7cbfe9f7..720ebded5 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index 3019bfdda..4eab1d9ed 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -3269,6 +3272,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl index 478774999..e2cf917c9 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl index db5eac632..a1d92bb25 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index 1453aac36..8e87cd5eb 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -2679,6 +2679,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl index bd3d3538a..1e5bd1549 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl index e23c0b78c..891cf57b9 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl index fcfbd8cbe..74751ea7f 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl index f0568ecff..d3420b33e 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v index 9057654bd..224cda30f 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1015,6 +1018,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl index 662b6bf6c..761eb81a8 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl index 87e4c29c8..a7a3c7337 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl index 95583af28..18f1f4d03 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl index df503faaa..4f53af53b 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index d9d71194c..ffbda4999 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1579,6 +1582,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/KR260/fpga/fpga/config.tcl b/fpga/mqnic/KR260/fpga/fpga/config.tcl index f64dc57a8..39876117f 100644 --- a/fpga/mqnic/KR260/fpga/fpga/config.tcl +++ b/fpga/mqnic/KR260/fpga/fpga/config.tcl @@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl index e77364885..bab627d69 100644 --- a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl @@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga.v b/fpga/mqnic/KR260/fpga/rtl/fpga.v index cea4039f6..fa8bb673f 100644 --- a/fpga/mqnic/KR260/fpga/rtl/fpga.v +++ b/fpga/mqnic/KR260/fpga/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -693,6 +696,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl index e9f11be62..20746e6a2 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl @@ -101,6 +101,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl index 2f142fda1..0e482d503 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl @@ -101,6 +101,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v index 2bf431ecf..a6528e856 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v @@ -71,6 +71,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1329,6 +1332,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl index 4911f8bc8..a1f8a7ef2 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl @@ -101,6 +101,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl index 61ef1c1e2..1b07117d3 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl @@ -101,6 +101,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v index beff31c08..24ca1200a 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v @@ -71,6 +71,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1044,6 +1047,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index f56ca8396..17a69ea0c 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index 68c759259..a02419034 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl index fd80882e6..33f7716ed 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index e2c6b0a9e..4980471aa 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1596,6 +1599,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl index 97eab7b0f..163107b54 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl index 7399e65d7..4cebffb1a 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl index a4fc15255..7aa572f91 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v index 1b462a35b..9cc4ea6ad 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1172,6 +1175,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index 5bb9a4bfd..bccffb161 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl index e0364f9c0..90e872c76 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl index 8bdff334a..7520c962b 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index f6baf62cf..19b022a09 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1519,6 +1522,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 1139f9e76..22b1cbb21 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index c3581efef..01dc3067c 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index fbd47146a..9bb62ad38 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1688,6 +1691,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl index 4ef98ae78..625e812ac 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl index 431ade4e6..f30b4170c 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index 43afa03cb..72facb0c6 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1979,6 +1982,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl index e7ffc7750..3166cf115 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl index 2ec11568b..8c8c03903 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index e7e17fa9d..d36819099 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -2488,6 +2491,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl index 1f974eb44..cb75c651b 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl index 13ed1bfd3..97339a380 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl index c87ab4c04..aac599463 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v index d8d0929a2..556f1075b 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -2507,6 +2510,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl index dd4d7f81e..82e151367 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl @@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl index c9099f2bc..dfa2994e3 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl @@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index 2ef6b4fc7..4a2bbbf72 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -75,6 +75,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1010,6 +1013,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl index ccb18e8e6..6b7bfdb52 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl index 2f89361b9..37268c1e2 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl @@ -104,6 +104,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index 0e3881ba2..569e759ab 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -1063,6 +1066,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index c18fcffaa..8811a4205 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl index 7e7092dcb..61dbb9702 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl @@ -96,6 +96,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index 114264888..fd445391e 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -75,6 +75,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -931,6 +934,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index 4bc72eb60..4c1bcff6c 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index 0651eec95..9f7c270ee 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index aa2a7890f..b613492c3 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index df2383e55..79f4bfbd6 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -2067,6 +2070,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl index 27e944eb1..f677705f0 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl index 887f7c19a..dc4e569fc 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl @@ -113,6 +113,9 @@ dict set params TX_CPL_FIFO_DEPTH "32" dict set params TX_CHECKSUM_ENABLE "1" dict set params RX_HASH_ENABLE "1" dict set params RX_CHECKSUM_ENABLE "1" +dict set params ENABLE_PADDING "1" +dict set params ENABLE_DIC "1" +dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" dict set params RX_FIFO_DEPTH "32768" dict set params MAX_TX_SIZE "9214" diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v index ae7a39739..d6affd110 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v @@ -74,6 +74,9 @@ module fpga # parameter TX_CHECKSUM_ENABLE = 1, parameter RX_HASH_ENABLE = 1, parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 32768, parameter RX_FIFO_DEPTH = 32768, parameter MAX_TX_SIZE = 9214, @@ -2393,6 +2396,9 @@ fpga_core #( .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .MAX_TX_SIZE(MAX_TX_SIZE),