diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
index 3b65375c0..4f058384c 100644
--- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
@@ -144,6 +144,7 @@ export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
 export PARAM_PTP_CLOCK_PIPELINE ?= 0
 export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
 export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
+export PARAM_PTP_SEPARATE_TX_CLOCK ?= 0
 export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
 export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
 export PARAM_PTP_PEROUT_ENABLE ?= 0
@@ -261,6 +262,7 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@@ -358,6 +360,7 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -GPTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 666bbe29d..eebec40d5 100644
--- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -964,6 +964,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['PTP_CLOCK_PIPELINE'] = 0
     parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
     parameters['PTP_USE_SAMPLE_CLOCK'] = 1
+    parameters['PTP_SEPARATE_TX_CLOCK'] = 0
     parameters['PTP_SEPARATE_RX_CLOCK'] = 0
     parameters['PTP_PORT_CDC_PIPELINE'] = 0
     parameters['PTP_PEROUT_ENABLE'] = 0
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
index 2b0dc572f..b7e0bc396 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
@@ -143,6 +143,7 @@ export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
 export PARAM_PTP_CLOCK_PIPELINE ?= 0
 export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
 export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
+export PARAM_PTP_SEPARATE_TX_CLOCK ?= 0
 export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
 export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
 export PARAM_PTP_PEROUT_ENABLE ?= 0
@@ -260,6 +261,7 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@@ -357,6 +359,7 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -GPTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 35f31d0d1..d2638b027 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -804,6 +804,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['PTP_CLOCK_PIPELINE'] = 0
     parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
     parameters['PTP_USE_SAMPLE_CLOCK'] = 1
+    parameters['PTP_SEPARATE_TX_CLOCK'] = 0
     parameters['PTP_SEPARATE_RX_CLOCK'] = 0
     parameters['PTP_PORT_CDC_PIPELINE'] = 0
     parameters['PTP_PEROUT_ENABLE'] = 0
diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v
index 22313c5b0..c5d326866 100644
--- a/fpga/common/rtl/mqnic_core.v
+++ b/fpga/common/rtl/mqnic_core.v
@@ -66,6 +66,7 @@ module mqnic_core #
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_USE_SAMPLE_CLOCK = 0,
+    parameter PTP_SEPARATE_TX_CLOCK = 0,
     parameter PTP_SEPARATE_RX_CLOCK = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
@@ -374,6 +375,8 @@ module mqnic_core #
     input  wire [PORT_COUNT-1:0]                        tx_clk,
     input  wire [PORT_COUNT-1:0]                        tx_rst,
 
+    input  wire [PORT_COUNT-1:0]                        tx_ptp_clk,
+    input  wire [PORT_COUNT-1:0]                        tx_ptp_rst,
     output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]           tx_ptp_ts_96,
     output wire [PORT_COUNT-1:0]                        tx_ptp_ts_step,
 
@@ -2780,6 +2783,9 @@ generate
             wire port_rx_clk = rx_clk[n*PORTS_PER_IF+m];
             wire port_rx_rst = rx_rst[n*PORTS_PER_IF+m];
 
+            wire port_tx_ptp_clk = tx_ptp_clk[n*PORTS_PER_IF+m];
+            wire port_tx_ptp_rst = tx_ptp_rst[n*PORTS_PER_IF+m];
+
             wire port_rx_ptp_clk = rx_ptp_clk[n*PORTS_PER_IF+m];
             wire port_rx_ptp_rst = rx_ptp_rst[n*PORTS_PER_IF+m];
 
@@ -2814,8 +2820,8 @@ generate
                 tx_ptp_cdc_inst (
                     .input_clk(ptp_clk),
                     .input_rst(ptp_rst),
-                    .output_clk(port_tx_clk),
-                    .output_rst(port_tx_rst),
+                    .output_clk(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_clk : port_tx_clk),
+                    .output_rst(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_rst : port_tx_rst),
                     .sample_clk(ptp_sample_clk),
                     .input_ts(ptp_ts_96),
                     .input_ts_step(ptp_ts_step),
diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v
index 2b5512fc4..bd4d70c82 100644
--- a/fpga/common/rtl/mqnic_core_axi.v
+++ b/fpga/common/rtl/mqnic_core_axi.v
@@ -336,6 +336,8 @@ module mqnic_core_axi #
     input  wire [PORT_COUNT-1:0]                      tx_clk,
     input  wire [PORT_COUNT-1:0]                      tx_rst,
 
+    input  wire [PORT_COUNT-1:0]                      tx_ptp_clk,
+    input  wire [PORT_COUNT-1:0]                      tx_ptp_rst,
     output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]         tx_ptp_ts_96,
     output wire [PORT_COUNT-1:0]                      tx_ptp_ts_step,
 
@@ -1104,6 +1106,8 @@ core_inst (
     .tx_clk(tx_clk),
     .tx_rst(tx_rst),
 
+    .tx_ptp_clk(tx_ptp_clk),
+    .tx_ptp_rst(tx_ptp_rst),
     .tx_ptp_ts_96(tx_ptp_ts_96),
     .tx_ptp_ts_step(tx_ptp_ts_step),
 
diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v
index 583c3a5b8..3d4b7f33a 100644
--- a/fpga/common/rtl/mqnic_core_pcie.v
+++ b/fpga/common/rtl/mqnic_core_pcie.v
@@ -66,6 +66,7 @@ module mqnic_core_pcie #
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_USE_SAMPLE_CLOCK = 0,
+    parameter PTP_SEPARATE_TX_CLOCK = 0,
     parameter PTP_SEPARATE_RX_CLOCK = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
@@ -359,6 +360,8 @@ module mqnic_core_pcie #
     input  wire [PORT_COUNT-1:0]                         tx_clk,
     input  wire [PORT_COUNT-1:0]                         tx_rst,
 
+    input  wire [PORT_COUNT-1:0]                         tx_ptp_clk,
+    input  wire [PORT_COUNT-1:0]                         tx_ptp_rst,
     output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            tx_ptp_ts_96,
     output wire [PORT_COUNT-1:0]                         tx_ptp_ts_step,
 
@@ -1465,6 +1468,7 @@ mqnic_core #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1771,6 +1775,8 @@ core_inst (
     .tx_clk(tx_clk),
     .tx_rst(tx_rst),
 
+    .tx_ptp_clk(tx_ptp_clk),
+    .tx_ptp_rst(tx_ptp_rst),
     .tx_ptp_ts_96(tx_ptp_ts_96),
     .tx_ptp_ts_step(tx_ptp_ts_step),
 
diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v
index 105255389..47d300dc4 100644
--- a/fpga/common/rtl/mqnic_core_pcie_s10.v
+++ b/fpga/common/rtl/mqnic_core_pcie_s10.v
@@ -66,6 +66,7 @@ module mqnic_core_pcie_s10 #
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_USE_SAMPLE_CLOCK = 0,
+    parameter PTP_SEPARATE_TX_CLOCK = 0,
     parameter PTP_SEPARATE_RX_CLOCK = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
@@ -297,6 +298,8 @@ module mqnic_core_pcie_s10 #
     input  wire [PORT_COUNT-1:0]                         eth_tx_clk,
     input  wire [PORT_COUNT-1:0]                         eth_tx_rst,
 
+    input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk,
+    input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst,
     output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_96,
     output wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step,
 
@@ -634,6 +637,7 @@ mqnic_core_pcie #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -925,6 +929,8 @@ core_pcie_inst (
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
 
+    .tx_ptp_clk(eth_tx_ptp_clk),
+    .tx_ptp_rst(eth_tx_ptp_rst),
     .tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v
index 30a743279..d01b57e54 100644
--- a/fpga/common/rtl/mqnic_core_pcie_us.v
+++ b/fpga/common/rtl/mqnic_core_pcie_us.v
@@ -66,6 +66,7 @@ module mqnic_core_pcie_us #
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_USE_SAMPLE_CLOCK = 0,
+    parameter PTP_SEPARATE_TX_CLOCK = 0,
     parameter PTP_SEPARATE_RX_CLOCK = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
@@ -356,6 +357,8 @@ module mqnic_core_pcie_us #
     input  wire [PORT_COUNT-1:0]                         eth_tx_clk,
     input  wire [PORT_COUNT-1:0]                         eth_tx_rst,
 
+    input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk,
+    input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst,
     output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_96,
     output wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step,
 
@@ -749,6 +752,7 @@ mqnic_core_pcie #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1040,6 +1044,8 @@ core_pcie_inst (
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
 
+    .tx_ptp_clk(eth_tx_ptp_clk),
+    .tx_ptp_rst(eth_tx_ptp_rst),
     .tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile
index 61f26d94a..d6d953f5b 100644
--- a/fpga/common/tb/mqnic_core_axi/Makefile
+++ b/fpga/common/tb/mqnic_core_axi/Makefile
@@ -127,6 +127,7 @@ export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
 export PARAM_PTP_CLOCK_PIPELINE ?= 0
 export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
 export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
+export PARAM_PTP_SEPARATE_TX_CLOCK ?= 0
 export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
 export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
 export PARAM_PTP_PEROUT_ENABLE ?= 0
@@ -242,6 +243,7 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@@ -337,6 +339,7 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -GPTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
index d8498e57d..7c19855aa 100644
--- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
+++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
@@ -560,6 +560,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
     parameters['PTP_CLOCK_PIPELINE'] = 0
     parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
     parameters['PTP_USE_SAMPLE_CLOCK'] = 1
+    parameters['PTP_SEPARATE_TX_CLOCK'] = 0
     parameters['PTP_SEPARATE_RX_CLOCK'] = 0
     parameters['PTP_PORT_CDC_PIPELINE'] = 0
     parameters['PTP_PEROUT_ENABLE'] = 0
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
index 88f090e57..b8a551cdc 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
@@ -140,6 +140,7 @@ export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
 export PARAM_PTP_CLOCK_PIPELINE ?= 0
 export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
 export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
+export PARAM_PTP_SEPARATE_TX_CLOCK ?= 0
 export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
 export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
 export PARAM_PTP_PEROUT_ENABLE ?= 0
@@ -262,6 +263,7 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@@ -364,6 +366,7 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -GPTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
index 59953f243..69011e60b 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
+++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
@@ -721,6 +721,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
     parameters['PTP_CLOCK_PIPELINE'] = 0
     parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
     parameters['PTP_USE_SAMPLE_CLOCK'] = 1
+    parameters['PTP_SEPARATE_TX_CLOCK'] = 0
     parameters['PTP_SEPARATE_RX_CLOCK'] = 0
     parameters['PTP_PORT_CDC_PIPELINE'] = 0
     parameters['PTP_PEROUT_ENABLE'] = 0
diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile
index d478d731a..77099bff9 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile
@@ -141,6 +141,7 @@ export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
 export PARAM_PTP_CLOCK_PIPELINE ?= 0
 export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
 export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
+export PARAM_PTP_SEPARATE_TX_CLOCK ?= 0
 export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
 export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
 export PARAM_PTP_PEROUT_ENABLE ?= 0
@@ -258,6 +259,7 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@@ -355,6 +357,7 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -GPTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 03f15e904..9301009dc 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -796,6 +796,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['PTP_CLOCK_PIPELINE'] = 0
     parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
     parameters['PTP_USE_SAMPLE_CLOCK'] = 1
+    parameters['PTP_SEPARATE_TX_CLOCK'] = 0
     parameters['PTP_SEPARATE_RX_CLOCK'] = 0
     parameters['PTP_PORT_CDC_PIPELINE'] = 0
     parameters['PTP_PEROUT_ENABLE'] = 0
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
index c9794b64f..135747439 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
@@ -143,6 +143,7 @@ export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
 export PARAM_PTP_CLOCK_PIPELINE ?= 0
 export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
 export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
+export PARAM_PTP_SEPARATE_TX_CLOCK ?= 0
 export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
 export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
 export PARAM_PTP_PEROUT_ENABLE ?= 0
@@ -260,6 +261,7 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@@ -357,6 +359,7 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
 	COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
+	COMPILE_ARGS += -GPTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
 	COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
 	COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
 	COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
index 50326cf10..9ceb2a84e 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
@@ -851,6 +851,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['PTP_CLOCK_PIPELINE'] = 0
     parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
     parameters['PTP_USE_SAMPLE_CLOCK'] = 1
+    parameters['PTP_SEPARATE_TX_CLOCK'] = 0
     parameters['PTP_SEPARATE_RX_CLOCK'] = 0
     parameters['PTP_PORT_CDC_PIPELINE'] = 0
     parameters['PTP_PEROUT_ENABLE'] = 0
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
index fba01a201..2b8006cd0 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
@@ -847,6 +847,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1136,6 +1137,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
index e6570feaa..883375fe3 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
@@ -1119,6 +1119,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1408,6 +1409,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
index 45d91ed2e..fe83096f1 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
@@ -855,6 +855,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1144,6 +1145,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
index fc50dbffd..a9ac76e93 100644
--- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
@@ -1128,6 +1128,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1417,6 +1418,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
index 576dcb72d..dfeb441b7 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
@@ -855,6 +855,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1144,6 +1145,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
index 645bedb45..0949ec0ae 100644
--- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
@@ -1128,6 +1128,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1417,6 +1418,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
index a98d48884..5c639ebda 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
@@ -731,6 +731,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1020,6 +1021,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
index 3005f92ce..1cc386d0b 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
@@ -1004,6 +1004,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1293,6 +1294,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
index cb665f7ac..3f007efb8 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
@@ -721,6 +721,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1010,6 +1011,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
index 791c02ab2..efd90cafc 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
@@ -913,6 +913,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1202,6 +1203,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
index 6a7bf4729..74216d075 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
@@ -1147,6 +1147,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1436,6 +1437,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
index 78c6c9f67..9416e134a 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
@@ -749,6 +749,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1038,6 +1039,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
index 86142710b..6ec45d7a9 100644
--- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
@@ -903,6 +903,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1192,6 +1193,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
index c9d011899..a86fb19b6 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
@@ -1183,6 +1183,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1472,6 +1473,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
index 78f667de2..e3d00e88c 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
@@ -1001,6 +1001,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1290,6 +1291,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
index af0eafdb3..c3782d2df 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
@@ -827,6 +827,7 @@ mqnic_core_pcie_s10 #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1048,6 +1049,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
index 4e249e02b..0114a7b95 100644
--- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
@@ -953,6 +953,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1242,6 +1243,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
index 8f7673bdf..121e0f263 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
@@ -823,6 +823,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1112,6 +1113,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
index 9d493dbd9..2e89fbfbd 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
@@ -1096,6 +1096,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1385,6 +1386,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
index cda6fa500..c1fe37617 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
@@ -778,6 +778,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1067,6 +1068,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
index b034026c3..54ce4d420 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
@@ -1051,6 +1051,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1340,6 +1341,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
index c9291b060..d4ad24232 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
@@ -1034,6 +1034,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1323,6 +1324,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
index 3634b0725..3cbbfc9ef 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
@@ -1470,6 +1470,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1759,6 +1760,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
index 0ba2037c6..09d568e8d 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
@@ -811,6 +811,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1096,6 +1097,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
index 06e0859c7..17c7e6c23 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
@@ -768,6 +768,7 @@ mqnic_core_axi #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1032,6 +1033,8 @@ core_inst (
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
 
+    .tx_ptp_clk(0),
+    .tx_ptp_rst(0),
     .tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
index 2763e3073..67a849439 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
@@ -880,6 +880,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1169,6 +1170,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
index 6d45906c3..614684183 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
@@ -1152,6 +1152,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
+    .PTP_SEPARATE_TX_CLOCK(0),
     .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@@ -1441,6 +1442,8 @@ core_inst (
     .eth_tx_clk(eth_tx_clk),
     .eth_tx_rst(eth_tx_rst),
 
+    .eth_tx_ptp_clk(0),
+    .eth_tx_ptp_rst(0),
     .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
     .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),