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Update designs for PCIe module changes

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This commit is contained in:
Alex Forencich 2021-08-02 23:04:52 -07:00
parent 6e178377c3
commit e0e34a9f0d
33 changed files with 898 additions and 0 deletions
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2
fpga/common/rtl/cpl_write.v
View File

@ -137,6 +137,7 @@ module cpl_write #
* DMA write descriptor status input * DMA write descriptor status input
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire [3:0] s_axis_dma_write_desc_status_error,
input wire s_axis_dma_write_desc_status_valid, input wire s_axis_dma_write_desc_status_valid,
/* /*
@ -345,6 +346,7 @@ dma_client_axis_sink_inst (
.m_axis_write_desc_status_id(), .m_axis_write_desc_status_id(),
.m_axis_write_desc_status_dest(), .m_axis_write_desc_status_dest(),
.m_axis_write_desc_status_user(), .m_axis_write_desc_status_user(),
.m_axis_write_desc_status_error(),
.m_axis_write_desc_status_valid(dma_write_desc_status_valid), .m_axis_write_desc_status_valid(dma_write_desc_status_valid),
/* /*

2
fpga/common/rtl/desc_fetch.v
View File

@ -164,6 +164,7 @@ module desc_fetch #
* DMA read descriptor status input * DMA read descriptor status input
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire [3:0] s_axis_dma_read_desc_status_error,
input wire s_axis_dma_read_desc_status_valid, input wire s_axis_dma_read_desc_status_valid,
/* /*
@ -398,6 +399,7 @@ dma_client_axis_source_inst (
* DMA read descriptor status output * DMA read descriptor status output
*/ */
.m_axis_read_desc_status_tag(dma_read_desc_status_tag), .m_axis_read_desc_status_tag(dma_read_desc_status_tag),
.m_axis_read_desc_status_error(),
.m_axis_read_desc_status_valid(dma_read_desc_status_valid), .m_axis_read_desc_status_valid(dma_read_desc_status_valid),
/* /*

16
fpga/common/rtl/mqnic_interface.v
View File

@ -170,6 +170,7 @@ module mqnic_interface #
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_ctrl_dma_read_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_ctrl_dma_read_desc_status_tag,
input wire [3:0] s_axis_ctrl_dma_read_desc_status_error,
input wire s_axis_ctrl_dma_read_desc_status_valid, input wire s_axis_ctrl_dma_read_desc_status_valid,
/* /*
@ -187,6 +188,7 @@ module mqnic_interface #
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_ctrl_dma_write_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_ctrl_dma_write_desc_status_tag,
input wire [3:0] s_axis_ctrl_dma_write_desc_status_error,
input wire s_axis_ctrl_dma_write_desc_status_valid, input wire s_axis_ctrl_dma_write_desc_status_valid,
/* /*
@ -204,6 +206,7 @@ module mqnic_interface #
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_data_dma_read_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_data_dma_read_desc_status_tag,
input wire [3:0] s_axis_data_dma_read_desc_status_error,
input wire s_axis_data_dma_read_desc_status_valid, input wire s_axis_data_dma_read_desc_status_valid,
/* /*
@ -221,6 +224,7 @@ module mqnic_interface #
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_data_dma_write_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_data_dma_write_desc_status_tag,
input wire [3:0] s_axis_data_dma_write_desc_status_error,
input wire s_axis_data_dma_write_desc_status_valid, input wire s_axis_data_dma_write_desc_status_valid,
/* /*
@ -549,6 +553,7 @@ wire [PORTS-1:0] port_dma_read_desc_valid;
wire [PORTS-1:0] port_dma_read_desc_ready; wire [PORTS-1:0] port_dma_read_desc_ready;
wire [PORTS*DMA_TAG_WIDTH_INT-1:0] port_dma_read_desc_status_tag; wire [PORTS*DMA_TAG_WIDTH_INT-1:0] port_dma_read_desc_status_tag;
wire [PORTS*4-1:0] port_dma_read_desc_status_error;
wire [PORTS-1:0] port_dma_read_desc_status_valid; wire [PORTS-1:0] port_dma_read_desc_status_valid;
wire [PORTS*DMA_ADDR_WIDTH-1:0] port_dma_write_desc_dma_addr; wire [PORTS*DMA_ADDR_WIDTH-1:0] port_dma_write_desc_dma_addr;
@ -559,6 +564,7 @@ wire [PORTS-1:0] port_dma_write_desc_valid;
wire [PORTS-1:0] port_dma_write_desc_ready; wire [PORTS-1:0] port_dma_write_desc_ready;
wire [PORTS*DMA_TAG_WIDTH_INT-1:0] port_dma_write_desc_status_tag; wire [PORTS*DMA_TAG_WIDTH_INT-1:0] port_dma_write_desc_status_tag;
wire [PORTS*4-1:0] port_dma_write_desc_status_error;
wire [PORTS-1:0] port_dma_write_desc_status_valid; wire [PORTS-1:0] port_dma_write_desc_status_valid;
wire [PORTS*SEG_COUNT*SEG_BE_WIDTH-1:0] port_dma_ram_wr_cmd_be; wire [PORTS*SEG_COUNT*SEG_BE_WIDTH-1:0] port_dma_ram_wr_cmd_be;
@ -1561,6 +1567,7 @@ desc_fetch_inst (
* DMA read descriptor status input * DMA read descriptor status input
*/ */
.s_axis_dma_read_desc_status_tag(s_axis_ctrl_dma_read_desc_status_tag), .s_axis_dma_read_desc_status_tag(s_axis_ctrl_dma_read_desc_status_tag),
.s_axis_dma_read_desc_status_error(s_axis_ctrl_dma_read_desc_status_error),
.s_axis_dma_read_desc_status_valid(s_axis_ctrl_dma_read_desc_status_valid), .s_axis_dma_read_desc_status_valid(s_axis_ctrl_dma_read_desc_status_valid),
/* /*
@ -1713,6 +1720,7 @@ cpl_write_inst (
* DMA write descriptor status input * DMA write descriptor status input
*/ */
.s_axis_dma_write_desc_status_tag(s_axis_ctrl_dma_write_desc_status_tag), .s_axis_dma_write_desc_status_tag(s_axis_ctrl_dma_write_desc_status_tag),
.s_axis_dma_write_desc_status_error(s_axis_ctrl_dma_write_desc_status_error),
.s_axis_dma_write_desc_status_valid(s_axis_ctrl_dma_write_desc_status_valid), .s_axis_dma_write_desc_status_valid(s_axis_ctrl_dma_write_desc_status_valid),
/* /*
@ -1771,6 +1779,7 @@ if (PORTS > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(s_axis_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(s_axis_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(s_axis_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(s_axis_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(s_axis_data_dma_read_desc_status_valid),
/* /*
@ -1788,6 +1797,7 @@ if (PORTS > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(port_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(port_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(port_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(port_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(port_dma_read_desc_status_valid),
/* /*
@ -1805,6 +1815,7 @@ if (PORTS > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(s_axis_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(s_axis_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(s_axis_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(s_axis_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(s_axis_data_dma_write_desc_status_valid),
/* /*
@ -1822,6 +1833,7 @@ if (PORTS > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(port_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(port_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(port_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(port_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(port_dma_write_desc_status_valid),
/* /*
@ -1872,6 +1884,7 @@ end else begin
assign port_dma_read_desc_ready = m_axis_data_dma_read_desc_ready; assign port_dma_read_desc_ready = m_axis_data_dma_read_desc_ready;
assign port_dma_read_desc_status_tag = s_axis_data_dma_read_desc_status_tag; assign port_dma_read_desc_status_tag = s_axis_data_dma_read_desc_status_tag;
assign port_dma_read_desc_status_error = s_axis_data_dma_read_desc_status_error;
assign port_dma_read_desc_status_valid = s_axis_data_dma_read_desc_status_valid; assign port_dma_read_desc_status_valid = s_axis_data_dma_read_desc_status_valid;
assign m_axis_data_dma_write_desc_dma_addr = port_dma_write_desc_dma_addr; assign m_axis_data_dma_write_desc_dma_addr = port_dma_write_desc_dma_addr;
@ -1883,6 +1896,7 @@ end else begin
assign port_dma_write_desc_ready = m_axis_data_dma_write_desc_ready; assign port_dma_write_desc_ready = m_axis_data_dma_write_desc_ready;
assign port_dma_write_desc_status_tag = s_axis_data_dma_write_desc_status_tag; assign port_dma_write_desc_status_tag = s_axis_data_dma_write_desc_status_tag;
assign port_dma_write_desc_status_error = s_axis_data_dma_write_desc_status_error;
assign port_dma_write_desc_status_valid = s_axis_data_dma_write_desc_status_valid; assign port_dma_write_desc_status_valid = s_axis_data_dma_write_desc_status_valid;
assign port_dma_ram_wr_cmd_be = data_dma_ram_wr_cmd_be; assign port_dma_ram_wr_cmd_be = data_dma_ram_wr_cmd_be;
@ -2153,6 +2167,7 @@ generate
* DMA read descriptor status input * DMA read descriptor status input
*/ */
.s_axis_dma_read_desc_status_tag(port_dma_read_desc_status_tag[n*DMA_TAG_WIDTH_INT +: DMA_TAG_WIDTH_INT]), .s_axis_dma_read_desc_status_tag(port_dma_read_desc_status_tag[n*DMA_TAG_WIDTH_INT +: DMA_TAG_WIDTH_INT]),
.s_axis_dma_read_desc_status_error(port_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_dma_read_desc_status_valid(port_dma_read_desc_status_valid[n +: 1]), .s_axis_dma_read_desc_status_valid(port_dma_read_desc_status_valid[n +: 1]),
/* /*
@ -2169,6 +2184,7 @@ generate
* DMA write descriptor status input * DMA write descriptor status input
*/ */
.s_axis_dma_write_desc_status_tag(port_dma_write_desc_status_tag[n*DMA_TAG_WIDTH_INT +: DMA_TAG_WIDTH_INT]), .s_axis_dma_write_desc_status_tag(port_dma_write_desc_status_tag[n*DMA_TAG_WIDTH_INT +: DMA_TAG_WIDTH_INT]),
.s_axis_dma_write_desc_status_error(port_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_dma_write_desc_status_valid(port_dma_write_desc_status_valid[n +: 1]), .s_axis_dma_write_desc_status_valid(port_dma_write_desc_status_valid[n +: 1]),
/* /*

10
fpga/common/rtl/mqnic_port.v
View File

@ -218,6 +218,7 @@ module mqnic_port #
* DMA read descriptor status input * DMA read descriptor status input
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire [3:0] s_axis_dma_read_desc_status_error,
input wire s_axis_dma_read_desc_status_valid, input wire s_axis_dma_read_desc_status_valid,
/* /*
@ -234,6 +235,7 @@ module mqnic_port #
* DMA write descriptor status input * DMA write descriptor status input
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire [3:0] s_axis_dma_write_desc_status_error,
input wire s_axis_dma_write_desc_status_valid, input wire s_axis_dma_write_desc_status_valid,
/* /*
@ -543,6 +545,7 @@ wire dma_tx_desc_valid;
wire dma_tx_desc_ready; wire dma_tx_desc_ready;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_status_tag; wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_status_tag;
wire [3:0] dma_tx_desc_status_error;
wire dma_tx_desc_status_valid; wire dma_tx_desc_status_valid;
wire [RAM_ADDR_WIDTH-1:0] dma_rx_desc_addr; wire [RAM_ADDR_WIDTH-1:0] dma_rx_desc_addr;
@ -554,6 +557,7 @@ wire dma_rx_desc_ready;
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len; wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag; wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag;
wire dma_rx_desc_status_user; wire dma_rx_desc_status_user;
wire [3:0] dma_rx_desc_status_error;
wire dma_rx_desc_status_valid; wire dma_rx_desc_status_valid;
wire dma_enable = 1; wire dma_enable = 1;
@ -1244,6 +1248,7 @@ tx_engine_inst (
* DMA read descriptor status input * DMA read descriptor status input
*/ */
.s_axis_dma_read_desc_status_tag(s_axis_dma_read_desc_status_tag), .s_axis_dma_read_desc_status_tag(s_axis_dma_read_desc_status_tag),
.s_axis_dma_read_desc_status_error(s_axis_dma_read_desc_status_error),
.s_axis_dma_read_desc_status_valid(s_axis_dma_read_desc_status_valid), .s_axis_dma_read_desc_status_valid(s_axis_dma_read_desc_status_valid),
/* /*
@ -1260,6 +1265,7 @@ tx_engine_inst (
* Transmit descriptor status input * Transmit descriptor status input
*/ */
.s_axis_tx_desc_status_tag(dma_tx_desc_status_tag), .s_axis_tx_desc_status_tag(dma_tx_desc_status_tag),
.s_axis_tx_desc_status_error(dma_tx_desc_status_error),
.s_axis_tx_desc_status_valid(dma_tx_desc_status_valid), .s_axis_tx_desc_status_valid(dma_tx_desc_status_valid),
/* /*
@ -1433,6 +1439,7 @@ rx_engine_inst (
* DMA write descriptor status input * DMA write descriptor status input
*/ */
.s_axis_dma_write_desc_status_tag(s_axis_dma_write_desc_status_tag), .s_axis_dma_write_desc_status_tag(s_axis_dma_write_desc_status_tag),
.s_axis_dma_write_desc_status_error(s_axis_dma_write_desc_status_error),
.s_axis_dma_write_desc_status_valid(s_axis_dma_write_desc_status_valid), .s_axis_dma_write_desc_status_valid(s_axis_dma_write_desc_status_valid),
/* /*
@ -1450,6 +1457,7 @@ rx_engine_inst (
.s_axis_rx_desc_status_len(dma_rx_desc_status_len), .s_axis_rx_desc_status_len(dma_rx_desc_status_len),
.s_axis_rx_desc_status_tag(dma_rx_desc_status_tag), .s_axis_rx_desc_status_tag(dma_rx_desc_status_tag),
.s_axis_rx_desc_status_user(dma_rx_desc_status_user), .s_axis_rx_desc_status_user(dma_rx_desc_status_user),
.s_axis_rx_desc_status_error(dma_rx_desc_status_error),
.s_axis_rx_desc_status_valid(dma_rx_desc_status_valid), .s_axis_rx_desc_status_valid(dma_rx_desc_status_valid),
/* /*
@ -1919,6 +1927,7 @@ dma_client_axis_source_inst (
* DMA read descriptor status output * DMA read descriptor status output
*/ */
.m_axis_read_desc_status_tag(dma_tx_desc_status_tag), .m_axis_read_desc_status_tag(dma_tx_desc_status_tag),
.m_axis_read_desc_status_error(dma_tx_desc_status_error),
.m_axis_read_desc_status_valid(dma_tx_desc_status_valid), .m_axis_read_desc_status_valid(dma_tx_desc_status_valid),
/* /*
@ -2027,6 +2036,7 @@ dma_client_axis_sink_inst (
.m_axis_write_desc_status_id(), .m_axis_write_desc_status_id(),
.m_axis_write_desc_status_dest(), .m_axis_write_desc_status_dest(),
.m_axis_write_desc_status_user(dma_rx_desc_status_user), .m_axis_write_desc_status_user(dma_rx_desc_status_user),
.m_axis_write_desc_status_error(dma_rx_desc_status_error),
.m_axis_write_desc_status_valid(dma_rx_desc_status_valid), .m_axis_write_desc_status_valid(dma_rx_desc_status_valid),
/* /*

2
fpga/common/rtl/rx_engine.v
View File

@ -175,6 +175,7 @@ module rx_engine #
* DMA write descriptor status input * DMA write descriptor status input
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire [3:0] s_axis_dma_write_desc_status_error,
input wire s_axis_dma_write_desc_status_valid, input wire s_axis_dma_write_desc_status_valid,
/* /*
@ -192,6 +193,7 @@ module rx_engine #
input wire [DMA_CLIENT_LEN_WIDTH-1:0] s_axis_rx_desc_status_len, input wire [DMA_CLIENT_LEN_WIDTH-1:0] s_axis_rx_desc_status_len,
input wire [DMA_CLIENT_TAG_WIDTH-1:0] s_axis_rx_desc_status_tag, input wire [DMA_CLIENT_TAG_WIDTH-1:0] s_axis_rx_desc_status_tag,
input wire s_axis_rx_desc_status_user, input wire s_axis_rx_desc_status_user,
input wire [3:0] s_axis_rx_desc_status_error,
input wire s_axis_rx_desc_status_valid, input wire s_axis_rx_desc_status_valid,
/* /*

2
fpga/common/rtl/tx_engine.v
View File

@ -173,6 +173,7 @@ module tx_engine #
* DMA read descriptor status input * DMA read descriptor status input
*/ */
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag, input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire [3:0] s_axis_dma_read_desc_status_error,
input wire s_axis_dma_read_desc_status_valid, input wire s_axis_dma_read_desc_status_valid,
/* /*
@ -189,6 +190,7 @@ module tx_engine #
* Transmit descriptor status input * Transmit descriptor status input
*/ */
input wire [DMA_CLIENT_TAG_WIDTH-1:0] s_axis_tx_desc_status_tag, input wire [DMA_CLIENT_TAG_WIDTH-1:0] s_axis_tx_desc_status_tag,
input wire [3:0] s_axis_tx_desc_status_error,
input wire s_axis_tx_desc_status_valid, input wire s_axis_tx_desc_status_valid,
/* /*

32
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -412,6 +412,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -423,6 +424,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1040,6 +1042,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1057,6 +1060,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1304,6 +1308,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1315,6 +1320,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1326,6 +1332,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1337,6 +1344,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1405,6 +1413,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1422,6 +1431,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1439,6 +1449,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1456,6 +1467,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1504,6 +1516,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1515,6 +1528,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1526,6 +1540,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1537,6 +1552,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1607,6 +1623,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1624,6 +1641,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1641,6 +1659,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1658,6 +1677,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1733,6 +1753,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1750,6 +1771,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1767,6 +1789,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1784,6 +1807,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1834,6 +1858,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1845,6 +1870,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1871,6 +1897,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1882,6 +1909,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2273,6 +2301,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2290,6 +2319,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2307,6 +2337,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2324,6 +2355,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -475,6 +475,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -486,6 +487,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1103,6 +1105,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1120,6 +1123,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1367,6 +1371,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1378,6 +1383,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1389,6 +1395,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1400,6 +1407,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1468,6 +1476,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1485,6 +1494,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1502,6 +1512,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1519,6 +1530,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1567,6 +1579,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1578,6 +1591,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1589,6 +1603,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1600,6 +1615,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1670,6 +1686,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1687,6 +1704,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1704,6 +1722,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1721,6 +1740,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1796,6 +1816,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1813,6 +1834,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1830,6 +1852,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1847,6 +1870,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1897,6 +1921,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1908,6 +1933,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1934,6 +1960,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1945,6 +1972,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2362,6 +2390,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2379,6 +2408,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2396,6 +2426,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2413,6 +2444,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -475,6 +475,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -486,6 +487,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1103,6 +1105,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1120,6 +1123,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1367,6 +1371,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1378,6 +1383,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1389,6 +1395,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1400,6 +1407,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1468,6 +1476,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1485,6 +1494,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1502,6 +1512,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1519,6 +1530,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1567,6 +1579,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1578,6 +1591,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1589,6 +1603,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1600,6 +1615,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1670,6 +1686,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1687,6 +1704,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1704,6 +1722,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1721,6 +1740,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1796,6 +1816,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1813,6 +1834,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1830,6 +1852,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1847,6 +1870,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1897,6 +1921,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1908,6 +1933,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1934,6 +1960,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1945,6 +1972,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2362,6 +2390,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2379,6 +2408,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2396,6 +2426,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2413,6 +2444,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -432,6 +432,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -443,6 +444,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1030,6 +1032,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1047,6 +1050,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1294,6 +1298,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1305,6 +1310,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1316,6 +1322,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1327,6 +1334,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1395,6 +1403,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1412,6 +1421,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1429,6 +1439,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1446,6 +1457,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1494,6 +1506,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1505,6 +1518,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1516,6 +1530,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1527,6 +1542,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1597,6 +1613,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1614,6 +1631,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1631,6 +1649,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1648,6 +1667,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1723,6 +1743,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1740,6 +1761,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1757,6 +1779,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1774,6 +1797,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1824,6 +1848,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1835,6 +1860,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1861,6 +1887,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1872,6 +1899,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2260,6 +2288,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2277,6 +2306,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2294,6 +2324,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2311,6 +2342,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v
View File

@ -492,6 +492,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -503,6 +504,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1044,6 +1046,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1061,6 +1064,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1308,6 +1312,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1319,6 +1324,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1330,6 +1336,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1341,6 +1348,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1409,6 +1417,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1426,6 +1435,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1443,6 +1453,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1460,6 +1471,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1508,6 +1520,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1519,6 +1532,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1530,6 +1544,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1541,6 +1556,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1611,6 +1627,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1628,6 +1645,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1645,6 +1663,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1662,6 +1681,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1737,6 +1757,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1754,6 +1775,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1771,6 +1793,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1788,6 +1811,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1838,6 +1862,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1849,6 +1874,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1875,6 +1901,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1886,6 +1913,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2300,6 +2328,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2317,6 +2346,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2334,6 +2364,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2351,6 +2382,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -432,6 +432,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -443,6 +444,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1030,6 +1032,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1047,6 +1050,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1294,6 +1298,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1305,6 +1310,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1316,6 +1322,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1327,6 +1334,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1395,6 +1403,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1412,6 +1421,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1429,6 +1439,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1446,6 +1457,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1494,6 +1506,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1505,6 +1518,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1516,6 +1530,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1527,6 +1542,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1597,6 +1613,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1614,6 +1631,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1631,6 +1649,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1648,6 +1667,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1723,6 +1743,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1740,6 +1761,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1757,6 +1779,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1774,6 +1797,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1824,6 +1848,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1835,6 +1860,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1861,6 +1887,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1872,6 +1899,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2260,6 +2288,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2277,6 +2306,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2294,6 +2324,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2311,6 +2342,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v
View File

@ -492,6 +492,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -503,6 +504,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1044,6 +1046,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1061,6 +1064,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1308,6 +1312,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1319,6 +1324,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1330,6 +1336,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1341,6 +1348,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1409,6 +1417,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1426,6 +1435,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1443,6 +1453,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1460,6 +1471,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1508,6 +1520,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1519,6 +1532,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1530,6 +1544,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1541,6 +1556,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1611,6 +1627,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1628,6 +1645,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1645,6 +1663,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1662,6 +1681,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1737,6 +1757,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1754,6 +1775,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1771,6 +1793,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1788,6 +1811,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1838,6 +1862,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1849,6 +1874,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1875,6 +1901,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1886,6 +1913,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2300,6 +2328,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2317,6 +2346,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2334,6 +2364,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2351,6 +2382,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -404,6 +404,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -415,6 +416,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -941,6 +943,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -958,6 +961,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1205,6 +1209,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1216,6 +1221,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1227,6 +1233,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1238,6 +1245,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1306,6 +1314,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1323,6 +1332,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1340,6 +1350,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1357,6 +1368,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1405,6 +1417,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1416,6 +1429,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1427,6 +1441,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1438,6 +1453,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1508,6 +1524,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1525,6 +1542,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1542,6 +1560,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1559,6 +1578,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1634,6 +1654,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1651,6 +1672,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1668,6 +1690,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1685,6 +1708,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1735,6 +1759,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1746,6 +1771,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1772,6 +1798,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1783,6 +1810,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2171,6 +2199,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2188,6 +2217,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2205,6 +2235,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2222,6 +2253,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
View File

@ -464,6 +464,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -475,6 +476,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -955,6 +957,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -972,6 +975,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1219,6 +1223,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1230,6 +1235,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1241,6 +1247,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1252,6 +1259,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1320,6 +1328,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1337,6 +1346,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1354,6 +1364,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1371,6 +1382,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1419,6 +1431,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1430,6 +1443,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1441,6 +1455,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1452,6 +1467,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1522,6 +1538,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1539,6 +1556,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1556,6 +1574,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1573,6 +1592,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1648,6 +1668,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1665,6 +1686,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1682,6 +1704,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1699,6 +1722,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1749,6 +1773,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1760,6 +1785,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1786,6 +1812,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1797,6 +1824,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2211,6 +2239,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2228,6 +2257,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2245,6 +2275,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2262,6 +2293,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -386,6 +386,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -397,6 +398,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -923,6 +925,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -940,6 +943,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1187,6 +1191,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1198,6 +1203,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1209,6 +1215,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1220,6 +1227,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1288,6 +1296,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1305,6 +1314,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1322,6 +1332,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1339,6 +1350,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1387,6 +1399,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1398,6 +1411,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1409,6 +1423,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1420,6 +1435,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1490,6 +1506,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1507,6 +1524,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1524,6 +1542,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1541,6 +1560,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1616,6 +1636,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1633,6 +1654,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1650,6 +1672,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1667,6 +1690,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1717,6 +1741,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1728,6 +1753,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1754,6 +1780,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1765,6 +1792,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2070,6 +2098,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2087,6 +2116,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2104,6 +2134,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2121,6 +2152,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v
View File

@ -426,6 +426,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -437,6 +438,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -917,6 +919,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -934,6 +937,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1181,6 +1185,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1192,6 +1197,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1203,6 +1209,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1214,6 +1221,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1282,6 +1290,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1299,6 +1308,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1316,6 +1326,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1333,6 +1344,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1381,6 +1393,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1392,6 +1405,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1403,6 +1417,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1414,6 +1429,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1484,6 +1500,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1501,6 +1518,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1518,6 +1536,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1535,6 +1554,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1610,6 +1630,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1627,6 +1648,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1644,6 +1666,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1661,6 +1684,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1711,6 +1735,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1722,6 +1747,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1748,6 +1774,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1759,6 +1786,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2094,6 +2122,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2111,6 +2140,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2128,6 +2158,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2145,6 +2176,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -387,6 +387,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -398,6 +399,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1028,6 +1030,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1045,6 +1048,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1292,6 +1296,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1303,6 +1308,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1314,6 +1320,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1325,6 +1332,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1393,6 +1401,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1410,6 +1419,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1427,6 +1437,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1444,6 +1455,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1492,6 +1504,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1503,6 +1516,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1514,6 +1528,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1525,6 +1540,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1595,6 +1611,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1612,6 +1629,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1629,6 +1647,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1646,6 +1665,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1721,6 +1741,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1738,6 +1759,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1755,6 +1777,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1772,6 +1795,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1822,6 +1846,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1833,6 +1858,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1859,6 +1885,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1870,6 +1897,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2113,6 +2141,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2130,6 +2159,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2147,6 +2177,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2164,6 +2195,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v
View File

@ -389,6 +389,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -400,6 +401,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1028,6 +1030,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1045,6 +1048,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1292,6 +1296,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1303,6 +1308,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1314,6 +1320,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1325,6 +1332,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1393,6 +1401,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1410,6 +1419,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1427,6 +1437,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1444,6 +1455,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1492,6 +1504,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1503,6 +1516,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1514,6 +1528,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1525,6 +1540,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1595,6 +1611,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1612,6 +1629,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1629,6 +1647,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1646,6 +1665,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1721,6 +1741,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1738,6 +1759,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1755,6 +1777,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1772,6 +1795,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1822,6 +1846,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1833,6 +1858,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1859,6 +1885,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1870,6 +1897,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2113,6 +2141,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2130,6 +2159,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2147,6 +2177,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2164,6 +2195,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -388,6 +388,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -399,6 +400,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -916,6 +918,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -933,6 +936,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1180,6 +1184,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1191,6 +1196,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1202,6 +1208,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1213,6 +1220,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1281,6 +1289,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1298,6 +1307,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1315,6 +1325,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1332,6 +1343,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1380,6 +1392,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1391,6 +1404,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1402,6 +1416,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1413,6 +1428,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1483,6 +1499,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1500,6 +1517,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1517,6 +1535,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1534,6 +1553,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1609,6 +1629,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1626,6 +1647,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1643,6 +1665,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1660,6 +1683,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1710,6 +1734,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1721,6 +1746,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1747,6 +1773,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1758,6 +1785,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2041,6 +2069,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2058,6 +2087,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2075,6 +2105,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2092,6 +2123,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -426,6 +426,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -437,6 +438,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1012,6 +1014,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1029,6 +1032,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1276,6 +1280,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1287,6 +1292,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1298,6 +1304,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1309,6 +1316,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1377,6 +1385,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1394,6 +1403,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1411,6 +1421,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1428,6 +1439,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1476,6 +1488,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1487,6 +1500,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1498,6 +1512,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1509,6 +1524,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1579,6 +1595,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1596,6 +1613,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1613,6 +1631,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1630,6 +1649,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1705,6 +1725,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1722,6 +1743,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1739,6 +1761,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1756,6 +1779,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1806,6 +1830,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1817,6 +1842,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1843,6 +1869,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1854,6 +1881,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2222,6 +2250,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2239,6 +2268,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2256,6 +2286,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2273,6 +2304,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
View File

@ -418,6 +418,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -429,6 +430,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1019,6 +1021,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1036,6 +1039,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1283,6 +1287,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1294,6 +1299,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1305,6 +1311,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1316,6 +1323,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1384,6 +1392,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1401,6 +1410,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1418,6 +1428,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1435,6 +1446,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1483,6 +1495,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1494,6 +1507,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1505,6 +1519,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1516,6 +1531,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1586,6 +1602,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1603,6 +1620,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1620,6 +1638,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1637,6 +1656,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1712,6 +1732,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1729,6 +1750,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1746,6 +1768,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1763,6 +1786,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1813,6 +1837,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1824,6 +1849,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1850,6 +1876,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1861,6 +1888,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2283,6 +2311,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2300,6 +2329,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2317,6 +2347,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2334,6 +2365,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -478,6 +478,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -489,6 +490,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1079,6 +1081,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1096,6 +1099,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1343,6 +1347,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1354,6 +1359,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1365,6 +1371,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1376,6 +1383,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1444,6 +1452,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1461,6 +1470,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1478,6 +1488,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1495,6 +1506,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1543,6 +1555,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1554,6 +1567,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1565,6 +1579,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1576,6 +1591,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1646,6 +1662,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1663,6 +1680,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1680,6 +1698,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1697,6 +1716,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1772,6 +1792,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1789,6 +1810,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1806,6 +1828,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1823,6 +1846,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1873,6 +1897,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1884,6 +1909,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1910,6 +1936,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1921,6 +1948,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2369,6 +2397,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2386,6 +2415,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2403,6 +2433,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2420,6 +2451,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
View File

@ -407,6 +407,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -418,6 +419,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -958,6 +960,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -975,6 +978,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1222,6 +1226,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1233,6 +1238,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1244,6 +1250,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1255,6 +1262,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1323,6 +1331,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1340,6 +1349,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1357,6 +1367,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1374,6 +1385,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1422,6 +1434,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1433,6 +1446,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1444,6 +1458,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1455,6 +1470,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1525,6 +1541,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1542,6 +1559,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1559,6 +1577,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1576,6 +1595,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1651,6 +1671,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1668,6 +1689,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1685,6 +1707,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1702,6 +1725,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1752,6 +1776,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1763,6 +1788,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1789,6 +1815,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1800,6 +1827,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2188,6 +2216,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2205,6 +2234,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2222,6 +2252,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2239,6 +2270,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v
View File

@ -467,6 +467,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -478,6 +479,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -972,6 +974,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -989,6 +992,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1236,6 +1240,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1247,6 +1252,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1258,6 +1264,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1269,6 +1276,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1337,6 +1345,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1354,6 +1363,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1371,6 +1381,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1388,6 +1399,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1436,6 +1448,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1447,6 +1460,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1458,6 +1472,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1469,6 +1484,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1539,6 +1555,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1556,6 +1573,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1573,6 +1591,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1590,6 +1609,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1665,6 +1685,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1682,6 +1703,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1699,6 +1721,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1716,6 +1739,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1766,6 +1790,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1777,6 +1802,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1803,6 +1829,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1814,6 +1841,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2228,6 +2256,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2245,6 +2274,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2262,6 +2292,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2279,6 +2310,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
View File

@ -360,6 +360,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -371,6 +372,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -804,6 +806,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -821,6 +824,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1068,6 +1072,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1079,6 +1084,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1090,6 +1096,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1101,6 +1108,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1169,6 +1177,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1186,6 +1195,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1203,6 +1213,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1220,6 +1231,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1268,6 +1280,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1279,6 +1292,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1290,6 +1304,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1301,6 +1316,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1371,6 +1387,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1388,6 +1405,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1405,6 +1423,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1422,6 +1441,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1497,6 +1517,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1514,6 +1535,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1531,6 +1553,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1548,6 +1571,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1598,6 +1622,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1609,6 +1634,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1635,6 +1661,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1646,6 +1673,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -1893,6 +1921,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -1910,6 +1939,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -1927,6 +1957,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -1944,6 +1975,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
View File

@ -419,6 +419,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -430,6 +431,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1137,6 +1139,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1154,6 +1157,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1401,6 +1405,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1412,6 +1417,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1423,6 +1429,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1434,6 +1441,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1502,6 +1510,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1519,6 +1528,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1536,6 +1546,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1553,6 +1564,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1601,6 +1613,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1612,6 +1625,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1623,6 +1637,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1634,6 +1649,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1704,6 +1720,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1721,6 +1738,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1738,6 +1756,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1755,6 +1774,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1830,6 +1850,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1847,6 +1868,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1864,6 +1886,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1881,6 +1904,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1931,6 +1955,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1942,6 +1967,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1968,6 +1994,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1979,6 +2006,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2403,6 +2431,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2420,6 +2449,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2437,6 +2467,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2454,6 +2485,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v
View File

@ -482,6 +482,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -493,6 +494,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1200,6 +1202,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1217,6 +1220,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1464,6 +1468,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1475,6 +1480,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1486,6 +1492,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1497,6 +1504,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1565,6 +1573,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1582,6 +1591,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1599,6 +1609,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1616,6 +1627,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1664,6 +1676,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1675,6 +1688,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1686,6 +1700,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1697,6 +1712,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1767,6 +1783,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1784,6 +1801,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1801,6 +1819,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1818,6 +1837,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1893,6 +1913,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1910,6 +1931,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1927,6 +1949,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1944,6 +1967,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1994,6 +2018,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -2005,6 +2030,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -2031,6 +2057,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -2042,6 +2069,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2492,6 +2520,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2509,6 +2538,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2526,6 +2556,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2543,6 +2574,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -482,6 +482,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -493,6 +494,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1200,6 +1202,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1217,6 +1220,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1464,6 +1468,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1475,6 +1480,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1486,6 +1492,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1497,6 +1504,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1565,6 +1573,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1582,6 +1591,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1599,6 +1609,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1616,6 +1627,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1664,6 +1676,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1675,6 +1688,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1686,6 +1700,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1697,6 +1712,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1767,6 +1783,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1784,6 +1801,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1801,6 +1819,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1818,6 +1837,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1893,6 +1913,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1910,6 +1931,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1927,6 +1949,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1944,6 +1967,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1994,6 +2018,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -2005,6 +2030,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -2031,6 +2057,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -2042,6 +2069,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2492,6 +2520,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2509,6 +2538,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2526,6 +2556,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2543,6 +2574,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -475,6 +475,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -486,6 +487,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1103,6 +1105,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1120,6 +1123,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1367,6 +1371,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1378,6 +1383,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1389,6 +1395,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1400,6 +1407,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1468,6 +1476,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1485,6 +1494,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1502,6 +1512,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1519,6 +1530,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1567,6 +1579,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1578,6 +1591,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1589,6 +1603,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1600,6 +1615,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1670,6 +1686,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1687,6 +1704,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1704,6 +1722,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1721,6 +1740,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1796,6 +1816,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1813,6 +1834,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1830,6 +1852,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1847,6 +1870,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1897,6 +1921,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1908,6 +1933,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1934,6 +1960,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1945,6 +1972,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2362,6 +2390,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2379,6 +2408,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2396,6 +2426,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2413,6 +2444,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -387,6 +387,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -398,6 +399,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1028,6 +1030,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1045,6 +1048,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1292,6 +1296,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1303,6 +1308,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1314,6 +1320,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1325,6 +1332,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1393,6 +1401,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1410,6 +1419,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1427,6 +1437,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1444,6 +1455,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1492,6 +1504,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1503,6 +1516,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1514,6 +1528,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1525,6 +1540,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1595,6 +1611,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1612,6 +1629,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1629,6 +1647,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1646,6 +1665,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1721,6 +1741,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1738,6 +1759,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1755,6 +1777,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1772,6 +1795,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1822,6 +1846,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1833,6 +1858,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1859,6 +1885,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1870,6 +1897,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2113,6 +2141,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2130,6 +2159,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2147,6 +2177,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2164,6 +2195,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -426,6 +426,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -437,6 +438,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1012,6 +1014,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1029,6 +1032,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1276,6 +1280,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1287,6 +1292,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1298,6 +1304,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1309,6 +1316,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1377,6 +1385,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1394,6 +1403,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1411,6 +1421,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1428,6 +1439,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1476,6 +1488,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1487,6 +1500,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1498,6 +1512,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1509,6 +1524,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1579,6 +1595,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1596,6 +1613,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1613,6 +1631,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1630,6 +1649,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1705,6 +1725,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1722,6 +1743,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1739,6 +1761,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1756,6 +1779,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1806,6 +1830,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1817,6 +1842,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1843,6 +1869,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1854,6 +1881,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2222,6 +2250,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2239,6 +2268,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2256,6 +2286,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2273,6 +2304,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*

32
fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -478,6 +478,7 @@ wire pcie_dma_read_desc_valid;
wire pcie_dma_read_desc_ready; wire pcie_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
wire [3:0] pcie_dma_read_desc_status_error;
wire pcie_dma_read_desc_status_valid; wire pcie_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
@ -489,6 +490,7 @@ wire pcie_dma_write_desc_valid;
wire pcie_dma_write_desc_ready; wire pcie_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
wire [3:0] pcie_dma_write_desc_status_error;
wire pcie_dma_write_desc_status_valid; wire pcie_dma_write_desc_status_valid;
wire pcie_dma_enable = 1; wire pcie_dma_enable = 1;
@ -1079,6 +1081,7 @@ dma_if_pcie_us_inst (
* AXI read descriptor status output * AXI read descriptor status output
*/ */
.m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1096,6 +1099,7 @@ dma_if_pcie_us_inst (
* AXI write descriptor status output * AXI write descriptor status output
*/ */
.m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1343,6 +1347,7 @@ wire pcie_ctrl_dma_read_desc_valid;
wire pcie_ctrl_dma_read_desc_ready; wire pcie_ctrl_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_read_desc_status_tag;
wire [3:0] pcie_ctrl_dma_read_desc_status_error;
wire pcie_ctrl_dma_read_desc_status_valid; wire pcie_ctrl_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_ctrl_dma_write_desc_pcie_addr;
@ -1354,6 +1359,7 @@ wire pcie_ctrl_dma_write_desc_valid;
wire pcie_ctrl_dma_write_desc_ready; wire pcie_ctrl_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_ctrl_dma_write_desc_status_tag;
wire [3:0] pcie_ctrl_dma_write_desc_status_error;
wire pcie_ctrl_dma_write_desc_status_valid; wire pcie_ctrl_dma_write_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_read_desc_pcie_addr;
@ -1365,6 +1371,7 @@ wire pcie_data_dma_read_desc_valid;
wire pcie_data_dma_read_desc_ready; wire pcie_data_dma_read_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_read_desc_status_tag;
wire [3:0] pcie_data_dma_read_desc_status_error;
wire pcie_data_dma_read_desc_status_valid; wire pcie_data_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr; wire [PCIE_ADDR_WIDTH-1:0] pcie_data_dma_write_desc_pcie_addr;
@ -1376,6 +1383,7 @@ wire pcie_data_dma_write_desc_valid;
wire pcie_data_dma_write_desc_ready; wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire [3:0] pcie_data_dma_write_desc_status_error;
wire pcie_data_dma_write_desc_status_valid; wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
@ -1444,6 +1452,7 @@ dma_if_mux_inst (
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
/* /*
@ -1461,6 +1470,7 @@ dma_if_mux_inst (
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}), .m_axis_read_desc_status_tag({pcie_data_dma_read_desc_status_tag, pcie_ctrl_dma_read_desc_status_tag}),
.m_axis_read_desc_status_error({pcie_data_dma_read_desc_status_error, pcie_ctrl_dma_read_desc_status_error}),
.m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}), .m_axis_read_desc_status_valid({pcie_data_dma_read_desc_status_valid, pcie_ctrl_dma_read_desc_status_valid}),
/* /*
@ -1478,6 +1488,7 @@ dma_if_mux_inst (
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
/* /*
@ -1495,6 +1506,7 @@ dma_if_mux_inst (
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}), .m_axis_write_desc_status_tag({pcie_data_dma_write_desc_status_tag, pcie_ctrl_dma_write_desc_status_tag}),
.m_axis_write_desc_status_error({pcie_data_dma_write_desc_status_error, pcie_ctrl_dma_write_desc_status_error}),
.m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}), .m_axis_write_desc_status_valid({pcie_data_dma_write_desc_status_valid, pcie_ctrl_dma_write_desc_status_valid}),
/* /*
@ -1543,6 +1555,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1554,6 +1567,7 @@ wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_ctrl_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_ctrl_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_ctrl_dma_write_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_read_desc_pcie_addr;
@ -1565,6 +1579,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_read_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_read_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_read_desc_status_valid;
wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr; wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_data_dma_write_desc_pcie_addr;
@ -1576,6 +1591,7 @@ wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_valid;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_ready;
wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag; wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_data_dma_write_desc_status_tag;
wire [IF_COUNT*4-1:0] if_pcie_data_dma_write_desc_status_error;
wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid; wire [IF_COUNT-1:0] if_pcie_data_dma_write_desc_status_valid;
wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel; wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_ctrl_dma_ram_wr_cmd_sel;
@ -1646,6 +1662,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_ctrl_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_ctrl_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1663,6 +1680,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid),
/* /*
@ -1680,6 +1698,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_ctrl_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_ctrl_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1697,6 +1716,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid),
/* /*
@ -1772,6 +1792,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status input (from DMA interface) * Read descriptor status input (from DMA interface)
*/ */
.s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag), .s_axis_read_desc_status_tag(pcie_data_dma_read_desc_status_tag),
.s_axis_read_desc_status_error(pcie_data_dma_read_desc_status_error),
.s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid), .s_axis_read_desc_status_valid(pcie_data_dma_read_desc_status_valid),
/* /*
@ -1789,6 +1810,7 @@ if (IF_COUNT > 1) begin
* Read descriptor status output * Read descriptor status output
*/ */
.m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag), .m_axis_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(if_pcie_data_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid), .m_axis_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid),
/* /*
@ -1806,6 +1828,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status input (from DMA interface) * Write descriptor status input (from DMA interface)
*/ */
.s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag), .s_axis_write_desc_status_tag(pcie_data_dma_write_desc_status_tag),
.s_axis_write_desc_status_error(pcie_data_dma_write_desc_status_error),
.s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid), .s_axis_write_desc_status_valid(pcie_data_dma_write_desc_status_valid),
/* /*
@ -1823,6 +1846,7 @@ if (IF_COUNT > 1) begin
* Write descriptor status output * Write descriptor status output
*/ */
.m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag), .m_axis_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(if_pcie_data_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid), .m_axis_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid),
/* /*
@ -1873,6 +1897,7 @@ end else begin
assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready; assign if_pcie_ctrl_dma_read_desc_ready = pcie_ctrl_dma_read_desc_ready;
assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag; assign if_pcie_ctrl_dma_read_desc_status_tag = pcie_ctrl_dma_read_desc_status_tag;
assign if_pcie_ctrl_dma_read_desc_status_error = pcie_ctrl_dma_read_desc_status_error;
assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid; assign if_pcie_ctrl_dma_read_desc_status_valid = pcie_ctrl_dma_read_desc_status_valid;
assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr; assign pcie_ctrl_dma_write_desc_pcie_addr = if_pcie_ctrl_dma_write_desc_pcie_addr;
@ -1884,6 +1909,7 @@ end else begin
assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready; assign if_pcie_ctrl_dma_write_desc_ready = pcie_ctrl_dma_write_desc_ready;
assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag; assign if_pcie_ctrl_dma_write_desc_status_tag = pcie_ctrl_dma_write_desc_status_tag;
assign if_pcie_ctrl_dma_write_desc_status_error = pcie_ctrl_dma_write_desc_status_error;
assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid; assign if_pcie_ctrl_dma_write_desc_status_valid = pcie_ctrl_dma_write_desc_status_valid;
assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel; assign if_ctrl_dma_ram_wr_cmd_sel = ctrl_dma_ram_wr_cmd_sel;
@ -1910,6 +1936,7 @@ end else begin
assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready; assign if_pcie_data_dma_read_desc_ready = pcie_data_dma_read_desc_ready;
assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag; assign if_pcie_data_dma_read_desc_status_tag = pcie_data_dma_read_desc_status_tag;
assign if_pcie_data_dma_read_desc_status_error = pcie_data_dma_read_desc_status_error;
assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid; assign if_pcie_data_dma_read_desc_status_valid = pcie_data_dma_read_desc_status_valid;
assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr; assign pcie_data_dma_write_desc_pcie_addr = if_pcie_data_dma_write_desc_pcie_addr;
@ -1921,6 +1948,7 @@ end else begin
assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready; assign if_pcie_data_dma_write_desc_ready = pcie_data_dma_write_desc_ready;
assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag; assign if_pcie_data_dma_write_desc_status_tag = pcie_data_dma_write_desc_status_tag;
assign if_pcie_data_dma_write_desc_status_error = pcie_data_dma_write_desc_status_error;
assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid; assign if_pcie_data_dma_write_desc_status_valid = pcie_data_dma_write_desc_status_valid;
assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel; assign if_data_dma_ram_wr_cmd_sel = data_dma_ram_wr_cmd_sel;
@ -2369,6 +2397,7 @@ generate
* DMA read descriptor status input (control) * DMA read descriptor status input (control)
*/ */
.s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_read_desc_status_tag(if_pcie_ctrl_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_read_desc_status_error(if_pcie_ctrl_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]), .s_axis_ctrl_dma_read_desc_status_valid(if_pcie_ctrl_dma_read_desc_status_valid[n]),
/* /*
@ -2386,6 +2415,7 @@ generate
* DMA write descriptor status input (control) * DMA write descriptor status input (control)
*/ */
.s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_ctrl_dma_write_desc_status_tag(if_pcie_ctrl_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_ctrl_dma_write_desc_status_error(if_pcie_ctrl_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]), .s_axis_ctrl_dma_write_desc_status_valid(if_pcie_ctrl_dma_write_desc_status_valid[n]),
/* /*
@ -2403,6 +2433,7 @@ generate
* DMA read descriptor status input (data) * DMA read descriptor status input (data)
*/ */
.s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_read_desc_status_tag(if_pcie_data_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_read_desc_status_error(if_pcie_data_dma_read_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]), .s_axis_data_dma_read_desc_status_valid(if_pcie_data_dma_read_desc_status_valid[n]),
/* /*
@ -2420,6 +2451,7 @@ generate
* DMA write descriptor status input (data) * DMA write descriptor status input (data)
*/ */
.s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), .s_axis_data_dma_write_desc_status_tag(if_pcie_data_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
.s_axis_data_dma_write_desc_status_error(if_pcie_data_dma_write_desc_status_error[n*4 +: 4]),
.s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]), .s_axis_data_dma_write_desc_status_valid(if_pcie_data_dma_write_desc_status_valid[n]),
/* /*