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Update port and interface modules

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This commit is contained in:
Alex Forencich 2020-04-20 21:25:21 -07:00
parent 7087a595e9
commit e14cfa0a58
2 changed files with 15 additions and 0 deletions
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11
fpga/common/rtl/interface.v
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@ -100,6 +100,8 @@ module interface #
parameter QUEUE_PTR_WIDTH = 16, parameter QUEUE_PTR_WIDTH = 16,
// Queue log size field width // Queue log size field width
parameter LOG_QUEUE_SIZE_WIDTH = 4, parameter LOG_QUEUE_SIZE_WIDTH = 4,
// Log desc block size field width
parameter LOG_BLOCK_SIZE_WIDTH = 2,
// Enable PTP timestamping // Enable PTP timestamping
parameter PTP_TS_ENABLE = 1, parameter PTP_TS_ENABLE = 1,
// PTP timestamp width // PTP timestamp width
@ -591,6 +593,7 @@ wire tx_desc_dequeue_req_ready;
wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_dequeue_resp_queue; wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_dequeue_resp_queue;
wire [QUEUE_PTR_WIDTH-1:0] tx_desc_dequeue_resp_ptr; wire [QUEUE_PTR_WIDTH-1:0] tx_desc_dequeue_resp_ptr;
wire [DMA_ADDR_WIDTH-1:0] tx_desc_dequeue_resp_addr; wire [DMA_ADDR_WIDTH-1:0] tx_desc_dequeue_resp_addr;
wire [LOG_BLOCK_SIZE_WIDTH-1:0] tx_desc_dequeue_resp_block_size;
wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_dequeue_resp_cpl; wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_dequeue_resp_cpl;
wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_desc_dequeue_resp_tag; wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_desc_dequeue_resp_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] tx_desc_dequeue_resp_op_tag; wire [QUEUE_OP_TAG_WIDTH-1:0] tx_desc_dequeue_resp_op_tag;
@ -631,6 +634,7 @@ wire rx_desc_dequeue_req_ready;
wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_resp_queue; wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_resp_queue;
wire [QUEUE_PTR_WIDTH-1:0] rx_desc_dequeue_resp_ptr; wire [QUEUE_PTR_WIDTH-1:0] rx_desc_dequeue_resp_ptr;
wire [DMA_ADDR_WIDTH-1:0] rx_desc_dequeue_resp_addr; wire [DMA_ADDR_WIDTH-1:0] rx_desc_dequeue_resp_addr;
wire [LOG_BLOCK_SIZE_WIDTH-1:0] rx_desc_dequeue_resp_block_size;
wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_resp_cpl; wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_resp_cpl;
wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_desc_dequeue_resp_tag; wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_desc_dequeue_resp_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] rx_desc_dequeue_resp_op_tag; wire [QUEUE_OP_TAG_WIDTH-1:0] rx_desc_dequeue_resp_op_tag;
@ -1011,6 +1015,7 @@ queue_manager #(
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH),
.DESC_SIZE(DESC_SIZE), .DESC_SIZE(DESC_SIZE),
.LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH),
.PIPELINE(TX_QUEUE_PIPELINE), .PIPELINE(TX_QUEUE_PIPELINE),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_TX_QM_ADDR_WIDTH), .AXIL_ADDR_WIDTH(AXIL_TX_QM_ADDR_WIDTH),
@ -1034,6 +1039,7 @@ tx_queue_manager_inst (
.m_axis_dequeue_resp_queue(tx_desc_dequeue_resp_queue), .m_axis_dequeue_resp_queue(tx_desc_dequeue_resp_queue),
.m_axis_dequeue_resp_ptr(tx_desc_dequeue_resp_ptr), .m_axis_dequeue_resp_ptr(tx_desc_dequeue_resp_ptr),
.m_axis_dequeue_resp_addr(tx_desc_dequeue_resp_addr), .m_axis_dequeue_resp_addr(tx_desc_dequeue_resp_addr),
.m_axis_dequeue_resp_block_size(tx_desc_dequeue_resp_block_size),
.m_axis_dequeue_resp_cpl(tx_desc_dequeue_resp_cpl), .m_axis_dequeue_resp_cpl(tx_desc_dequeue_resp_cpl),
.m_axis_dequeue_resp_tag(tx_desc_dequeue_resp_tag), .m_axis_dequeue_resp_tag(tx_desc_dequeue_resp_tag),
.m_axis_dequeue_resp_op_tag(tx_desc_dequeue_resp_op_tag), .m_axis_dequeue_resp_op_tag(tx_desc_dequeue_resp_op_tag),
@ -1178,6 +1184,7 @@ queue_manager #(
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH),
.DESC_SIZE(DESC_SIZE), .DESC_SIZE(DESC_SIZE),
.LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH),
.PIPELINE(RX_QUEUE_PIPELINE), .PIPELINE(RX_QUEUE_PIPELINE),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_RX_QM_ADDR_WIDTH), .AXIL_ADDR_WIDTH(AXIL_RX_QM_ADDR_WIDTH),
@ -1201,6 +1208,7 @@ rx_queue_manager_inst (
.m_axis_dequeue_resp_queue(rx_desc_dequeue_resp_queue), .m_axis_dequeue_resp_queue(rx_desc_dequeue_resp_queue),
.m_axis_dequeue_resp_ptr(rx_desc_dequeue_resp_ptr), .m_axis_dequeue_resp_ptr(rx_desc_dequeue_resp_ptr),
.m_axis_dequeue_resp_addr(rx_desc_dequeue_resp_addr), .m_axis_dequeue_resp_addr(rx_desc_dequeue_resp_addr),
.m_axis_dequeue_resp_block_size(rx_desc_dequeue_resp_block_size),
.m_axis_dequeue_resp_cpl(rx_desc_dequeue_resp_cpl), .m_axis_dequeue_resp_cpl(rx_desc_dequeue_resp_cpl),
.m_axis_dequeue_resp_tag(rx_desc_dequeue_resp_tag), .m_axis_dequeue_resp_tag(rx_desc_dequeue_resp_tag),
.m_axis_dequeue_resp_op_tag(rx_desc_dequeue_resp_op_tag), .m_axis_dequeue_resp_op_tag(rx_desc_dequeue_resp_op_tag),
@ -1464,6 +1472,7 @@ desc_fetch #(
.CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.DESC_SIZE(DESC_SIZE), .DESC_SIZE(DESC_SIZE),
.LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH),
.DESC_TABLE_SIZE(32) .DESC_TABLE_SIZE(32)
) )
desc_fetch_inst ( desc_fetch_inst (
@ -1515,6 +1524,7 @@ desc_fetch_inst (
.s_axis_desc_dequeue_resp_queue({rx_desc_dequeue_resp_queue, tx_desc_dequeue_resp_queue}), .s_axis_desc_dequeue_resp_queue({rx_desc_dequeue_resp_queue, tx_desc_dequeue_resp_queue}),
.s_axis_desc_dequeue_resp_ptr({rx_desc_dequeue_resp_ptr, tx_desc_dequeue_resp_ptr}), .s_axis_desc_dequeue_resp_ptr({rx_desc_dequeue_resp_ptr, tx_desc_dequeue_resp_ptr}),
.s_axis_desc_dequeue_resp_addr({rx_desc_dequeue_resp_addr, tx_desc_dequeue_resp_addr}), .s_axis_desc_dequeue_resp_addr({rx_desc_dequeue_resp_addr, tx_desc_dequeue_resp_addr}),
.s_axis_desc_dequeue_resp_block_size({rx_desc_dequeue_resp_block_size, tx_desc_dequeue_resp_block_size}),
.s_axis_desc_dequeue_resp_cpl({rx_desc_dequeue_resp_cpl, tx_desc_dequeue_resp_cpl}), .s_axis_desc_dequeue_resp_cpl({rx_desc_dequeue_resp_cpl, tx_desc_dequeue_resp_cpl}),
.s_axis_desc_dequeue_resp_tag({rx_desc_dequeue_resp_tag, tx_desc_dequeue_resp_tag}), .s_axis_desc_dequeue_resp_tag({rx_desc_dequeue_resp_tag, tx_desc_dequeue_resp_tag}),
.s_axis_desc_dequeue_resp_op_tag({rx_desc_dequeue_resp_op_tag, tx_desc_dequeue_resp_op_tag}), .s_axis_desc_dequeue_resp_op_tag({rx_desc_dequeue_resp_op_tag, tx_desc_dequeue_resp_op_tag}),
@ -2023,6 +2033,7 @@ generate
.TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1),
.TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER(TX_SCHEDULER),
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),

4
fpga/common/rtl/port.v
View File

@ -74,6 +74,8 @@ module port #
parameter RX_DESC_TABLE_SIZE = 16, parameter RX_DESC_TABLE_SIZE = 16,
// Receive packet table size (number of in-progress packets) // Receive packet table size (number of in-progress packets)
parameter RX_PKT_TABLE_SIZE = 8, parameter RX_PKT_TABLE_SIZE = 8,
// Width of descriptor table field for tracking outstanding DMA operations
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Transmit scheduler type // Transmit scheduler type
parameter TX_SCHEDULER = "RR", parameter TX_SCHEDULER = "RR",
// Scheduler operation table size // Scheduler operation table size
@ -1131,6 +1133,7 @@ tx_engine #(
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), .CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
.PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
.MAX_TX_SIZE(MAX_TX_SIZE), .MAX_TX_SIZE(MAX_TX_SIZE),
.DESC_SIZE(DESC_SIZE), .DESC_SIZE(DESC_SIZE),
@ -1316,6 +1319,7 @@ rx_engine #(
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), .CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
.MAX_RX_SIZE(MAX_RX_SIZE), .MAX_RX_SIZE(MAX_RX_SIZE),
.DESC_SIZE(DESC_SIZE), .DESC_SIZE(DESC_SIZE),
.CPL_SIZE(CPL_SIZE), .CPL_SIZE(CPL_SIZE),