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Fix port widths

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-07-11 23:32:19 -07:00
parent edd1d546d5
commit e15fe3cbc9
1 changed files with 2 additions and 2 deletions
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4
rtl/pcie_s10_if.v
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@ -221,8 +221,8 @@ module pcie_s10_if #
output wire [7:0] bus_num,
output wire [F_COUNT*3-1:0] max_read_request_size,
output wire [F_COUNT*3-1:0] max_payload_size,
output wire [F_COUNT*3-1:0] msix_enable,
output wire [F_COUNT*3-1:0] msix_mask,
output wire [F_COUNT-1:0] msix_enable,
output wire [F_COUNT-1:0] msix_mask,
/*
* MSI request inputs