merged changes in axis

lib/axis/README.md

@@ -42,6 +42,20 @@ Supports power of two depths only.
 Basic frame-based asynchronous FIFO with tkeep signal and parametrizable data
 width and depth.  Supports power of two depths only.
 
+### axis_crosspoint module
+
+Basic crosspoint switch.  tready signal not supported.  Parametrizable data
+width.  
+
+Can be generated with arbitrary port counts with axis_crosspoint.py.
+
+### axis_crosspoint_64 module
+
+Basic crosspoint switch with tkeep.  tready signal not supported.
+Parametrizable data width.  
+
+Can be generated with arbitrary port counts with axis_crosspoint_64.py.
+
 ### axis_fifo module
 
 Basic word-based synchronous FIFO with parametrizable data width and depth.
@@ -68,10 +82,23 @@ Frame joiner with optional tag.  8 bit data path only.
 
 Can be generated with arbitrary port counts with axis_frame_join.py.
 
-### axis_ll_bringe module
+### axis_ll_bridge module
 
 AXI stream to LocalLink bridge.
 
+### axis_mux_N module
+
+Frame-aware AXI stream muliplexer with parametrizable data width.
+
+Can be generated with arbitrary port counts with axis_mux.py.
+
+### axis_mux_64_N module
+
+Frame-aware AXI stream muliplexer with tkeep signal and parametrizable data
+width.
+
+Can be generated with arbitrary port counts with axis_mux_64.py.
+
 ### axis_rate_limit module
 
 Fractional rate limiter, supports word and frame modes.  Inserts wait states
@@ -122,6 +149,10 @@ LocalLink to AXI stream bridge.
     rtl/axis_async_fifo_64.v        : Asynchronous FIFO (64 bit)
     rtl/axis_async_frame_fifo.v     : Asynchronous frame FIFO
     rtl/axis_async_frame_fifo_64.v  : Asynchronous frame FIFO (64 bit)
+    rtl/axis_crosspoint.py          : Crosspoint switch generator
+    rtl/axis_crosspoint_4x4.v       : 4x4 crosspoint switch
+    rtl/axis_crosspoint_64.py       : Crosspoint switch generator (64 bit)
+    rtl/axis_crosspoint_64_4x4.v    : 4x4 crosspoint switch (64 bit)
     rtl/axis_fifo.v                 : Synchronous FIFO
     rtl/axis_fifo_64.v              : Synchronous FIFO (64 bit)
     rtl/axis_frame_fifo.v           : Synchronous frame FIFO
@@ -129,6 +160,10 @@ LocalLink to AXI stream bridge.
     rtl/axis_frame_join.py          : Frame joiner generator
     rtl/axis_frame_join_4.v         : 4 port frame joiner
     rtl/axis_ll_bridge.v            : AXI stream to LocalLink bridge
+    rtl/axis_mux.py                 : Multiplexer generator
+    rtl/axis_mux_4.v                : 4 port multiplexer
+    rtl/axis_mux_64.py              : Multiplexer generator (64 bit)
+    rtl/axis_mux_64_4.v             : 4 port multiplexer (64 bit)
     rtl/axis_rate_limit.v           : Fractional rate limiter
     rtl/axis_rate_limit_64.v        : Fractional rate limiter (64 bit)
     rtl/axis_register.v             : AXI Stream register

lib/axis/rtl/arbiter.v

@@ -0,0 +1,141 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Arbiter module
+ */
+module arbiter #
+(
+    parameter PORTS = 4,
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter TYPE = "PRIORITY",
+    // block type: "NONE", "REQUEST", "ACKNOWLEDGE"
+    parameter BLOCK = "NONE"
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+    
+    input  wire [PORTS-1:0]         request,
+    input  wire [PORTS-1:0]         acknowledge,
+
+    output wire [PORTS-1:0]         grant,
+    output wire                     grant_valid,
+    output wire [$clog2(PORTS)-1:0] grant_encoded
+);
+
+reg [PORTS-1:0] grant_reg = 0, grant_next;
+reg grant_valid_reg = 0, grant_valid_next;
+reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
+
+assign grant_valid = grant_valid_reg;
+assign grant = grant_reg;
+assign grant_encoded = grant_encoded_reg;
+
+wire request_valid;
+wire [$clog2(PORTS)-1:0] request_index;
+wire [PORTS-1:0] request_mask;
+
+priority_encoder #(
+    .WIDTH(PORTS)
+)
+priority_encoder_inst (
+    .input_unencoded(request),
+    .output_valid(request_valid),
+    .output_encoded(request_index),
+    .output_unencoded(request_mask)
+);
+
+reg [PORTS-1:0] mask_reg = 0, mask_next;
+
+wire masked_request_valid;
+wire [$clog2(PORTS)-1:0] masked_request_index;
+wire [PORTS-1:0] masked_request_mask;
+
+priority_encoder #(
+    .WIDTH(PORTS)
+)
+priority_encoder_masked (
+    .input_unencoded(request & mask_reg),
+    .output_valid(masked_request_valid),
+    .output_encoded(masked_request_index),
+    .output_unencoded(masked_request_mask)
+);
+
+always @* begin
+    grant_next = 0;
+    grant_valid_next = 0;
+    grant_encoded_next = 0;
+    mask_next = mask_reg;
+
+    if (BLOCK == "REQUEST" && grant_reg & request) begin
+        // granted request still asserted; hold it
+        grant_valid_next = grant_valid_reg;
+        grant_next = grant_reg;
+        grant_encoded_next = grant_encoded_reg;
+    end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
+        // granted request not yet acknowledged; hold it
+        grant_valid_next = grant_valid_reg;
+        grant_next = grant_reg;
+        grant_encoded_next = grant_encoded_reg;
+    end else if (request_valid) begin
+        if (TYPE == "PRIORITY") begin
+            grant_valid_next = 1;
+            grant_next = request_mask;
+            grant_encoded_next = request_index;
+        end else if (TYPE == "ROUND_ROBIN") begin
+            if (masked_request_valid) begin
+                grant_valid_next = 1;
+                grant_next = masked_request_mask;
+                grant_encoded_next = masked_request_index;
+                mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
+            end else begin
+                grant_valid_next = 1;
+                grant_next = request_mask;
+                grant_encoded_next = request_index;
+                mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
+            end
+        end
+    end
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        grant_reg <= 0;
+        grant_valid_reg <= 0;
+        grant_encoded_reg <= 0;
+        mask_reg <= 0;
+    end else begin
+        grant_reg <= grant_next;
+        grant_valid_reg <= grant_valid_next;
+        grant_encoded_reg <= grant_encoded_next;
+        mask_reg <= mask_next;
+    end
+end
+
+endmodule

lib/axis/rtl/axis_arb_mux.py

@@ -0,0 +1,193 @@
+#!/usr/bin/env python
+"""axis_mux
+
+Generates an arbitrated AXI Stream mux with the specified number of ports
+
+Usage: axis_crosspoint [OPTION]...
+  -?, --help     display this help and exit
+  -p, --ports    specify number of ports
+  -n, --name     specify module name
+  -o, --output   specify output file name
+"""
+
+import io
+import sys
+import getopt
+from math import *
+from jinja2 import Template
+
+class Usage(Exception):
+    def __init__(self, msg):
+        self.msg = msg
+
+def main(argv=None):
+    if argv is None:
+        argv = sys.argv
+    try:
+        try:
+            opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
+        except getopt.error as msg:
+             raise Usage(msg)
+        # more code, unchanged  
+    except Usage as err:
+        print(err.msg, file=sys.stderr)
+        print("for help use --help", file=sys.stderr)
+        return 2
+
+    ports = 4
+    name = None
+    out_name = None
+
+    # process options
+    for o, a in opts:
+        if o in ('-?', '--help'):
+            print(__doc__)
+            sys.exit(0)
+        if o in ('-p', '--ports'):
+            ports = int(a)
+        if o in ('-n', '--name'):
+            name = a
+        if o in ('-o', '--output'):
+            out_name = a
+
+    if name is None:
+        name = "axis_arb_mux_{0}".format(ports)
+
+    if out_name is None:
+        out_name = name + ".v"
+
+    print("Opening file '%s'..." % out_name)
+
+    try:
+        out_file = open(out_name, 'w')
+    except Exception as ex:
+        print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
+        exit(1)
+
+    print("Generating {0} port AXI Stream arbitrated mux {1}...".format(ports, name))
+
+    select_width = ceil(log2(ports))
+
+    t = Template(u"""/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream {{n}} port arbitrated multiplexer
+ */
+module {{name}} #
+(
+    parameter DATA_WIDTH = 8,
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter ARB_TYPE = "PRIORITY"
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI inputs
+     */
+{%- for p in ports %}
+    input  wire [DATA_WIDTH-1:0]  input_{{p}}_axis_tdata,
+    input  wire                   input_{{p}}_axis_tvalid,
+    output wire                   input_{{p}}_axis_tready,
+    input  wire                   input_{{p}}_axis_tlast,
+    input  wire                   input_{{p}}_axis_tuser,
+{% endfor %}
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser
+);
+
+wire [{{n-1}}:0] request;
+wire [{{n-1}}:0] acknowledge;
+wire [{{n-1}}:0] grant;
+wire [{{w-1}}:0] grant_encoded;
+{% for p in ports %}
+assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast;
+assign request[{{p}}] = input_{{p}}_axis_tvalid & ~acknowledge[{{p}}];
+{%- endfor %}
+
+// mux instance
+axis_mux_{{n}} #(
+    .DATA_WIDTH(DATA_WIDTH)
+)
+mux_inst (
+    .clk(clk),
+    .rst(rst),
+{%- for p in ports %}
+    .input_{{p}}_axis_tdata(input_{{p}}_axis_tdata),
+    .input_{{p}}_axis_tvalid(input_{{p}}_axis_tvalid & grant[{{p}}]),
+    .input_{{p}}_axis_tready(input_{{p}}_axis_tready),
+    .input_{{p}}_axis_tlast(input_{{p}}_axis_tlast),
+    .input_{{p}}_axis_tuser(input_{{p}}_axis_tuser),
+{%- endfor %}
+    .output_axis_tdata(output_axis_tdata),
+    .output_axis_tvalid(output_axis_tvalid),
+    .output_axis_tready(output_axis_tready),
+    .output_axis_tlast(output_axis_tlast),
+    .output_axis_tuser(output_axis_tuser),
+    .select(grant_encoded)
+);
+
+// arbiter instance
+arbiter #(
+    .PORTS({{n}}),
+    .TYPE(ARB_TYPE),
+    .BLOCK("ACKNOWLEDGE")
+)
+arb_inst (
+    .clk(clk),
+    .rst(rst),
+    .request(request),
+    .acknowledge(acknowledge),
+    .grant(grant),
+    .grant_encoded(grant_encoded)
+);
+
+endmodule
+
+""")
+    
+    out_file.write(t.render(
+        n=ports,
+        w=select_width,
+        name=name,
+        ports=range(ports)
+    ))
+    
+    print("Done")
+
+if __name__ == "__main__":
+    sys.exit(main())
+

lib/axis/rtl/axis_arb_mux_4.v

@@ -0,0 +1,143 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream 4 port arbitrated multiplexer
+ */
+module axis_arb_mux_4 #
+(
+    parameter DATA_WIDTH = 8,
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter ARB_TYPE = "PRIORITY"
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI inputs
+     */
+    input  wire [DATA_WIDTH-1:0]  input_0_axis_tdata,
+    input  wire                   input_0_axis_tvalid,
+    output wire                   input_0_axis_tready,
+    input  wire                   input_0_axis_tlast,
+    input  wire                   input_0_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_1_axis_tdata,
+    input  wire                   input_1_axis_tvalid,
+    output wire                   input_1_axis_tready,
+    input  wire                   input_1_axis_tlast,
+    input  wire                   input_1_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_2_axis_tdata,
+    input  wire                   input_2_axis_tvalid,
+    output wire                   input_2_axis_tready,
+    input  wire                   input_2_axis_tlast,
+    input  wire                   input_2_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_3_axis_tdata,
+    input  wire                   input_3_axis_tvalid,
+    output wire                   input_3_axis_tready,
+    input  wire                   input_3_axis_tlast,
+    input  wire                   input_3_axis_tuser,
+
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser
+);
+
+wire [3:0] request;
+wire [3:0] acknowledge;
+wire [3:0] grant;
+wire [1:0] grant_encoded;
+
+assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
+assign request[0] = input_0_axis_tvalid & ~acknowledge[0];
+assign acknowledge[1] = input_1_axis_tvalid & input_1_axis_tready & input_1_axis_tlast;
+assign request[1] = input_1_axis_tvalid & ~acknowledge[1];
+assign acknowledge[2] = input_2_axis_tvalid & input_2_axis_tready & input_2_axis_tlast;
+assign request[2] = input_2_axis_tvalid & ~acknowledge[2];
+assign acknowledge[3] = input_3_axis_tvalid & input_3_axis_tready & input_3_axis_tlast;
+assign request[3] = input_3_axis_tvalid & ~acknowledge[3];
+
+// mux instance
+axis_mux_4 #(
+    .DATA_WIDTH(DATA_WIDTH)
+)
+mux_inst (
+    .clk(clk),
+    .rst(rst),
+    .input_0_axis_tdata(input_0_axis_tdata),
+    .input_0_axis_tvalid(input_0_axis_tvalid & grant[0]),
+    .input_0_axis_tready(input_0_axis_tready),
+    .input_0_axis_tlast(input_0_axis_tlast),
+    .input_0_axis_tuser(input_0_axis_tuser),
+    .input_1_axis_tdata(input_1_axis_tdata),
+    .input_1_axis_tvalid(input_1_axis_tvalid & grant[1]),
+    .input_1_axis_tready(input_1_axis_tready),
+    .input_1_axis_tlast(input_1_axis_tlast),
+    .input_1_axis_tuser(input_1_axis_tuser),
+    .input_2_axis_tdata(input_2_axis_tdata),
+    .input_2_axis_tvalid(input_2_axis_tvalid & grant[2]),
+    .input_2_axis_tready(input_2_axis_tready),
+    .input_2_axis_tlast(input_2_axis_tlast),
+    .input_2_axis_tuser(input_2_axis_tuser),
+    .input_3_axis_tdata(input_3_axis_tdata),
+    .input_3_axis_tvalid(input_3_axis_tvalid & grant[3]),
+    .input_3_axis_tready(input_3_axis_tready),
+    .input_3_axis_tlast(input_3_axis_tlast),
+    .input_3_axis_tuser(input_3_axis_tuser),
+    .output_axis_tdata(output_axis_tdata),
+    .output_axis_tvalid(output_axis_tvalid),
+    .output_axis_tready(output_axis_tready),
+    .output_axis_tlast(output_axis_tlast),
+    .output_axis_tuser(output_axis_tuser),
+    .select(grant_encoded)
+);
+
+// arbiter instance
+arbiter #(
+    .PORTS(4),
+    .TYPE(ARB_TYPE),
+    .BLOCK("ACKNOWLEDGE")
+)
+arb_inst (
+    .clk(clk),
+    .rst(rst),
+    .request(request),
+    .acknowledge(acknowledge),
+    .grant(grant),
+    .grant_encoded(grant_encoded)
+);
+
+endmodule

lib/axis/rtl/axis_arb_mux_64.py

@@ -0,0 +1,198 @@
+#!/usr/bin/env python
+"""axis_mux
+
+Generates an arbitrated AXI Stream mux with the specified number of ports
+
+Usage: axis_crosspoint [OPTION]...
+  -?, --help     display this help and exit
+  -p, --ports    specify number of ports
+  -n, --name     specify module name
+  -o, --output   specify output file name
+"""
+
+import io
+import sys
+import getopt
+from math import *
+from jinja2 import Template
+
+class Usage(Exception):
+    def __init__(self, msg):
+        self.msg = msg
+
+def main(argv=None):
+    if argv is None:
+        argv = sys.argv
+    try:
+        try:
+            opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
+        except getopt.error as msg:
+             raise Usage(msg)
+        # more code, unchanged  
+    except Usage as err:
+        print(err.msg, file=sys.stderr)
+        print("for help use --help", file=sys.stderr)
+        return 2
+
+    ports = 4
+    name = None
+    out_name = None
+
+    # process options
+    for o, a in opts:
+        if o in ('-?', '--help'):
+            print(__doc__)
+            sys.exit(0)
+        if o in ('-p', '--ports'):
+            ports = int(a)
+        if o in ('-n', '--name'):
+            name = a
+        if o in ('-o', '--output'):
+            out_name = a
+
+    if name is None:
+        name = "axis_arb_mux_64_{0}".format(ports)
+
+    if out_name is None:
+        out_name = name + ".v"
+
+    print("Opening file '%s'..." % out_name)
+
+    try:
+        out_file = open(out_name, 'w')
+    except Exception as ex:
+        print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
+        exit(1)
+
+    print("Generating {0} port AXI Stream arbitrated mux {1}...".format(ports, name))
+
+    select_width = ceil(log2(ports))
+
+    t = Template(u"""/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream {{n}} port arbitrated multiplexer (64 bit datapath)
+ */
+module {{name}} #
+(
+    parameter DATA_WIDTH = 64,
+    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter ARB_TYPE = "PRIORITY"
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI inputs
+     */
+{%- for p in ports %}
+    input  wire [DATA_WIDTH-1:0]  input_{{p}}_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_{{p}}_axis_tkeep,
+    input  wire                   input_{{p}}_axis_tvalid,
+    output wire                   input_{{p}}_axis_tready,
+    input  wire                   input_{{p}}_axis_tlast,
+    input  wire                   input_{{p}}_axis_tuser,
+{% endfor %}
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_axis_tkeep,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser
+);
+
+wire [{{n-1}}:0] request;
+wire [{{n-1}}:0] acknowledge;
+wire [{{n-1}}:0] grant;
+wire [{{w-1}}:0] grant_encoded;
+{% for p in ports %}
+assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast;
+assign request[{{p}}] = input_{{p}}_axis_tvalid & ~acknowledge[{{p}}];
+{%- endfor %}
+
+// mux instance
+axis_mux_64_{{n}} #(
+    .DATA_WIDTH(DATA_WIDTH)
+)
+mux_inst (
+    .clk(clk),
+    .rst(rst),
+{%- for p in ports %}
+    .input_{{p}}_axis_tdata(input_{{p}}_axis_tdata),
+    .input_{{p}}_axis_tkeep(input_{{p}}_axis_tkeep),
+    .input_{{p}}_axis_tvalid(input_{{p}}_axis_tvalid & grant[{{p}}]),
+    .input_{{p}}_axis_tready(input_{{p}}_axis_tready),
+    .input_{{p}}_axis_tlast(input_{{p}}_axis_tlast),
+    .input_{{p}}_axis_tuser(input_{{p}}_axis_tuser),
+{%- endfor %}
+    .output_axis_tdata(output_axis_tdata),
+    .output_axis_tkeep(output_axis_tkeep),
+    .output_axis_tvalid(output_axis_tvalid),
+    .output_axis_tready(output_axis_tready),
+    .output_axis_tlast(output_axis_tlast),
+    .output_axis_tuser(output_axis_tuser),
+    .select(grant_encoded)
+);
+
+// arbiter instance
+arbiter #(
+    .PORTS({{n}}),
+    .TYPE(ARB_TYPE),
+    .BLOCK("ACKNOWLEDGE")
+)
+arb_inst (
+    .clk(clk),
+    .rst(rst),
+    .request(request),
+    .acknowledge(acknowledge),
+    .grant(grant),
+    .grant_encoded(grant_encoded)
+);
+
+endmodule
+
+""")
+    
+    out_file.write(t.render(
+        n=ports,
+        w=select_width,
+        name=name,
+        ports=range(ports)
+    ))
+    
+    print("Done")
+
+if __name__ == "__main__":
+    sys.exit(main())
+

lib/axis/rtl/axis_arb_mux_64_4.v

@@ -0,0 +1,154 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream 4 port arbitrated multiplexer (64 bit datapath)
+ */
+module axis_arb_mux_64_4 #
+(
+    parameter DATA_WIDTH = 64,
+    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter ARB_TYPE = "PRIORITY"
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI inputs
+     */
+    input  wire [DATA_WIDTH-1:0]  input_0_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_0_axis_tkeep,
+    input  wire                   input_0_axis_tvalid,
+    output wire                   input_0_axis_tready,
+    input  wire                   input_0_axis_tlast,
+    input  wire                   input_0_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_1_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_1_axis_tkeep,
+    input  wire                   input_1_axis_tvalid,
+    output wire                   input_1_axis_tready,
+    input  wire                   input_1_axis_tlast,
+    input  wire                   input_1_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_2_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_2_axis_tkeep,
+    input  wire                   input_2_axis_tvalid,
+    output wire                   input_2_axis_tready,
+    input  wire                   input_2_axis_tlast,
+    input  wire                   input_2_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_3_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_3_axis_tkeep,
+    input  wire                   input_3_axis_tvalid,
+    output wire                   input_3_axis_tready,
+    input  wire                   input_3_axis_tlast,
+    input  wire                   input_3_axis_tuser,
+
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_axis_tkeep,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser
+);
+
+wire [3:0] request;
+wire [3:0] acknowledge;
+wire [3:0] grant;
+wire [1:0] grant_encoded;
+
+assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
+assign request[0] = input_0_axis_tvalid & ~acknowledge[0];
+assign acknowledge[1] = input_1_axis_tvalid & input_1_axis_tready & input_1_axis_tlast;
+assign request[1] = input_1_axis_tvalid & ~acknowledge[1];
+assign acknowledge[2] = input_2_axis_tvalid & input_2_axis_tready & input_2_axis_tlast;
+assign request[2] = input_2_axis_tvalid & ~acknowledge[2];
+assign acknowledge[3] = input_3_axis_tvalid & input_3_axis_tready & input_3_axis_tlast;
+assign request[3] = input_3_axis_tvalid & ~acknowledge[3];
+
+// mux instance
+axis_mux_64_4 #(
+    .DATA_WIDTH(DATA_WIDTH)
+)
+mux_inst (
+    .clk(clk),
+    .rst(rst),
+    .input_0_axis_tdata(input_0_axis_tdata),
+    .input_0_axis_tkeep(input_0_axis_tkeep),
+    .input_0_axis_tvalid(input_0_axis_tvalid & grant[0]),
+    .input_0_axis_tready(input_0_axis_tready),
+    .input_0_axis_tlast(input_0_axis_tlast),
+    .input_0_axis_tuser(input_0_axis_tuser),
+    .input_1_axis_tdata(input_1_axis_tdata),
+    .input_1_axis_tkeep(input_1_axis_tkeep),
+    .input_1_axis_tvalid(input_1_axis_tvalid & grant[1]),
+    .input_1_axis_tready(input_1_axis_tready),
+    .input_1_axis_tlast(input_1_axis_tlast),
+    .input_1_axis_tuser(input_1_axis_tuser),
+    .input_2_axis_tdata(input_2_axis_tdata),
+    .input_2_axis_tkeep(input_2_axis_tkeep),
+    .input_2_axis_tvalid(input_2_axis_tvalid & grant[2]),
+    .input_2_axis_tready(input_2_axis_tready),
+    .input_2_axis_tlast(input_2_axis_tlast),
+    .input_2_axis_tuser(input_2_axis_tuser),
+    .input_3_axis_tdata(input_3_axis_tdata),
+    .input_3_axis_tkeep(input_3_axis_tkeep),
+    .input_3_axis_tvalid(input_3_axis_tvalid & grant[3]),
+    .input_3_axis_tready(input_3_axis_tready),
+    .input_3_axis_tlast(input_3_axis_tlast),
+    .input_3_axis_tuser(input_3_axis_tuser),
+    .output_axis_tdata(output_axis_tdata),
+    .output_axis_tkeep(output_axis_tkeep),
+    .output_axis_tvalid(output_axis_tvalid),
+    .output_axis_tready(output_axis_tready),
+    .output_axis_tlast(output_axis_tlast),
+    .output_axis_tuser(output_axis_tuser),
+    .select(grant_encoded)
+);
+
+// arbiter instance
+arbiter #(
+    .PORTS(4),
+    .TYPE(ARB_TYPE),
+    .BLOCK("ACKNOWLEDGE")
+)
+arb_inst (
+    .clk(clk),
+    .rst(rst),
+    .request(request),
+    .acknowledge(acknowledge),
+    .grant(grant),
+    .grant_encoded(grant_encoded)
+);
+
+endmodule

lib/axis/rtl/axis_crosspoint.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python
 """axis_crosspoint
 
-Generates an AXI Stream crosspoint switch with a specific number of ports
+Generates an AXI Stream crosspoint switch with the specified number of ports
 
 Usage: axis_crosspoint [OPTION]...
   -?, --help     display this help and exit
@@ -106,29 +106,29 @@ module {{name}} #
 (
     input  wire        clk,
     input  wire        rst,
-    
+
     /*
      * AXI Stream inputs
      */
-    {%- for p in ports %}
+{%- for p in ports %}
     input  wire [DATA_WIDTH-1:0]  input_{{p}}_axis_tdata,
     input  wire                   input_{{p}}_axis_tvalid,
     input  wire                   input_{{p}}_axis_tlast,
-    {% endfor %}
+{% endfor %}
     /*
      * AXI Stream outputs
      */
-    {%- for p in ports %}
+{%- for p in ports %}
     output wire [DATA_WIDTH-1:0]  output_{{p}}_axis_tdata,
     output wire                   output_{{p}}_axis_tvalid,
     output wire                   output_{{p}}_axis_tlast,
-    {% endfor %}
+{% endfor %}
     /*
      * Control
      */
-    {%- for p in ports %}
+{%- for p in ports %}
     input  wire [{{w-1}}:0]             output_{{p}}_select{% if not loop.last %},{% endif %}
-    {%- endfor %}
+{%- endfor %}
 );
 {% for p in ports %}
 reg [DATA_WIDTH-1:0]  input_{{p}}_axis_tdata_reg = 0;
@@ -153,38 +153,38 @@ assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
 
 always @(posedge clk or posedge rst) begin
     if (rst) begin
-        {%- for p in ports %}
+{%- for p in ports %}
         output_{{p}}_select_reg <= 0;
-        {%- endfor %}
-        {% for p in ports %}
+{%- endfor %}
+{% for p in ports %}
         input_{{p}}_axis_tvalid_reg <= 0;
         input_{{p}}_axis_tlast_reg <= 0;
-        {%- endfor %}
-        {% for p in ports %}
+{%- endfor %}
+{% for p in ports %}
         output_{{p}}_axis_tvalid_reg <= 0;
         output_{{p}}_axis_tlast_reg <= 0;
-        {%- endfor %}
+{%- endfor %}
     end else begin
-        {%- for p in ports %}
+{%- for p in ports %}
         input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
         input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid;
         input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
-        {% endfor %}
-        {%- for p in ports %}
+{% endfor %}
+{%- for p in ports %}
         output_{{p}}_select_reg <= output_{{p}}_select;
-        {%- endfor %}
-        {%- for p in ports %}
-        
+{%- endfor %}
+{%- for p in ports %}
+
         case (output_{{p}}_select_reg)
-            {%- for q in ports %}
+{%- for q in ports %}
             {{w}}'d{{q}}: begin
                 output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
                 output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg;
                 output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
             end
-            {%- endfor %}
+{%- endfor %}
         endcase
-        {%- endfor %}
+{%- endfor %}
     end
 end
 

lib/axis/rtl/axis_crosspoint_4x4.v

@@ -36,45 +36,45 @@ module axis_crosspoint_4x4 #
 (
     input  wire        clk,
     input  wire        rst,
-    
+
     /*
      * AXI Stream inputs
      */
     input  wire [DATA_WIDTH-1:0]  input_0_axis_tdata,
     input  wire                   input_0_axis_tvalid,
     input  wire                   input_0_axis_tlast,
-    
+
     input  wire [DATA_WIDTH-1:0]  input_1_axis_tdata,
     input  wire                   input_1_axis_tvalid,
     input  wire                   input_1_axis_tlast,
-    
+
     input  wire [DATA_WIDTH-1:0]  input_2_axis_tdata,
     input  wire                   input_2_axis_tvalid,
     input  wire                   input_2_axis_tlast,
-    
+
     input  wire [DATA_WIDTH-1:0]  input_3_axis_tdata,
     input  wire                   input_3_axis_tvalid,
     input  wire                   input_3_axis_tlast,
-    
+
     /*
      * AXI Stream outputs
      */
     output wire [DATA_WIDTH-1:0]  output_0_axis_tdata,
     output wire                   output_0_axis_tvalid,
     output wire                   output_0_axis_tlast,
-    
+
     output wire [DATA_WIDTH-1:0]  output_1_axis_tdata,
     output wire                   output_1_axis_tvalid,
     output wire                   output_1_axis_tlast,
-    
+
     output wire [DATA_WIDTH-1:0]  output_2_axis_tdata,
     output wire                   output_2_axis_tvalid,
     output wire                   output_2_axis_tlast,
-    
+
     output wire [DATA_WIDTH-1:0]  output_3_axis_tdata,
     output wire                   output_3_axis_tvalid,
     output wire                   output_3_axis_tlast,
-    
+
     /*
      * Control
      */
@@ -144,7 +144,7 @@ always @(posedge clk or posedge rst) begin
         output_1_select_reg <= 0;
         output_2_select_reg <= 0;
         output_3_select_reg <= 0;
-        
+
         input_0_axis_tvalid_reg <= 0;
         input_0_axis_tlast_reg <= 0;
         input_1_axis_tvalid_reg <= 0;
@@ -153,7 +153,7 @@ always @(posedge clk or posedge rst) begin
         input_2_axis_tlast_reg <= 0;
         input_3_axis_tvalid_reg <= 0;
         input_3_axis_tlast_reg <= 0;
-        
+
         output_0_axis_tvalid_reg <= 0;
         output_0_axis_tlast_reg <= 0;
         output_1_axis_tvalid_reg <= 0;
@@ -166,24 +166,24 @@ always @(posedge clk or posedge rst) begin
         input_0_axis_tdata_reg <= input_0_axis_tdata;
         input_0_axis_tvalid_reg <= input_0_axis_tvalid;
         input_0_axis_tlast_reg <= input_0_axis_tlast;
-        
+
         input_1_axis_tdata_reg <= input_1_axis_tdata;
         input_1_axis_tvalid_reg <= input_1_axis_tvalid;
         input_1_axis_tlast_reg <= input_1_axis_tlast;
-        
+
         input_2_axis_tdata_reg <= input_2_axis_tdata;
         input_2_axis_tvalid_reg <= input_2_axis_tvalid;
         input_2_axis_tlast_reg <= input_2_axis_tlast;
-        
+
         input_3_axis_tdata_reg <= input_3_axis_tdata;
         input_3_axis_tvalid_reg <= input_3_axis_tvalid;
         input_3_axis_tlast_reg <= input_3_axis_tlast;
-        
+
         output_0_select_reg <= output_0_select;
         output_1_select_reg <= output_1_select;
         output_2_select_reg <= output_2_select;
         output_3_select_reg <= output_3_select;
-        
+
         case (output_0_select_reg)
             2'd0: begin
                 output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
@@ -206,7 +206,7 @@ always @(posedge clk or posedge rst) begin
                 output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
             end
         endcase
-        
+
         case (output_1_select_reg)
             2'd0: begin
                 output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
@@ -229,7 +229,7 @@ always @(posedge clk or posedge rst) begin
                 output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
             end
         endcase
-        
+
         case (output_2_select_reg)
             2'd0: begin
                 output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
@@ -252,7 +252,7 @@ always @(posedge clk or posedge rst) begin
                 output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
             end
         endcase
-        
+
         case (output_3_select_reg)
             2'd0: begin
                 output_3_axis_tdata_reg <= input_0_axis_tdata_reg;

lib/axis/rtl/axis_crosspoint_64.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python
 """axis_crosspoint_64_64
 
-Generates an AXI Stream crosspoint switch with a specific number of ports
+Generates an AXI Stream crosspoint switch with the specified number of ports
 
 Usage: axis_crosspoint_64 [OPTION]...
   -?, --help     display this help and exit
@@ -107,31 +107,31 @@ module {{name}} #
 (
     input  wire        clk,
     input  wire        rst,
-    
+
     /*
      * AXI Stream inputs
      */
-    {%- for p in ports %}
+{%- for p in ports %}
     input  wire [DATA_WIDTH-1:0]  input_{{p}}_axis_tdata,
     input  wire [KEEP_WIDTH-1:0]  input_{{p}}_axis_tkeep,
     input  wire                   input_{{p}}_axis_tvalid,
     input  wire                   input_{{p}}_axis_tlast,
-    {% endfor %}
+{% endfor %}
     /*
      * AXI Stream outputs
      */
-    {%- for p in ports %}
+{%- for p in ports %}
     output wire [DATA_WIDTH-1:0]  output_{{p}}_axis_tdata,
     output wire [KEEP_WIDTH-1:0]  output_{{p}}_axis_tkeep,
     output wire                   output_{{p}}_axis_tvalid,
     output wire                   output_{{p}}_axis_tlast,
-    {% endfor %}
+{% endfor %}
     /*
      * Control
      */
-    {%- for p in ports %}
+{%- for p in ports %}
     input  wire [{{w-1}}:0]             output_{{p}}_select{% if not loop.last %},{% endif %}
-    {%- endfor %}
+{%- endfor %}
 );
 {% for p in ports %}
 reg [DATA_WIDTH-1:0]  input_{{p}}_axis_tdata_reg = 0;
@@ -159,40 +159,40 @@ assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
 
 always @(posedge clk or posedge rst) begin
     if (rst) begin
-        {%- for p in ports %}
+{%- for p in ports %}
         output_{{p}}_select_reg <= 0;
-        {%- endfor %}
-        {% for p in ports %}
+{%- endfor %}
+{% for p in ports %}
         input_{{p}}_axis_tvalid_reg <= 0;
         input_{{p}}_axis_tlast_reg <= 0;
-        {%- endfor %}
-        {% for p in ports %}
+{%- endfor %}
+{% for p in ports %}
         output_{{p}}_axis_tvalid_reg <= 0;
         output_{{p}}_axis_tlast_reg <= 0;
-        {%- endfor %}
+{%- endfor %}
     end else begin
-        {%- for p in ports %}
+{%- for p in ports %}
         input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
         input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep;
         input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid;
         input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
-        {% endfor %}
-        {%- for p in ports %}
+{% endfor %}
+{%- for p in ports %}
         output_{{p}}_select_reg <= output_{{p}}_select;
-        {%- endfor %}
-        {%- for p in ports %}
-        
+{%- endfor %}
+{%- for p in ports %}
+
         case (output_{{p}}_select_reg)
-            {%- for q in ports %}
+{%- for q in ports %}
             {{w}}'d{{q}}: begin
                 output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
                 output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg;
                 output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg;
                 output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
             end
-            {%- endfor %}
+{%- endfor %}
         endcase
-        {%- endfor %}
+{%- endfor %}
     end
 end
 

lib/axis/rtl/axis_crosspoint_64_4x4.v

@@ -37,7 +37,7 @@ module axis_crosspoint_64_4x4 #
 (
     input  wire        clk,
     input  wire        rst,
-    
+
     /*
      * AXI Stream inputs
      */
@@ -45,22 +45,22 @@ module axis_crosspoint_64_4x4 #
     input  wire [KEEP_WIDTH-1:0]  input_0_axis_tkeep,
     input  wire                   input_0_axis_tvalid,
     input  wire                   input_0_axis_tlast,
-    
+
     input  wire [DATA_WIDTH-1:0]  input_1_axis_tdata,
     input  wire [KEEP_WIDTH-1:0]  input_1_axis_tkeep,
     input  wire                   input_1_axis_tvalid,
     input  wire                   input_1_axis_tlast,
-    
+
     input  wire [DATA_WIDTH-1:0]  input_2_axis_tdata,
     input  wire [KEEP_WIDTH-1:0]  input_2_axis_tkeep,
     input  wire                   input_2_axis_tvalid,
     input  wire                   input_2_axis_tlast,
-    
+
     input  wire [DATA_WIDTH-1:0]  input_3_axis_tdata,
     input  wire [KEEP_WIDTH-1:0]  input_3_axis_tkeep,
     input  wire                   input_3_axis_tvalid,
     input  wire                   input_3_axis_tlast,
-    
+
     /*
      * AXI Stream outputs
      */
@@ -68,22 +68,22 @@ module axis_crosspoint_64_4x4 #
     output wire [KEEP_WIDTH-1:0]  output_0_axis_tkeep,
     output wire                   output_0_axis_tvalid,
     output wire                   output_0_axis_tlast,
-    
+
     output wire [DATA_WIDTH-1:0]  output_1_axis_tdata,
     output wire [KEEP_WIDTH-1:0]  output_1_axis_tkeep,
     output wire                   output_1_axis_tvalid,
     output wire                   output_1_axis_tlast,
-    
+
     output wire [DATA_WIDTH-1:0]  output_2_axis_tdata,
     output wire [KEEP_WIDTH-1:0]  output_2_axis_tkeep,
     output wire                   output_2_axis_tvalid,
     output wire                   output_2_axis_tlast,
-    
+
     output wire [DATA_WIDTH-1:0]  output_3_axis_tdata,
     output wire [KEEP_WIDTH-1:0]  output_3_axis_tkeep,
     output wire                   output_3_axis_tvalid,
     output wire                   output_3_axis_tlast,
-    
+
     /*
      * Control
      */
@@ -165,7 +165,7 @@ always @(posedge clk or posedge rst) begin
         output_1_select_reg <= 0;
         output_2_select_reg <= 0;
         output_3_select_reg <= 0;
-        
+
         input_0_axis_tvalid_reg <= 0;
         input_0_axis_tlast_reg <= 0;
         input_1_axis_tvalid_reg <= 0;
@@ -174,7 +174,7 @@ always @(posedge clk or posedge rst) begin
         input_2_axis_tlast_reg <= 0;
         input_3_axis_tvalid_reg <= 0;
         input_3_axis_tlast_reg <= 0;
-        
+
         output_0_axis_tvalid_reg <= 0;
         output_0_axis_tlast_reg <= 0;
         output_1_axis_tvalid_reg <= 0;
@@ -188,27 +188,27 @@ always @(posedge clk or posedge rst) begin
         input_0_axis_tkeep_reg <= input_0_axis_tkeep;
         input_0_axis_tvalid_reg <= input_0_axis_tvalid;
         input_0_axis_tlast_reg <= input_0_axis_tlast;
-        
+
         input_1_axis_tdata_reg <= input_1_axis_tdata;
         input_1_axis_tkeep_reg <= input_1_axis_tkeep;
         input_1_axis_tvalid_reg <= input_1_axis_tvalid;
         input_1_axis_tlast_reg <= input_1_axis_tlast;
-        
+
         input_2_axis_tdata_reg <= input_2_axis_tdata;
         input_2_axis_tkeep_reg <= input_2_axis_tkeep;
         input_2_axis_tvalid_reg <= input_2_axis_tvalid;
         input_2_axis_tlast_reg <= input_2_axis_tlast;
-        
+
         input_3_axis_tdata_reg <= input_3_axis_tdata;
         input_3_axis_tkeep_reg <= input_3_axis_tkeep;
         input_3_axis_tvalid_reg <= input_3_axis_tvalid;
         input_3_axis_tlast_reg <= input_3_axis_tlast;
-        
+
         output_0_select_reg <= output_0_select;
         output_1_select_reg <= output_1_select;
         output_2_select_reg <= output_2_select;
         output_3_select_reg <= output_3_select;
-        
+
         case (output_0_select_reg)
             2'd0: begin
                 output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
@@ -235,7 +235,7 @@ always @(posedge clk or posedge rst) begin
                 output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
             end
         endcase
-        
+
         case (output_1_select_reg)
             2'd0: begin
                 output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
@@ -262,7 +262,7 @@ always @(posedge clk or posedge rst) begin
                 output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
             end
         endcase
-        
+
         case (output_2_select_reg)
             2'd0: begin
                 output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
@@ -289,7 +289,7 @@ always @(posedge clk or posedge rst) begin
                 output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
             end
         endcase
-        
+
         case (output_3_select_reg)
             2'd0: begin
                 output_3_axis_tdata_reg <= input_0_axis_tdata_reg;

lib/axis/rtl/axis_demux.py

@@ -0,0 +1,290 @@
+#!/usr/bin/env python
+"""axis_mux
+
+Generates an AXI Stream demux with the specified number of ports
+
+Usage: axis_crosspoint [OPTION]...
+  -?, --help     display this help and exit
+  -p, --ports    specify number of ports
+  -n, --name     specify module name
+  -o, --output   specify output file name
+"""
+
+import io
+import sys
+import getopt
+from math import *
+from jinja2 import Template
+
+class Usage(Exception):
+    def __init__(self, msg):
+        self.msg = msg
+
+def main(argv=None):
+    if argv is None:
+        argv = sys.argv
+    try:
+        try:
+            opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
+        except getopt.error as msg:
+             raise Usage(msg)
+        # more code, unchanged  
+    except Usage as err:
+        print(err.msg, file=sys.stderr)
+        print("for help use --help", file=sys.stderr)
+        return 2
+
+    ports = 4
+    name = None
+    out_name = None
+
+    # process options
+    for o, a in opts:
+        if o in ('-?', '--help'):
+            print(__doc__)
+            sys.exit(0)
+        if o in ('-p', '--ports'):
+            ports = int(a)
+        if o in ('-n', '--name'):
+            name = a
+        if o in ('-o', '--output'):
+            out_name = a
+
+    if name is None:
+        name = "axis_demux_{0}".format(ports)
+
+    if out_name is None:
+        out_name = name + ".v"
+
+    print("Opening file '%s'..." % out_name)
+
+    try:
+        out_file = open(out_name, 'w')
+    except Exception as ex:
+        print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
+        exit(1)
+
+    print("Generating {0} port AXI Stream demux {1}...".format(ports, name))
+
+    select_width = ceil(log2(ports))
+
+    t = Template(u"""/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream {{n}} port demultiplexer
+ */
+module {{name}} #
+(
+    parameter DATA_WIDTH = 8
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI input
+     */
+    input  wire [DATA_WIDTH-1:0]  input_axis_tdata,
+    input  wire                   input_axis_tvalid,
+    output wire                   input_axis_tready,
+    input  wire                   input_axis_tlast,
+    input  wire                   input_axis_tuser,
+    
+    /*
+     * AXI outputs
+     */
+{%- for p in ports %}
+    output wire [DATA_WIDTH-1:0]  output_{{p}}_axis_tdata,
+    output wire                   output_{{p}}_axis_tvalid,
+    input  wire                   output_{{p}}_axis_tready,
+    output wire                   output_{{p}}_axis_tlast,
+    output wire                   output_{{p}}_axis_tuser,
+{% endfor %}
+    /*
+     * Control
+     */
+    input  wire [{{w-1}}:0]             select
+);
+
+// // internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
+reg [{{w-1}}:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_axis_tready_reg = 0, input_axis_tready_next;
+assign input_axis_tready = input_axis_tready_reg;
+
+// mux for output control signals
+reg current_output_tready;
+reg current_output_tvalid;
+always @* begin
+    case (select_reg)
+{%- for p in ports %}
+        {{w}}'d{{p}}: begin
+            current_output_tvalid = output_{{p}}_axis_tvalid;
+            current_output_tready = output_{{p}}_axis_tready;
+        end
+{%- endfor %}
+    endcase
+end
+
+always @* begin
+    select_next = select_reg;
+    frame_next = frame_reg;
+
+    input_axis_tready_next = 0;
+
+    if (frame_reg) begin
+        if (input_axis_tvalid & input_axis_tready) begin
+            // end of frame detection
+            frame_next = ~input_axis_tlast;
+        end
+    end else if (input_axis_tvalid & ~current_output_tvalid) begin
+        // start of frame, grab select value
+        frame_next = 1;
+        select_next = select;
+    end
+
+    input_axis_tready_next = output_axis_tready_int_early & frame_next;
+
+    output_axis_tdata_int = input_axis_tdata;
+    output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
+    output_axis_tlast_int = input_axis_tlast;
+    output_axis_tuser_int = input_axis_tuser;
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        select_reg <= 0;
+        frame_reg <= 0;
+        input_axis_tready_reg <= 0;
+    end else begin
+        select_reg <= select_next;
+        frame_reg <= frame_next;
+        input_axis_tready_reg <= input_axis_tready_next;
+    end
+end
+
+// output datapath logic
+reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
+{%- for p in ports %}
+reg                  output_{{p}}_axis_tvalid_reg = 0;
+{%- endfor %}
+reg                  output_axis_tlast_reg = 0;
+reg                  output_axis_tuser_reg = 0;
+
+reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
+reg                  temp_axis_tvalid_reg = 0;
+reg                  temp_axis_tlast_reg = 0;
+reg                  temp_axis_tuser_reg = 0;
+{% for p in ports %}
+assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
+assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
+assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
+assign output_{{p}}_axis_tuser = output_axis_tuser_reg;
+{% endfor %}
+// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
+assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        output_axis_tdata_reg <= 0;
+{%- for p in ports %}
+        output_{{p}}_axis_tvalid_reg <= 0;
+{%- endfor %}
+        output_axis_tlast_reg <= 0;
+        output_axis_tuser_reg <= 0;
+        output_axis_tready_int <= 0;
+        temp_axis_tdata_reg <= 0;
+        temp_axis_tvalid_reg <= 0;
+        temp_axis_tlast_reg <= 0;
+        temp_axis_tuser_reg <= 0;
+    end else begin
+        // transfer sink ready state to source
+        output_axis_tready_int <= output_axis_tready_int_early;
+
+        if (output_axis_tready_int) begin
+            // input is ready
+            if (current_output_tready | ~current_output_tvalid) begin
+                // output is ready or currently not valid, transfer data to output
+                output_axis_tdata_reg <= output_axis_tdata_int;
+                case (select_reg)
+{%- for p in ports %}
+                    {{w}}'d{{p}}: output_{{p}}_axis_tvalid_reg <= output_axis_tvalid_int;
+{%- endfor %}
+                endcase
+                output_axis_tlast_reg <= output_axis_tlast_int;
+                output_axis_tuser_reg <= output_axis_tuser_int;
+            end else begin
+                // output is not ready, store input in temp
+                temp_axis_tdata_reg <= output_axis_tdata_int;
+                temp_axis_tvalid_reg <= output_axis_tvalid_int;
+                temp_axis_tlast_reg <= output_axis_tlast_int;
+                temp_axis_tuser_reg <= output_axis_tuser_int;
+            end
+        end else if (current_output_tready) begin
+            // input is not ready, but output is ready
+            output_axis_tdata_reg <= temp_axis_tdata_reg;
+            case (select_reg)
+{%- for p in ports %}
+                {{w}}'d{{p}}: output_{{p}}_axis_tvalid_reg <= temp_axis_tvalid_reg;
+{%- endfor %}
+            endcase
+            output_axis_tlast_reg <= temp_axis_tlast_reg;
+            output_axis_tuser_reg <= temp_axis_tuser_reg;
+            temp_axis_tdata_reg <= 0;
+            temp_axis_tvalid_reg <= 0;
+            temp_axis_tlast_reg <= 0;
+            temp_axis_tuser_reg <= 0;
+        end
+    end
+end
+
+endmodule
+
+""")
+    
+    out_file.write(t.render(
+        n=ports,
+        w=select_width,
+        name=name,
+        ports=range(ports)
+    ))
+    
+    print("Done")
+
+if __name__ == "__main__":
+    sys.exit(main())
+

lib/axis/rtl/axis_demux_4.v

@@ -0,0 +1,251 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream 4 port demultiplexer
+ */
+module axis_demux_4 #
+(
+    parameter DATA_WIDTH = 8
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI input
+     */
+    input  wire [DATA_WIDTH-1:0]  input_axis_tdata,
+    input  wire                   input_axis_tvalid,
+    output wire                   input_axis_tready,
+    input  wire                   input_axis_tlast,
+    input  wire                   input_axis_tuser,
+    
+    /*
+     * AXI outputs
+     */
+    output wire [DATA_WIDTH-1:0]  output_0_axis_tdata,
+    output wire                   output_0_axis_tvalid,
+    input  wire                   output_0_axis_tready,
+    output wire                   output_0_axis_tlast,
+    output wire                   output_0_axis_tuser,
+
+    output wire [DATA_WIDTH-1:0]  output_1_axis_tdata,
+    output wire                   output_1_axis_tvalid,
+    input  wire                   output_1_axis_tready,
+    output wire                   output_1_axis_tlast,
+    output wire                   output_1_axis_tuser,
+
+    output wire [DATA_WIDTH-1:0]  output_2_axis_tdata,
+    output wire                   output_2_axis_tvalid,
+    input  wire                   output_2_axis_tready,
+    output wire                   output_2_axis_tlast,
+    output wire                   output_2_axis_tuser,
+
+    output wire [DATA_WIDTH-1:0]  output_3_axis_tdata,
+    output wire                   output_3_axis_tvalid,
+    input  wire                   output_3_axis_tready,
+    output wire                   output_3_axis_tlast,
+    output wire                   output_3_axis_tuser,
+
+    /*
+     * Control
+     */
+    input  wire [1:0]             select
+);
+
+// // internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
+reg [1:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_axis_tready_reg = 0, input_axis_tready_next;
+assign input_axis_tready = input_axis_tready_reg;
+
+// mux for output control signals
+reg current_output_tready;
+reg current_output_tvalid;
+always @* begin
+    case (select_reg)
+        2'd0: begin
+            current_output_tvalid = output_0_axis_tvalid;
+            current_output_tready = output_0_axis_tready;
+        end
+        2'd1: begin
+            current_output_tvalid = output_1_axis_tvalid;
+            current_output_tready = output_1_axis_tready;
+        end
+        2'd2: begin
+            current_output_tvalid = output_2_axis_tvalid;
+            current_output_tready = output_2_axis_tready;
+        end
+        2'd3: begin
+            current_output_tvalid = output_3_axis_tvalid;
+            current_output_tready = output_3_axis_tready;
+        end
+    endcase
+end
+
+always @* begin
+    select_next = select_reg;
+    frame_next = frame_reg;
+
+    input_axis_tready_next = 0;
+
+    if (frame_reg) begin
+        if (input_axis_tvalid & input_axis_tready) begin
+            // end of frame detection
+            frame_next = ~input_axis_tlast;
+        end
+    end else if (input_axis_tvalid & ~current_output_tvalid) begin
+        // start of frame, grab select value
+        frame_next = 1;
+        select_next = select;
+    end
+
+    input_axis_tready_next = output_axis_tready_int_early & frame_next;
+
+    output_axis_tdata_int = input_axis_tdata;
+    output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
+    output_axis_tlast_int = input_axis_tlast;
+    output_axis_tuser_int = input_axis_tuser;
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        select_reg <= 0;
+        frame_reg <= 0;
+        input_axis_tready_reg <= 0;
+    end else begin
+        select_reg <= select_next;
+        frame_reg <= frame_next;
+        input_axis_tready_reg <= input_axis_tready_next;
+    end
+end
+
+// output datapath logic
+reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
+reg                  output_0_axis_tvalid_reg = 0;
+reg                  output_1_axis_tvalid_reg = 0;
+reg                  output_2_axis_tvalid_reg = 0;
+reg                  output_3_axis_tvalid_reg = 0;
+reg                  output_axis_tlast_reg = 0;
+reg                  output_axis_tuser_reg = 0;
+
+reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
+reg                  temp_axis_tvalid_reg = 0;
+reg                  temp_axis_tlast_reg = 0;
+reg                  temp_axis_tuser_reg = 0;
+
+assign output_0_axis_tdata = output_axis_tdata_reg;
+assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
+assign output_0_axis_tlast = output_axis_tlast_reg;
+assign output_0_axis_tuser = output_axis_tuser_reg;
+
+assign output_1_axis_tdata = output_axis_tdata_reg;
+assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
+assign output_1_axis_tlast = output_axis_tlast_reg;
+assign output_1_axis_tuser = output_axis_tuser_reg;
+
+assign output_2_axis_tdata = output_axis_tdata_reg;
+assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
+assign output_2_axis_tlast = output_axis_tlast_reg;
+assign output_2_axis_tuser = output_axis_tuser_reg;
+
+assign output_3_axis_tdata = output_axis_tdata_reg;
+assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
+assign output_3_axis_tlast = output_axis_tlast_reg;
+assign output_3_axis_tuser = output_axis_tuser_reg;
+
+// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
+assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        output_axis_tdata_reg <= 0;
+        output_0_axis_tvalid_reg <= 0;
+        output_1_axis_tvalid_reg <= 0;
+        output_2_axis_tvalid_reg <= 0;
+        output_3_axis_tvalid_reg <= 0;
+        output_axis_tlast_reg <= 0;
+        output_axis_tuser_reg <= 0;
+        output_axis_tready_int <= 0;
+        temp_axis_tdata_reg <= 0;
+        temp_axis_tvalid_reg <= 0;
+        temp_axis_tlast_reg <= 0;
+        temp_axis_tuser_reg <= 0;
+    end else begin
+        // transfer sink ready state to source
+        output_axis_tready_int <= output_axis_tready_int_early;
+
+        if (output_axis_tready_int) begin
+            // input is ready
+            if (current_output_tready | ~current_output_tvalid) begin
+                // output is ready or currently not valid, transfer data to output
+                output_axis_tdata_reg <= output_axis_tdata_int;
+                case (select_reg)
+                    2'd0: output_0_axis_tvalid_reg <= output_axis_tvalid_int;
+                    2'd1: output_1_axis_tvalid_reg <= output_axis_tvalid_int;
+                    2'd2: output_2_axis_tvalid_reg <= output_axis_tvalid_int;
+                    2'd3: output_3_axis_tvalid_reg <= output_axis_tvalid_int;
+                endcase
+                output_axis_tlast_reg <= output_axis_tlast_int;
+                output_axis_tuser_reg <= output_axis_tuser_int;
+            end else begin
+                // output is not ready, store input in temp
+                temp_axis_tdata_reg <= output_axis_tdata_int;
+                temp_axis_tvalid_reg <= output_axis_tvalid_int;
+                temp_axis_tlast_reg <= output_axis_tlast_int;
+                temp_axis_tuser_reg <= output_axis_tuser_int;
+            end
+        end else if (current_output_tready) begin
+            // input is not ready, but output is ready
+            output_axis_tdata_reg <= temp_axis_tdata_reg;
+            case (select_reg)
+                2'd0: output_0_axis_tvalid_reg <= temp_axis_tvalid_reg;
+                2'd1: output_1_axis_tvalid_reg <= temp_axis_tvalid_reg;
+                2'd2: output_2_axis_tvalid_reg <= temp_axis_tvalid_reg;
+                2'd3: output_3_axis_tvalid_reg <= temp_axis_tvalid_reg;
+            endcase
+            output_axis_tlast_reg <= temp_axis_tlast_reg;
+            output_axis_tuser_reg <= temp_axis_tuser_reg;
+            temp_axis_tdata_reg <= 0;
+            temp_axis_tvalid_reg <= 0;
+            temp_axis_tlast_reg <= 0;
+            temp_axis_tuser_reg <= 0;
+        end
+    end
+end
+
+endmodule

lib/axis/rtl/axis_demux_64.py

@@ -0,0 +1,304 @@
+#!/usr/bin/env python
+"""axis_mux
+
+Generates an AXI Stream demux with the specified number of ports
+
+Usage: axis_crosspoint [OPTION]...
+  -?, --help     display this help and exit
+  -p, --ports    specify number of ports
+  -n, --name     specify module name
+  -o, --output   specify output file name
+"""
+
+import io
+import sys
+import getopt
+from math import *
+from jinja2 import Template
+
+class Usage(Exception):
+    def __init__(self, msg):
+        self.msg = msg
+
+def main(argv=None):
+    if argv is None:
+        argv = sys.argv
+    try:
+        try:
+            opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
+        except getopt.error as msg:
+             raise Usage(msg)
+        # more code, unchanged  
+    except Usage as err:
+        print(err.msg, file=sys.stderr)
+        print("for help use --help", file=sys.stderr)
+        return 2
+
+    ports = 4
+    name = None
+    out_name = None
+
+    # process options
+    for o, a in opts:
+        if o in ('-?', '--help'):
+            print(__doc__)
+            sys.exit(0)
+        if o in ('-p', '--ports'):
+            ports = int(a)
+        if o in ('-n', '--name'):
+            name = a
+        if o in ('-o', '--output'):
+            out_name = a
+
+    if name is None:
+        name = "axis_demux_64_{0}".format(ports)
+
+    if out_name is None:
+        out_name = name + ".v"
+
+    print("Opening file '%s'..." % out_name)
+
+    try:
+        out_file = open(out_name, 'w')
+    except Exception as ex:
+        print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
+        exit(1)
+
+    print("Generating {0} port AXI Stream demux {1}...".format(ports, name))
+
+    select_width = ceil(log2(ports))
+
+    t = Template(u"""/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream {{n}} port demultiplexer (64 bit datapath)
+ */
+module {{name}} #
+(
+    parameter DATA_WIDTH = 64,
+    parameter KEEP_WIDTH = (DATA_WIDTH/8)
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI input
+     */
+    input  wire [DATA_WIDTH-1:0]  input_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_axis_tkeep,
+    input  wire                   input_axis_tvalid,
+    output wire                   input_axis_tready,
+    input  wire                   input_axis_tlast,
+    input  wire                   input_axis_tuser,
+    
+    /*
+     * AXI outputs
+     */
+{%- for p in ports %}
+    output wire [DATA_WIDTH-1:0]  output_{{p}}_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_{{p}}_axis_tkeep,
+    output wire                   output_{{p}}_axis_tvalid,
+    input  wire                   output_{{p}}_axis_tready,
+    output wire                   output_{{p}}_axis_tlast,
+    output wire                   output_{{p}}_axis_tuser,
+{% endfor %}
+    /*
+     * Control
+     */
+    input  wire [{{w-1}}:0]             select
+);
+
+// // internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
+reg [{{w-1}}:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_axis_tready_reg = 0, input_axis_tready_next;
+assign input_axis_tready = input_axis_tready_reg;
+
+// mux for output control signals
+reg current_output_tready;
+reg current_output_tvalid;
+always @* begin
+    case (select_reg)
+{%- for p in ports %}
+        {{w}}'d{{p}}: begin
+            current_output_tvalid = output_{{p}}_axis_tvalid;
+            current_output_tready = output_{{p}}_axis_tready;
+        end
+{%- endfor %}
+    endcase
+end
+
+always @* begin
+    select_next = select_reg;
+    frame_next = frame_reg;
+
+    input_axis_tready_next = 0;
+
+    if (frame_reg) begin
+        if (input_axis_tvalid & input_axis_tready) begin
+            // end of frame detection
+            frame_next = ~input_axis_tlast;
+        end
+    end else if (input_axis_tvalid & ~current_output_tvalid) begin
+        // start of frame, grab select value
+        frame_next = 1;
+        select_next = select;
+    end
+
+    input_axis_tready_next = output_axis_tready_int_early & frame_next;
+
+    output_axis_tdata_int = input_axis_tdata;
+    output_axis_tkeep_int = input_axis_tkeep;
+    output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
+    output_axis_tlast_int = input_axis_tlast;
+    output_axis_tuser_int = input_axis_tuser;
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        select_reg <= 0;
+        frame_reg <= 0;
+        input_axis_tready_reg <= 0;
+    end else begin
+        select_reg <= select_next;
+        frame_reg <= frame_next;
+        input_axis_tready_reg <= input_axis_tready_next;
+    end
+end
+
+// output datapath logic
+reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
+reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
+{%- for p in ports %}
+reg                  output_{{p}}_axis_tvalid_reg = 0;
+{%- endfor %}
+reg                  output_axis_tlast_reg = 0;
+reg                  output_axis_tuser_reg = 0;
+
+reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
+reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
+reg                  temp_axis_tvalid_reg = 0;
+reg                  temp_axis_tlast_reg = 0;
+reg                  temp_axis_tuser_reg = 0;
+{% for p in ports %}
+assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
+assign output_{{p}}_axis_tkeep = output_axis_tkeep_reg;
+assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
+assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
+assign output_{{p}}_axis_tuser = output_axis_tuser_reg;
+{% endfor %}
+// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
+assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        output_axis_tdata_reg <= 0;
+        output_axis_tkeep_reg <= 0;
+{%- for p in ports %}
+        output_{{p}}_axis_tvalid_reg <= 0;
+{%- endfor %}
+        output_axis_tlast_reg <= 0;
+        output_axis_tuser_reg <= 0;
+        output_axis_tready_int <= 0;
+        temp_axis_tdata_reg <= 0;
+        temp_axis_tkeep_reg <= 0;
+        temp_axis_tvalid_reg <= 0;
+        temp_axis_tlast_reg <= 0;
+        temp_axis_tuser_reg <= 0;
+    end else begin
+        // transfer sink ready state to source
+        output_axis_tready_int <= output_axis_tready_int_early;
+
+        if (output_axis_tready_int) begin
+            // input is ready
+            if (current_output_tready | ~current_output_tvalid) begin
+                // output is ready or currently not valid, transfer data to output
+                output_axis_tdata_reg <= output_axis_tdata_int;
+                output_axis_tkeep_reg <= output_axis_tkeep_int;
+                case (select_reg)
+{%- for p in ports %}
+                    {{w}}'d{{p}}: output_{{p}}_axis_tvalid_reg <= output_axis_tvalid_int;
+{%- endfor %}
+                endcase
+                output_axis_tlast_reg <= output_axis_tlast_int;
+                output_axis_tuser_reg <= output_axis_tuser_int;
+            end else begin
+                // output is not ready, store input in temp
+                temp_axis_tdata_reg <= output_axis_tdata_int;
+                temp_axis_tkeep_reg <= output_axis_tkeep_int;
+                temp_axis_tvalid_reg <= output_axis_tvalid_int;
+                temp_axis_tlast_reg <= output_axis_tlast_int;
+                temp_axis_tuser_reg <= output_axis_tuser_int;
+            end
+        end else if (current_output_tready) begin
+            // input is not ready, but output is ready
+            output_axis_tdata_reg <= temp_axis_tdata_reg;
+            output_axis_tkeep_reg <= temp_axis_tkeep_reg;
+            case (select_reg)
+{%- for p in ports %}
+                {{w}}'d{{p}}: output_{{p}}_axis_tvalid_reg <= temp_axis_tvalid_reg;
+{%- endfor %}
+            endcase
+            output_axis_tlast_reg <= temp_axis_tlast_reg;
+            output_axis_tuser_reg <= temp_axis_tuser_reg;
+            temp_axis_tdata_reg <= 0;
+            temp_axis_tkeep_reg <= 0;
+            temp_axis_tvalid_reg <= 0;
+            temp_axis_tlast_reg <= 0;
+            temp_axis_tuser_reg <= 0;
+        end
+    end
+end
+
+endmodule
+
+""")
+    
+    out_file.write(t.render(
+        n=ports,
+        w=select_width,
+        name=name,
+        ports=range(ports)
+    ))
+    
+    print("Done")
+
+if __name__ == "__main__":
+    sys.exit(main())
+

lib/axis/rtl/axis_demux_64_4.v

@@ -0,0 +1,271 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream 4 port demultiplexer (64 bit datapath)
+ */
+module axis_demux_64_4 #
+(
+    parameter DATA_WIDTH = 64,
+    parameter KEEP_WIDTH = (DATA_WIDTH/8)
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI input
+     */
+    input  wire [DATA_WIDTH-1:0]  input_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_axis_tkeep,
+    input  wire                   input_axis_tvalid,
+    output wire                   input_axis_tready,
+    input  wire                   input_axis_tlast,
+    input  wire                   input_axis_tuser,
+    
+    /*
+     * AXI outputs
+     */
+    output wire [DATA_WIDTH-1:0]  output_0_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_0_axis_tkeep,
+    output wire                   output_0_axis_tvalid,
+    input  wire                   output_0_axis_tready,
+    output wire                   output_0_axis_tlast,
+    output wire                   output_0_axis_tuser,
+
+    output wire [DATA_WIDTH-1:0]  output_1_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_1_axis_tkeep,
+    output wire                   output_1_axis_tvalid,
+    input  wire                   output_1_axis_tready,
+    output wire                   output_1_axis_tlast,
+    output wire                   output_1_axis_tuser,
+
+    output wire [DATA_WIDTH-1:0]  output_2_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_2_axis_tkeep,
+    output wire                   output_2_axis_tvalid,
+    input  wire                   output_2_axis_tready,
+    output wire                   output_2_axis_tlast,
+    output wire                   output_2_axis_tuser,
+
+    output wire [DATA_WIDTH-1:0]  output_3_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_3_axis_tkeep,
+    output wire                   output_3_axis_tvalid,
+    input  wire                   output_3_axis_tready,
+    output wire                   output_3_axis_tlast,
+    output wire                   output_3_axis_tuser,
+
+    /*
+     * Control
+     */
+    input  wire [1:0]             select
+);
+
+// // internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
+reg [1:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_axis_tready_reg = 0, input_axis_tready_next;
+assign input_axis_tready = input_axis_tready_reg;
+
+// mux for output control signals
+reg current_output_tready;
+reg current_output_tvalid;
+always @* begin
+    case (select_reg)
+        2'd0: begin
+            current_output_tvalid = output_0_axis_tvalid;
+            current_output_tready = output_0_axis_tready;
+        end
+        2'd1: begin
+            current_output_tvalid = output_1_axis_tvalid;
+            current_output_tready = output_1_axis_tready;
+        end
+        2'd2: begin
+            current_output_tvalid = output_2_axis_tvalid;
+            current_output_tready = output_2_axis_tready;
+        end
+        2'd3: begin
+            current_output_tvalid = output_3_axis_tvalid;
+            current_output_tready = output_3_axis_tready;
+        end
+    endcase
+end
+
+always @* begin
+    select_next = select_reg;
+    frame_next = frame_reg;
+
+    input_axis_tready_next = 0;
+
+    if (frame_reg) begin
+        if (input_axis_tvalid & input_axis_tready) begin
+            // end of frame detection
+            frame_next = ~input_axis_tlast;
+        end
+    end else if (input_axis_tvalid & ~current_output_tvalid) begin
+        // start of frame, grab select value
+        frame_next = 1;
+        select_next = select;
+    end
+
+    input_axis_tready_next = output_axis_tready_int_early & frame_next;
+
+    output_axis_tdata_int = input_axis_tdata;
+    output_axis_tkeep_int = input_axis_tkeep;
+    output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
+    output_axis_tlast_int = input_axis_tlast;
+    output_axis_tuser_int = input_axis_tuser;
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        select_reg <= 0;
+        frame_reg <= 0;
+        input_axis_tready_reg <= 0;
+    end else begin
+        select_reg <= select_next;
+        frame_reg <= frame_next;
+        input_axis_tready_reg <= input_axis_tready_next;
+    end
+end
+
+// output datapath logic
+reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
+reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
+reg                  output_0_axis_tvalid_reg = 0;
+reg                  output_1_axis_tvalid_reg = 0;
+reg                  output_2_axis_tvalid_reg = 0;
+reg                  output_3_axis_tvalid_reg = 0;
+reg                  output_axis_tlast_reg = 0;
+reg                  output_axis_tuser_reg = 0;
+
+reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
+reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
+reg                  temp_axis_tvalid_reg = 0;
+reg                  temp_axis_tlast_reg = 0;
+reg                  temp_axis_tuser_reg = 0;
+
+assign output_0_axis_tdata = output_axis_tdata_reg;
+assign output_0_axis_tkeep = output_axis_tkeep_reg;
+assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
+assign output_0_axis_tlast = output_axis_tlast_reg;
+assign output_0_axis_tuser = output_axis_tuser_reg;
+
+assign output_1_axis_tdata = output_axis_tdata_reg;
+assign output_1_axis_tkeep = output_axis_tkeep_reg;
+assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
+assign output_1_axis_tlast = output_axis_tlast_reg;
+assign output_1_axis_tuser = output_axis_tuser_reg;
+
+assign output_2_axis_tdata = output_axis_tdata_reg;
+assign output_2_axis_tkeep = output_axis_tkeep_reg;
+assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
+assign output_2_axis_tlast = output_axis_tlast_reg;
+assign output_2_axis_tuser = output_axis_tuser_reg;
+
+assign output_3_axis_tdata = output_axis_tdata_reg;
+assign output_3_axis_tkeep = output_axis_tkeep_reg;
+assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
+assign output_3_axis_tlast = output_axis_tlast_reg;
+assign output_3_axis_tuser = output_axis_tuser_reg;
+
+// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
+assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        output_axis_tdata_reg <= 0;
+        output_axis_tkeep_reg <= 0;
+        output_0_axis_tvalid_reg <= 0;
+        output_1_axis_tvalid_reg <= 0;
+        output_2_axis_tvalid_reg <= 0;
+        output_3_axis_tvalid_reg <= 0;
+        output_axis_tlast_reg <= 0;
+        output_axis_tuser_reg <= 0;
+        output_axis_tready_int <= 0;
+        temp_axis_tdata_reg <= 0;
+        temp_axis_tkeep_reg <= 0;
+        temp_axis_tvalid_reg <= 0;
+        temp_axis_tlast_reg <= 0;
+        temp_axis_tuser_reg <= 0;
+    end else begin
+        // transfer sink ready state to source
+        output_axis_tready_int <= output_axis_tready_int_early;
+
+        if (output_axis_tready_int) begin
+            // input is ready
+            if (current_output_tready | ~current_output_tvalid) begin
+                // output is ready or currently not valid, transfer data to output
+                output_axis_tdata_reg <= output_axis_tdata_int;
+                output_axis_tkeep_reg <= output_axis_tkeep_int;
+                case (select_reg)
+                    2'd0: output_0_axis_tvalid_reg <= output_axis_tvalid_int;
+                    2'd1: output_1_axis_tvalid_reg <= output_axis_tvalid_int;
+                    2'd2: output_2_axis_tvalid_reg <= output_axis_tvalid_int;
+                    2'd3: output_3_axis_tvalid_reg <= output_axis_tvalid_int;
+                endcase
+                output_axis_tlast_reg <= output_axis_tlast_int;
+                output_axis_tuser_reg <= output_axis_tuser_int;
+            end else begin
+                // output is not ready, store input in temp
+                temp_axis_tdata_reg <= output_axis_tdata_int;
+                temp_axis_tkeep_reg <= output_axis_tkeep_int;
+                temp_axis_tvalid_reg <= output_axis_tvalid_int;
+                temp_axis_tlast_reg <= output_axis_tlast_int;
+                temp_axis_tuser_reg <= output_axis_tuser_int;
+            end
+        end else if (current_output_tready) begin
+            // input is not ready, but output is ready
+            output_axis_tdata_reg <= temp_axis_tdata_reg;
+            output_axis_tkeep_reg <= temp_axis_tkeep_reg;
+            case (select_reg)
+                2'd0: output_0_axis_tvalid_reg <= temp_axis_tvalid_reg;
+                2'd1: output_1_axis_tvalid_reg <= temp_axis_tvalid_reg;
+                2'd2: output_2_axis_tvalid_reg <= temp_axis_tvalid_reg;
+                2'd3: output_3_axis_tvalid_reg <= temp_axis_tvalid_reg;
+            endcase
+            output_axis_tlast_reg <= temp_axis_tlast_reg;
+            output_axis_tuser_reg <= temp_axis_tuser_reg;
+            temp_axis_tdata_reg <= 0;
+            temp_axis_tkeep_reg <= 0;
+            temp_axis_tvalid_reg <= 0;
+            temp_axis_tlast_reg <= 0;
+            temp_axis_tuser_reg <= 0;
+        end
+    end
+end
+
+endmodule

lib/axis/rtl/axis_mux.py

@@ -0,0 +1,308 @@
+#!/usr/bin/env python
+"""axis_mux
+
+Generates an AXI Stream mux with the specified number of ports
+
+Usage: axis_crosspoint [OPTION]...
+  -?, --help     display this help and exit
+  -p, --ports    specify number of ports
+  -n, --name     specify module name
+  -o, --output   specify output file name
+"""
+
+import io
+import sys
+import getopt
+from math import *
+from jinja2 import Template
+
+class Usage(Exception):
+    def __init__(self, msg):
+        self.msg = msg
+
+def main(argv=None):
+    if argv is None:
+        argv = sys.argv
+    try:
+        try:
+            opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
+        except getopt.error as msg:
+             raise Usage(msg)
+        # more code, unchanged  
+    except Usage as err:
+        print(err.msg, file=sys.stderr)
+        print("for help use --help", file=sys.stderr)
+        return 2
+
+    ports = 4
+    name = None
+    out_name = None
+
+    # process options
+    for o, a in opts:
+        if o in ('-?', '--help'):
+            print(__doc__)
+            sys.exit(0)
+        if o in ('-p', '--ports'):
+            ports = int(a)
+        if o in ('-n', '--name'):
+            name = a
+        if o in ('-o', '--output'):
+            out_name = a
+
+    if name is None:
+        name = "axis_mux_{0}".format(ports)
+
+    if out_name is None:
+        out_name = name + ".v"
+
+    print("Opening file '%s'..." % out_name)
+
+    try:
+        out_file = open(out_name, 'w')
+    except Exception as ex:
+        print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
+        exit(1)
+
+    print("Generating {0} port AXI Stream mux {1}...".format(ports, name))
+
+    select_width = ceil(log2(ports))
+
+    t = Template(u"""/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream {{n}} port multiplexer
+ */
+module {{name}} #
+(
+    parameter DATA_WIDTH = 8
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI inputs
+     */
+{%- for p in ports %}
+    input  wire [DATA_WIDTH-1:0]  input_{{p}}_axis_tdata,
+    input  wire                   input_{{p}}_axis_tvalid,
+    output wire                   input_{{p}}_axis_tready,
+    input  wire                   input_{{p}}_axis_tlast,
+    input  wire                   input_{{p}}_axis_tuser,
+{% endfor %}
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser,
+
+    /*
+     * Control
+     */
+    input  wire [{{w-1}}:0]             select
+);
+
+// internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
+reg [{{w-1}}:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+{% for p in ports %}
+reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
+{%- endfor %}
+{% for p in ports %}
+assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
+{%- endfor %}
+
+// mux for start of packet detection
+reg selected_input_tvalid;
+always @* begin
+    case (select)
+{%- for p in ports %}
+        {{w}}'d{{p}}: selected_input_tvalid = input_{{p}}_axis_tvalid;
+{%- endfor %}
+    endcase
+end
+
+// mux for incoming packet
+reg [DATA_WIDTH-1:0] current_input_tdata;
+reg current_input_tvalid;
+reg current_input_tready;
+reg current_input_tlast;
+reg current_input_tuser;
+always @* begin
+    case (select_reg)
+{%- for p in ports %}
+        {{w}}'d{{p}}: begin
+            current_input_tdata = input_{{p}}_axis_tdata;
+            current_input_tvalid = input_{{p}}_axis_tvalid;
+            current_input_tready = input_{{p}}_axis_tready;
+            current_input_tlast = input_{{p}}_axis_tlast;
+            current_input_tuser = input_{{p}}_axis_tuser;
+        end
+{%- endfor %}
+    endcase
+end
+
+always @* begin
+    select_next = select_reg;
+    frame_next = frame_reg;
+{% for p in ports %}
+    input_{{p}}_axis_tready_next = 0;
+{%- endfor %}
+
+    if (frame_reg) begin
+        if (current_input_tvalid & current_input_tready) begin
+            // end of frame detection
+            frame_next = ~current_input_tlast;
+        end
+    end else if (selected_input_tvalid) begin
+        // start of frame, grab select value
+        frame_next = 1;
+        select_next = select;
+    end
+
+    // generate ready signal on selected port
+    case (select_next)
+{%- for p in ports %}
+        {{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early & frame_next;
+{%- endfor %}
+    endcase
+
+    // pass through selected packet data
+    output_axis_tdata_int = current_input_tdata;
+    output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
+    output_axis_tlast_int = current_input_tlast;
+    output_axis_tuser_int = current_input_tuser;
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        select_reg <= 0;
+        frame_reg <= 0;
+{%- for p in ports %}
+        input_{{p}}_axis_tready_reg <= 0;
+{%- endfor %}
+    end else begin
+        select_reg <= select_next;
+        frame_reg <= frame_next;
+{%- for p in ports %}
+        input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
+{%- endfor %}
+    end
+end
+
+// output datapath logic
+reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
+reg                  output_axis_tvalid_reg = 0;
+reg                  output_axis_tlast_reg = 0;
+reg                  output_axis_tuser_reg = 0;
+
+reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
+reg                  temp_axis_tvalid_reg = 0;
+reg                  temp_axis_tlast_reg = 0;
+reg                  temp_axis_tuser_reg = 0;
+
+assign output_axis_tdata = output_axis_tdata_reg;
+assign output_axis_tvalid = output_axis_tvalid_reg;
+assign output_axis_tlast = output_axis_tlast_reg;
+assign output_axis_tuser = output_axis_tuser_reg;
+
+// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
+assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        output_axis_tdata_reg <= 0;
+        output_axis_tvalid_reg <= 0;
+        output_axis_tlast_reg <= 0;
+        output_axis_tuser_reg <= 0;
+        output_axis_tready_int <= 0;
+        temp_axis_tdata_reg <= 0;
+        temp_axis_tvalid_reg <= 0;
+        temp_axis_tlast_reg <= 0;
+        temp_axis_tuser_reg <= 0;
+    end else begin
+        // transfer sink ready state to source
+        output_axis_tready_int <= output_axis_tready_int_early;
+
+        if (output_axis_tready_int) begin
+            // input is ready
+            if (output_axis_tready | ~output_axis_tvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                output_axis_tdata_reg <= output_axis_tdata_int;
+                output_axis_tvalid_reg <= output_axis_tvalid_int;
+                output_axis_tlast_reg <= output_axis_tlast_int;
+                output_axis_tuser_reg <= output_axis_tuser_int;
+            end else begin
+                // output is not ready, store input in temp
+                temp_axis_tdata_reg <= output_axis_tdata_int;
+                temp_axis_tvalid_reg <= output_axis_tvalid_int;
+                temp_axis_tlast_reg <= output_axis_tlast_int;
+                temp_axis_tuser_reg <= output_axis_tuser_int;
+            end
+        end else if (output_axis_tready) begin
+            // input is not ready, but output is ready
+            output_axis_tdata_reg <= temp_axis_tdata_reg;
+            output_axis_tvalid_reg <= temp_axis_tvalid_reg;
+            output_axis_tlast_reg <= temp_axis_tlast_reg;
+            output_axis_tuser_reg <= temp_axis_tuser_reg;
+            temp_axis_tdata_reg <= 0;
+            temp_axis_tvalid_reg <= 0;
+            temp_axis_tlast_reg <= 0;
+            temp_axis_tuser_reg <= 0;
+        end
+    end
+end
+
+endmodule
+
+""")
+    
+    out_file.write(t.render(
+        n=ports,
+        w=select_width,
+        name=name,
+        ports=range(ports)
+    ))
+    
+    print("Done")
+
+if __name__ == "__main__":
+    sys.exit(main())
+

lib/axis/rtl/axis_mux_4.v

@@ -0,0 +1,269 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream 4 port multiplexer
+ */
+module axis_mux_4 #
+(
+    parameter DATA_WIDTH = 8
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI inputs
+     */
+    input  wire [DATA_WIDTH-1:0]  input_0_axis_tdata,
+    input  wire                   input_0_axis_tvalid,
+    output wire                   input_0_axis_tready,
+    input  wire                   input_0_axis_tlast,
+    input  wire                   input_0_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_1_axis_tdata,
+    input  wire                   input_1_axis_tvalid,
+    output wire                   input_1_axis_tready,
+    input  wire                   input_1_axis_tlast,
+    input  wire                   input_1_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_2_axis_tdata,
+    input  wire                   input_2_axis_tvalid,
+    output wire                   input_2_axis_tready,
+    input  wire                   input_2_axis_tlast,
+    input  wire                   input_2_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_3_axis_tdata,
+    input  wire                   input_3_axis_tvalid,
+    output wire                   input_3_axis_tready,
+    input  wire                   input_3_axis_tlast,
+    input  wire                   input_3_axis_tuser,
+
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser,
+
+    /*
+     * Control
+     */
+    input  wire [1:0]             select
+);
+
+// internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
+reg [1:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_0_axis_tready_reg = 0, input_0_axis_tready_next;
+reg input_1_axis_tready_reg = 0, input_1_axis_tready_next;
+reg input_2_axis_tready_reg = 0, input_2_axis_tready_next;
+reg input_3_axis_tready_reg = 0, input_3_axis_tready_next;
+
+assign input_0_axis_tready = input_0_axis_tready_reg;
+assign input_1_axis_tready = input_1_axis_tready_reg;
+assign input_2_axis_tready = input_2_axis_tready_reg;
+assign input_3_axis_tready = input_3_axis_tready_reg;
+
+// mux for start of packet detection
+reg selected_input_tvalid;
+always @* begin
+    case (select)
+        2'd0: selected_input_tvalid = input_0_axis_tvalid;
+        2'd1: selected_input_tvalid = input_1_axis_tvalid;
+        2'd2: selected_input_tvalid = input_2_axis_tvalid;
+        2'd3: selected_input_tvalid = input_3_axis_tvalid;
+    endcase
+end
+
+// mux for incoming packet
+reg [DATA_WIDTH-1:0] current_input_tdata;
+reg current_input_tvalid;
+reg current_input_tready;
+reg current_input_tlast;
+reg current_input_tuser;
+always @* begin
+    case (select_reg)
+        2'd0: begin
+            current_input_tdata = input_0_axis_tdata;
+            current_input_tvalid = input_0_axis_tvalid;
+            current_input_tready = input_0_axis_tready;
+            current_input_tlast = input_0_axis_tlast;
+            current_input_tuser = input_0_axis_tuser;
+        end
+        2'd1: begin
+            current_input_tdata = input_1_axis_tdata;
+            current_input_tvalid = input_1_axis_tvalid;
+            current_input_tready = input_1_axis_tready;
+            current_input_tlast = input_1_axis_tlast;
+            current_input_tuser = input_1_axis_tuser;
+        end
+        2'd2: begin
+            current_input_tdata = input_2_axis_tdata;
+            current_input_tvalid = input_2_axis_tvalid;
+            current_input_tready = input_2_axis_tready;
+            current_input_tlast = input_2_axis_tlast;
+            current_input_tuser = input_2_axis_tuser;
+        end
+        2'd3: begin
+            current_input_tdata = input_3_axis_tdata;
+            current_input_tvalid = input_3_axis_tvalid;
+            current_input_tready = input_3_axis_tready;
+            current_input_tlast = input_3_axis_tlast;
+            current_input_tuser = input_3_axis_tuser;
+        end
+    endcase
+end
+
+always @* begin
+    select_next = select_reg;
+    frame_next = frame_reg;
+
+    input_0_axis_tready_next = 0;
+    input_1_axis_tready_next = 0;
+    input_2_axis_tready_next = 0;
+    input_3_axis_tready_next = 0;
+
+    if (frame_reg) begin
+        if (current_input_tvalid & current_input_tready) begin
+            // end of frame detection
+            frame_next = ~current_input_tlast;
+        end
+    end else if (selected_input_tvalid) begin
+        // start of frame, grab select value
+        frame_next = 1;
+        select_next = select;
+    end
+
+    // generate ready signal on selected port
+    case (select_next)
+        2'd0: input_0_axis_tready_next = output_axis_tready_int_early & frame_next;
+        2'd1: input_1_axis_tready_next = output_axis_tready_int_early & frame_next;
+        2'd2: input_2_axis_tready_next = output_axis_tready_int_early & frame_next;
+        2'd3: input_3_axis_tready_next = output_axis_tready_int_early & frame_next;
+    endcase
+
+    // pass through selected packet data
+    output_axis_tdata_int = current_input_tdata;
+    output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
+    output_axis_tlast_int = current_input_tlast;
+    output_axis_tuser_int = current_input_tuser;
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        select_reg <= 0;
+        frame_reg <= 0;
+        input_0_axis_tready_reg <= 0;
+        input_1_axis_tready_reg <= 0;
+        input_2_axis_tready_reg <= 0;
+        input_3_axis_tready_reg <= 0;
+    end else begin
+        select_reg <= select_next;
+        frame_reg <= frame_next;
+        input_0_axis_tready_reg <= input_0_axis_tready_next;
+        input_1_axis_tready_reg <= input_1_axis_tready_next;
+        input_2_axis_tready_reg <= input_2_axis_tready_next;
+        input_3_axis_tready_reg <= input_3_axis_tready_next;
+    end
+end
+
+// output datapath logic
+reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
+reg                  output_axis_tvalid_reg = 0;
+reg                  output_axis_tlast_reg = 0;
+reg                  output_axis_tuser_reg = 0;
+
+reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
+reg                  temp_axis_tvalid_reg = 0;
+reg                  temp_axis_tlast_reg = 0;
+reg                  temp_axis_tuser_reg = 0;
+
+assign output_axis_tdata = output_axis_tdata_reg;
+assign output_axis_tvalid = output_axis_tvalid_reg;
+assign output_axis_tlast = output_axis_tlast_reg;
+assign output_axis_tuser = output_axis_tuser_reg;
+
+// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
+assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        output_axis_tdata_reg <= 0;
+        output_axis_tvalid_reg <= 0;
+        output_axis_tlast_reg <= 0;
+        output_axis_tuser_reg <= 0;
+        output_axis_tready_int <= 0;
+        temp_axis_tdata_reg <= 0;
+        temp_axis_tvalid_reg <= 0;
+        temp_axis_tlast_reg <= 0;
+        temp_axis_tuser_reg <= 0;
+    end else begin
+        // transfer sink ready state to source
+        output_axis_tready_int <= output_axis_tready_int_early;
+
+        if (output_axis_tready_int) begin
+            // input is ready
+            if (output_axis_tready | ~output_axis_tvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                output_axis_tdata_reg <= output_axis_tdata_int;
+                output_axis_tvalid_reg <= output_axis_tvalid_int;
+                output_axis_tlast_reg <= output_axis_tlast_int;
+                output_axis_tuser_reg <= output_axis_tuser_int;
+            end else begin
+                // output is not ready, store input in temp
+                temp_axis_tdata_reg <= output_axis_tdata_int;
+                temp_axis_tvalid_reg <= output_axis_tvalid_int;
+                temp_axis_tlast_reg <= output_axis_tlast_int;
+                temp_axis_tuser_reg <= output_axis_tuser_int;
+            end
+        end else if (output_axis_tready) begin
+            // input is not ready, but output is ready
+            output_axis_tdata_reg <= temp_axis_tdata_reg;
+            output_axis_tvalid_reg <= temp_axis_tvalid_reg;
+            output_axis_tlast_reg <= temp_axis_tlast_reg;
+            output_axis_tuser_reg <= temp_axis_tuser_reg;
+            temp_axis_tdata_reg <= 0;
+            temp_axis_tvalid_reg <= 0;
+            temp_axis_tlast_reg <= 0;
+            temp_axis_tuser_reg <= 0;
+        end
+    end
+end
+
+endmodule

lib/axis/rtl/axis_mux_64.py

@@ -0,0 +1,324 @@
+#!/usr/bin/env python
+"""axis_mux
+
+Generates an AXI Stream mux with the specified number of ports
+
+Usage: axis_crosspoint [OPTION]...
+  -?, --help     display this help and exit
+  -p, --ports    specify number of ports
+  -n, --name     specify module name
+  -o, --output   specify output file name
+"""
+
+import io
+import sys
+import getopt
+from math import *
+from jinja2 import Template
+
+class Usage(Exception):
+    def __init__(self, msg):
+        self.msg = msg
+
+def main(argv=None):
+    if argv is None:
+        argv = sys.argv
+    try:
+        try:
+            opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
+        except getopt.error as msg:
+             raise Usage(msg)
+        # more code, unchanged  
+    except Usage as err:
+        print(err.msg, file=sys.stderr)
+        print("for help use --help", file=sys.stderr)
+        return 2
+
+    ports = 4
+    name = None
+    out_name = None
+
+    # process options
+    for o, a in opts:
+        if o in ('-?', '--help'):
+            print(__doc__)
+            sys.exit(0)
+        if o in ('-p', '--ports'):
+            ports = int(a)
+        if o in ('-n', '--name'):
+            name = a
+        if o in ('-o', '--output'):
+            out_name = a
+
+    if name is None:
+        name = "axis_mux_64_{0}".format(ports)
+
+    if out_name is None:
+        out_name = name + ".v"
+
+    print("Opening file '%s'..." % out_name)
+
+    try:
+        out_file = open(out_name, 'w')
+    except Exception as ex:
+        print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
+        exit(1)
+
+    print("Generating {0} port AXI Stream mux {1}...".format(ports, name))
+
+    select_width = ceil(log2(ports))
+
+    t = Template(u"""/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream {{n}} port multiplexer (64 bit datapath)
+ */
+module {{name}} #
+(
+    parameter DATA_WIDTH = 64,
+    parameter KEEP_WIDTH = (DATA_WIDTH/8)
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI inputs
+     */
+{%- for p in ports %}
+    input  wire [DATA_WIDTH-1:0]  input_{{p}}_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_{{p}}_axis_tkeep,
+    input  wire                   input_{{p}}_axis_tvalid,
+    output wire                   input_{{p}}_axis_tready,
+    input  wire                   input_{{p}}_axis_tlast,
+    input  wire                   input_{{p}}_axis_tuser,
+{% endfor %}
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_axis_tkeep,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser,
+
+    /*
+     * Control
+     */
+    input  wire [{{w-1}}:0]             select
+);
+
+// internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
+reg [{{w-1}}:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+{% for p in ports %}
+reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
+{%- endfor %}
+{% for p in ports %}
+assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
+{%- endfor %}
+
+// mux for start of packet detection
+reg selected_input_tvalid;
+always @* begin
+    case (select)
+{%- for p in ports %}
+        {{w}}'d{{p}}: selected_input_tvalid = input_{{p}}_axis_tvalid;
+{%- endfor %}
+    endcase
+end
+
+// mux for incoming packet
+reg [DATA_WIDTH-1:0] current_input_tdata;
+reg [KEEP_WIDTH-1:0] current_input_tkeep;
+reg current_input_tvalid;
+reg current_input_tready;
+reg current_input_tlast;
+reg current_input_tuser;
+always @* begin
+    case (select_reg)
+{%- for p in ports %}
+        {{w}}'d{{p}}: begin
+            current_input_tdata = input_{{p}}_axis_tdata;
+            current_input_tkeep = input_{{p}}_axis_tkeep;
+            current_input_tvalid = input_{{p}}_axis_tvalid;
+            current_input_tready = input_{{p}}_axis_tready;
+            current_input_tlast = input_{{p}}_axis_tlast;
+            current_input_tuser = input_{{p}}_axis_tuser;
+        end
+{%- endfor %}
+    endcase
+end
+
+always @* begin
+    select_next = select_reg;
+    frame_next = frame_reg;
+{% for p in ports %}
+    input_{{p}}_axis_tready_next = 0;
+{%- endfor %}
+
+    if (frame_reg) begin
+        if (current_input_tvalid & current_input_tready) begin
+            // end of frame detection
+            frame_next = ~current_input_tlast;
+        end
+    end else if (selected_input_tvalid) begin
+        // start of frame, grab select value
+        frame_next = 1;
+        select_next = select;
+    end
+
+    // generate ready signal on selected port
+    case (select_next)
+{%- for p in ports %}
+        {{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early & frame_next;
+{%- endfor %}
+    endcase
+
+    // pass through selected packet data
+    output_axis_tdata_int = current_input_tdata;
+    output_axis_tkeep_int = current_input_tkeep;
+    output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
+    output_axis_tlast_int = current_input_tlast;
+    output_axis_tuser_int = current_input_tuser;
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        select_reg <= 0;
+        frame_reg <= 0;
+{%- for p in ports %}
+        input_{{p}}_axis_tready_reg <= 0;
+{%- endfor %}
+    end else begin
+        select_reg <= select_next;
+        frame_reg <= frame_next;
+{%- for p in ports %}
+        input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
+{%- endfor %}
+    end
+end
+
+// output datapath logic
+reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
+reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
+reg                  output_axis_tvalid_reg = 0;
+reg                  output_axis_tlast_reg = 0;
+reg                  output_axis_tuser_reg = 0;
+
+reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
+reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
+reg                  temp_axis_tvalid_reg = 0;
+reg                  temp_axis_tlast_reg = 0;
+reg                  temp_axis_tuser_reg = 0;
+
+assign output_axis_tdata = output_axis_tdata_reg;
+assign output_axis_tkeep = output_axis_tkeep_reg;
+assign output_axis_tvalid = output_axis_tvalid_reg;
+assign output_axis_tlast = output_axis_tlast_reg;
+assign output_axis_tuser = output_axis_tuser_reg;
+
+// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
+assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        output_axis_tdata_reg <= 0;
+        output_axis_tkeep_reg <= 0;
+        output_axis_tvalid_reg <= 0;
+        output_axis_tlast_reg <= 0;
+        output_axis_tuser_reg <= 0;
+        output_axis_tready_int <= 0;
+        temp_axis_tdata_reg <= 0;
+        temp_axis_tkeep_reg <= 0;
+        temp_axis_tvalid_reg <= 0;
+        temp_axis_tlast_reg <= 0;
+        temp_axis_tuser_reg <= 0;
+    end else begin
+        // transfer sink ready state to source
+        output_axis_tready_int <= output_axis_tready_int_early;
+
+        if (output_axis_tready_int) begin
+            // input is ready
+            if (output_axis_tready | ~output_axis_tvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                output_axis_tdata_reg <= output_axis_tdata_int;
+                output_axis_tkeep_reg <= output_axis_tkeep_int;
+                output_axis_tvalid_reg <= output_axis_tvalid_int;
+                output_axis_tlast_reg <= output_axis_tlast_int;
+                output_axis_tuser_reg <= output_axis_tuser_int;
+            end else begin
+                // output is not ready, store input in temp
+                temp_axis_tdata_reg <= output_axis_tdata_int;
+                temp_axis_tkeep_reg <= output_axis_tkeep_int;
+                temp_axis_tvalid_reg <= output_axis_tvalid_int;
+                temp_axis_tlast_reg <= output_axis_tlast_int;
+                temp_axis_tuser_reg <= output_axis_tuser_int;
+            end
+        end else if (output_axis_tready) begin
+            // input is not ready, but output is ready
+            output_axis_tdata_reg <= temp_axis_tdata_reg;
+            output_axis_tkeep_reg <= temp_axis_tkeep_reg;
+            output_axis_tvalid_reg <= temp_axis_tvalid_reg;
+            output_axis_tlast_reg <= temp_axis_tlast_reg;
+            output_axis_tuser_reg <= temp_axis_tuser_reg;
+            temp_axis_tdata_reg <= 0;
+            temp_axis_tkeep_reg <= 0;
+            temp_axis_tvalid_reg <= 0;
+            temp_axis_tlast_reg <= 0;
+            temp_axis_tuser_reg <= 0;
+        end
+    end
+end
+
+endmodule
+
+""")
+    
+    out_file.write(t.render(
+        n=ports,
+        w=select_width,
+        name=name,
+        ports=range(ports)
+    ))
+    
+    print("Done")
+
+if __name__ == "__main__":
+    sys.exit(main())
+

lib/axis/rtl/axis_mux_64_4.v

@@ -0,0 +1,291 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream 4 port multiplexer (64 bit datapath)
+ */
+module axis_mux_64_4 #
+(
+    parameter DATA_WIDTH = 64,
+    parameter KEEP_WIDTH = (DATA_WIDTH/8)
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI inputs
+     */
+    input  wire [DATA_WIDTH-1:0]  input_0_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_0_axis_tkeep,
+    input  wire                   input_0_axis_tvalid,
+    output wire                   input_0_axis_tready,
+    input  wire                   input_0_axis_tlast,
+    input  wire                   input_0_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_1_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_1_axis_tkeep,
+    input  wire                   input_1_axis_tvalid,
+    output wire                   input_1_axis_tready,
+    input  wire                   input_1_axis_tlast,
+    input  wire                   input_1_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_2_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_2_axis_tkeep,
+    input  wire                   input_2_axis_tvalid,
+    output wire                   input_2_axis_tready,
+    input  wire                   input_2_axis_tlast,
+    input  wire                   input_2_axis_tuser,
+
+    input  wire [DATA_WIDTH-1:0]  input_3_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  input_3_axis_tkeep,
+    input  wire                   input_3_axis_tvalid,
+    output wire                   input_3_axis_tready,
+    input  wire                   input_3_axis_tlast,
+    input  wire                   input_3_axis_tuser,
+
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  output_axis_tkeep,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser,
+
+    /*
+     * Control
+     */
+    input  wire [1:0]             select
+);
+
+// internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
+reg [1:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_0_axis_tready_reg = 0, input_0_axis_tready_next;
+reg input_1_axis_tready_reg = 0, input_1_axis_tready_next;
+reg input_2_axis_tready_reg = 0, input_2_axis_tready_next;
+reg input_3_axis_tready_reg = 0, input_3_axis_tready_next;
+
+assign input_0_axis_tready = input_0_axis_tready_reg;
+assign input_1_axis_tready = input_1_axis_tready_reg;
+assign input_2_axis_tready = input_2_axis_tready_reg;
+assign input_3_axis_tready = input_3_axis_tready_reg;
+
+// mux for start of packet detection
+reg selected_input_tvalid;
+always @* begin
+    case (select)
+        2'd0: selected_input_tvalid = input_0_axis_tvalid;
+        2'd1: selected_input_tvalid = input_1_axis_tvalid;
+        2'd2: selected_input_tvalid = input_2_axis_tvalid;
+        2'd3: selected_input_tvalid = input_3_axis_tvalid;
+    endcase
+end
+
+// mux for incoming packet
+reg [DATA_WIDTH-1:0] current_input_tdata;
+reg [KEEP_WIDTH-1:0] current_input_tkeep;
+reg current_input_tvalid;
+reg current_input_tready;
+reg current_input_tlast;
+reg current_input_tuser;
+always @* begin
+    case (select_reg)
+        2'd0: begin
+            current_input_tdata = input_0_axis_tdata;
+            current_input_tkeep = input_0_axis_tkeep;
+            current_input_tvalid = input_0_axis_tvalid;
+            current_input_tready = input_0_axis_tready;
+            current_input_tlast = input_0_axis_tlast;
+            current_input_tuser = input_0_axis_tuser;
+        end
+        2'd1: begin
+            current_input_tdata = input_1_axis_tdata;
+            current_input_tkeep = input_1_axis_tkeep;
+            current_input_tvalid = input_1_axis_tvalid;
+            current_input_tready = input_1_axis_tready;
+            current_input_tlast = input_1_axis_tlast;
+            current_input_tuser = input_1_axis_tuser;
+        end
+        2'd2: begin
+            current_input_tdata = input_2_axis_tdata;
+            current_input_tkeep = input_2_axis_tkeep;
+            current_input_tvalid = input_2_axis_tvalid;
+            current_input_tready = input_2_axis_tready;
+            current_input_tlast = input_2_axis_tlast;
+            current_input_tuser = input_2_axis_tuser;
+        end
+        2'd3: begin
+            current_input_tdata = input_3_axis_tdata;
+            current_input_tkeep = input_3_axis_tkeep;
+            current_input_tvalid = input_3_axis_tvalid;
+            current_input_tready = input_3_axis_tready;
+            current_input_tlast = input_3_axis_tlast;
+            current_input_tuser = input_3_axis_tuser;
+        end
+    endcase
+end
+
+always @* begin
+    select_next = select_reg;
+    frame_next = frame_reg;
+
+    input_0_axis_tready_next = 0;
+    input_1_axis_tready_next = 0;
+    input_2_axis_tready_next = 0;
+    input_3_axis_tready_next = 0;
+
+    if (frame_reg) begin
+        if (current_input_tvalid & current_input_tready) begin
+            // end of frame detection
+            frame_next = ~current_input_tlast;
+        end
+    end else if (selected_input_tvalid) begin
+        // start of frame, grab select value
+        frame_next = 1;
+        select_next = select;
+    end
+
+    // generate ready signal on selected port
+    case (select_next)
+        2'd0: input_0_axis_tready_next = output_axis_tready_int_early & frame_next;
+        2'd1: input_1_axis_tready_next = output_axis_tready_int_early & frame_next;
+        2'd2: input_2_axis_tready_next = output_axis_tready_int_early & frame_next;
+        2'd3: input_3_axis_tready_next = output_axis_tready_int_early & frame_next;
+    endcase
+
+    // pass through selected packet data
+    output_axis_tdata_int = current_input_tdata;
+    output_axis_tkeep_int = current_input_tkeep;
+    output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
+    output_axis_tlast_int = current_input_tlast;
+    output_axis_tuser_int = current_input_tuser;
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        select_reg <= 0;
+        frame_reg <= 0;
+        input_0_axis_tready_reg <= 0;
+        input_1_axis_tready_reg <= 0;
+        input_2_axis_tready_reg <= 0;
+        input_3_axis_tready_reg <= 0;
+    end else begin
+        select_reg <= select_next;
+        frame_reg <= frame_next;
+        input_0_axis_tready_reg <= input_0_axis_tready_next;
+        input_1_axis_tready_reg <= input_1_axis_tready_next;
+        input_2_axis_tready_reg <= input_2_axis_tready_next;
+        input_3_axis_tready_reg <= input_3_axis_tready_next;
+    end
+end
+
+// output datapath logic
+reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
+reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
+reg                  output_axis_tvalid_reg = 0;
+reg                  output_axis_tlast_reg = 0;
+reg                  output_axis_tuser_reg = 0;
+
+reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
+reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
+reg                  temp_axis_tvalid_reg = 0;
+reg                  temp_axis_tlast_reg = 0;
+reg                  temp_axis_tuser_reg = 0;
+
+assign output_axis_tdata = output_axis_tdata_reg;
+assign output_axis_tkeep = output_axis_tkeep_reg;
+assign output_axis_tvalid = output_axis_tvalid_reg;
+assign output_axis_tlast = output_axis_tlast_reg;
+assign output_axis_tuser = output_axis_tuser_reg;
+
+// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
+assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        output_axis_tdata_reg <= 0;
+        output_axis_tkeep_reg <= 0;
+        output_axis_tvalid_reg <= 0;
+        output_axis_tlast_reg <= 0;
+        output_axis_tuser_reg <= 0;
+        output_axis_tready_int <= 0;
+        temp_axis_tdata_reg <= 0;
+        temp_axis_tkeep_reg <= 0;
+        temp_axis_tvalid_reg <= 0;
+        temp_axis_tlast_reg <= 0;
+        temp_axis_tuser_reg <= 0;
+    end else begin
+        // transfer sink ready state to source
+        output_axis_tready_int <= output_axis_tready_int_early;
+
+        if (output_axis_tready_int) begin
+            // input is ready
+            if (output_axis_tready | ~output_axis_tvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                output_axis_tdata_reg <= output_axis_tdata_int;
+                output_axis_tkeep_reg <= output_axis_tkeep_int;
+                output_axis_tvalid_reg <= output_axis_tvalid_int;
+                output_axis_tlast_reg <= output_axis_tlast_int;
+                output_axis_tuser_reg <= output_axis_tuser_int;
+            end else begin
+                // output is not ready, store input in temp
+                temp_axis_tdata_reg <= output_axis_tdata_int;
+                temp_axis_tkeep_reg <= output_axis_tkeep_int;
+                temp_axis_tvalid_reg <= output_axis_tvalid_int;
+                temp_axis_tlast_reg <= output_axis_tlast_int;
+                temp_axis_tuser_reg <= output_axis_tuser_int;
+            end
+        end else if (output_axis_tready) begin
+            // input is not ready, but output is ready
+            output_axis_tdata_reg <= temp_axis_tdata_reg;
+            output_axis_tkeep_reg <= temp_axis_tkeep_reg;
+            output_axis_tvalid_reg <= temp_axis_tvalid_reg;
+            output_axis_tlast_reg <= temp_axis_tlast_reg;
+            output_axis_tuser_reg <= temp_axis_tuser_reg;
+            temp_axis_tdata_reg <= 0;
+            temp_axis_tkeep_reg <= 0;
+            temp_axis_tvalid_reg <= 0;
+            temp_axis_tlast_reg <= 0;
+            temp_axis_tuser_reg <= 0;
+        end
+    end
+end
+
+endmodule

lib/axis/rtl/axis_rate_limit.v

@@ -31,8 +31,7 @@ THE SOFTWARE.
  */
 module axis_rate_limit #
 (
-    parameter DATA_WIDTH = 64,
-    parameter KEEP_WIDTH = (DATA_WIDTH/8)
+    parameter DATA_WIDTH = 8
 )
 (
     input  wire                   clk,

lib/axis/rtl/priority_encoder.v

@@ -0,0 +1,82 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Priority encoder module
+ */
+module priority_encoder #
+(
+    parameter WIDTH = 4
+)
+(
+    input  wire [WIDTH-1:0]         input_unencoded,
+    output wire                     output_valid,
+    output wire [$clog2(WIDTH)-1:0] output_encoded,
+    output wire [WIDTH-1:0]         output_unencoded
+);
+
+// power-of-two width
+localparam W1 = 2**$clog2(WIDTH);
+localparam W2 = W1/2;
+
+generate
+    if (WIDTH == 2) begin
+        // two inputs - just an OR gate
+        assign output_valid = |input_unencoded;
+        assign output_encoded = input_unencoded[1];
+    end else begin
+        // more than two inputs - split into two parts and recurse
+        // also pad input to correct power-of-two width
+        wire [$clog2(W2)-1:0] out1, out2;
+        wire valid1, valid2;
+        priority_encoder #(
+            .WIDTH(W2)
+        )
+        priority_encoder_inst1 (
+            .input_unencoded(input_unencoded[W2-1:0]),
+            .output_valid(valid1),
+            .output_encoded(out1)
+        );
+        priority_encoder #(
+            .WIDTH(W2)
+        )
+        priority_encoder_inst2 (
+            .input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
+            .output_valid(valid2),
+            .output_encoded(out2)
+        );
+        // multiplexer to select part
+        assign output_valid = valid1 | valid2;
+        assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
+    end
+endgenerate
+
+// unencoded output
+assign output_unencoded = 1 << output_encoded;
+
+endmodule

lib/axis/tb/test_arbiter.py

@@ -0,0 +1,180 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+module = 'arbiter'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("test_%s.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_arbiter(clk,
+                rst,
+                current_test,
+
+                request,
+                acknowledge,
+
+                grant,
+                grant_valid,
+                grant_encoded):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                request=request,
+                acknowledge=acknowledge,
+
+                grant=grant,
+                grant_valid=grant_valid,
+                grant_encoded=grant_encoded)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    request = Signal(intbv(0)[32:])
+    acknowledge = Signal(intbv(0)[32:])
+
+    # Outputs
+    grant = Signal(intbv(0)[32:])
+    grant_valid = Signal(bool(0))
+    grant_encoded = Signal(intbv(0)[5:])
+
+    # DUT
+    dut = dut_arbiter(clk,
+                      rst,
+                      current_test,
+
+                      request,
+                      acknowledge,
+
+                      grant,
+                      grant_valid,
+                      grant_encoded)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        print("test 1: one bit")
+        current_test.next = 1
+
+        yield clk.posedge
+
+        for i in range(32):
+            l = [i]
+            request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
+            yield clk.posedge
+            request.next = 0
+            yield clk.posedge
+
+            assert grant == 1 << i
+            assert grant_encoded == i
+
+            yield clk.posedge
+
+        yield delay(100)
+
+        yield clk.posedge
+
+        print("test 2: two bits")
+        current_test.next = 2
+        
+        for i in range(32):
+            for j in range(32):
+                l = [i, j]
+                request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
+                yield clk.posedge
+                request.next = 0
+                yield clk.posedge
+
+                assert grant == 1 << max(l)
+                assert grant_encoded == max(l)
+
+                request.next = 0
+
+                yield clk.posedge
+
+        print("test 3: five bits")
+        current_test.next = 3
+
+        for i in range(32):
+            l = [(i*x) % 32 for x in [1,2,3,4,5]]
+            request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
+            yield clk.posedge
+            request.next = 0
+            yield clk.posedge
+
+            assert grant == 1 << max(l)
+            assert grant_encoded == max(l)
+
+            prev = int(grant_encoded)
+
+            yield clk.posedge
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_arbiter.v

@@ -0,0 +1,80 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_arbiter;
+
+// parameters
+localparam PORTS = 32;
+localparam TYPE = "PRIORITY";
+localparam BLOCK = "REQUEST";
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [PORTS-1:0] request = 0;
+reg [PORTS-1:0] acknowledge = 0;
+
+// Outputs
+wire [PORTS-1:0] grant;
+wire grant_valid;
+wire [$clog2(PORTS)-1:0] grant_encoded;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                request,
+                acknowledge);
+    $to_myhdl(grant,
+              grant_valid,
+              grant_encoded);
+
+    // dump file
+    $dumpfile("test_arbiter.lxt");
+    $dumpvars(0, test_arbiter);
+end
+
+arbiter #(
+    .PORTS(PORTS),
+    .TYPE(TYPE),
+    .BLOCK(BLOCK)
+)
+UUT (
+    .clk(clk),
+    .rst(rst),
+    .request(request),
+    .acknowledge(acknowledge),
+    .grant(grant),
+    .grant_valid(grant_valid),
+    .grant_encoded(grant_encoded)
+);
+
+endmodule

lib/axis/tb/test_arbiter_rr.py

@@ -0,0 +1,237 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+module = 'arbiter'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("test_%s_rr.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_arbiter_rr(clk,
+                   rst,
+                   current_test,
+
+                   request,
+                   acknowledge,
+
+                   grant,
+                   grant_valid,
+                   grant_encoded):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                request=request,
+                acknowledge=acknowledge,
+
+                grant=grant,
+                grant_valid=grant_valid,
+                grant_encoded=grant_encoded)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    request = Signal(intbv(0)[32:])
+    acknowledge = Signal(intbv(0)[32:])
+
+    # Outputs
+    grant = Signal(intbv(0)[32:])
+    grant_valid = Signal(bool(0))
+    grant_encoded = Signal(intbv(0)[5:])
+
+    # DUT
+    dut = dut_arbiter_rr(clk,
+                         rst,
+                         current_test,
+
+                         request,
+                         acknowledge,
+
+                         grant,
+                         grant_valid,
+                         grant_encoded)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        prev = 0
+
+        print("test 1: one bit")
+        current_test.next = 1
+
+        yield clk.posedge
+
+        for i in range(32):
+            l = [i]
+            request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
+            yield clk.posedge
+            request.next = 0
+            yield clk.posedge
+
+            # emulate round robin
+            l2 = [x for x in l if x < prev]
+            if len(l2) == 0:
+                l2 = l
+            g = max(l2)
+
+            assert grant == 1 << g
+            assert grant_encoded == g
+
+            prev = int(grant_encoded)
+
+            yield clk.posedge
+
+        yield delay(100)
+
+        yield clk.posedge
+
+        print("test 2: cycle")
+        current_test.next = 2
+
+        for i in range(32):
+            l = [0, 5, 10, 15, 20, 25, 30]
+            request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
+            yield clk.posedge
+            request.next = 0
+            yield clk.posedge
+
+            # emulate round robin
+            l2 = [x for x in l if x < prev]
+            if len(l2) == 0:
+                l2 = l
+            g = max(l2)
+
+            assert grant == 1 << g
+            assert grant_encoded == g
+
+            prev = int(grant_encoded)
+
+            yield clk.posedge
+
+        yield delay(100)
+
+        yield clk.posedge
+
+        print("test 3: two bits")
+        current_test.next = 3
+        
+        for i in range(32):
+            for j in range(32):
+                l = [i, j]
+                request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
+                yield clk.posedge
+                request.next = 0
+                yield clk.posedge
+
+                # emulate round robin
+                l2 = [x for x in l if x < prev]
+                if len(l2) == 0:
+                    l2 = l
+                g = max(l2)
+
+                assert grant == 1 << g
+                assert grant_encoded == g
+
+                prev = int(grant_encoded)
+
+                yield clk.posedge
+
+        yield delay(100)
+
+        yield clk.posedge
+
+        print("test 4: five bits")
+        current_test.next = 4
+
+        for i in range(32):
+            l = [(i*x) % 32 for x in [1,2,3,4,5]]
+            request.next = reduce(lambda x, y: x|y, [1<<y for y in l])
+            yield clk.posedge
+            request.next = 0
+            yield clk.posedge
+
+            # emulate round robin
+            l2 = [x for x in l if x < prev]
+            if len(l2) == 0:
+                l2 = l
+            g = max(l2)
+
+            assert grant == 1 << g
+            assert grant_encoded == g
+
+            prev = int(grant_encoded)
+
+            yield clk.posedge
+
+        yield delay(100)
+
+        yield clk.posedge
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_arbiter_rr.v

@@ -0,0 +1,80 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_arbiter_rr;
+
+// parameters
+localparam PORTS = 32;
+localparam TYPE = "ROUND_ROBIN";
+localparam BLOCK = "REQUEST";
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [PORTS-1:0] request = 0;
+reg [PORTS-1:0] acknowledge = 0;
+
+// Outputs
+wire [PORTS-1:0] grant;
+wire grant_valid;
+wire [$clog2(PORTS)-1:0] grant_encoded;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                request,
+                acknowledge);
+    $to_myhdl(grant,
+              grant_valid,
+              grant_encoded);
+
+    // dump file
+    $dumpfile("test_arbiter_rr.lxt");
+    $dumpvars(0, test_arbiter_rr);
+end
+
+arbiter #(
+    .PORTS(PORTS),
+    .TYPE(TYPE),
+    .BLOCK(BLOCK)
+)
+UUT (
+    .clk(clk),
+    .rst(rst),
+    .request(request),
+    .acknowledge(acknowledge),
+    .grant(grant),
+    .grant_valid(grant_valid),
+    .grant_encoded(grant_encoded)
+);
+
+endmodule

lib/axis/tb/test_axis_arb_mux_4.py

@@ -0,0 +1,544 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+from Queue import Queue
+
+import axis_ep
+
+module = 'axis_arb_mux_4'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/axis_mux_4.v")
+srcs.append("../rtl/arbiter.v")
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("test_%s.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_axis_arb_mux_4(clk,
+                 rst,
+                 current_test,
+
+                 input_0_axis_tdata,
+                 input_0_axis_tvalid,
+                 input_0_axis_tready,
+                 input_0_axis_tlast,
+                 input_0_axis_tuser,
+                 input_1_axis_tdata,
+                 input_1_axis_tvalid,
+                 input_1_axis_tready,
+                 input_1_axis_tlast,
+                 input_1_axis_tuser,
+                 input_2_axis_tdata,
+                 input_2_axis_tvalid,
+                 input_2_axis_tready,
+                 input_2_axis_tlast,
+                 input_2_axis_tuser,
+                 input_3_axis_tdata,
+                 input_3_axis_tvalid,
+                 input_3_axis_tready,
+                 input_3_axis_tlast,
+                 input_3_axis_tuser,
+
+                 output_axis_tdata,
+                 output_axis_tvalid,
+                 output_axis_tready,
+                 output_axis_tlast,
+                 output_axis_tuser):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                input_0_axis_tdata=input_0_axis_tdata,
+                input_0_axis_tvalid=input_0_axis_tvalid,
+                input_0_axis_tready=input_0_axis_tready,
+                input_0_axis_tlast=input_0_axis_tlast,
+                input_0_axis_tuser=input_0_axis_tuser,
+                input_1_axis_tdata=input_1_axis_tdata,
+                input_1_axis_tvalid=input_1_axis_tvalid,
+                input_1_axis_tready=input_1_axis_tready,
+                input_1_axis_tlast=input_1_axis_tlast,
+                input_1_axis_tuser=input_1_axis_tuser,
+                input_2_axis_tdata=input_2_axis_tdata,
+                input_2_axis_tvalid=input_2_axis_tvalid,
+                input_2_axis_tready=input_2_axis_tready,
+                input_2_axis_tlast=input_2_axis_tlast,
+                input_2_axis_tuser=input_2_axis_tuser,
+                input_3_axis_tdata=input_3_axis_tdata,
+                input_3_axis_tvalid=input_3_axis_tvalid,
+                input_3_axis_tready=input_3_axis_tready,
+                input_3_axis_tlast=input_3_axis_tlast,
+                input_3_axis_tuser=input_3_axis_tuser,
+
+                output_axis_tdata=output_axis_tdata,
+                output_axis_tvalid=output_axis_tvalid,
+                output_axis_tready=output_axis_tready,
+                output_axis_tlast=output_axis_tlast,
+                output_axis_tuser=output_axis_tuser)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    input_0_axis_tdata = Signal(intbv(0)[8:])
+    input_0_axis_tvalid = Signal(bool(0))
+    input_0_axis_tlast = Signal(bool(0))
+    input_0_axis_tuser = Signal(bool(0))
+    input_1_axis_tdata = Signal(intbv(0)[8:])
+    input_1_axis_tvalid = Signal(bool(0))
+    input_1_axis_tlast = Signal(bool(0))
+    input_1_axis_tuser = Signal(bool(0))
+    input_2_axis_tdata = Signal(intbv(0)[8:])
+    input_2_axis_tvalid = Signal(bool(0))
+    input_2_axis_tlast = Signal(bool(0))
+    input_2_axis_tuser = Signal(bool(0))
+    input_3_axis_tdata = Signal(intbv(0)[8:])
+    input_3_axis_tvalid = Signal(bool(0))
+    input_3_axis_tlast = Signal(bool(0))
+    input_3_axis_tuser = Signal(bool(0))
+
+    output_axis_tready = Signal(bool(0))
+
+    # Outputs
+    input_0_axis_tready = Signal(bool(0))
+    input_1_axis_tready = Signal(bool(0))
+    input_2_axis_tready = Signal(bool(0))
+    input_3_axis_tready = Signal(bool(0))
+
+    output_axis_tdata = Signal(intbv(0)[8:])
+    output_axis_tvalid = Signal(bool(0))
+    output_axis_tlast = Signal(bool(0))
+    output_axis_tuser = Signal(bool(0))
+
+    # sources and sinks
+    source_0_queue = Queue()
+    source_0_pause = Signal(bool(0))
+    source_1_queue = Queue()
+    source_1_pause = Signal(bool(0))
+    source_2_queue = Queue()
+    source_2_pause = Signal(bool(0))
+    source_3_queue = Queue()
+    source_3_pause = Signal(bool(0))
+    sink_queue = Queue()
+    sink_pause = Signal(bool(0))
+
+    source_0 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_0_axis_tdata,
+                                       tvalid=input_0_axis_tvalid,
+                                       tready=input_0_axis_tready,
+                                       tlast=input_0_axis_tlast,
+                                       tuser=input_0_axis_tuser,
+                                       fifo=source_0_queue,
+                                       pause=source_0_pause,
+                                       name='source0')
+    source_1 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_1_axis_tdata,
+                                       tvalid=input_1_axis_tvalid,
+                                       tready=input_1_axis_tready,
+                                       tlast=input_1_axis_tlast,
+                                       tuser=input_1_axis_tuser,
+                                       fifo=source_1_queue,
+                                       pause=source_1_pause,
+                                       name='source1')
+    source_2 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_2_axis_tdata,
+                                       tvalid=input_2_axis_tvalid,
+                                       tready=input_2_axis_tready,
+                                       tlast=input_2_axis_tlast,
+                                       tuser=input_2_axis_tuser,
+                                       fifo=source_2_queue,
+                                       pause=source_2_pause,
+                                       name='source2')
+    source_3 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_3_axis_tdata,
+                                       tvalid=input_3_axis_tvalid,
+                                       tready=input_3_axis_tready,
+                                       tlast=input_3_axis_tlast,
+                                       tuser=input_3_axis_tuser,
+                                       fifo=source_3_queue,
+                                       pause=source_3_pause,
+                                       name='source3')
+
+    sink = axis_ep.AXIStreamSink(clk,
+                                 rst,
+                                 tdata=output_axis_tdata,
+                                 tvalid=output_axis_tvalid,
+                                 tready=output_axis_tready,
+                                 tlast=output_axis_tlast,
+                                 tuser=output_axis_tuser,
+                                 fifo=sink_queue,
+                                 pause=sink_pause,
+                                 name='sink')
+
+    # DUT
+    dut = dut_axis_arb_mux_4(clk,
+                       rst,
+                       current_test,
+
+                       input_0_axis_tdata,
+                       input_0_axis_tvalid,
+                       input_0_axis_tready,
+                       input_0_axis_tlast,
+                       input_0_axis_tuser,
+                       input_1_axis_tdata,
+                       input_1_axis_tvalid,
+                       input_1_axis_tready,
+                       input_1_axis_tlast,
+                       input_1_axis_tuser,
+                       input_2_axis_tdata,
+                       input_2_axis_tvalid,
+                       input_2_axis_tready,
+                       input_2_axis_tlast,
+                       input_2_axis_tuser,
+                       input_3_axis_tdata,
+                       input_3_axis_tvalid,
+                       input_3_axis_tready,
+                       input_3_axis_tlast,
+                       input_3_axis_tuser,
+
+                       output_axis_tdata,
+                       output_axis_tvalid,
+                       output_axis_tready,
+                       output_axis_tlast,
+                       output_axis_tuser)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        yield clk.posedge
+        print("test 1: port 0")
+        current_test.next = 1
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x00\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_0_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 2: port 1")
+        current_test.next = 2
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 3: back-to-back packets, same port")
+        current_test.next = 3
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x00\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x00\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_0_queue.put(test_frame1)
+        source_0_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 4: back-to-back packets, different ports")
+        current_test.next = 4
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x02\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 5: alterate pause source")
+        current_test.next = 5
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x02\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            source_0_pause.next = True
+            source_1_pause.next = True
+            source_2_pause.next = True
+            source_3_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            source_0_pause.next = False
+            source_1_pause.next = False
+            source_2_pause.next = False
+            source_3_pause.next = False
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 6: alterate pause sink")
+        current_test.next = 6
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x02\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            sink_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            sink_pause.next = False
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 4: back-to-back packets, different ports, arbitration test")
+        current_test.next = 4
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x02\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        source_1_queue.put(test_frame1)
+        source_1_queue.put(test_frame1)
+        source_1_queue.put(test_frame1)
+        source_1_queue.put(test_frame1)
+        yield clk.posedge
+
+        yield delay(800)
+        yield clk.posedge
+        source_2_queue.put(test_frame2)
+        
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_axis_arb_mux_4.v

@@ -0,0 +1,137 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_axis_arb_mux_4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [7:0] input_0_axis_tdata = 0;
+reg input_0_axis_tvalid = 0;
+reg input_0_axis_tlast = 0;
+reg input_0_axis_tuser = 0;
+reg [7:0] input_1_axis_tdata = 0;
+reg input_1_axis_tvalid = 0;
+reg input_1_axis_tlast = 0;
+reg input_1_axis_tuser = 0;
+reg [7:0] input_2_axis_tdata = 0;
+reg input_2_axis_tvalid = 0;
+reg input_2_axis_tlast = 0;
+reg input_2_axis_tuser = 0;
+reg [7:0] input_3_axis_tdata = 0;
+reg input_3_axis_tvalid = 0;
+reg input_3_axis_tlast = 0;
+reg input_3_axis_tuser = 0;
+
+reg output_axis_tready = 0;
+
+// Outputs
+wire input_0_axis_tready;
+wire input_1_axis_tready;
+wire input_2_axis_tready;
+wire input_3_axis_tready;
+
+wire [7:0] output_axis_tdata;
+wire output_axis_tvalid;
+wire output_axis_tlast;
+wire output_axis_tuser;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                input_0_axis_tdata,
+                input_0_axis_tvalid,
+                input_0_axis_tlast,
+                input_0_axis_tuser,
+                input_1_axis_tdata,
+                input_1_axis_tvalid,
+                input_1_axis_tlast,
+                input_1_axis_tuser,
+                input_2_axis_tdata,
+                input_2_axis_tvalid,
+                input_2_axis_tlast,
+                input_2_axis_tuser,
+                input_3_axis_tdata,
+                input_3_axis_tvalid,
+                input_3_axis_tlast,
+                input_3_axis_tuser,
+                output_axis_tready);
+    $to_myhdl(input_0_axis_tready,
+              input_1_axis_tready,
+              input_2_axis_tready,
+              input_3_axis_tready,
+              output_axis_tdata,
+              output_axis_tvalid,
+              output_axis_tlast,
+              output_axis_tuser);
+
+    // dump file
+    $dumpfile("test_axis_arb_mux_4.lxt");
+    $dumpvars(0, test_axis_arb_mux_4);
+end
+
+axis_arb_mux_4 #(
+    .DATA_WIDTH(8)
+)
+UUT (
+    .clk(clk),
+    .rst(rst),
+    // AXI inputs
+    .input_0_axis_tdata(input_0_axis_tdata),
+    .input_0_axis_tvalid(input_0_axis_tvalid),
+    .input_0_axis_tready(input_0_axis_tready),
+    .input_0_axis_tlast(input_0_axis_tlast),
+    .input_0_axis_tuser(input_0_axis_tuser),
+    .input_1_axis_tdata(input_1_axis_tdata),
+    .input_1_axis_tvalid(input_1_axis_tvalid),
+    .input_1_axis_tready(input_1_axis_tready),
+    .input_1_axis_tlast(input_1_axis_tlast),
+    .input_1_axis_tuser(input_1_axis_tuser),
+    .input_2_axis_tdata(input_2_axis_tdata),
+    .input_2_axis_tvalid(input_2_axis_tvalid),
+    .input_2_axis_tready(input_2_axis_tready),
+    .input_2_axis_tlast(input_2_axis_tlast),
+    .input_2_axis_tuser(input_2_axis_tuser),
+    .input_3_axis_tdata(input_3_axis_tdata),
+    .input_3_axis_tvalid(input_3_axis_tvalid),
+    .input_3_axis_tready(input_3_axis_tready),
+    .input_3_axis_tlast(input_3_axis_tlast),
+    .input_3_axis_tuser(input_3_axis_tuser),
+    // AXI output
+    .output_axis_tdata(output_axis_tdata),
+    .output_axis_tvalid(output_axis_tvalid),
+    .output_axis_tready(output_axis_tready),
+    .output_axis_tlast(output_axis_tlast),
+    .output_axis_tuser(output_axis_tuser)
+);
+
+endmodule

lib/axis/tb/test_axis_arb_mux_64_4.py

@@ -0,0 +1,569 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+from Queue import Queue
+
+import axis_ep
+
+module = 'axis_arb_mux_64_4'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/axis_mux_64_4.v")
+srcs.append("../rtl/arbiter.v")
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("test_%s.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_axis_arb_mux_64_4(clk,
+                 rst,
+                 current_test,
+
+                 input_0_axis_tdata,
+                 input_0_axis_tkeep,
+                 input_0_axis_tvalid,
+                 input_0_axis_tready,
+                 input_0_axis_tlast,
+                 input_0_axis_tuser,
+                 input_1_axis_tdata,
+                 input_1_axis_tkeep,
+                 input_1_axis_tvalid,
+                 input_1_axis_tready,
+                 input_1_axis_tlast,
+                 input_1_axis_tuser,
+                 input_2_axis_tdata,
+                 input_2_axis_tkeep,
+                 input_2_axis_tvalid,
+                 input_2_axis_tready,
+                 input_2_axis_tlast,
+                 input_2_axis_tuser,
+                 input_3_axis_tdata,
+                 input_3_axis_tkeep,
+                 input_3_axis_tvalid,
+                 input_3_axis_tready,
+                 input_3_axis_tlast,
+                 input_3_axis_tuser,
+
+                 output_axis_tdata,
+                 output_axis_tkeep,
+                 output_axis_tvalid,
+                 output_axis_tready,
+                 output_axis_tlast,
+                 output_axis_tuser):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                input_0_axis_tdata=input_0_axis_tdata,
+                input_0_axis_tkeep=input_0_axis_tkeep,
+                input_0_axis_tvalid=input_0_axis_tvalid,
+                input_0_axis_tready=input_0_axis_tready,
+                input_0_axis_tlast=input_0_axis_tlast,
+                input_0_axis_tuser=input_0_axis_tuser,
+                input_1_axis_tdata=input_1_axis_tdata,
+                input_1_axis_tkeep=input_1_axis_tkeep,
+                input_1_axis_tvalid=input_1_axis_tvalid,
+                input_1_axis_tready=input_1_axis_tready,
+                input_1_axis_tlast=input_1_axis_tlast,
+                input_1_axis_tuser=input_1_axis_tuser,
+                input_2_axis_tdata=input_2_axis_tdata,
+                input_2_axis_tkeep=input_2_axis_tkeep,
+                input_2_axis_tvalid=input_2_axis_tvalid,
+                input_2_axis_tready=input_2_axis_tready,
+                input_2_axis_tlast=input_2_axis_tlast,
+                input_2_axis_tuser=input_2_axis_tuser,
+                input_3_axis_tdata=input_3_axis_tdata,
+                input_3_axis_tkeep=input_3_axis_tkeep,
+                input_3_axis_tvalid=input_3_axis_tvalid,
+                input_3_axis_tready=input_3_axis_tready,
+                input_3_axis_tlast=input_3_axis_tlast,
+                input_3_axis_tuser=input_3_axis_tuser,
+
+                output_axis_tdata=output_axis_tdata,
+                output_axis_tkeep=output_axis_tkeep,
+                output_axis_tvalid=output_axis_tvalid,
+                output_axis_tready=output_axis_tready,
+                output_axis_tlast=output_axis_tlast,
+                output_axis_tuser=output_axis_tuser)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    input_0_axis_tdata = Signal(intbv(0)[64:])
+    input_0_axis_tkeep = Signal(intbv(0)[8:])
+    input_0_axis_tvalid = Signal(bool(0))
+    input_0_axis_tlast = Signal(bool(0))
+    input_0_axis_tuser = Signal(bool(0))
+    input_1_axis_tdata = Signal(intbv(0)[64:])
+    input_1_axis_tkeep = Signal(intbv(0)[8:])
+    input_1_axis_tvalid = Signal(bool(0))
+    input_1_axis_tlast = Signal(bool(0))
+    input_1_axis_tuser = Signal(bool(0))
+    input_2_axis_tdata = Signal(intbv(0)[64:])
+    input_2_axis_tkeep = Signal(intbv(0)[8:])
+    input_2_axis_tvalid = Signal(bool(0))
+    input_2_axis_tlast = Signal(bool(0))
+    input_2_axis_tuser = Signal(bool(0))
+    input_3_axis_tdata = Signal(intbv(0)[64:])
+    input_3_axis_tkeep = Signal(intbv(0)[8:])
+    input_3_axis_tvalid = Signal(bool(0))
+    input_3_axis_tlast = Signal(bool(0))
+    input_3_axis_tuser = Signal(bool(0))
+
+    output_axis_tready = Signal(bool(0))
+
+    # Outputs
+    input_0_axis_tready = Signal(bool(0))
+    input_1_axis_tready = Signal(bool(0))
+    input_2_axis_tready = Signal(bool(0))
+    input_3_axis_tready = Signal(bool(0))
+
+    output_axis_tdata = Signal(intbv(0)[64:])
+    output_axis_tkeep = Signal(intbv(0)[8:])
+    output_axis_tvalid = Signal(bool(0))
+    output_axis_tlast = Signal(bool(0))
+    output_axis_tuser = Signal(bool(0))
+
+    # sources and sinks
+    source_0_queue = Queue()
+    source_0_pause = Signal(bool(0))
+    source_1_queue = Queue()
+    source_1_pause = Signal(bool(0))
+    source_2_queue = Queue()
+    source_2_pause = Signal(bool(0))
+    source_3_queue = Queue()
+    source_3_pause = Signal(bool(0))
+    sink_queue = Queue()
+    sink_pause = Signal(bool(0))
+
+    source_0 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_0_axis_tdata,
+                                       tkeep=input_0_axis_tkeep,
+                                       tvalid=input_0_axis_tvalid,
+                                       tready=input_0_axis_tready,
+                                       tlast=input_0_axis_tlast,
+                                       tuser=input_0_axis_tuser,
+                                       fifo=source_0_queue,
+                                       pause=source_0_pause,
+                                       name='source0')
+    source_1 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_1_axis_tdata,
+                                       tkeep=input_1_axis_tkeep,
+                                       tvalid=input_1_axis_tvalid,
+                                       tready=input_1_axis_tready,
+                                       tlast=input_1_axis_tlast,
+                                       tuser=input_1_axis_tuser,
+                                       fifo=source_1_queue,
+                                       pause=source_1_pause,
+                                       name='source1')
+    source_2 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_2_axis_tdata,
+                                       tkeep=input_2_axis_tkeep,
+                                       tvalid=input_2_axis_tvalid,
+                                       tready=input_2_axis_tready,
+                                       tlast=input_2_axis_tlast,
+                                       tuser=input_2_axis_tuser,
+                                       fifo=source_2_queue,
+                                       pause=source_2_pause,
+                                       name='source2')
+    source_3 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_3_axis_tdata,
+                                       tkeep=input_3_axis_tkeep,
+                                       tvalid=input_3_axis_tvalid,
+                                       tready=input_3_axis_tready,
+                                       tlast=input_3_axis_tlast,
+                                       tuser=input_3_axis_tuser,
+                                       fifo=source_3_queue,
+                                       pause=source_3_pause,
+                                       name='source3')
+
+    sink = axis_ep.AXIStreamSink(clk,
+                                 rst,
+                                 tdata=output_axis_tdata,
+                                 tkeep=output_axis_tkeep,
+                                 tvalid=output_axis_tvalid,
+                                 tready=output_axis_tready,
+                                 tlast=output_axis_tlast,
+                                 tuser=output_axis_tuser,
+                                 fifo=sink_queue,
+                                 pause=sink_pause,
+                                 name='sink')
+
+    # DUT
+    dut = dut_axis_arb_mux_64_4(clk,
+                       rst,
+                       current_test,
+
+                       input_0_axis_tdata,
+                       input_0_axis_tkeep,
+                       input_0_axis_tvalid,
+                       input_0_axis_tready,
+                       input_0_axis_tlast,
+                       input_0_axis_tuser,
+                       input_1_axis_tdata,
+                       input_1_axis_tkeep,
+                       input_1_axis_tvalid,
+                       input_1_axis_tready,
+                       input_1_axis_tlast,
+                       input_1_axis_tuser,
+                       input_2_axis_tdata,
+                       input_2_axis_tkeep,
+                       input_2_axis_tvalid,
+                       input_2_axis_tready,
+                       input_2_axis_tlast,
+                       input_2_axis_tuser,
+                       input_3_axis_tdata,
+                       input_3_axis_tkeep,
+                       input_3_axis_tvalid,
+                       input_3_axis_tready,
+                       input_3_axis_tlast,
+                       input_3_axis_tuser,
+
+                       output_axis_tdata,
+                       output_axis_tkeep,
+                       output_axis_tvalid,
+                       output_axis_tready,
+                       output_axis_tlast,
+                       output_axis_tuser)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        yield clk.posedge
+        print("test 1: port 0")
+        current_test.next = 1
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x00\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_0_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 2: port 1")
+        current_test.next = 2
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 3: back-to-back packets, same port")
+        current_test.next = 3
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x00\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x00\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_0_queue.put(test_frame1)
+        source_0_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 4: back-to-back packets, different ports")
+        current_test.next = 4
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x02\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 5: alterate pause source")
+        current_test.next = 5
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x02\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            source_0_pause.next = True
+            source_1_pause.next = True
+            source_2_pause.next = True
+            source_3_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            source_0_pause.next = False
+            source_1_pause.next = False
+            source_2_pause.next = False
+            source_3_pause.next = False
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 6: alterate pause sink")
+        current_test.next = 6
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x02\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            sink_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            sink_pause.next = False
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 4: back-to-back packets, different ports, arbitration test")
+        current_test.next = 4
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x01\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x02\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        source_1_queue.put(test_frame1)
+        source_1_queue.put(test_frame1)
+        source_1_queue.put(test_frame1)
+        source_1_queue.put(test_frame1)
+        yield clk.posedge
+
+        yield delay(150)
+        yield clk.posedge
+        source_2_queue.put(test_frame2)
+        
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_axis_arb_mux_64_4.v

@@ -0,0 +1,152 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_axis_arb_mux_64_4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [63:0] input_0_axis_tdata = 0;
+reg [7:0] input_0_axis_tkeep = 0;
+reg input_0_axis_tvalid = 0;
+reg input_0_axis_tlast = 0;
+reg input_0_axis_tuser = 0;
+reg [63:0] input_1_axis_tdata = 0;
+reg [7:0] input_1_axis_tkeep = 0;
+reg input_1_axis_tvalid = 0;
+reg input_1_axis_tlast = 0;
+reg input_1_axis_tuser = 0;
+reg [63:0] input_2_axis_tdata = 0;
+reg [7:0] input_2_axis_tkeep = 0;
+reg input_2_axis_tvalid = 0;
+reg input_2_axis_tlast = 0;
+reg input_2_axis_tuser = 0;
+reg [63:0] input_3_axis_tdata = 0;
+reg [7:0] input_3_axis_tkeep = 0;
+reg input_3_axis_tvalid = 0;
+reg input_3_axis_tlast = 0;
+reg input_3_axis_tuser = 0;
+
+reg output_axis_tready = 0;
+
+// Outputs
+wire input_0_axis_tready;
+wire input_1_axis_tready;
+wire input_2_axis_tready;
+wire input_3_axis_tready;
+
+wire [63:0] output_axis_tdata;
+wire [7:0] output_axis_tkeep;
+wire output_axis_tvalid;
+wire output_axis_tlast;
+wire output_axis_tuser;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                input_0_axis_tdata,
+                input_0_axis_tkeep,
+                input_0_axis_tvalid,
+                input_0_axis_tlast,
+                input_0_axis_tuser,
+                input_1_axis_tdata,
+                input_1_axis_tkeep,
+                input_1_axis_tvalid,
+                input_1_axis_tlast,
+                input_1_axis_tuser,
+                input_2_axis_tdata,
+                input_2_axis_tkeep,
+                input_2_axis_tvalid,
+                input_2_axis_tlast,
+                input_2_axis_tuser,
+                input_3_axis_tdata,
+                input_3_axis_tkeep,
+                input_3_axis_tvalid,
+                input_3_axis_tlast,
+                input_3_axis_tuser,
+                output_axis_tready);
+    $to_myhdl(input_0_axis_tready,
+              input_1_axis_tready,
+              input_2_axis_tready,
+              input_3_axis_tready,
+              output_axis_tdata,
+              output_axis_tkeep,
+              output_axis_tvalid,
+              output_axis_tlast,
+              output_axis_tuser);
+
+    // dump file
+    $dumpfile("test_axis_arb_mux_64_4.lxt");
+    $dumpvars(0, test_axis_arb_mux_64_4);
+end
+
+axis_arb_mux_64_4 #(
+    .DATA_WIDTH(64)
+)
+UUT (
+    .clk(clk),
+    .rst(rst),
+    // AXI inputs
+    .input_0_axis_tdata(input_0_axis_tdata),
+    .input_0_axis_tkeep(input_0_axis_tkeep),
+    .input_0_axis_tvalid(input_0_axis_tvalid),
+    .input_0_axis_tready(input_0_axis_tready),
+    .input_0_axis_tlast(input_0_axis_tlast),
+    .input_0_axis_tuser(input_0_axis_tuser),
+    .input_1_axis_tdata(input_1_axis_tdata),
+    .input_1_axis_tkeep(input_1_axis_tkeep),
+    .input_1_axis_tvalid(input_1_axis_tvalid),
+    .input_1_axis_tready(input_1_axis_tready),
+    .input_1_axis_tlast(input_1_axis_tlast),
+    .input_1_axis_tuser(input_1_axis_tuser),
+    .input_2_axis_tdata(input_2_axis_tdata),
+    .input_2_axis_tkeep(input_2_axis_tkeep),
+    .input_2_axis_tvalid(input_2_axis_tvalid),
+    .input_2_axis_tready(input_2_axis_tready),
+    .input_2_axis_tlast(input_2_axis_tlast),
+    .input_2_axis_tuser(input_2_axis_tuser),
+    .input_3_axis_tdata(input_3_axis_tdata),
+    .input_3_axis_tkeep(input_3_axis_tkeep),
+    .input_3_axis_tvalid(input_3_axis_tvalid),
+    .input_3_axis_tready(input_3_axis_tready),
+    .input_3_axis_tlast(input_3_axis_tlast),
+    .input_3_axis_tuser(input_3_axis_tuser),
+    // AXI output
+    .output_axis_tdata(output_axis_tdata),
+    .output_axis_tkeep(output_axis_tkeep),
+    .output_axis_tvalid(output_axis_tvalid),
+    .output_axis_tready(output_axis_tready),
+    .output_axis_tlast(output_axis_tlast),
+    .output_axis_tuser(output_axis_tuser)
+);
+
+endmodule

lib/axis/tb/test_axis_demux_4.py

@@ -0,0 +1,500 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+from Queue import Queue
+
+import axis_ep
+
+module = 'axis_demux_4'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("test_%s.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_axis_demux_4(clk,
+                 rst,
+                 current_test,
+
+                 input_axis_tdata,
+                 input_axis_tvalid,
+                 input_axis_tready,
+                 input_axis_tlast,
+                 input_axis_tuser,
+
+                 output_0_axis_tdata,
+                 output_0_axis_tvalid,
+                 output_0_axis_tready,
+                 output_0_axis_tlast,
+                 output_0_axis_tuser,
+                 output_1_axis_tdata,
+                 output_1_axis_tvalid,
+                 output_1_axis_tready,
+                 output_1_axis_tlast,
+                 output_1_axis_tuser,
+                 output_2_axis_tdata,
+                 output_2_axis_tvalid,
+                 output_2_axis_tready,
+                 output_2_axis_tlast,
+                 output_2_axis_tuser,
+                 output_3_axis_tdata,
+                 output_3_axis_tvalid,
+                 output_3_axis_tready,
+                 output_3_axis_tlast,
+                 output_3_axis_tuser,
+
+                 select):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                input_axis_tdata=input_axis_tdata,
+                input_axis_tvalid=input_axis_tvalid,
+                input_axis_tready=input_axis_tready,
+                input_axis_tlast=input_axis_tlast,
+                input_axis_tuser=input_axis_tuser,
+
+                output_0_axis_tdata=output_0_axis_tdata,
+                output_0_axis_tvalid=output_0_axis_tvalid,
+                output_0_axis_tready=output_0_axis_tready,
+                output_0_axis_tlast=output_0_axis_tlast,
+                output_0_axis_tuser=output_0_axis_tuser,
+                output_1_axis_tdata=output_1_axis_tdata,
+                output_1_axis_tvalid=output_1_axis_tvalid,
+                output_1_axis_tready=output_1_axis_tready,
+                output_1_axis_tlast=output_1_axis_tlast,
+                output_1_axis_tuser=output_1_axis_tuser,
+                output_2_axis_tdata=output_2_axis_tdata,
+                output_2_axis_tvalid=output_2_axis_tvalid,
+                output_2_axis_tready=output_2_axis_tready,
+                output_2_axis_tlast=output_2_axis_tlast,
+                output_2_axis_tuser=output_2_axis_tuser,
+                output_3_axis_tdata=output_3_axis_tdata,
+                output_3_axis_tvalid=output_3_axis_tvalid,
+                output_3_axis_tready=output_3_axis_tready,
+                output_3_axis_tlast=output_3_axis_tlast,
+                output_3_axis_tuser=output_3_axis_tuser,
+
+                select=select)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    input_axis_tdata = Signal(intbv(0)[8:])
+    input_axis_tvalid = Signal(bool(0))
+    input_axis_tlast = Signal(bool(0))
+    input_axis_tuser = Signal(bool(0))
+    
+    output_0_axis_tready = Signal(bool(0))
+    output_1_axis_tready = Signal(bool(0))
+    output_2_axis_tready = Signal(bool(0))
+    output_3_axis_tready = Signal(bool(0))
+
+    select = Signal(intbv(0)[2:])
+
+    # Outputs
+    input_axis_tready = Signal(bool(0))
+
+    output_0_axis_tdata = Signal(intbv(0)[8:])
+    output_0_axis_tvalid = Signal(bool(0))
+    output_0_axis_tlast = Signal(bool(0))
+    output_0_axis_tuser = Signal(bool(0))
+    output_1_axis_tdata = Signal(intbv(0)[8:])
+    output_1_axis_tvalid = Signal(bool(0))
+    output_1_axis_tlast = Signal(bool(0))
+    output_1_axis_tuser = Signal(bool(0))
+    output_2_axis_tdata = Signal(intbv(0)[8:])
+    output_2_axis_tvalid = Signal(bool(0))
+    output_2_axis_tlast = Signal(bool(0))
+    output_2_axis_tuser = Signal(bool(0))
+    output_3_axis_tdata = Signal(intbv(0)[8:])
+    output_3_axis_tvalid = Signal(bool(0))
+    output_3_axis_tlast = Signal(bool(0))
+    output_3_axis_tuser = Signal(bool(0))
+
+    # sources and sinks
+    source_queue = Queue()
+    source_pause = Signal(bool(0))
+    sink_0_queue = Queue()
+    sink_0_pause = Signal(bool(0))
+    sink_1_queue = Queue()
+    sink_1_pause = Signal(bool(0))
+    sink_2_queue = Queue()
+    sink_2_pause = Signal(bool(0))
+    sink_3_queue = Queue()
+    sink_3_pause = Signal(bool(0))
+
+    source = axis_ep.AXIStreamSource(clk,
+                                     rst,
+                                     tdata=input_axis_tdata,
+                                     tvalid=input_axis_tvalid,
+                                     tready=input_axis_tready,
+                                     tlast=input_axis_tlast,
+                                     tuser=input_axis_tuser,
+                                     fifo=source_queue,
+                                     pause=source_pause,
+                                     name='source')
+
+    sink_0 = axis_ep.AXIStreamSink(clk,
+                                   rst,
+                                   tdata=output_0_axis_tdata,
+                                   tvalid=output_0_axis_tvalid,
+                                   tready=output_0_axis_tready,
+                                   tlast=output_0_axis_tlast,
+                                   tuser=output_0_axis_tuser,
+                                   fifo=sink_0_queue,
+                                   pause=sink_0_pause,
+                                   name='sink0')
+
+    sink_1 = axis_ep.AXIStreamSink(clk,
+                                   rst,
+                                   tdata=output_1_axis_tdata,
+                                   tvalid=output_1_axis_tvalid,
+                                   tready=output_1_axis_tready,
+                                   tlast=output_1_axis_tlast,
+                                   tuser=output_1_axis_tuser,
+                                   fifo=sink_1_queue,
+                                   pause=sink_1_pause,
+                                   name='sink1')
+
+    sink_2 = axis_ep.AXIStreamSink(clk,
+                                   rst,
+                                   tdata=output_2_axis_tdata,
+                                   tvalid=output_2_axis_tvalid,
+                                   tready=output_2_axis_tready,
+                                   tlast=output_2_axis_tlast,
+                                   tuser=output_2_axis_tuser,
+                                   fifo=sink_2_queue,
+                                   pause=sink_2_pause,
+                                   name='sink2')
+
+    sink_3 = axis_ep.AXIStreamSink(clk,
+                                   rst,
+                                   tdata=output_3_axis_tdata,
+                                   tvalid=output_3_axis_tvalid,
+                                   tready=output_3_axis_tready,
+                                   tlast=output_3_axis_tlast,
+                                   tuser=output_3_axis_tuser,
+                                   fifo=sink_3_queue,
+                                   pause=sink_3_pause,
+                                   name='sink3')
+
+    # DUT
+    dut = dut_axis_demux_4(clk,
+                       rst,
+                       current_test,
+
+                       input_axis_tdata,
+                       input_axis_tvalid,
+                       input_axis_tready,
+                       input_axis_tlast,
+                       input_axis_tuser,
+
+                       output_0_axis_tdata,
+                       output_0_axis_tvalid,
+                       output_0_axis_tready,
+                       output_0_axis_tlast,
+                       output_0_axis_tuser,
+                       output_1_axis_tdata,
+                       output_1_axis_tvalid,
+                       output_1_axis_tready,
+                       output_1_axis_tlast,
+                       output_1_axis_tuser,
+                       output_2_axis_tdata,
+                       output_2_axis_tvalid,
+                       output_2_axis_tready,
+                       output_2_axis_tlast,
+                       output_2_axis_tuser,
+                       output_3_axis_tdata,
+                       output_3_axis_tvalid,
+                       output_3_axis_tready,
+                       output_3_axis_tlast,
+                       output_3_axis_tuser,
+
+                       select)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        yield clk.posedge
+        print("test 1: select port 0")
+        current_test.next = 1
+
+        select.next = 0
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_0_queue.empty():
+            rx_frame = sink_0_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 2: select port 1")
+        current_test.next = 2
+
+        select.next = 1
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_1_queue.empty():
+            rx_frame = sink_1_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 3: back-to-back packets, same port")
+        current_test.next = 3
+
+        select.next = 0
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame1)
+        source_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_0_queue.empty():
+            rx_frame = sink_0_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_0_queue.empty():
+            rx_frame = sink_0_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 4: back-to-back packets, different ports")
+        current_test.next = 4
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame1)
+        source_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_2_queue.empty():
+            rx_frame = sink_1_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_2_queue.empty():
+            rx_frame = sink_2_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 5: alterate pause source")
+        current_test.next = 5
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame1)
+        source_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            source_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            source_pause.next = False
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_1_queue.empty():
+            rx_frame = sink_1_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_2_queue.empty():
+            rx_frame = sink_2_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 6: alterate pause sink")
+        current_test.next = 6
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame1)
+        source_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            sink_0_pause.next = True
+            sink_1_pause.next = True
+            sink_2_pause.next = True
+            sink_3_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            sink_0_pause.next = False
+            sink_1_pause.next = False
+            sink_2_pause.next = False
+            sink_3_pause.next = False
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_1_queue.empty():
+            rx_frame = sink_1_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_2_queue.empty():
+            rx_frame = sink_2_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, source, sink_0, sink_1, sink_2, sink_3, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_axis_demux_4.v

@@ -0,0 +1,142 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_axis_demux_4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [7:0] input_axis_tdata = 0;
+reg input_axis_tvalid = 0;
+reg input_axis_tlast = 0;
+reg input_axis_tuser = 0;
+
+reg output_0_axis_tready = 0;
+reg output_1_axis_tready = 0;
+reg output_2_axis_tready = 0;
+reg output_3_axis_tready = 0;
+
+reg [1:0] select = 0;
+
+// Outputs
+wire input_axis_tready;
+
+wire [7:0] output_0_axis_tdata;
+wire output_0_axis_tvalid;
+wire output_0_axis_tlast;
+wire output_0_axis_tuser;
+wire [7:0] output_1_axis_tdata;
+wire output_1_axis_tvalid;
+wire output_1_axis_tlast;
+wire output_1_axis_tuser;
+wire [7:0] output_2_axis_tdata;
+wire output_2_axis_tvalid;
+wire output_2_axis_tlast;
+wire output_2_axis_tuser;
+wire [7:0] output_3_axis_tdata;
+wire output_3_axis_tvalid;
+wire output_3_axis_tlast;
+wire output_3_axis_tuser;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                input_axis_tdata,
+                input_axis_tvalid,
+                input_axis_tlast,
+                input_axis_tuser,
+                output_0_axis_tready,
+                output_1_axis_tready,
+                output_2_axis_tready,
+                output_3_axis_tready,
+                select);
+    $to_myhdl(input_axis_tready,
+              output_0_axis_tdata,
+              output_0_axis_tvalid,
+              output_0_axis_tlast,
+              output_0_axis_tuser,
+              output_1_axis_tdata,
+              output_1_axis_tvalid,
+              output_1_axis_tlast,
+              output_1_axis_tuser,
+              output_2_axis_tdata,
+              output_2_axis_tvalid,
+              output_2_axis_tlast,
+              output_2_axis_tuser,
+              output_3_axis_tdata,
+              output_3_axis_tvalid,
+              output_3_axis_tlast,
+              output_3_axis_tuser);
+
+    // dump file
+    $dumpfile("test_axis_demux_4.lxt");
+    $dumpvars(0, test_axis_demux_4);
+end
+
+axis_demux_4 #(
+    .DATA_WIDTH(8)
+)
+UUT (
+    .clk(clk),
+    .rst(rst),
+    // AXI input
+    .input_axis_tdata(input_axis_tdata),
+    .input_axis_tvalid(input_axis_tvalid),
+    .input_axis_tready(input_axis_tready),
+    .input_axis_tlast(input_axis_tlast),
+    .input_axis_tuser(input_axis_tuser),
+    // AXI outputs
+    .output_0_axis_tdata(output_0_axis_tdata),
+    .output_0_axis_tvalid(output_0_axis_tvalid),
+    .output_0_axis_tready(output_0_axis_tready),
+    .output_0_axis_tlast(output_0_axis_tlast),
+    .output_0_axis_tuser(output_0_axis_tuser),
+    .output_1_axis_tdata(output_1_axis_tdata),
+    .output_1_axis_tvalid(output_1_axis_tvalid),
+    .output_1_axis_tready(output_1_axis_tready),
+    .output_1_axis_tlast(output_1_axis_tlast),
+    .output_1_axis_tuser(output_1_axis_tuser),
+    .output_2_axis_tdata(output_2_axis_tdata),
+    .output_2_axis_tvalid(output_2_axis_tvalid),
+    .output_2_axis_tready(output_2_axis_tready),
+    .output_2_axis_tlast(output_2_axis_tlast),
+    .output_2_axis_tuser(output_2_axis_tuser),
+    .output_3_axis_tdata(output_3_axis_tdata),
+    .output_3_axis_tvalid(output_3_axis_tvalid),
+    .output_3_axis_tready(output_3_axis_tready),
+    .output_3_axis_tlast(output_3_axis_tlast),
+    .output_3_axis_tuser(output_3_axis_tuser),
+    // Control
+    .select(select)
+);
+
+endmodule

lib/axis/tb/test_axis_demux_64_4.py

@@ -0,0 +1,525 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+from Queue import Queue
+
+import axis_ep
+
+module = 'axis_demux_64_4'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("test_%s.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_axis_demux_64_4(clk,
+                 rst,
+                 current_test,
+
+                 input_axis_tdata,
+                 input_axis_tkeep,
+                 input_axis_tvalid,
+                 input_axis_tready,
+                 input_axis_tlast,
+                 input_axis_tuser,
+
+                 output_0_axis_tdata,
+                 output_0_axis_tkeep,
+                 output_0_axis_tvalid,
+                 output_0_axis_tready,
+                 output_0_axis_tlast,
+                 output_0_axis_tuser,
+                 output_1_axis_tdata,
+                 output_1_axis_tkeep,
+                 output_1_axis_tvalid,
+                 output_1_axis_tready,
+                 output_1_axis_tlast,
+                 output_1_axis_tuser,
+                 output_2_axis_tdata,
+                 output_2_axis_tkeep,
+                 output_2_axis_tvalid,
+                 output_2_axis_tready,
+                 output_2_axis_tlast,
+                 output_2_axis_tuser,
+                 output_3_axis_tdata,
+                 output_3_axis_tkeep,
+                 output_3_axis_tvalid,
+                 output_3_axis_tready,
+                 output_3_axis_tlast,
+                 output_3_axis_tuser,
+
+                 select):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                input_axis_tdata=input_axis_tdata,
+                input_axis_tkeep=input_axis_tkeep,
+                input_axis_tvalid=input_axis_tvalid,
+                input_axis_tready=input_axis_tready,
+                input_axis_tlast=input_axis_tlast,
+                input_axis_tuser=input_axis_tuser,
+
+                output_0_axis_tdata=output_0_axis_tdata,
+                output_0_axis_tkeep=output_0_axis_tkeep,
+                output_0_axis_tvalid=output_0_axis_tvalid,
+                output_0_axis_tready=output_0_axis_tready,
+                output_0_axis_tlast=output_0_axis_tlast,
+                output_0_axis_tuser=output_0_axis_tuser,
+                output_1_axis_tdata=output_1_axis_tdata,
+                output_1_axis_tkeep=output_1_axis_tkeep,
+                output_1_axis_tvalid=output_1_axis_tvalid,
+                output_1_axis_tready=output_1_axis_tready,
+                output_1_axis_tlast=output_1_axis_tlast,
+                output_1_axis_tuser=output_1_axis_tuser,
+                output_2_axis_tdata=output_2_axis_tdata,
+                output_2_axis_tkeep=output_2_axis_tkeep,
+                output_2_axis_tvalid=output_2_axis_tvalid,
+                output_2_axis_tready=output_2_axis_tready,
+                output_2_axis_tlast=output_2_axis_tlast,
+                output_2_axis_tuser=output_2_axis_tuser,
+                output_3_axis_tdata=output_3_axis_tdata,
+                output_3_axis_tkeep=output_3_axis_tkeep,
+                output_3_axis_tvalid=output_3_axis_tvalid,
+                output_3_axis_tready=output_3_axis_tready,
+                output_3_axis_tlast=output_3_axis_tlast,
+                output_3_axis_tuser=output_3_axis_tuser,
+
+                select=select)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    input_axis_tdata = Signal(intbv(0)[64:])
+    input_axis_tkeep = Signal(intbv(0)[8:])
+    input_axis_tvalid = Signal(bool(0))
+    input_axis_tlast = Signal(bool(0))
+    input_axis_tuser = Signal(bool(0))
+    
+    output_0_axis_tready = Signal(bool(0))
+    output_1_axis_tready = Signal(bool(0))
+    output_2_axis_tready = Signal(bool(0))
+    output_3_axis_tready = Signal(bool(0))
+
+    select = Signal(intbv(0)[2:])
+
+    # Outputs
+    input_axis_tready = Signal(bool(0))
+
+    output_0_axis_tdata = Signal(intbv(0)[64:])
+    output_0_axis_tkeep = Signal(intbv(0)[8:])
+    output_0_axis_tvalid = Signal(bool(0))
+    output_0_axis_tlast = Signal(bool(0))
+    output_0_axis_tuser = Signal(bool(0))
+    output_1_axis_tdata = Signal(intbv(0)[64:])
+    output_1_axis_tkeep = Signal(intbv(0)[8:])
+    output_1_axis_tvalid = Signal(bool(0))
+    output_1_axis_tlast = Signal(bool(0))
+    output_1_axis_tuser = Signal(bool(0))
+    output_2_axis_tdata = Signal(intbv(0)[64:])
+    output_2_axis_tkeep = Signal(intbv(0)[8:])
+    output_2_axis_tvalid = Signal(bool(0))
+    output_2_axis_tlast = Signal(bool(0))
+    output_2_axis_tuser = Signal(bool(0))
+    output_3_axis_tdata = Signal(intbv(0)[64:])
+    output_3_axis_tkeep = Signal(intbv(0)[8:])
+    output_3_axis_tvalid = Signal(bool(0))
+    output_3_axis_tlast = Signal(bool(0))
+    output_3_axis_tuser = Signal(bool(0))
+
+    # sources and sinks
+    source_queue = Queue()
+    source_pause = Signal(bool(0))
+    sink_0_queue = Queue()
+    sink_0_pause = Signal(bool(0))
+    sink_1_queue = Queue()
+    sink_1_pause = Signal(bool(0))
+    sink_2_queue = Queue()
+    sink_2_pause = Signal(bool(0))
+    sink_3_queue = Queue()
+    sink_3_pause = Signal(bool(0))
+
+    source = axis_ep.AXIStreamSource(clk,
+                                     rst,
+                                     tdata=input_axis_tdata,
+                                     tkeep=input_axis_tkeep,
+                                     tvalid=input_axis_tvalid,
+                                     tready=input_axis_tready,
+                                     tlast=input_axis_tlast,
+                                     tuser=input_axis_tuser,
+                                     fifo=source_queue,
+                                     pause=source_pause,
+                                     name='source')
+
+    sink_0 = axis_ep.AXIStreamSink(clk,
+                                   rst,
+                                   tdata=output_0_axis_tdata,
+                                   tkeep=output_0_axis_tkeep,
+                                   tvalid=output_0_axis_tvalid,
+                                   tready=output_0_axis_tready,
+                                   tlast=output_0_axis_tlast,
+                                   tuser=output_0_axis_tuser,
+                                   fifo=sink_0_queue,
+                                   pause=sink_0_pause,
+                                   name='sink0')
+
+    sink_1 = axis_ep.AXIStreamSink(clk,
+                                   rst,
+                                   tdata=output_1_axis_tdata,
+                                   tkeep=output_1_axis_tkeep,
+                                   tvalid=output_1_axis_tvalid,
+                                   tready=output_1_axis_tready,
+                                   tlast=output_1_axis_tlast,
+                                   tuser=output_1_axis_tuser,
+                                   fifo=sink_1_queue,
+                                   pause=sink_1_pause,
+                                   name='sink1')
+
+    sink_2 = axis_ep.AXIStreamSink(clk,
+                                   rst,
+                                   tdata=output_2_axis_tdata,
+                                   tkeep=output_2_axis_tkeep,
+                                   tvalid=output_2_axis_tvalid,
+                                   tready=output_2_axis_tready,
+                                   tlast=output_2_axis_tlast,
+                                   tuser=output_2_axis_tuser,
+                                   fifo=sink_2_queue,
+                                   pause=sink_2_pause,
+                                   name='sink2')
+
+    sink_3 = axis_ep.AXIStreamSink(clk,
+                                   rst,
+                                   tdata=output_3_axis_tdata,
+                                   tkeep=output_3_axis_tkeep,
+                                   tvalid=output_3_axis_tvalid,
+                                   tready=output_3_axis_tready,
+                                   tlast=output_3_axis_tlast,
+                                   tuser=output_3_axis_tuser,
+                                   fifo=sink_3_queue,
+                                   pause=sink_3_pause,
+                                   name='sink3')
+
+    # DUT
+    dut = dut_axis_demux_64_4(clk,
+                       rst,
+                       current_test,
+
+                       input_axis_tdata,
+                       input_axis_tkeep,
+                       input_axis_tvalid,
+                       input_axis_tready,
+                       input_axis_tlast,
+                       input_axis_tuser,
+
+                       output_0_axis_tdata,
+                       output_0_axis_tkeep,
+                       output_0_axis_tvalid,
+                       output_0_axis_tready,
+                       output_0_axis_tlast,
+                       output_0_axis_tuser,
+                       output_1_axis_tdata,
+                       output_1_axis_tkeep,
+                       output_1_axis_tvalid,
+                       output_1_axis_tready,
+                       output_1_axis_tlast,
+                       output_1_axis_tuser,
+                       output_2_axis_tdata,
+                       output_2_axis_tkeep,
+                       output_2_axis_tvalid,
+                       output_2_axis_tready,
+                       output_2_axis_tlast,
+                       output_2_axis_tuser,
+                       output_3_axis_tdata,
+                       output_3_axis_tkeep,
+                       output_3_axis_tvalid,
+                       output_3_axis_tready,
+                       output_3_axis_tlast,
+                       output_3_axis_tuser,
+
+                       select)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        yield clk.posedge
+        print("test 1: select port 0")
+        current_test.next = 1
+
+        select.next = 0
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_0_queue.empty():
+            rx_frame = sink_0_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 2: select port 1")
+        current_test.next = 2
+
+        select.next = 1
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_1_queue.empty():
+            rx_frame = sink_1_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 3: back-to-back packets, same port")
+        current_test.next = 3
+
+        select.next = 0
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame1)
+        source_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_0_queue.empty():
+            rx_frame = sink_0_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_0_queue.empty():
+            rx_frame = sink_0_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 4: back-to-back packets, different ports")
+        current_test.next = 4
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame1)
+        source_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_2_queue.empty():
+            rx_frame = sink_1_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_2_queue.empty():
+            rx_frame = sink_2_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 5: alterate pause source")
+        current_test.next = 5
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame1)
+        source_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            source_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            source_pause.next = False
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_1_queue.empty():
+            rx_frame = sink_1_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_2_queue.empty():
+            rx_frame = sink_2_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 6: alterate pause sink")
+        current_test.next = 6
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_queue.put(test_frame1)
+        source_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_axis_tvalid:
+            sink_0_pause.next = True
+            sink_1_pause.next = True
+            sink_2_pause.next = True
+            sink_3_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            sink_0_pause.next = False
+            sink_1_pause.next = False
+            sink_2_pause.next = False
+            sink_3_pause.next = False
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_1_queue.empty():
+            rx_frame = sink_1_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_2_queue.empty():
+            rx_frame = sink_2_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, source, sink_0, sink_1, sink_2, sink_3, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_axis_demux_64_4.v

@@ -0,0 +1,157 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_axis_demux_64_4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [63:0] input_axis_tdata = 0;
+reg [7:0] input_axis_tkeep = 0;
+reg input_axis_tvalid = 0;
+reg input_axis_tlast = 0;
+reg input_axis_tuser = 0;
+
+reg output_0_axis_tready = 0;
+reg output_1_axis_tready = 0;
+reg output_2_axis_tready = 0;
+reg output_3_axis_tready = 0;
+
+reg [1:0] select = 0;
+
+// Outputs
+wire input_axis_tready;
+
+wire [63:0] output_0_axis_tdata;
+wire [7:0] output_0_axis_tkeep;
+wire output_0_axis_tvalid;
+wire output_0_axis_tlast;
+wire output_0_axis_tuser;
+wire [63:0] output_1_axis_tdata;
+wire [7:0] output_1_axis_tkeep;
+wire output_1_axis_tvalid;
+wire output_1_axis_tlast;
+wire output_1_axis_tuser;
+wire [63:0] output_2_axis_tdata;
+wire [7:0] output_2_axis_tkeep;
+wire output_2_axis_tvalid;
+wire output_2_axis_tlast;
+wire output_2_axis_tuser;
+wire [63:0] output_3_axis_tdata;
+wire [7:0] output_3_axis_tkeep;
+wire output_3_axis_tvalid;
+wire output_3_axis_tlast;
+wire output_3_axis_tuser;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                input_axis_tdata,
+                input_axis_tkeep,
+                input_axis_tvalid,
+                input_axis_tlast,
+                input_axis_tuser,
+                output_0_axis_tready,
+                output_1_axis_tready,
+                output_2_axis_tready,
+                output_3_axis_tready,
+                select);
+    $to_myhdl(input_axis_tready,
+              output_0_axis_tdata,
+              output_0_axis_tkeep,
+              output_0_axis_tvalid,
+              output_0_axis_tlast,
+              output_0_axis_tuser,
+              output_1_axis_tdata,
+              output_1_axis_tkeep,
+              output_1_axis_tvalid,
+              output_1_axis_tlast,
+              output_1_axis_tuser,
+              output_2_axis_tdata,
+              output_2_axis_tkeep,
+              output_2_axis_tvalid,
+              output_2_axis_tlast,
+              output_2_axis_tuser,
+              output_3_axis_tdata,
+              output_3_axis_tkeep,
+              output_3_axis_tvalid,
+              output_3_axis_tlast,
+              output_3_axis_tuser);
+
+    // dump file
+    $dumpfile("test_axis_demux_64_4.lxt");
+    $dumpvars(0, test_axis_demux_64_4);
+end
+
+axis_demux_64_4 #(
+    .DATA_WIDTH(64)
+)
+UUT (
+    .clk(clk),
+    .rst(rst),
+    // AXI input
+    .input_axis_tdata(input_axis_tdata),
+    .input_axis_tkeep(input_axis_tkeep),
+    .input_axis_tvalid(input_axis_tvalid),
+    .input_axis_tready(input_axis_tready),
+    .input_axis_tlast(input_axis_tlast),
+    .input_axis_tuser(input_axis_tuser),
+    // AXI outputs
+    .output_0_axis_tdata(output_0_axis_tdata),
+    .output_0_axis_tkeep(output_0_axis_tkeep),
+    .output_0_axis_tvalid(output_0_axis_tvalid),
+    .output_0_axis_tready(output_0_axis_tready),
+    .output_0_axis_tlast(output_0_axis_tlast),
+    .output_0_axis_tuser(output_0_axis_tuser),
+    .output_1_axis_tdata(output_1_axis_tdata),
+    .output_1_axis_tkeep(output_1_axis_tkeep),
+    .output_1_axis_tvalid(output_1_axis_tvalid),
+    .output_1_axis_tready(output_1_axis_tready),
+    .output_1_axis_tlast(output_1_axis_tlast),
+    .output_1_axis_tuser(output_1_axis_tuser),
+    .output_2_axis_tdata(output_2_axis_tdata),
+    .output_2_axis_tkeep(output_2_axis_tkeep),
+    .output_2_axis_tvalid(output_2_axis_tvalid),
+    .output_2_axis_tready(output_2_axis_tready),
+    .output_2_axis_tlast(output_2_axis_tlast),
+    .output_2_axis_tuser(output_2_axis_tuser),
+    .output_3_axis_tdata(output_3_axis_tdata),
+    .output_3_axis_tkeep(output_3_axis_tkeep),
+    .output_3_axis_tvalid(output_3_axis_tvalid),
+    .output_3_axis_tready(output_3_axis_tready),
+    .output_3_axis_tlast(output_3_axis_tlast),
+    .output_3_axis_tuser(output_3_axis_tuser),
+    // Control
+    .select(select)
+);
+
+endmodule

lib/axis/tb/test_axis_mux_4.py

@@ -0,0 +1,497 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+from Queue import Queue
+
+import axis_ep
+
+module = 'axis_mux_4'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("test_%s.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_axis_mux_4(clk,
+                 rst,
+                 current_test,
+
+                 input_0_axis_tdata,
+                 input_0_axis_tvalid,
+                 input_0_axis_tready,
+                 input_0_axis_tlast,
+                 input_0_axis_tuser,
+                 input_1_axis_tdata,
+                 input_1_axis_tvalid,
+                 input_1_axis_tready,
+                 input_1_axis_tlast,
+                 input_1_axis_tuser,
+                 input_2_axis_tdata,
+                 input_2_axis_tvalid,
+                 input_2_axis_tready,
+                 input_2_axis_tlast,
+                 input_2_axis_tuser,
+                 input_3_axis_tdata,
+                 input_3_axis_tvalid,
+                 input_3_axis_tready,
+                 input_3_axis_tlast,
+                 input_3_axis_tuser,
+
+                 output_axis_tdata,
+                 output_axis_tvalid,
+                 output_axis_tready,
+                 output_axis_tlast,
+                 output_axis_tuser,
+
+                 select):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                input_0_axis_tdata=input_0_axis_tdata,
+                input_0_axis_tvalid=input_0_axis_tvalid,
+                input_0_axis_tready=input_0_axis_tready,
+                input_0_axis_tlast=input_0_axis_tlast,
+                input_0_axis_tuser=input_0_axis_tuser,
+                input_1_axis_tdata=input_1_axis_tdata,
+                input_1_axis_tvalid=input_1_axis_tvalid,
+                input_1_axis_tready=input_1_axis_tready,
+                input_1_axis_tlast=input_1_axis_tlast,
+                input_1_axis_tuser=input_1_axis_tuser,
+                input_2_axis_tdata=input_2_axis_tdata,
+                input_2_axis_tvalid=input_2_axis_tvalid,
+                input_2_axis_tready=input_2_axis_tready,
+                input_2_axis_tlast=input_2_axis_tlast,
+                input_2_axis_tuser=input_2_axis_tuser,
+                input_3_axis_tdata=input_3_axis_tdata,
+                input_3_axis_tvalid=input_3_axis_tvalid,
+                input_3_axis_tready=input_3_axis_tready,
+                input_3_axis_tlast=input_3_axis_tlast,
+                input_3_axis_tuser=input_3_axis_tuser,
+
+                output_axis_tdata=output_axis_tdata,
+                output_axis_tvalid=output_axis_tvalid,
+                output_axis_tready=output_axis_tready,
+                output_axis_tlast=output_axis_tlast,
+                output_axis_tuser=output_axis_tuser,
+
+                select=select)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    input_0_axis_tdata = Signal(intbv(0)[8:])
+    input_0_axis_tvalid = Signal(bool(0))
+    input_0_axis_tlast = Signal(bool(0))
+    input_0_axis_tuser = Signal(bool(0))
+    input_1_axis_tdata = Signal(intbv(0)[8:])
+    input_1_axis_tvalid = Signal(bool(0))
+    input_1_axis_tlast = Signal(bool(0))
+    input_1_axis_tuser = Signal(bool(0))
+    input_2_axis_tdata = Signal(intbv(0)[8:])
+    input_2_axis_tvalid = Signal(bool(0))
+    input_2_axis_tlast = Signal(bool(0))
+    input_2_axis_tuser = Signal(bool(0))
+    input_3_axis_tdata = Signal(intbv(0)[8:])
+    input_3_axis_tvalid = Signal(bool(0))
+    input_3_axis_tlast = Signal(bool(0))
+    input_3_axis_tuser = Signal(bool(0))
+
+    output_axis_tready = Signal(bool(0))
+
+    select = Signal(intbv(0)[2:])
+
+    # Outputs
+    input_0_axis_tready = Signal(bool(0))
+    input_1_axis_tready = Signal(bool(0))
+    input_2_axis_tready = Signal(bool(0))
+    input_3_axis_tready = Signal(bool(0))
+
+    output_axis_tdata = Signal(intbv(0)[8:])
+    output_axis_tvalid = Signal(bool(0))
+    output_axis_tlast = Signal(bool(0))
+    output_axis_tuser = Signal(bool(0))
+
+    # sources and sinks
+    source_0_queue = Queue()
+    source_0_pause = Signal(bool(0))
+    source_1_queue = Queue()
+    source_1_pause = Signal(bool(0))
+    source_2_queue = Queue()
+    source_2_pause = Signal(bool(0))
+    source_3_queue = Queue()
+    source_3_pause = Signal(bool(0))
+    sink_queue = Queue()
+    sink_pause = Signal(bool(0))
+
+    source_0 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_0_axis_tdata,
+                                       tvalid=input_0_axis_tvalid,
+                                       tready=input_0_axis_tready,
+                                       tlast=input_0_axis_tlast,
+                                       tuser=input_0_axis_tuser,
+                                       fifo=source_0_queue,
+                                       pause=source_0_pause,
+                                       name='source0')
+    source_1 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_1_axis_tdata,
+                                       tvalid=input_1_axis_tvalid,
+                                       tready=input_1_axis_tready,
+                                       tlast=input_1_axis_tlast,
+                                       tuser=input_1_axis_tuser,
+                                       fifo=source_1_queue,
+                                       pause=source_1_pause,
+                                       name='source1')
+    source_2 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_2_axis_tdata,
+                                       tvalid=input_2_axis_tvalid,
+                                       tready=input_2_axis_tready,
+                                       tlast=input_2_axis_tlast,
+                                       tuser=input_2_axis_tuser,
+                                       fifo=source_2_queue,
+                                       pause=source_2_pause,
+                                       name='source2')
+    source_3 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_3_axis_tdata,
+                                       tvalid=input_3_axis_tvalid,
+                                       tready=input_3_axis_tready,
+                                       tlast=input_3_axis_tlast,
+                                       tuser=input_3_axis_tuser,
+                                       fifo=source_3_queue,
+                                       pause=source_3_pause,
+                                       name='source3')
+
+    sink = axis_ep.AXIStreamSink(clk,
+                                 rst,
+                                 tdata=output_axis_tdata,
+                                 tvalid=output_axis_tvalid,
+                                 tready=output_axis_tready,
+                                 tlast=output_axis_tlast,
+                                 tuser=output_axis_tuser,
+                                 fifo=sink_queue,
+                                 pause=sink_pause,
+                                 name='sink')
+
+    # DUT
+    dut = dut_axis_mux_4(clk,
+                       rst,
+                       current_test,
+
+                       input_0_axis_tdata,
+                       input_0_axis_tvalid,
+                       input_0_axis_tready,
+                       input_0_axis_tlast,
+                       input_0_axis_tuser,
+                       input_1_axis_tdata,
+                       input_1_axis_tvalid,
+                       input_1_axis_tready,
+                       input_1_axis_tlast,
+                       input_1_axis_tuser,
+                       input_2_axis_tdata,
+                       input_2_axis_tvalid,
+                       input_2_axis_tready,
+                       input_2_axis_tlast,
+                       input_2_axis_tuser,
+                       input_3_axis_tdata,
+                       input_3_axis_tvalid,
+                       input_3_axis_tready,
+                       input_3_axis_tlast,
+                       input_3_axis_tuser,
+
+                       output_axis_tdata,
+                       output_axis_tvalid,
+                       output_axis_tready,
+                       output_axis_tlast,
+                       output_axis_tuser,
+
+                       select)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        yield clk.posedge
+        print("test 1: select port 0")
+        current_test.next = 1
+
+        select.next = 0
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_0_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 2: select port 1")
+        current_test.next = 2
+
+        select.next = 1
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 3: back-to-back packets, same port")
+        current_test.next = 3
+
+        select.next = 0
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_0_queue.put(test_frame1)
+        source_0_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 4: back-to-back packets, different ports")
+        current_test.next = 4
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 5: alterate pause source")
+        current_test.next = 5
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            source_0_pause.next = True
+            source_1_pause.next = True
+            source_2_pause.next = True
+            source_3_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            source_0_pause.next = False
+            source_1_pause.next = False
+            source_2_pause.next = False
+            source_3_pause.next = False
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 6: alterate pause sink")
+        current_test.next = 6
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            sink_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            sink_pause.next = False
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_axis_mux_4.v

@@ -0,0 +1,142 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_axis_mux_4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [7:0] input_0_axis_tdata = 0;
+reg input_0_axis_tvalid = 0;
+reg input_0_axis_tlast = 0;
+reg input_0_axis_tuser = 0;
+reg [7:0] input_1_axis_tdata = 0;
+reg input_1_axis_tvalid = 0;
+reg input_1_axis_tlast = 0;
+reg input_1_axis_tuser = 0;
+reg [7:0] input_2_axis_tdata = 0;
+reg input_2_axis_tvalid = 0;
+reg input_2_axis_tlast = 0;
+reg input_2_axis_tuser = 0;
+reg [7:0] input_3_axis_tdata = 0;
+reg input_3_axis_tvalid = 0;
+reg input_3_axis_tlast = 0;
+reg input_3_axis_tuser = 0;
+
+reg output_axis_tready = 0;
+
+reg [1:0] select = 0;
+
+// Outputs
+wire input_0_axis_tready;
+wire input_1_axis_tready;
+wire input_2_axis_tready;
+wire input_3_axis_tready;
+
+wire [7:0] output_axis_tdata;
+wire output_axis_tvalid;
+wire output_axis_tlast;
+wire output_axis_tuser;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                input_0_axis_tdata,
+                input_0_axis_tvalid,
+                input_0_axis_tlast,
+                input_0_axis_tuser,
+                input_1_axis_tdata,
+                input_1_axis_tvalid,
+                input_1_axis_tlast,
+                input_1_axis_tuser,
+                input_2_axis_tdata,
+                input_2_axis_tvalid,
+                input_2_axis_tlast,
+                input_2_axis_tuser,
+                input_3_axis_tdata,
+                input_3_axis_tvalid,
+                input_3_axis_tlast,
+                input_3_axis_tuser,
+                output_axis_tready,
+                select);
+    $to_myhdl(input_0_axis_tready,
+              input_1_axis_tready,
+              input_2_axis_tready,
+              input_3_axis_tready,
+              output_axis_tdata,
+              output_axis_tvalid,
+              output_axis_tlast,
+              output_axis_tuser);
+
+    // dump file
+    $dumpfile("test_axis_mux_4.lxt");
+    $dumpvars(0, test_axis_mux_4);
+end
+
+axis_mux_4 #(
+    .DATA_WIDTH(8)
+)
+UUT (
+    .clk(clk),
+    .rst(rst),
+    // AXI inputs
+    .input_0_axis_tdata(input_0_axis_tdata),
+    .input_0_axis_tvalid(input_0_axis_tvalid),
+    .input_0_axis_tready(input_0_axis_tready),
+    .input_0_axis_tlast(input_0_axis_tlast),
+    .input_0_axis_tuser(input_0_axis_tuser),
+    .input_1_axis_tdata(input_1_axis_tdata),
+    .input_1_axis_tvalid(input_1_axis_tvalid),
+    .input_1_axis_tready(input_1_axis_tready),
+    .input_1_axis_tlast(input_1_axis_tlast),
+    .input_1_axis_tuser(input_1_axis_tuser),
+    .input_2_axis_tdata(input_2_axis_tdata),
+    .input_2_axis_tvalid(input_2_axis_tvalid),
+    .input_2_axis_tready(input_2_axis_tready),
+    .input_2_axis_tlast(input_2_axis_tlast),
+    .input_2_axis_tuser(input_2_axis_tuser),
+    .input_3_axis_tdata(input_3_axis_tdata),
+    .input_3_axis_tvalid(input_3_axis_tvalid),
+    .input_3_axis_tready(input_3_axis_tready),
+    .input_3_axis_tlast(input_3_axis_tlast),
+    .input_3_axis_tuser(input_3_axis_tuser),
+    // AXI output
+    .output_axis_tdata(output_axis_tdata),
+    .output_axis_tvalid(output_axis_tvalid),
+    .output_axis_tready(output_axis_tready),
+    .output_axis_tlast(output_axis_tlast),
+    .output_axis_tuser(output_axis_tuser),
+    // Control
+    .select(select)
+);
+
+endmodule

lib/axis/tb/test_axis_mux_64_4.py

@@ -0,0 +1,522 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+from Queue import Queue
+
+import axis_ep
+
+module = 'axis_mux_64_4'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("test_%s.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_axis_mux_64_4(clk,
+                 rst,
+                 current_test,
+
+                 input_0_axis_tdata,
+                 input_0_axis_tkeep,
+                 input_0_axis_tvalid,
+                 input_0_axis_tready,
+                 input_0_axis_tlast,
+                 input_0_axis_tuser,
+                 input_1_axis_tdata,
+                 input_1_axis_tkeep,
+                 input_1_axis_tvalid,
+                 input_1_axis_tready,
+                 input_1_axis_tlast,
+                 input_1_axis_tuser,
+                 input_2_axis_tdata,
+                 input_2_axis_tkeep,
+                 input_2_axis_tvalid,
+                 input_2_axis_tready,
+                 input_2_axis_tlast,
+                 input_2_axis_tuser,
+                 input_3_axis_tdata,
+                 input_3_axis_tkeep,
+                 input_3_axis_tvalid,
+                 input_3_axis_tready,
+                 input_3_axis_tlast,
+                 input_3_axis_tuser,
+
+                 output_axis_tdata,
+                 output_axis_tkeep,
+                 output_axis_tvalid,
+                 output_axis_tready,
+                 output_axis_tlast,
+                 output_axis_tuser,
+
+                 select):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                input_0_axis_tdata=input_0_axis_tdata,
+                input_0_axis_tkeep=input_0_axis_tkeep,
+                input_0_axis_tvalid=input_0_axis_tvalid,
+                input_0_axis_tready=input_0_axis_tready,
+                input_0_axis_tlast=input_0_axis_tlast,
+                input_0_axis_tuser=input_0_axis_tuser,
+                input_1_axis_tdata=input_1_axis_tdata,
+                input_1_axis_tkeep=input_1_axis_tkeep,
+                input_1_axis_tvalid=input_1_axis_tvalid,
+                input_1_axis_tready=input_1_axis_tready,
+                input_1_axis_tlast=input_1_axis_tlast,
+                input_1_axis_tuser=input_1_axis_tuser,
+                input_2_axis_tdata=input_2_axis_tdata,
+                input_2_axis_tkeep=input_2_axis_tkeep,
+                input_2_axis_tvalid=input_2_axis_tvalid,
+                input_2_axis_tready=input_2_axis_tready,
+                input_2_axis_tlast=input_2_axis_tlast,
+                input_2_axis_tuser=input_2_axis_tuser,
+                input_3_axis_tdata=input_3_axis_tdata,
+                input_3_axis_tkeep=input_3_axis_tkeep,
+                input_3_axis_tvalid=input_3_axis_tvalid,
+                input_3_axis_tready=input_3_axis_tready,
+                input_3_axis_tlast=input_3_axis_tlast,
+                input_3_axis_tuser=input_3_axis_tuser,
+
+                output_axis_tdata=output_axis_tdata,
+                output_axis_tkeep=output_axis_tkeep,
+                output_axis_tvalid=output_axis_tvalid,
+                output_axis_tready=output_axis_tready,
+                output_axis_tlast=output_axis_tlast,
+                output_axis_tuser=output_axis_tuser,
+
+                select=select)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    input_0_axis_tdata = Signal(intbv(0)[64:])
+    input_0_axis_tkeep = Signal(intbv(0)[8:])
+    input_0_axis_tvalid = Signal(bool(0))
+    input_0_axis_tlast = Signal(bool(0))
+    input_0_axis_tuser = Signal(bool(0))
+    input_1_axis_tdata = Signal(intbv(0)[64:])
+    input_1_axis_tkeep = Signal(intbv(0)[8:])
+    input_1_axis_tvalid = Signal(bool(0))
+    input_1_axis_tlast = Signal(bool(0))
+    input_1_axis_tuser = Signal(bool(0))
+    input_2_axis_tdata = Signal(intbv(0)[64:])
+    input_2_axis_tkeep = Signal(intbv(0)[8:])
+    input_2_axis_tvalid = Signal(bool(0))
+    input_2_axis_tlast = Signal(bool(0))
+    input_2_axis_tuser = Signal(bool(0))
+    input_3_axis_tdata = Signal(intbv(0)[64:])
+    input_3_axis_tkeep = Signal(intbv(0)[8:])
+    input_3_axis_tvalid = Signal(bool(0))
+    input_3_axis_tlast = Signal(bool(0))
+    input_3_axis_tuser = Signal(bool(0))
+
+    output_axis_tready = Signal(bool(0))
+
+    select = Signal(intbv(0)[2:])
+
+    # Outputs
+    input_0_axis_tready = Signal(bool(0))
+    input_1_axis_tready = Signal(bool(0))
+    input_2_axis_tready = Signal(bool(0))
+    input_3_axis_tready = Signal(bool(0))
+
+    output_axis_tdata = Signal(intbv(0)[64:])
+    output_axis_tkeep = Signal(intbv(0)[8:])
+    output_axis_tvalid = Signal(bool(0))
+    output_axis_tlast = Signal(bool(0))
+    output_axis_tuser = Signal(bool(0))
+
+    # sources and sinks
+    source_0_queue = Queue()
+    source_0_pause = Signal(bool(0))
+    source_1_queue = Queue()
+    source_1_pause = Signal(bool(0))
+    source_2_queue = Queue()
+    source_2_pause = Signal(bool(0))
+    source_3_queue = Queue()
+    source_3_pause = Signal(bool(0))
+    sink_queue = Queue()
+    sink_pause = Signal(bool(0))
+
+    source_0 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_0_axis_tdata,
+                                       tkeep=input_0_axis_tkeep,
+                                       tvalid=input_0_axis_tvalid,
+                                       tready=input_0_axis_tready,
+                                       tlast=input_0_axis_tlast,
+                                       tuser=input_0_axis_tuser,
+                                       fifo=source_0_queue,
+                                       pause=source_0_pause,
+                                       name='source0')
+    source_1 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_1_axis_tdata,
+                                       tkeep=input_1_axis_tkeep,
+                                       tvalid=input_1_axis_tvalid,
+                                       tready=input_1_axis_tready,
+                                       tlast=input_1_axis_tlast,
+                                       tuser=input_1_axis_tuser,
+                                       fifo=source_1_queue,
+                                       pause=source_1_pause,
+                                       name='source1')
+    source_2 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_2_axis_tdata,
+                                       tkeep=input_2_axis_tkeep,
+                                       tvalid=input_2_axis_tvalid,
+                                       tready=input_2_axis_tready,
+                                       tlast=input_2_axis_tlast,
+                                       tuser=input_2_axis_tuser,
+                                       fifo=source_2_queue,
+                                       pause=source_2_pause,
+                                       name='source2')
+    source_3 = axis_ep.AXIStreamSource(clk,
+                                       rst,
+                                       tdata=input_3_axis_tdata,
+                                       tkeep=input_3_axis_tkeep,
+                                       tvalid=input_3_axis_tvalid,
+                                       tready=input_3_axis_tready,
+                                       tlast=input_3_axis_tlast,
+                                       tuser=input_3_axis_tuser,
+                                       fifo=source_3_queue,
+                                       pause=source_3_pause,
+                                       name='source3')
+
+    sink = axis_ep.AXIStreamSink(clk,
+                                 rst,
+                                 tdata=output_axis_tdata,
+                                 tkeep=output_axis_tkeep,
+                                 tvalid=output_axis_tvalid,
+                                 tready=output_axis_tready,
+                                 tlast=output_axis_tlast,
+                                 tuser=output_axis_tuser,
+                                 fifo=sink_queue,
+                                 pause=sink_pause,
+                                 name='sink')
+
+    # DUT
+    dut = dut_axis_mux_64_4(clk,
+                       rst,
+                       current_test,
+
+                       input_0_axis_tdata,
+                       input_0_axis_tkeep,
+                       input_0_axis_tvalid,
+                       input_0_axis_tready,
+                       input_0_axis_tlast,
+                       input_0_axis_tuser,
+                       input_1_axis_tdata,
+                       input_1_axis_tkeep,
+                       input_1_axis_tvalid,
+                       input_1_axis_tready,
+                       input_1_axis_tlast,
+                       input_1_axis_tuser,
+                       input_2_axis_tdata,
+                       input_2_axis_tkeep,
+                       input_2_axis_tvalid,
+                       input_2_axis_tready,
+                       input_2_axis_tlast,
+                       input_2_axis_tuser,
+                       input_3_axis_tdata,
+                       input_3_axis_tkeep,
+                       input_3_axis_tvalid,
+                       input_3_axis_tready,
+                       input_3_axis_tlast,
+                       input_3_axis_tuser,
+
+                       output_axis_tdata,
+                       output_axis_tkeep,
+                       output_axis_tvalid,
+                       output_axis_tready,
+                       output_axis_tlast,
+                       output_axis_tuser,
+
+                       select)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        yield clk.posedge
+        print("test 1: select port 0")
+        current_test.next = 1
+
+        select.next = 0
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_0_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 2: select port 1")
+        current_test.next = 2
+
+        select.next = 1
+
+        test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 3: back-to-back packets, same port")
+        current_test.next = 3
+
+        select.next = 0
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_0_queue.put(test_frame1)
+        source_0_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 4: back-to-back packets, different ports")
+        current_test.next = 4
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 5: alterate pause source")
+        current_test.next = 5
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            source_0_pause.next = True
+            source_1_pause.next = True
+            source_2_pause.next = True
+            source_3_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            source_0_pause.next = False
+            source_1_pause.next = False
+            source_2_pause.next = False
+            source_3_pause.next = False
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 6: alterate pause sink")
+        current_test.next = 6
+
+        select.next = 1
+
+        test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
+                                            '\x5A\x51\x52\x53\x54\x55' +
+                                            '\x80\x00' +
+                                            '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+        source_1_queue.put(test_frame1)
+        source_2_queue.put(test_frame2)
+        yield clk.posedge
+
+        while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
+            sink_pause.next = True
+            yield clk.posedge
+            yield clk.posedge
+            yield clk.posedge
+            sink_pause.next = False
+            yield clk.posedge
+            select.next = 2
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame1
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame2
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_axis_mux_64_4.v

@@ -0,0 +1,157 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_axis_mux_64_4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [63:0] input_0_axis_tdata = 0;
+reg [7:0] input_0_axis_tkeep = 0;
+reg input_0_axis_tvalid = 0;
+reg input_0_axis_tlast = 0;
+reg input_0_axis_tuser = 0;
+reg [63:0] input_1_axis_tdata = 0;
+reg [7:0] input_1_axis_tkeep = 0;
+reg input_1_axis_tvalid = 0;
+reg input_1_axis_tlast = 0;
+reg input_1_axis_tuser = 0;
+reg [63:0] input_2_axis_tdata = 0;
+reg [7:0] input_2_axis_tkeep = 0;
+reg input_2_axis_tvalid = 0;
+reg input_2_axis_tlast = 0;
+reg input_2_axis_tuser = 0;
+reg [63:0] input_3_axis_tdata = 0;
+reg [7:0] input_3_axis_tkeep = 0;
+reg input_3_axis_tvalid = 0;
+reg input_3_axis_tlast = 0;
+reg input_3_axis_tuser = 0;
+
+reg output_axis_tready = 0;
+
+reg [1:0] select = 0;
+
+// Outputs
+wire input_0_axis_tready;
+wire input_1_axis_tready;
+wire input_2_axis_tready;
+wire input_3_axis_tready;
+
+wire [63:0] output_axis_tdata;
+wire [7:0] output_axis_tkeep;
+wire output_axis_tvalid;
+wire output_axis_tlast;
+wire output_axis_tuser;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                input_0_axis_tdata,
+                input_0_axis_tkeep,
+                input_0_axis_tvalid,
+                input_0_axis_tlast,
+                input_0_axis_tuser,
+                input_1_axis_tdata,
+                input_1_axis_tkeep,
+                input_1_axis_tvalid,
+                input_1_axis_tlast,
+                input_1_axis_tuser,
+                input_2_axis_tdata,
+                input_2_axis_tkeep,
+                input_2_axis_tvalid,
+                input_2_axis_tlast,
+                input_2_axis_tuser,
+                input_3_axis_tdata,
+                input_3_axis_tkeep,
+                input_3_axis_tvalid,
+                input_3_axis_tlast,
+                input_3_axis_tuser,
+                output_axis_tready,
+                select);
+    $to_myhdl(input_0_axis_tready,
+              input_1_axis_tready,
+              input_2_axis_tready,
+              input_3_axis_tready,
+              output_axis_tdata,
+              output_axis_tkeep,
+              output_axis_tvalid,
+              output_axis_tlast,
+              output_axis_tuser);
+
+    // dump file
+    $dumpfile("test_axis_mux_64_4.lxt");
+    $dumpvars(0, test_axis_mux_64_4);
+end
+
+axis_mux_64_4 #(
+    .DATA_WIDTH(64)
+)
+UUT (
+    .clk(clk),
+    .rst(rst),
+    // AXI inputs
+    .input_0_axis_tdata(input_0_axis_tdata),
+    .input_0_axis_tkeep(input_0_axis_tkeep),
+    .input_0_axis_tvalid(input_0_axis_tvalid),
+    .input_0_axis_tready(input_0_axis_tready),
+    .input_0_axis_tlast(input_0_axis_tlast),
+    .input_0_axis_tuser(input_0_axis_tuser),
+    .input_1_axis_tdata(input_1_axis_tdata),
+    .input_1_axis_tkeep(input_1_axis_tkeep),
+    .input_1_axis_tvalid(input_1_axis_tvalid),
+    .input_1_axis_tready(input_1_axis_tready),
+    .input_1_axis_tlast(input_1_axis_tlast),
+    .input_1_axis_tuser(input_1_axis_tuser),
+    .input_2_axis_tdata(input_2_axis_tdata),
+    .input_2_axis_tkeep(input_2_axis_tkeep),
+    .input_2_axis_tvalid(input_2_axis_tvalid),
+    .input_2_axis_tready(input_2_axis_tready),
+    .input_2_axis_tlast(input_2_axis_tlast),
+    .input_2_axis_tuser(input_2_axis_tuser),
+    .input_3_axis_tdata(input_3_axis_tdata),
+    .input_3_axis_tkeep(input_3_axis_tkeep),
+    .input_3_axis_tvalid(input_3_axis_tvalid),
+    .input_3_axis_tready(input_3_axis_tready),
+    .input_3_axis_tlast(input_3_axis_tlast),
+    .input_3_axis_tuser(input_3_axis_tuser),
+    // AXI output
+    .output_axis_tdata(output_axis_tdata),
+    .output_axis_tkeep(output_axis_tkeep),
+    .output_axis_tvalid(output_axis_tvalid),
+    .output_axis_tready(output_axis_tready),
+    .output_axis_tlast(output_axis_tlast),
+    .output_axis_tuser(output_axis_tuser),
+    // Control
+    .select(select)
+);
+
+endmodule

lib/axis/tb/test_priority_encoder.py

@@ -0,0 +1,147 @@
+#!/usr/bin/env python2
+"""
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+module = 'priority_encoder'
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("test_%s.v" % module)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
+
+def dut_priority_encoder(clk,
+                         rst,
+                         current_test,
+
+                         input_unencoded,
+
+                         output_valid,
+                         output_encoded,
+                         output_unencoded):
+
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+    return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
+                clk=clk,
+                rst=rst,
+                current_test=current_test,
+
+                input_unencoded=input_unencoded,
+
+                output_valid=output_valid,
+                output_encoded=output_encoded,
+                output_unencoded=output_unencoded)
+
+def bench():
+
+    # Inputs
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    input_unencoded = Signal(intbv(0)[32:])
+
+    # Outputs
+    output_valid = Signal(bool(0))
+    output_encoded = Signal(intbv(0)[5:])
+    output_unencoded = Signal(intbv(0)[32:])
+
+    # DUT
+    dut = dut_priority_encoder(clk,
+                               rst,
+                               current_test,
+
+                               input_unencoded,
+
+                               output_valid,
+                               output_encoded,
+                               output_unencoded)
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        yield clk.posedge
+
+        print("test 1: one bit")
+        current_test.next = 1
+
+        for i in range(32):
+            input_unencoded.next = 1 << i
+
+            yield clk.posedge
+
+            assert output_encoded == i
+            assert output_unencoded == 1 << i
+
+        yield delay(100)
+
+        yield clk.posedge
+
+        print("test 2: two bits")
+        current_test.next = 2
+        
+        for i in range(32):
+            for j in range(32):
+
+                input_unencoded.next = (1 << i) | (1 << j)
+
+                yield clk.posedge
+
+                assert output_encoded == max(i,j)
+                assert output_unencoded == 1 << max(i,j)
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return dut, clkgen, check
+
+def test_bench():
+    os.chdir(os.path.dirname(os.path.abspath(__file__)))
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
+

lib/axis/tb/test_priority_encoder.v

@@ -0,0 +1,71 @@
+/*
+
+Copyright (c) 2014 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+module test_priority_encoder;
+
+// parameters
+localparam WIDTH = 32;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [WIDTH-1:0] input_unencoded = 0;
+
+// Outputs
+wire output_valid;
+wire [$clog2(WIDTH)-1:0] output_encoded;
+wire [WIDTH-1:0] output_unencoded;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(clk,
+                rst,
+                current_test,
+                input_unencoded);
+    $to_myhdl(output_valid,
+              output_encoded,
+              output_unencoded);
+
+    // dump file
+    $dumpfile("test_priority_encoder.lxt");
+    $dumpvars(0, test_priority_encoder);
+end
+
+priority_encoder #(
+    .WIDTH(WIDTH)
+)
+UUT (
+    .input_unencoded(input_unencoded),
+    .output_valid(output_valid),
+    .output_encoded(output_encoded),
+    .output_unencoded(output_unencoded)
+);
+
+endmodule