diff --git a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py
index e50b9eca5..cbf4aa0c7 100755
--- a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py
@@ -147,7 +147,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 8
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/AU200/fpga_axi/fpga.xdc b/fpga/lib/pcie/example/AU200/fpga_axi/fpga.xdc
index 1e053f8ae..b6d0a6de6 100644
--- a/fpga/lib/pcie/example/AU200/fpga_axi/fpga.xdc
+++ b/fpga/lib/pcie/example/AU200/fpga_axi/fpga.xdc
@@ -11,7 +11,6 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 63.8          [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
-set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B         [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 
 # System clocks
diff --git a/fpga/lib/pcie/example/AU200/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/AU200/fpga_axi/fpga/Makefile
index b8373bd1f..245ecb112 100644
--- a/fpga/lib/pcie/example/AU200/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/AU200/fpga_axi/fpga/Makefile
@@ -47,3 +47,40 @@ program: $(FPGA_TOP).bit
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
diff --git a/fpga/lib/pcie/example/AU200/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/AU200/fpga_axi/tb/test_fpga_core.py
index fd7119f1d..478bc3dbb 100755
--- a/fpga/lib/pcie/example/AU200/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/AU200/fpga_axi/tb/test_fpga_core.py
@@ -151,7 +151,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 16
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/AU250/fpga_axi/fpga.xdc b/fpga/lib/pcie/example/AU250/fpga_axi/fpga.xdc
index 80534d1cd..5f92fd5c3 100644
--- a/fpga/lib/pcie/example/AU250/fpga_axi/fpga.xdc
+++ b/fpga/lib/pcie/example/AU250/fpga_axi/fpga.xdc
@@ -11,7 +11,6 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 63.8          [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
-set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B         [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 
 # System clocks
diff --git a/fpga/lib/pcie/example/AU250/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/AU250/fpga_axi/fpga/Makefile
index 931305cc8..23f1474dd 100644
--- a/fpga/lib/pcie/example/AU250/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/AU250/fpga_axi/fpga/Makefile
@@ -47,3 +47,40 @@ program: $(FPGA_TOP).bit
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
diff --git a/fpga/lib/pcie/example/AU250/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/AU250/fpga_axi/tb/test_fpga_core.py
index fd7119f1d..478bc3dbb 100755
--- a/fpga/lib/pcie/example/AU250/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/AU250/fpga_axi/tb/test_fpga_core.py
@@ -151,7 +151,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 16
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/AU280/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/AU280/fpga_axi/fpga/Makefile
index b2cb6a8c7..01c063136 100644
--- a/fpga/lib/pcie/example/AU280/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/AU280/fpga_axi/fpga/Makefile
@@ -47,3 +47,40 @@ program: $(FPGA_TOP).bit
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
diff --git a/fpga/lib/pcie/example/AU280/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/AU280/fpga_axi/tb/test_fpga_core.py
index 55212e652..d1d902ceb 100755
--- a/fpga/lib/pcie/example/AU280/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/AU280/fpga_axi/tb/test_fpga_core.py
@@ -144,7 +144,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 16
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/AU50/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/AU50/fpga_axi/fpga/Makefile
index df0153f86..ab3354e43 100644
--- a/fpga/lib/pcie/example/AU50/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/AU50/fpga_axi/fpga/Makefile
@@ -46,3 +46,40 @@ program: $(FPGA_TOP).bit
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
diff --git a/fpga/lib/pcie/example/AU50/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/AU50/fpga_axi/tb/test_fpga_core.py
index 55212e652..d1d902ceb 100755
--- a/fpga/lib/pcie/example/AU50/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/AU50/fpga_axi/tb/test_fpga_core.py
@@ -144,7 +144,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 16
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/fpga/Makefile
index c7b6ef167..1a644fc10 100644
--- a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/fpga/Makefile
@@ -48,7 +48,7 @@ program: $(FPGA_TOP).bit
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
 %.mcs %.prm: %.bit
-	echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x00800000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
 	echo "exit" >> generate_mcs.tcl
 	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
 	mkdir -p rev
@@ -66,7 +66,7 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "open_hw_target" >> flash.tcl
 	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
 	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
-	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {28f256p30t-bpi-x16}] 0]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s29gl256p-bpi-x16}] 0]" >> flash.tcl
 	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
 	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
@@ -75,7 +75,7 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
-	echo "set_property PROGRAM.BPI_RS_PINS {none} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.BPI_RS_PINS {24:23} [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
 	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
 	echo "program_hw_devices [current_hw_device]" >> flash.tcl
diff --git a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py
index 463cf492e..56514675a 100755
--- a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py
@@ -147,7 +147,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 8
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga.xdc b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga.xdc
index 9dabd99e7..fedc29b5e 100644
--- a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga.xdc
+++ b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga.xdc
@@ -9,7 +9,6 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup               [current_design]
 set_property BITSTREAM.CONFIG.CONFIGRATE 31.9                [current_design]
 set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 8                [current_design]
 set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 4           [current_design]
-set_property BITSTREAM.CONFIG.REVISIONSELECT_TRISTATE Enable [current_design]
 set_property CONFIG_MODE BPI16                               [current_design]
 set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable        [current_design]
 
diff --git a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga/Makefile
index 007439126..a5633e0a4 100644
--- a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga/Makefile
@@ -48,7 +48,7 @@ program: $(FPGA_TOP).bit
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
 %.mcs %.prm: %.bit
-	echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x00800000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
 	echo "exit" >> generate_mcs.tcl
 	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
 	mkdir -p rev
@@ -75,7 +75,7 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
-	echo "set_property PROGRAM.BPI_RS_PINS {none} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.BPI_RS_PINS {24:23} [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
 	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
 	echo "program_hw_devices [current_hw_device]" >> flash.tcl
diff --git a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py
index 5c5ffab20..e7fa7953f 100755
--- a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py
@@ -147,7 +147,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 8
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/VCU108/fpga_axi/fpga.xdc b/fpga/lib/pcie/example/VCU108/fpga_axi/fpga.xdc
index d10a54e4a..da71b8ef5 100644
--- a/fpga/lib/pcie/example/VCU108/fpga_axi/fpga.xdc
+++ b/fpga/lib/pcie/example/VCU108/fpga_axi/fpga.xdc
@@ -151,4 +151,48 @@ set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_re
 # 100 MHz MGT reference clock
 create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
 
+# Flash
+#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
+#set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
+#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
+#set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
+#set_property -dict {LOC AN19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
+#set_property -dict {LOC AN18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
+#set_property -dict {LOC AR18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
+#set_property -dict {LOC AR17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
+#set_property -dict {LOC AT20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
+#set_property -dict {LOC AT19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
+#set_property -dict {LOC AT17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
+#set_property -dict {LOC AU17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
+#set_property -dict {LOC AR20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
+#set_property -dict {LOC AR19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
+#set_property -dict {LOC AV20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
+#set_property -dict {LOC AW20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
+#set_property -dict {LOC AU19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
+#set_property -dict {LOC AU18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
+#set_property -dict {LOC AV19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
+#set_property -dict {LOC AV18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
+#set_property -dict {LOC AW18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
+#set_property -dict {LOC AY18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
+#set_property -dict {LOC AY19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
+#set_property -dict {LOC BA19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
+#set_property -dict {LOC BA17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
+#set_property -dict {LOC BB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
+#set_property -dict {LOC BB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
+#set_property -dict {LOC BC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
+#set_property -dict {LOC BB18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
+#set_property -dict {LOC BC18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
+#set_property -dict {LOC AY20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
+#set_property -dict {LOC BA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
+#set_property -dict {LOC BD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
+#set_property -dict {LOC BD17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
+#set_property -dict {LOC BC20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
+#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[23]}]
+#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_region[0]}]
+#set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_region[1]}]
+#set_property -dict {LOC BF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
+#set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
+#set_property -dict {LOC AW17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
+#set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {flash_wait}]
+
 
diff --git a/fpga/lib/pcie/example/VCU108/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/VCU108/fpga_axi/fpga/Makefile
index c653c112a..d192a86a8 100644
--- a/fpga/lib/pcie/example/VCU108/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/VCU108/fpga_axi/fpga/Makefile
@@ -75,7 +75,7 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
-	echo "set_property PROGRAM.BPI_RS_PINS {none} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.BPI_RS_PINS {25:24} [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
 	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
 	echo "program_hw_devices [current_hw_device]" >> flash.tcl
diff --git a/fpga/lib/pcie/example/VCU108/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/VCU108/fpga_axi/tb/test_fpga_core.py
index 9b03a5786..0e0f0c532 100755
--- a/fpga/lib/pcie/example/VCU108/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/VCU108/fpga_axi/tb/test_fpga_core.py
@@ -146,7 +146,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 8
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/fpga.xdc b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/fpga.xdc
index fb134efa8..2fdf19749 100644
--- a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/fpga.xdc
+++ b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/fpga.xdc
@@ -223,4 +223,10 @@ set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_re
 create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
 #create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
 
+# Flash
+#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
+#set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
+#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}]
+#set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}]
+#set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}]
 
diff --git a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/tb/test_fpga_core.py b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/tb/test_fpga_core.py
index 81e282707..e28bdd2d3 100755
--- a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/tb/test_fpga_core.py
@@ -151,7 +151,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 8
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga.xdc b/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga.xdc
index 3e4c72530..2226a1e31 100644
--- a/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga.xdc
+++ b/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga.xdc
@@ -5,10 +5,13 @@
 set_property CFGBVS GND                                [current_design]
 set_property CONFIG_VOLTAGE 1.8                        [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
-set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
+set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE    [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 85.0          [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 
 # System clocks
 # 300 MHz (DDR 0)
diff --git a/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga/Makefile
index 9c516b5f8..0b2a0b90e 100644
--- a/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga/Makefile
@@ -47,8 +47,8 @@ program: $(FPGA_TOP).bit
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
-%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
-	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x04000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
 	echo "exit" >> generate_mcs.tcl
 	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
 	mkdir -p rev
@@ -56,11 +56,11 @@ program: $(FPGA_TOP).bit
 	while [ -e rev/$*_rev$$COUNT.bit ]; \
 	do COUNT=$$((COUNT+1)); done; \
 	COUNT=$$((COUNT-1)); \
-	for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
+	for x in .mcs .prm; \
 	do cp $*$$x rev/$*_rev$$COUNT$$x; \
 	echo "Output: rev/$*_rev$$COUNT$$x"; done;
 
-flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "open_hw" > flash.tcl
 	echo "connect_hw_server" >> flash.tcl
 	echo "open_hw_target" >> flash.tcl
@@ -68,8 +68,8 @@ flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm
 	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
 	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
 	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
-	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
-	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
diff --git a/fpga/lib/pcie/example/VCU1525/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/VCU1525/fpga_axi/tb/test_fpga_core.py
index fd7119f1d..478bc3dbb 100755
--- a/fpga/lib/pcie/example/VCU1525/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/VCU1525/fpga_axi/tb/test_fpga_core.py
@@ -151,7 +151,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 16
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/ZCU106/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/ZCU106/fpga_axi/tb/test_fpga_core.py
index 8e4535511..48d5e00c7 100755
--- a/fpga/lib/pcie/example/ZCU106/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/ZCU106/fpga_axi/tb/test_fpga_core.py
@@ -151,7 +151,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 4
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/example/fb2CG/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/fb2CG/fpga_axi/fpga/Makefile
index e252a9a9d..628b5b011 100644
--- a/fpga/lib/pcie/example/fb2CG/fpga_axi/fpga/Makefile
+++ b/fpga/lib/pcie/example/fb2CG/fpga_axi/fpga/Makefile
@@ -48,3 +48,40 @@ program: $(FPGA_TOP).bit
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu512-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
diff --git a/fpga/lib/pcie/example/fb2CG/fpga_axi/led.tcl b/fpga/lib/pcie/example/fb2CG/fpga_axi/led.tcl
index e430903ef..1e1bd643d 100644
--- a/fpga/lib/pcie/example/fb2CG/fpga_axi/led.tcl
+++ b/fpga/lib/pcie/example/fb2CG/fpga_axi/led.tcl
@@ -7,6 +7,6 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_
 
     if {[llength $select_ffs]} {
         set_property ASYNC_REG TRUE $select_ffs
-        set_false_path -from [all_registers] -to [get_cells "$inst/led_sync_reg_1_reg[*]"]
+        set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"]
     }
 }
diff --git a/fpga/lib/pcie/example/fb2CG/fpga_axi/tb/test_fpga_core.py b/fpga/lib/pcie/example/fb2CG/fpga_axi/tb/test_fpga_core.py
index d9d23641f..eca194d3e 100755
--- a/fpga/lib/pcie/example/fb2CG/fpga_axi/tb/test_fpga_core.py
+++ b/fpga/lib/pcie/example/fb2CG/fpga_axi/tb/test_fpga_core.py
@@ -148,7 +148,7 @@ def bench():
 
     dev.pcie_generation = 3
     dev.pcie_link_width = 16
-    dev.user_clock_frequency = 256e6
+    dev.user_clk_frequency = 250e6
 
     dev.functions[0].msi_multiple_message_capable = 5
 
diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v b/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v
index 0e3e090e4..8172001cd 100644
--- a/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v
+++ b/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v
@@ -402,9 +402,6 @@ assign m_axis_read_desc_status_valid = m_axis_read_desc_status_valid_reg;
 assign status_error_cor = status_error_cor_reg;
 assign status_error_uncor = status_error_uncor_reg;
 
-wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_max_read_request = req_pcie_addr_reg + {max_read_request_size_dw_reg, 2'b00};
-wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_op_count = req_pcie_addr_reg + req_op_count_reg;
-
 // PCIe tag management
 wire [PCIE_TAG_WIDTH-1:0] new_tag;
 wire new_tag_valid;
@@ -584,11 +581,11 @@ always @* begin
     // TLP size computation
     if (req_op_count_reg + req_pcie_addr_reg[1:0] <= {max_read_request_size_dw_reg, 2'b00}) begin
         // packet smaller than max read request size
-        if (req_pcie_addr_reg[12] != req_pcie_addr_plus_op_count[12]) begin
+        if (((req_pcie_addr_reg & 12'hfff) + (req_op_count_reg & 12'hfff)) >> 12 != 0 || req_op_count_reg >> 12 != 0) begin
             // crosses 4k boundary
             req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0];
             dword_count = 11'h400 - req_pcie_addr_reg[11:2];
-            req_last_tlp = req_pcie_addr_plus_op_count[11:0] == 0;
+            req_last_tlp = (((req_pcie_addr_reg & 12'hfff) + (req_op_count_reg & 12'hfff)) & 12'hfff) == 0;
             // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next
             req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1;
             req_pcie_addr[11:0] = 12'd0;
@@ -603,7 +600,7 @@ always @* begin
         end
     end else begin
         // packet larger than max read request size
-        if (req_pcie_addr_reg[12] != req_pcie_addr_plus_max_read_request[12]) begin
+        if (((req_pcie_addr_reg & 12'hfff) + {max_read_request_size_dw_reg, 2'b00}) >> 12 != 0) begin
             // crosses 4k boundary
             req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0];
             dword_count = 11'h400 - req_pcie_addr_reg[11:2];
diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v b/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v
index 70ab186f2..6ee660a9a 100644
--- a/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v
+++ b/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v
@@ -384,9 +384,6 @@ assign ram_rd_cmd_addr = ram_rd_cmd_addr_reg;
 assign ram_rd_cmd_valid = ram_rd_cmd_valid_reg;
 assign ram_rd_resp_ready = ram_rd_resp_ready_cmb;
 
-wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_max_payload = pcie_addr_reg + {max_payload_size_dw_reg, 2'b00};
-wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_op_count = pcie_addr_reg + op_count_reg;
-
 // operation tag management
 reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0;
 reg [PCIE_ADDR_WIDTH-1:0] op_table_start_pcie_addr;
@@ -476,7 +473,7 @@ always @* begin
 
             if (op_count_next <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_next[1:0]) begin
                 // packet smaller than max payload size
-                if ((pcie_addr_next ^ (pcie_addr_next + op_count_next)) & (1 << 12)) begin
+                if (((pcie_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
                     // crosses 4k boundary
                     tlp_count_next = 13'h1000 - pcie_addr_next[11:0];
                 end else begin
@@ -485,7 +482,7 @@ always @* begin
                 end
             end else begin
                 // packet larger than max payload size
-                if ((pcie_addr_next ^ (pcie_addr_next + {max_payload_size_dw_reg, 2'b00})) & (1 << 12)) begin
+                if (((pcie_addr_next & 12'hfff) + {max_payload_size_dw_reg, 2'b00}) >> 12 != 0) begin
                     // crosses 4k boundary
                     tlp_count_next = 13'h1000 - pcie_addr_next[11:0];
                 end else begin
@@ -536,7 +533,7 @@ always @* begin
 
                 if (op_count_next <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_next[1:0]) begin
                     // packet smaller than max payload size
-                    if ((pcie_addr_next ^ (pcie_addr_next + op_count_next)) & (1 << 12)) begin
+                    if (((pcie_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
                         // crosses 4k boundary
                         tlp_count_next = 13'h1000 - pcie_addr_next[11:0];
                     end else begin
@@ -545,7 +542,7 @@ always @* begin
                     end
                 end else begin
                     // packet larger than max payload size
-                    if ((pcie_addr_next ^ (pcie_addr_next + {max_payload_size_dw_reg, 2'b00})) & (1 << 12)) begin
+                    if (((pcie_addr_next & 12'hfff) + {max_payload_size_dw_reg, 2'b00}) >> 12 != 0) begin
                         // crosses 4k boundary
                         tlp_count_next = 13'h1000 - pcie_addr_next[11:0];
                     end else begin
diff --git a/fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v b/fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v
index bd03d5cd4..9d5ac6a18 100644
--- a/fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v
+++ b/fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v
@@ -428,10 +428,6 @@ assign m_axi_bready = m_axi_bready_reg;
 assign status_error_cor = status_error_cor_reg;
 assign status_error_uncor = status_error_uncor_reg;
 
-wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_max_read_request = req_pcie_addr_reg + {max_read_request_size_dw_reg, 2'b00};
-wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_op_count = req_pcie_addr_reg + req_op_count_reg;
-wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_tlp_count = req_pcie_addr_reg + req_tlp_count_reg;
-
 // PCIe tag management
 wire [PCIE_TAG_WIDTH-1:0] new_tag;
 wire new_tag_valid;
@@ -625,11 +621,11 @@ always @* begin
     // TLP size computation
     if (req_op_count_reg + req_pcie_addr_reg[1:0] <= {max_read_request_size_dw_reg, 2'b00}) begin
         // packet smaller than max read request size
-        if (req_pcie_addr_reg[12] != req_pcie_addr_plus_op_count[12]) begin
+        if (((req_pcie_addr_reg & 12'hfff) + (req_op_count_reg & 12'hfff)) >> 12 != 0 || req_op_count_reg >> 12 != 0) begin
             // crosses 4k boundary
             req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0];
             dword_count = 11'h400 - req_pcie_addr_reg[11:2];
-            req_last_tlp = req_pcie_addr_plus_op_count[11:0] == 0;
+            req_last_tlp = (((req_pcie_addr_reg & 12'hfff) + (req_op_count_reg & 12'hfff)) & 12'hfff) == 0;
             // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next
             req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1;
             req_pcie_addr[11:0] = 12'd0;
@@ -644,7 +640,7 @@ always @* begin
         end
     end else begin
         // packet larger than max read request size
-        if (req_pcie_addr_reg[12] != req_pcie_addr_plus_max_read_request[12]) begin
+        if (((req_pcie_addr_reg & 12'hfff) + {max_read_request_size_dw_reg, 2'b00}) >> 12 != 0) begin
             // crosses 4k boundary
             req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0];
             dword_count = 11'h400 - req_pcie_addr_reg[11:2];
@@ -1119,7 +1115,7 @@ always @* begin
                 // AXI transfer size computation
                 if (op_count_next <= AXI_MAX_BURST_SIZE-axi_addr_next[OFFSET_WIDTH-1:0] || AXI_MAX_BURST_SIZE >= 4096) begin
                     // packet smaller than max burst size
-                    if ((axi_addr_next ^ (axi_addr_next + op_count_next)) & (1 << 12)) begin
+                    if (((axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
                         // crosses 4k boundary
                         tr_count_next = 13'h1000 - axi_addr_next[11:0];
                     end else begin
@@ -1128,7 +1124,7 @@ always @* begin
                     end
                 end else begin
                     // packet larger than max burst size
-                    if ((axi_addr_next ^ (axi_addr_next + AXI_MAX_BURST_SIZE)) & (1 << 12)) begin
+                    if (((axi_addr_next & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
                         // crosses 4k boundary
                         tr_count_next = 13'h1000 - axi_addr_next[11:0];
                     end else begin
@@ -1208,7 +1204,7 @@ always @* begin
                     // AXI transfer size computation
                     if (op_count_next <= AXI_MAX_BURST_SIZE-axi_addr_next[OFFSET_WIDTH-1:0] || AXI_MAX_BURST_SIZE >= 4096) begin
                         // packet smaller than max burst size
-                        if ((axi_addr_next ^ (axi_addr_next + op_count_next)) & (1 << 12)) begin
+                        if (((axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
                             // crosses 4k boundary
                             tr_count_next = 13'h1000 - axi_addr_next[11:0];
                         end else begin
@@ -1217,7 +1213,7 @@ always @* begin
                         end
                     end else begin
                         // packet larger than max burst size
-                        if ((axi_addr_next ^ (axi_addr_next + AXI_MAX_BURST_SIZE)) & (1 << 12)) begin
+                        if (((axi_addr_next & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
                             // crosses 4k boundary
                             tr_count_next = 13'h1000 - axi_addr_next[11:0];
                         end else begin
diff --git a/fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v b/fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v
index 3f3adc55c..8c5055b72 100644
--- a/fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v
+++ b/fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v
@@ -363,14 +363,6 @@ assign m_axi_arprot = 3'b010;
 assign m_axi_arvalid = m_axi_arvalid_reg;
 assign m_axi_rready = m_axi_rready_reg;
 
-wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_max_payload = pcie_addr_reg + {max_payload_size_dw_reg, 2'b00};
-wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_op_count = pcie_addr_reg + op_count_reg;
-wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_tlp_count = pcie_addr_reg + tlp_count_reg;
-
-wire [AXI_ADDR_WIDTH-1:0] axi_addr_plus_max_burst = axi_addr_reg + AXI_MAX_BURST_SIZE;
-wire [AXI_ADDR_WIDTH-1:0] axi_addr_plus_op_count = axi_addr_reg + op_count_reg;
-wire [AXI_ADDR_WIDTH-1:0] axi_addr_plus_tlp_count = axi_addr_reg + tlp_count_reg;
-
 // operation tag management
 reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0;
 reg [PCIE_ADDR_WIDTH-1:0] op_table_start_pcie_addr;
@@ -439,11 +431,11 @@ always @* begin
     // TLP size computation
     if (op_count_reg <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_reg[1:0]) begin
         // packet smaller than max read request size
-        if (pcie_addr_reg[12] != pcie_addr_plus_op_count[12]) begin
+        if (((pcie_addr_reg & 12'hfff) + (op_count_reg & 12'hfff)) >> 12 != 0 || op_count_reg >> 12 != 0) begin
             // crosses 4k boundary
             tlp_count = 13'h1000 - pcie_addr_reg[11:0];
             dword_count = 11'h400 - pcie_addr_reg[11:2];
-            last_tlp = pcie_addr_plus_op_count[11:0] == 0;
+            last_tlp = (((pcie_addr_reg & 12'hfff) + (op_count_reg & 12'hfff)) & 12'hfff) == 0;
             // optimized pcie_addr = pcie_addr_reg + tlp_count
             pcie_addr[PCIE_ADDR_WIDTH-1:12] = pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1;
             pcie_addr[11:0] = 12'd0;
@@ -458,7 +450,7 @@ always @* begin
         end
     end else begin
         // packet larger than max read request size
-        if (pcie_addr_reg[12] != pcie_addr_plus_max_payload[12]) begin
+        if (((pcie_addr_reg & 12'hfff) + {max_payload_size_dw_reg, 2'b00}) >> 12 != 0) begin
             // crosses 4k boundary
             tlp_count = 13'h1000 - pcie_addr_reg[11:0];
             dword_count = 11'h400 - pcie_addr_reg[11:2];
@@ -480,10 +472,10 @@ always @* begin
     // AXI transfer size computation
     if (tlp_count_reg <= AXI_MAX_BURST_SIZE-axi_addr_reg[OFFSET_WIDTH-1:0] || AXI_MAX_BURST_SIZE >= 4096) begin
         // packet smaller than max read request size
-        if (axi_addr_reg[12] != axi_addr_plus_tlp_count[12]) begin
+        if (((axi_addr_reg & 12'hfff) + (tlp_count_reg & 12'hfff)) >> 12 != 0 || tlp_count_reg >> 12 != 0) begin
             // crosses 4k boundary
             tr_count = 13'h1000 - axi_addr_reg[11:0];
-            last_tr = axi_addr_plus_tlp_count[11:0] == 0;
+            last_tr = (((axi_addr_reg & 12'hfff) + (tlp_count_reg & 12'hfff)) & 12'hfff) == 0;
             // optimized axi_addr = axi_addr_reg + tr_count
             axi_addr[AXI_ADDR_WIDTH-1:12] = axi_addr_reg[AXI_ADDR_WIDTH-1:12]+1;
             axi_addr[11:0] = 12'd0;
@@ -497,7 +489,7 @@ always @* begin
         end
     end else begin
         // packet larger than max read request size
-        if (axi_addr_reg[12] != axi_addr_plus_max_burst[12]) begin
+        if (((axi_addr_reg & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
             // crosses 4k boundary
             tr_count = 13'h1000 - axi_addr_reg[11:0];
             last_tr = 1'b0;