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Use CMAC wrapper in 100G mqnic design for Alveo U50

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-11-10 17:07:12 -08:00
parent 39c5744e99
commit e51e5a84af
10 changed files with 345 additions and 399 deletions
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2
fpga/mqnic/AU50/fpga_100g/fpga.xdc
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@ -113,7 +113,7 @@ set_property -dict {LOC N37 } [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_131
#set_property -dict {LOC F18 IOSTANDARD LVDS} [get_ports qsfp_recclk_n] ;# to SI5394 IN0
# 161.1328125 MHz MGT reference clock (SI5394 OUT0)
#create_clock -period 6.206 -name qsfp_mgt_refclk_0 [get_ports qsfp_mgt_refclk_0_p]
create_clock -period 6.206 -name qsfp_mgt_refclk_0 [get_ports qsfp_mgt_refclk_0_p]
# 322.265625 MHz MGT reference clock (SI5394 OUT2)
#create_clock -period 3.103 -name qsfp_mgt_refclk_1 [get_ports qsfp_mgt_refclk_1_p]

9
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
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@ -42,6 +42,9 @@ SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
SYN_FILES += rtl/common/rx_hash.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += rtl/common/rb_drp.v
SYN_FILES += rtl/common/cmac_gty_wrapper.v
SYN_FILES += rtl/common/cmac_gty_ch_wrapper.v
SYN_FILES += rtl/common/stats_counter.v
SYN_FILES += rtl/common/stats_collect.v
SYN_FILES += rtl/common/stats_pcie_if.v
@ -119,11 +122,15 @@ XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
#XDC_FILES += hbm.xdc
# IP
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
IP_TCL_FILES += ip/cmac_usplus_0.tcl
IP_TCL_FILES += ip/cmac_usplus.tcl
IP_TCL_FILES += ip/cmac_gty.tcl
IP_TCL_FILES += ip/cms.tcl
#IP_TCL_FILES += ip/hbm_0.tcl

132
fpga/mqnic/AU50/fpga_100g/ip/cmac_gty.tcl Normal file
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@ -0,0 +1,132 @@
# Copyright 2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
set base_name {cmac_gty}
set preset {GTY-CAUI_4}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {0}
set refclk_freq {161.1328125}
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set user_data_width {80}
set int_data_width $user_data_width
set rx_eq_mode {LPM}
set extra_ports [list]
set extra_pll_ports [list]
# DRP connections
lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
# PLL reset and power down
lappend extra_pll_ports qpll0reset_in qpll1reset_in
lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
# channel polarity
lappend extra_ports txpolarity_in rxpolarity_in
# channel TX driver
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
# channel CDR
lappend extra_ports rxcdrlock_out rxcdrhold_in
# channel EQ
lappend extra_ports rxlpmen_in
# channel digital monitor
lappend extra_ports dmonitorout_out
# channel PRBS
lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
# channel eye scan
lappend extra_ports eyescandataerror_out
# channel loopback
lappend extra_ports loopback_in
set config [dict create]
dict set config TX_LINE_RATE $line_rate
dict set config TX_REFCLK_FREQUENCY $refclk_freq
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
dict set config TX_USER_DATA_WIDTH $user_data_width
dict set config TX_INT_DATA_WIDTH $int_data_width
dict set config RX_LINE_RATE $line_rate
dict set config RX_REFCLK_FREQUENCY $refclk_freq
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
dict set config RX_USER_DATA_WIDTH $user_data_width
dict set config RX_INT_DATA_WIDTH $int_data_width
dict set config RX_EQ_MODE $rx_eq_mode
if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
proc create_gtwizard_ip {name preset config} {
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
set ip [get_ips $name]
set_property CONFIG.preset $preset $ip
set config_list {}
dict for {name value} $config {
lappend config_list "CONFIG.${name}" $value
}
set_property -dict $config_list $ip
# enable only one site
set_property CONFIG.CHANNEL_ENABLE [lindex [get_property CONFIG.CHANNEL_ENABLE $ip] 0] $ip
}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config

19
fpga/mqnic/AU50/fpga_100g/ip/cmac_usplus.tcl Normal file
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@ -0,0 +1,19 @@
create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus
set_property -dict [list \
CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.NUM_LANES {4x25} \
CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \
CONFIG.GT_LOCATION {0} \
CONFIG.TX_FLOW_CONTROL {0} \
CONFIG.RX_FLOW_CONTROL {0} \
CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus]
# disable LOC constraint
set_property generate_synth_checkpoint false [get_files [get_property IP_FILE [get_ips cmac_usplus]]]
generate_target synthesis [get_files [get_property IP_FILE [get_ips cmac_usplus]]]
set_property is_enabled false [get_files -of_objects [get_files [get_property IP_FILE [get_ips cmac_usplus]]] cmac_usplus.xdc]

21
fpga/mqnic/AU50/fpga_100g/ip/cmac_usplus_0.tcl
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@ -1,21 +0,0 @@
create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus_0
set_property -dict [list \
CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.NUM_LANES {4x25} \
CONFIG.GT_REF_CLK_FREQ {161.1328125} \
CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \
CONFIG.TX_FLOW_CONTROL {0} \
CONFIG.RX_FLOW_CONTROL {0} \
CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y4} \
CONFIG.GT_GROUP_SELECT {X0Y28~X0Y31} \
CONFIG.LANE1_GT_LOC {X0Y28} \
CONFIG.LANE2_GT_LOC {X0Y29} \
CONFIG.LANE3_GT_LOC {X0Y30} \
CONFIG.LANE4_GT_LOC {X0Y31} \
CONFIG.ENABLE_PIPELINE_REG {1} \
CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus_0]

5
fpga/mqnic/AU50/fpga_100g/placement.xdc
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@ -22,8 +22,11 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_cmac_inst qsfp_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_cmac_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y7}
# CMACs
set_property LOC CMACE4_X0Y4 [get_cells -hierarchical -filter {NAME =~ qsfp_cmac_inst/cmac_inst/inst/i_cmac_usplus_top/* && REF_NAME==CMACE4}]

478
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
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@ -951,13 +951,6 @@ wire qsfp_tx_axis_tready_int;
wire qsfp_tx_axis_tlast_int;
wire [16+1-1:0] qsfp_tx_axis_tuser_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_tx_axis_tdata;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_tx_axis_tkeep;
wire qsfp_mac_tx_axis_tvalid;
wire qsfp_mac_tx_axis_tready;
wire qsfp_mac_tx_axis_tlast;
wire [16+1-1:0] qsfp_mac_tx_axis_tuser;
wire [79:0] qsfp_tx_ptp_time_int;
wire [79:0] qsfp_tx_ptp_ts_int;
wire [15:0] qsfp_tx_ptp_ts_tag_int;
@ -972,402 +965,138 @@ wire qsfp_rx_axis_tvalid_int;
wire qsfp_rx_axis_tlast_int;
wire [80+1-1:0] qsfp_rx_axis_tuser_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_rx_axis_tdata;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_rx_axis_tkeep;
wire qsfp_mac_rx_axis_tvalid;
wire qsfp_mac_rx_axis_tlast;
wire qsfp_mac_rx_axis_tuser;
wire [79:0] qsfp_mac_rx_ptp_ts;
wire qsfp_rx_ptp_clk_int;
wire qsfp_rx_ptp_rst_int;
wire [79:0] qsfp_rx_ptp_time_int;
wire qsfp_drp_clk = clk_125mhz_int;
wire qsfp_drp_rst = rst_125mhz_int;
wire [23:0] qsfp_drp_addr;
wire [15:0] qsfp_drp_di;
wire qsfp_drp_en;
wire qsfp_drp_we;
wire [15:0] qsfp_drp_do;
wire qsfp_drp_rdy;
wire qsfp_rx_status;
wire qsfp_ref_clk;
wire qsfp_txuserclk2;
wire qsfp_rxuserclk2;
wire qsfp_gtpowergood;
assign qsfp_tx_clk_int = qsfp_txuserclk2;
assign qsfp_rx_clk_int = qsfp_txuserclk2;
assign qsfp_rx_ptp_clk_int = qsfp_rxuserclk2;
wire qsfp_mgt_refclk_0;
wire qsfp_mgt_refclk_0_int;
wire qsfp_mgt_refclk_0_bufg;
assign clk_161mhz_ref_int = qsfp_ref_clk;
assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst (
.I (qsfp_mgt_refclk_0_p),
.IB (qsfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp_mgt_refclk_0),
.ODIV2 (qsfp_mgt_refclk_0_int)
);
BUFG_GT bufg_gt_qsfp_mgt_refclk_0_inst (
.CE (qsfp_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp_mgt_refclk_0_int),
.O (qsfp_mgt_refclk_0_bufg)
);
wire qsfp_rst;
sync_reset #(
.N(4)
)
sync_reset_qsfp_rx_ptp_rst_inst (
.clk(qsfp_rx_ptp_clk_int),
.rst(qsfp_tx_rst_int),
.out(qsfp_rx_ptp_rst_int)
qsfp_sync_reset_inst (
.clk(qsfp_mgt_refclk_0_bufg),
.rst(rst_125mhz_int),
.out(qsfp_rst)
);
cmac_pad #(
.DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.USER_WIDTH(16+1)
cmac_gty_wrapper #(
.DRP_CLK_FREQ_HZ(125000000),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RS_FEC_ENABLE(1)
)
qsfp_cmac_pad_inst (
.clk(qsfp_tx_clk_int),
.rst(qsfp_tx_rst_int),
.s_axis_tdata(qsfp_tx_axis_tdata_int),
.s_axis_tkeep(qsfp_tx_axis_tkeep_int),
.s_axis_tvalid(qsfp_tx_axis_tvalid_int),
.s_axis_tready(qsfp_tx_axis_tready_int),
.s_axis_tlast(qsfp_tx_axis_tlast_int),
.s_axis_tuser(qsfp_tx_axis_tuser_int),
.m_axis_tdata(qsfp_mac_tx_axis_tdata),
.m_axis_tkeep(qsfp_mac_tx_axis_tkeep),
.m_axis_tvalid(qsfp_mac_tx_axis_tvalid),
.m_axis_tready(qsfp_mac_tx_axis_tready),
.m_axis_tlast(qsfp_mac_tx_axis_tlast),
.m_axis_tuser(qsfp_mac_tx_axis_tuser)
);
mac_ts_insert #(
.PTP_TS_WIDTH(80),
.DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.S_USER_WIDTH(1),
.M_USER_WIDTH(80+1)
)
qsfp_mac_ts_insert_inst (
.clk(qsfp_rx_clk_int),
.rst(qsfp_rx_rst_int),
.ptp_ts(qsfp_mac_rx_ptp_ts),
.s_axis_tdata(qsfp_mac_rx_axis_tdata),
.s_axis_tkeep(qsfp_mac_rx_axis_tkeep),
.s_axis_tvalid(qsfp_mac_rx_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(qsfp_mac_rx_axis_tlast),
.s_axis_tuser(qsfp_mac_rx_axis_tuser),
.m_axis_tdata(qsfp_rx_axis_tdata_int),
.m_axis_tkeep(qsfp_rx_axis_tkeep_int),
.m_axis_tvalid(qsfp_rx_axis_tvalid_int),
.m_axis_tready(1'b1),
.m_axis_tlast(qsfp_rx_axis_tlast_int),
.m_axis_tuser(qsfp_rx_axis_tuser_int)
);
cmac_usplus_0
qsfp_cmac_inst (
.gt_rxp_in({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}), // input
.gt_rxn_in({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}), // input
.gt_txp_out({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}), // output
.gt_txn_out({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}), // output
.gt_txusrclk2(qsfp_txuserclk2), // output
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(qsfp_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
.gt_ref_clk_p(qsfp_mgt_refclk_0_p), // input
.gt_ref_clk_n(qsfp_mgt_refclk_0_n), // input
.init_clk(clk_125mhz_int), // input
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_rst),
.rx_axis_tvalid(qsfp_mac_rx_axis_tvalid), // output
.rx_axis_tdata(qsfp_mac_rx_axis_tdata), // output [511:0]
.rx_axis_tlast(qsfp_mac_rx_axis_tlast), // output
.rx_axis_tkeep(qsfp_mac_rx_axis_tkeep), // output [63:0]
.rx_axis_tuser(qsfp_mac_rx_axis_tuser), // output
/*
* Common
*/
.xcvr_gtpowergood_out(qsfp_gtpowergood),
.xcvr_ref_clk(qsfp_mgt_refclk_0),
.rx_otn_bip8_0(), // output [7:0]
.rx_otn_bip8_1(), // output [7:0]
.rx_otn_bip8_2(), // output [7:0]
.rx_otn_bip8_3(), // output [7:0]
.rx_otn_bip8_4(), // output [7:0]
.rx_otn_data_0(), // output [65:0]
.rx_otn_data_1(), // output [65:0]
.rx_otn_data_2(), // output [65:0]
.rx_otn_data_3(), // output [65:0]
.rx_otn_data_4(), // output [65:0]
.rx_otn_ena(), // output
.rx_otn_lane0(), // output
.rx_otn_vlmarker(), // output
.rx_preambleout(), // output [55:0]
.usr_rx_reset(qsfp_rx_rst_int), // output
.gt_rxusrclk2(qsfp_rxuserclk2), // output
/*
* DRP
*/
.drp_clk(qsfp_drp_clk),
.drp_rst(qsfp_drp_rst),
.drp_addr(qsfp_drp_addr),
.drp_di(qsfp_drp_di),
.drp_en(qsfp_drp_en),
.drp_we(qsfp_drp_we),
.drp_do(qsfp_drp_do),
.drp_rdy(qsfp_drp_rdy),
.rx_lane_aligner_fill_0(), // output [6:0]
.rx_lane_aligner_fill_1(), // output [6:0]
.rx_lane_aligner_fill_10(), // output [6:0]
.rx_lane_aligner_fill_11(), // output [6:0]
.rx_lane_aligner_fill_12(), // output [6:0]
.rx_lane_aligner_fill_13(), // output [6:0]
.rx_lane_aligner_fill_14(), // output [6:0]
.rx_lane_aligner_fill_15(), // output [6:0]
.rx_lane_aligner_fill_16(), // output [6:0]
.rx_lane_aligner_fill_17(), // output [6:0]
.rx_lane_aligner_fill_18(), // output [6:0]
.rx_lane_aligner_fill_19(), // output [6:0]
.rx_lane_aligner_fill_2(), // output [6:0]
.rx_lane_aligner_fill_3(), // output [6:0]
.rx_lane_aligner_fill_4(), // output [6:0]
.rx_lane_aligner_fill_5(), // output [6:0]
.rx_lane_aligner_fill_6(), // output [6:0]
.rx_lane_aligner_fill_7(), // output [6:0]
.rx_lane_aligner_fill_8(), // output [6:0]
.rx_lane_aligner_fill_9(), // output [6:0]
.rx_ptp_tstamp_out(qsfp_mac_rx_ptp_ts), // output [79:0]
.rx_ptp_pcslane_out(), // output [4:0]
.ctl_rx_systemtimerin(qsfp_rx_ptp_time_int), // input [79:0]
/*
* Serial data
*/
.xcvr_txp({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}),
.xcvr_txn({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}),
.xcvr_rxp({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}),
.xcvr_rxn({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}),
.stat_rx_aligned(), // output
.stat_rx_aligned_err(), // output
.stat_rx_bad_code(), // output [2:0]
.stat_rx_bad_fcs(), // output [2:0]
.stat_rx_bad_preamble(), // output
.stat_rx_bad_sfd(), // output
.stat_rx_bip_err_0(), // output
.stat_rx_bip_err_1(), // output
.stat_rx_bip_err_10(), // output
.stat_rx_bip_err_11(), // output
.stat_rx_bip_err_12(), // output
.stat_rx_bip_err_13(), // output
.stat_rx_bip_err_14(), // output
.stat_rx_bip_err_15(), // output
.stat_rx_bip_err_16(), // output
.stat_rx_bip_err_17(), // output
.stat_rx_bip_err_18(), // output
.stat_rx_bip_err_19(), // output
.stat_rx_bip_err_2(), // output
.stat_rx_bip_err_3(), // output
.stat_rx_bip_err_4(), // output
.stat_rx_bip_err_5(), // output
.stat_rx_bip_err_6(), // output
.stat_rx_bip_err_7(), // output
.stat_rx_bip_err_8(), // output
.stat_rx_bip_err_9(), // output
.stat_rx_block_lock(), // output [19:0]
.stat_rx_broadcast(), // output
.stat_rx_fragment(), // output [2:0]
.stat_rx_framing_err_0(), // output [1:0]
.stat_rx_framing_err_1(), // output [1:0]
.stat_rx_framing_err_10(), // output [1:0]
.stat_rx_framing_err_11(), // output [1:0]
.stat_rx_framing_err_12(), // output [1:0]
.stat_rx_framing_err_13(), // output [1:0]
.stat_rx_framing_err_14(), // output [1:0]
.stat_rx_framing_err_15(), // output [1:0]
.stat_rx_framing_err_16(), // output [1:0]
.stat_rx_framing_err_17(), // output [1:0]
.stat_rx_framing_err_18(), // output [1:0]
.stat_rx_framing_err_19(), // output [1:0]
.stat_rx_framing_err_2(), // output [1:0]
.stat_rx_framing_err_3(), // output [1:0]
.stat_rx_framing_err_4(), // output [1:0]
.stat_rx_framing_err_5(), // output [1:0]
.stat_rx_framing_err_6(), // output [1:0]
.stat_rx_framing_err_7(), // output [1:0]
.stat_rx_framing_err_8(), // output [1:0]
.stat_rx_framing_err_9(), // output [1:0]
.stat_rx_framing_err_valid_0(), // output
.stat_rx_framing_err_valid_1(), // output
.stat_rx_framing_err_valid_10(), // output
.stat_rx_framing_err_valid_11(), // output
.stat_rx_framing_err_valid_12(), // output
.stat_rx_framing_err_valid_13(), // output
.stat_rx_framing_err_valid_14(), // output
.stat_rx_framing_err_valid_15(), // output
.stat_rx_framing_err_valid_16(), // output
.stat_rx_framing_err_valid_17(), // output
.stat_rx_framing_err_valid_18(), // output
.stat_rx_framing_err_valid_19(), // output
.stat_rx_framing_err_valid_2(), // output
.stat_rx_framing_err_valid_3(), // output
.stat_rx_framing_err_valid_4(), // output
.stat_rx_framing_err_valid_5(), // output
.stat_rx_framing_err_valid_6(), // output
.stat_rx_framing_err_valid_7(), // output
.stat_rx_framing_err_valid_8(), // output
.stat_rx_framing_err_valid_9(), // output
.stat_rx_got_signal_os(), // output
.stat_rx_hi_ber(), // output
.stat_rx_inrangeerr(), // output
.stat_rx_internal_local_fault(), // output
.stat_rx_jabber(), // output
.stat_rx_local_fault(), // output
.stat_rx_mf_err(), // output [19:0]
.stat_rx_mf_len_err(), // output [19:0]
.stat_rx_mf_repeat_err(), // output [19:0]
.stat_rx_misaligned(), // output
.stat_rx_multicast(), // output
.stat_rx_oversize(), // output
.stat_rx_packet_1024_1518_bytes(), // output
.stat_rx_packet_128_255_bytes(), // output
.stat_rx_packet_1519_1522_bytes(), // output
.stat_rx_packet_1523_1548_bytes(), // output
.stat_rx_packet_1549_2047_bytes(), // output
.stat_rx_packet_2048_4095_bytes(), // output
.stat_rx_packet_256_511_bytes(), // output
.stat_rx_packet_4096_8191_bytes(), // output
.stat_rx_packet_512_1023_bytes(), // output
.stat_rx_packet_64_bytes(), // output
.stat_rx_packet_65_127_bytes(), // output
.stat_rx_packet_8192_9215_bytes(), // output
.stat_rx_packet_bad_fcs(), // output
.stat_rx_packet_large(), // output
.stat_rx_packet_small(), // output [2:0]
/*
* CMAC connections
*/
.tx_clk(qsfp_tx_clk_int),
.tx_rst(qsfp_tx_rst_int),
.ctl_rx_enable(1'b1), // input
.ctl_rx_force_resync(1'b0), // input
.ctl_rx_test_pattern(1'b0), // input
.ctl_rsfec_ieee_error_indication_mode(1'b0), // input
.ctl_rx_rsfec_enable(1'b1), // input
.ctl_rx_rsfec_enable_correction(1'b1), // input
.ctl_rx_rsfec_enable_indication(1'b1), // input
.core_rx_reset(1'b0), // input
.rx_clk(qsfp_rx_clk_int), // input
.tx_axis_tdata(qsfp_tx_axis_tdata_int),
.tx_axis_tkeep(qsfp_tx_axis_tkeep_int),
.tx_axis_tvalid(qsfp_tx_axis_tvalid_int),
.tx_axis_tready(qsfp_tx_axis_tready_int),
.tx_axis_tlast(qsfp_tx_axis_tlast_int),
.tx_axis_tuser(qsfp_tx_axis_tuser_int),
.stat_rx_received_local_fault(), // output
.stat_rx_remote_fault(), // output
.stat_rx_status(qsfp_rx_status), // output
.stat_rx_stomped_fcs(), // output [2:0]
.stat_rx_synced(), // output [19:0]
.stat_rx_synced_err(), // output [19:0]
.stat_rx_test_pattern_mismatch(), // output [2:0]
.stat_rx_toolong(), // output
.stat_rx_total_bytes(), // output [6:0]
.stat_rx_total_good_bytes(), // output [13:0]
.stat_rx_total_good_packets(), // output
.stat_rx_total_packets(), // output [2:0]
.stat_rx_truncated(), // output
.stat_rx_undersize(), // output [2:0]
.stat_rx_unicast(), // output
.stat_rx_vlan(), // output
.stat_rx_pcsl_demuxed(), // output [19:0]
.stat_rx_pcsl_number_0(), // output [4:0]
.stat_rx_pcsl_number_1(), // output [4:0]
.stat_rx_pcsl_number_10(), // output [4:0]
.stat_rx_pcsl_number_11(), // output [4:0]
.stat_rx_pcsl_number_12(), // output [4:0]
.stat_rx_pcsl_number_13(), // output [4:0]
.stat_rx_pcsl_number_14(), // output [4:0]
.stat_rx_pcsl_number_15(), // output [4:0]
.stat_rx_pcsl_number_16(), // output [4:0]
.stat_rx_pcsl_number_17(), // output [4:0]
.stat_rx_pcsl_number_18(), // output [4:0]
.stat_rx_pcsl_number_19(), // output [4:0]
.stat_rx_pcsl_number_2(), // output [4:0]
.stat_rx_pcsl_number_3(), // output [4:0]
.stat_rx_pcsl_number_4(), // output [4:0]
.stat_rx_pcsl_number_5(), // output [4:0]
.stat_rx_pcsl_number_6(), // output [4:0]
.stat_rx_pcsl_number_7(), // output [4:0]
.stat_rx_pcsl_number_8(), // output [4:0]
.stat_rx_pcsl_number_9(), // output [4:0]
.stat_rx_rsfec_am_lock0(), // output
.stat_rx_rsfec_am_lock1(), // output
.stat_rx_rsfec_am_lock2(), // output
.stat_rx_rsfec_am_lock3(), // output
.stat_rx_rsfec_corrected_cw_inc(), // output
.stat_rx_rsfec_cw_inc(), // output
.stat_rx_rsfec_err_count0_inc(), // output [2:0]
.stat_rx_rsfec_err_count1_inc(), // output [2:0]
.stat_rx_rsfec_err_count2_inc(), // output [2:0]
.stat_rx_rsfec_err_count3_inc(), // output [2:0]
.stat_rx_rsfec_hi_ser(), // output
.stat_rx_rsfec_lane_alignment_status(), // output
.stat_rx_rsfec_lane_fill_0(), // output [13:0]
.stat_rx_rsfec_lane_fill_1(), // output [13:0]
.stat_rx_rsfec_lane_fill_2(), // output [13:0]
.stat_rx_rsfec_lane_fill_3(), // output [13:0]
.stat_rx_rsfec_lane_mapping(), // output [7:0]
.stat_rx_rsfec_uncorrected_cw_inc(), // output
.tx_ptp_time(qsfp_tx_ptp_time_int),
.tx_ptp_ts(qsfp_tx_ptp_ts_int),
.tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag_int),
.tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid_int),
.ctl_tx_systemtimerin(qsfp_tx_ptp_time_int), // input [79:0]
.rx_clk(qsfp_rx_clk_int),
.rx_rst(qsfp_rx_rst_int),
.stat_tx_ptp_fifo_read_error(), // output
.stat_tx_ptp_fifo_write_error(), // output
.rx_axis_tdata(qsfp_rx_axis_tdata_int),
.rx_axis_tkeep(qsfp_rx_axis_tkeep_int),
.rx_axis_tvalid(qsfp_rx_axis_tvalid_int),
.rx_axis_tlast(qsfp_rx_axis_tlast_int),
.rx_axis_tuser(qsfp_rx_axis_tuser_int),
.tx_ptp_tstamp_valid_out(qsfp_tx_ptp_ts_valid_int), // output
.tx_ptp_pcslane_out(), // output [4:0]
.tx_ptp_tstamp_tag_out(qsfp_tx_ptp_ts_tag_int), // output [15:0]
.tx_ptp_tstamp_out(qsfp_tx_ptp_ts_int), // output [79:0]
.tx_ptp_1588op_in(2'b10), // input [1:0]
.tx_ptp_tag_field_in(qsfp_mac_tx_axis_tuser[16:1]), // input [15:0]
.rx_ptp_clk(qsfp_rx_ptp_clk_int),
.rx_ptp_rst(qsfp_rx_ptp_rst_int),
.rx_ptp_time(qsfp_rx_ptp_time_int),
.stat_tx_bad_fcs(), // output
.stat_tx_broadcast(), // output
.stat_tx_frame_error(), // output
.stat_tx_local_fault(), // output
.stat_tx_multicast(), // output
.stat_tx_packet_1024_1518_bytes(), // output
.stat_tx_packet_128_255_bytes(), // output
.stat_tx_packet_1519_1522_bytes(), // output
.stat_tx_packet_1523_1548_bytes(), // output
.stat_tx_packet_1549_2047_bytes(), // output
.stat_tx_packet_2048_4095_bytes(), // output
.stat_tx_packet_256_511_bytes(), // output
.stat_tx_packet_4096_8191_bytes(), // output
.stat_tx_packet_512_1023_bytes(), // output
.stat_tx_packet_64_bytes(), // output
.stat_tx_packet_65_127_bytes(), // output
.stat_tx_packet_8192_9215_bytes(), // output
.stat_tx_packet_large(), // output
.stat_tx_packet_small(), // output
.stat_tx_total_bytes(), // output [5:0]
.stat_tx_total_good_bytes(), // output [13:0]
.stat_tx_total_good_packets(), // output
.stat_tx_total_packets(), // output
.stat_tx_unicast(), // output
.stat_tx_vlan(), // output
.ctl_tx_enable(1'b1), // input
.ctl_tx_test_pattern(1'b0), // input
.ctl_tx_rsfec_enable(1'b1), // input
.ctl_tx_send_idle(1'b0), // input
.ctl_tx_send_rfi(1'b0), // input
.ctl_tx_send_lfi(1'b0), // input
.core_tx_reset(1'b0), // input
.tx_axis_tready(qsfp_mac_tx_axis_tready), // output
.tx_axis_tvalid(qsfp_mac_tx_axis_tvalid), // input
.tx_axis_tdata(qsfp_mac_tx_axis_tdata), // input [511:0]
.tx_axis_tlast(qsfp_mac_tx_axis_tlast), // input
.tx_axis_tkeep(qsfp_mac_tx_axis_tkeep), // input [63:0]
.tx_axis_tuser(qsfp_mac_tx_axis_tuser[0]), // input
.tx_ovfout(), // output
.tx_unfout(), // output
.tx_preamblein(56'd0), // input [55:0]
.usr_tx_reset(qsfp_tx_rst_int), // output
.core_drp_reset(1'b0), // input
.drp_clk(1'b0), // input
.drp_addr(10'd0), // input [9:0]
.drp_di(16'd0), // input [15:0]
.drp_en(1'b0), // input
.drp_do(), // output [15:0]
.drp_rdy(), // output
.drp_we(1'b0) // input
.rx_status(qsfp_rx_status)
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp_ref_clk;
assign ptp_clk = qsfp_mgt_refclk_0_bufg;
assign ptp_rst = qsfp_rst;
assign ptp_sample_clk = clk_125mhz_int;
sync_reset #(
.N(4)
)
sync_reset_ptp_rst_inst (
.clk(ptp_clk),
.rst(rst_125mhz_int),
.out(ptp_rst)
);
assign qsfp_led_stat_g = qsfp_rx_status;
// HBM
@ -2983,6 +2712,7 @@ core_inst (
.qsfp_tx_ptp_ts(qsfp_tx_ptp_ts_int),
.qsfp_tx_ptp_ts_tag(qsfp_tx_ptp_ts_tag_int),
.qsfp_tx_ptp_ts_valid(qsfp_tx_ptp_ts_valid_int),
.qsfp_rx_clk(qsfp_rx_clk_int),
.qsfp_rx_rst(qsfp_rx_rst_int),
.qsfp_rx_axis_tdata(qsfp_rx_axis_tdata_int),
@ -2993,8 +2723,18 @@ core_inst (
.qsfp_rx_ptp_clk(qsfp_rx_ptp_clk_int),
.qsfp_rx_ptp_rst(qsfp_rx_ptp_rst_int),
.qsfp_rx_ptp_time(qsfp_rx_ptp_time_int),
.qsfp_rx_status(qsfp_rx_status),
.qsfp_drp_clk(qsfp_drp_clk),
.qsfp_drp_rst(qsfp_drp_rst),
.qsfp_drp_addr(qsfp_drp_addr),
.qsfp_drp_di(qsfp_drp_di),
.qsfp_drp_en(qsfp_drp_en),
.qsfp_drp_we(qsfp_drp_we),
.qsfp_drp_do(qsfp_drp_do),
.qsfp_drp_rdy(qsfp_drp_rdy),
/*
* HBM
*/

71
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -322,6 +322,15 @@ module fpga_core #
input wire qsfp_rx_status,
input wire qsfp_drp_clk,
input wire qsfp_drp_rst,
output wire [23:0] qsfp_drp_addr,
output wire [15:0] qsfp_drp_di,
output wire qsfp_drp_en,
output wire qsfp_drp_we,
input wire [15:0] qsfp_drp_do,
input wire qsfp_drp_rdy,
/*
* HBM
*/
@ -415,6 +424,8 @@ parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3
localparam RB_BASE_ADDR = 16'h1000;
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
localparam RB_DRP_QSFP_BASE = RB_BASE_ADDR + 16'h40;
initial begin
if (PORT_COUNT > 1) begin
$error("Error: Max port count exceeded (instance %m)");
@ -448,6 +459,12 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data;
wire ctrl_reg_rd_wait;
wire ctrl_reg_rd_ack;
wire qsfp_drp_reg_wr_wait;
wire qsfp_drp_reg_wr_ack;
wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_drp_reg_rd_data;
wire qsfp_drp_reg_rd_wait;
wire qsfp_drp_reg_rd_ack;
reg ctrl_reg_wr_ack_reg = 1'b0;
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0;
@ -466,11 +483,11 @@ reg [3:0] m_axil_cms_wstrb_reg = 4'b0000;
reg m_axil_cms_wvalid_reg = 1'b0;
reg m_axil_cms_arvalid_reg = 1'b0;
assign ctrl_reg_wr_wait = 1'b0;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
assign ctrl_reg_rd_wait = 1'b0;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
assign ctrl_reg_wr_wait = qsfp_drp_reg_wr_wait;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_drp_reg_wr_ack;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_drp_reg_rd_data;
assign ctrl_reg_rd_wait = qsfp_drp_reg_rd_wait;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_drp_reg_rd_ack;
assign fpga_boot = fpga_boot_reg;
@ -575,7 +592,7 @@ always @(posedge clk_250mhz) begin
// Alveo BMC
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C140; // BMC ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= 0; // BMC ctrl: Next header
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_BASE; // BMC ctrl: Next header
RBB+8'h2C: ctrl_reg_rd_data_reg <= m_axil_cms_addr_reg; // BMC ctrl: Addr
RBB+8'h30: ctrl_reg_rd_data_reg <= m_axil_cms_rdata; // BMC ctrl: Data
default: ctrl_reg_rd_ack_reg <= 1'b0;
@ -599,6 +616,48 @@ always @(posedge clk_250mhz) begin
end
end
rb_drp #(
.DRP_ADDR_WIDTH(24),
.DRP_DATA_WIDTH(16),
.DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}),
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.RB_BASE_ADDR(RB_DRP_QSFP_BASE),
.RB_NEXT_PTR(0)
)
qsfp_rb_drp_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Register interface
*/
.reg_wr_addr(ctrl_reg_wr_addr),
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(qsfp_drp_reg_wr_wait),
.reg_wr_ack(qsfp_drp_reg_wr_ack),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(qsfp_drp_reg_rd_data),
.reg_rd_wait(qsfp_drp_reg_rd_wait),
.reg_rd_ack(qsfp_drp_reg_rd_ack),
/*
* DRP
*/
.drp_clk(qsfp_drp_clk),
.drp_rst(qsfp_drp_rst),
.drp_addr(qsfp_drp_addr),
.drp_di(qsfp_drp_di),
.drp_en(qsfp_drp_en),
.drp_we(qsfp_drp_we),
.drp_do(qsfp_drp_do),
.drp_rdy(qsfp_drp_rdy)
);
assign qsfp_led_act = ptp_pps_str;
assign qsfp_led_stat_g = 1'b0;
assign qsfp_led_stat_y = 1'b0;

1
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -73,6 +73,7 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
VERILOG_SOURCES += ../../rtl/common/rb_drp.v
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v

6
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -326,6 +326,11 @@ class TB(object):
dut.qsfp_rx_status.setimmediatevalue(1)
cocotb.start_soon(Clock(dut.qsfp_drp_clk, 8, units="ns").start())
dut.qsfp_drp_rst.setimmediatevalue(0)
dut.qsfp_drp_do.setimmediatevalue(0)
dut.qsfp_drp_rdy.setimmediatevalue(0)
dut.qspi_dq_i.setimmediatevalue(0)
self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024)
@ -600,6 +605,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "tx_checksum.v"),
os.path.join(rtl_dir, "common", "rx_hash.v"),
os.path.join(rtl_dir, "common", "rx_checksum.v"),
os.path.join(rtl_dir, "common", "rb_drp.v"),
os.path.join(rtl_dir, "common", "stats_counter.v"),
os.path.join(rtl_dir, "common", "stats_collect.v"),
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),