From b123525597237792fed0eef17df5985b2f5fab01 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 16 Nov 2014 01:38:20 -0800 Subject: [PATCH 1/3] Add enable signal --- rtl/axis_arb_mux.py | 3 +++ rtl/axis_arb_mux_4.v | 3 +++ rtl/axis_arb_mux_64.py | 3 +++ rtl/axis_arb_mux_64_4.v | 3 +++ rtl/axis_demux.py | 3 ++- rtl/axis_demux_4.v | 3 ++- rtl/axis_demux_64.py | 3 ++- rtl/axis_demux_64_4.v | 3 ++- rtl/axis_mux.py | 3 ++- rtl/axis_mux_4.v | 3 ++- rtl/axis_mux_64.py | 3 ++- rtl/axis_mux_64_4.v | 3 ++- tb/test_axis_demux_4.py | 5 +++++ tb/test_axis_demux_4.v | 3 +++ tb/test_axis_demux_64_4.py | 5 +++++ tb/test_axis_demux_64_4.v | 3 +++ tb/test_axis_mux_4.py | 5 +++++ tb/test_axis_mux_4.v | 3 +++ tb/test_axis_mux_64_4.py | 5 +++++ tb/test_axis_mux_64_4.v | 3 +++ 20 files changed, 60 insertions(+), 8 deletions(-) diff --git a/rtl/axis_arb_mux.py b/rtl/axis_arb_mux.py index 9b40e7fca..f6c689541 100755 --- a/rtl/axis_arb_mux.py +++ b/rtl/axis_arb_mux.py @@ -132,6 +132,7 @@ module {{name}} # wire [{{n-1}}:0] request; wire [{{n-1}}:0] acknowledge; wire [{{n-1}}:0] grant; +wire grant_valid; wire [{{w-1}}:0] grant_encoded; {% for p in ports %} assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast; @@ -157,6 +158,7 @@ mux_inst ( .output_axis_tready(output_axis_tready), .output_axis_tlast(output_axis_tlast), .output_axis_tuser(output_axis_tuser), + .enable(grant_valid), .select(grant_encoded) ); @@ -172,6 +174,7 @@ arb_inst ( .request(request), .acknowledge(acknowledge), .grant(grant), + .grant_valid(grant_valid), .grant_encoded(grant_encoded) ); diff --git a/rtl/axis_arb_mux_4.v b/rtl/axis_arb_mux_4.v index ac24f9193..ce700a0c7 100644 --- a/rtl/axis_arb_mux_4.v +++ b/rtl/axis_arb_mux_4.v @@ -79,6 +79,7 @@ module axis_arb_mux_4 # wire [3:0] request; wire [3:0] acknowledge; wire [3:0] grant; +wire grant_valid; wire [1:0] grant_encoded; assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast; @@ -122,6 +123,7 @@ mux_inst ( .output_axis_tready(output_axis_tready), .output_axis_tlast(output_axis_tlast), .output_axis_tuser(output_axis_tuser), + .enable(grant_valid), .select(grant_encoded) ); @@ -137,6 +139,7 @@ arb_inst ( .request(request), .acknowledge(acknowledge), .grant(grant), + .grant_valid(grant_valid), .grant_encoded(grant_encoded) ); diff --git a/rtl/axis_arb_mux_64.py b/rtl/axis_arb_mux_64.py index 75571c11e..f2f7ee514 100755 --- a/rtl/axis_arb_mux_64.py +++ b/rtl/axis_arb_mux_64.py @@ -135,6 +135,7 @@ module {{name}} # wire [{{n-1}}:0] request; wire [{{n-1}}:0] acknowledge; wire [{{n-1}}:0] grant; +wire grant_valid; wire [{{w-1}}:0] grant_encoded; {% for p in ports %} assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast; @@ -162,6 +163,7 @@ mux_inst ( .output_axis_tready(output_axis_tready), .output_axis_tlast(output_axis_tlast), .output_axis_tuser(output_axis_tuser), + .enable(grant_valid), .select(grant_encoded) ); @@ -177,6 +179,7 @@ arb_inst ( .request(request), .acknowledge(acknowledge), .grant(grant), + .grant_valid(grant_valid), .grant_encoded(grant_encoded) ); diff --git a/rtl/axis_arb_mux_64_4.v b/rtl/axis_arb_mux_64_4.v index d44ecc5ca..42c566f6b 100644 --- a/rtl/axis_arb_mux_64_4.v +++ b/rtl/axis_arb_mux_64_4.v @@ -85,6 +85,7 @@ module axis_arb_mux_64_4 # wire [3:0] request; wire [3:0] acknowledge; wire [3:0] grant; +wire grant_valid; wire [1:0] grant_encoded; assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast; @@ -133,6 +134,7 @@ mux_inst ( .output_axis_tready(output_axis_tready), .output_axis_tlast(output_axis_tlast), .output_axis_tuser(output_axis_tuser), + .enable(grant_valid), .select(grant_encoded) ); @@ -148,6 +150,7 @@ arb_inst ( .request(request), .acknowledge(acknowledge), .grant(grant), + .grant_valid(grant_valid), .grant_encoded(grant_encoded) ); diff --git a/rtl/axis_demux.py b/rtl/axis_demux.py index 601e87d29..d7ce6ceaa 100755 --- a/rtl/axis_demux.py +++ b/rtl/axis_demux.py @@ -129,6 +129,7 @@ module {{name}} # /* * Control */ + input wire enable, input wire [{{w-1}}:0] select ); @@ -172,7 +173,7 @@ always @* begin // end of frame detection frame_next = ~input_axis_tlast; end - end else if (input_axis_tvalid & ~current_output_tvalid) begin + end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin // start of frame, grab select value frame_next = 1; select_next = select; diff --git a/rtl/axis_demux_4.v b/rtl/axis_demux_4.v index 1209f07c0..e796b8347 100644 --- a/rtl/axis_demux_4.v +++ b/rtl/axis_demux_4.v @@ -76,6 +76,7 @@ module axis_demux_4 # /* * Control */ + input wire enable, input wire [1:0] select ); @@ -129,7 +130,7 @@ always @* begin // end of frame detection frame_next = ~input_axis_tlast; end - end else if (input_axis_tvalid & ~current_output_tvalid) begin + end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin // start of frame, grab select value frame_next = 1; select_next = select; diff --git a/rtl/axis_demux_64.py b/rtl/axis_demux_64.py index 7f485bb14..cf927c1fb 100755 --- a/rtl/axis_demux_64.py +++ b/rtl/axis_demux_64.py @@ -132,6 +132,7 @@ module {{name}} # /* * Control */ + input wire enable, input wire [{{w-1}}:0] select ); @@ -176,7 +177,7 @@ always @* begin // end of frame detection frame_next = ~input_axis_tlast; end - end else if (input_axis_tvalid & ~current_output_tvalid) begin + end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin // start of frame, grab select value frame_next = 1; select_next = select; diff --git a/rtl/axis_demux_64_4.v b/rtl/axis_demux_64_4.v index 47940c670..d64f0b13a 100644 --- a/rtl/axis_demux_64_4.v +++ b/rtl/axis_demux_64_4.v @@ -82,6 +82,7 @@ module axis_demux_64_4 # /* * Control */ + input wire enable, input wire [1:0] select ); @@ -136,7 +137,7 @@ always @* begin // end of frame detection frame_next = ~input_axis_tlast; end - end else if (input_axis_tvalid & ~current_output_tvalid) begin + end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin // start of frame, grab select value frame_next = 1; select_next = select; diff --git a/rtl/axis_mux.py b/rtl/axis_mux.py index 37c2f8a3a..122c96026 100755 --- a/rtl/axis_mux.py +++ b/rtl/axis_mux.py @@ -129,6 +129,7 @@ module {{name}} # /* * Control */ + input wire enable, input wire [{{w-1}}:0] select ); @@ -191,7 +192,7 @@ always @* begin // end of frame detection frame_next = ~current_input_tlast; end - end else if (selected_input_tvalid) begin + end else if (enable & selected_input_tvalid) begin // start of frame, grab select value frame_next = 1; select_next = select; diff --git a/rtl/axis_mux_4.v b/rtl/axis_mux_4.v index 12ad752a6..63f58ae9f 100644 --- a/rtl/axis_mux_4.v +++ b/rtl/axis_mux_4.v @@ -76,6 +76,7 @@ module axis_mux_4 # /* * Control */ + input wire enable, input wire [1:0] select ); @@ -164,7 +165,7 @@ always @* begin // end of frame detection frame_next = ~current_input_tlast; end - end else if (selected_input_tvalid) begin + end else if (enable & selected_input_tvalid) begin // start of frame, grab select value frame_next = 1; select_next = select; diff --git a/rtl/axis_mux_64.py b/rtl/axis_mux_64.py index 9b9165612..29b3f7aa9 100755 --- a/rtl/axis_mux_64.py +++ b/rtl/axis_mux_64.py @@ -132,6 +132,7 @@ module {{name}} # /* * Control */ + input wire enable, input wire [{{w-1}}:0] select ); @@ -197,7 +198,7 @@ always @* begin // end of frame detection frame_next = ~current_input_tlast; end - end else if (selected_input_tvalid) begin + end else if (enable & selected_input_tvalid) begin // start of frame, grab select value frame_next = 1; select_next = select; diff --git a/rtl/axis_mux_64_4.v b/rtl/axis_mux_64_4.v index bbf945e09..06d0d6749 100644 --- a/rtl/axis_mux_64_4.v +++ b/rtl/axis_mux_64_4.v @@ -82,6 +82,7 @@ module axis_mux_64_4 # /* * Control */ + input wire enable, input wire [1:0] select ); @@ -176,7 +177,7 @@ always @* begin // end of frame detection frame_next = ~current_input_tlast; end - end else if (selected_input_tvalid) begin + end else if (enable & selected_input_tvalid) begin // start of frame, grab select value frame_next = 1; select_next = select; diff --git a/tb/test_axis_demux_4.py b/tb/test_axis_demux_4.py index d6a56083c..c39a347c6 100755 --- a/tb/test_axis_demux_4.py +++ b/tb/test_axis_demux_4.py @@ -71,6 +71,7 @@ def dut_axis_demux_4(clk, output_3_axis_tlast, output_3_axis_tuser, + enable, select): if os.system(build_cmd): @@ -107,6 +108,7 @@ def dut_axis_demux_4(clk, output_3_axis_tlast=output_3_axis_tlast, output_3_axis_tuser=output_3_axis_tuser, + enable=enable, select=select) def bench(): @@ -126,6 +128,7 @@ def bench(): output_2_axis_tready = Signal(bool(0)) output_3_axis_tready = Signal(bool(0)) + enable = Signal(bool(0)) select = Signal(intbv(0)[2:]) # Outputs @@ -247,6 +250,7 @@ def bench(): output_3_axis_tlast, output_3_axis_tuser, + enable, select) @always(delay(4)) @@ -265,6 +269,7 @@ def bench(): yield clk.posedge yield clk.posedge + enable.next = True yield clk.posedge print("test 1: select port 0") diff --git a/tb/test_axis_demux_4.v b/tb/test_axis_demux_4.v index 056b23ff4..5f58f8627 100644 --- a/tb/test_axis_demux_4.v +++ b/tb/test_axis_demux_4.v @@ -43,6 +43,7 @@ reg output_1_axis_tready = 0; reg output_2_axis_tready = 0; reg output_3_axis_tready = 0; +reg enable = 0; reg [1:0] select = 0; // Outputs @@ -78,6 +79,7 @@ initial begin output_1_axis_tready, output_2_axis_tready, output_3_axis_tready, + enable, select); $to_myhdl(input_axis_tready, output_0_axis_tdata, @@ -136,6 +138,7 @@ UUT ( .output_3_axis_tlast(output_3_axis_tlast), .output_3_axis_tuser(output_3_axis_tuser), // Control + .enable(enable), .select(select) ); diff --git a/tb/test_axis_demux_64_4.py b/tb/test_axis_demux_64_4.py index 05e3fb06d..08aeb3a74 100755 --- a/tb/test_axis_demux_64_4.py +++ b/tb/test_axis_demux_64_4.py @@ -76,6 +76,7 @@ def dut_axis_demux_64_4(clk, output_3_axis_tlast, output_3_axis_tuser, + enable, select): if os.system(build_cmd): @@ -117,6 +118,7 @@ def dut_axis_demux_64_4(clk, output_3_axis_tlast=output_3_axis_tlast, output_3_axis_tuser=output_3_axis_tuser, + enable=enable, select=select) def bench(): @@ -137,6 +139,7 @@ def bench(): output_2_axis_tready = Signal(bool(0)) output_3_axis_tready = Signal(bool(0)) + enable = Signal(bool(0)) select = Signal(intbv(0)[2:]) # Outputs @@ -272,6 +275,7 @@ def bench(): output_3_axis_tlast, output_3_axis_tuser, + enable, select) @always(delay(4)) @@ -290,6 +294,7 @@ def bench(): yield clk.posedge yield clk.posedge + enable.next = True yield clk.posedge print("test 1: select port 0") diff --git a/tb/test_axis_demux_64_4.v b/tb/test_axis_demux_64_4.v index 70528466f..6233ac295 100644 --- a/tb/test_axis_demux_64_4.v +++ b/tb/test_axis_demux_64_4.v @@ -44,6 +44,7 @@ reg output_1_axis_tready = 0; reg output_2_axis_tready = 0; reg output_3_axis_tready = 0; +reg enable = 0; reg [1:0] select = 0; // Outputs @@ -84,6 +85,7 @@ initial begin output_1_axis_tready, output_2_axis_tready, output_3_axis_tready, + enable, select); $to_myhdl(input_axis_tready, output_0_axis_tdata, @@ -151,6 +153,7 @@ UUT ( .output_3_axis_tlast(output_3_axis_tlast), .output_3_axis_tuser(output_3_axis_tuser), // Control + .enable(enable), .select(select) ); diff --git a/tb/test_axis_mux_4.py b/tb/test_axis_mux_4.py index 08fd69232..97cccfdf4 100755 --- a/tb/test_axis_mux_4.py +++ b/tb/test_axis_mux_4.py @@ -71,6 +71,7 @@ def dut_axis_mux_4(clk, output_axis_tlast, output_axis_tuser, + enable, select): if os.system(build_cmd): @@ -107,6 +108,7 @@ def dut_axis_mux_4(clk, output_axis_tlast=output_axis_tlast, output_axis_tuser=output_axis_tuser, + enable=enable, select=select) def bench(): @@ -135,6 +137,7 @@ def bench(): output_axis_tready = Signal(bool(0)) + enable = Signal(bool(0)) select = Signal(intbv(0)[2:]) # Outputs @@ -244,6 +247,7 @@ def bench(): output_axis_tlast, output_axis_tuser, + enable, select) @always(delay(4)) @@ -262,6 +266,7 @@ def bench(): yield clk.posedge yield clk.posedge + enable.next = True yield clk.posedge print("test 1: select port 0") diff --git a/tb/test_axis_mux_4.v b/tb/test_axis_mux_4.v index d31c8429d..6fcbc7e6b 100644 --- a/tb/test_axis_mux_4.v +++ b/tb/test_axis_mux_4.v @@ -52,6 +52,7 @@ reg input_3_axis_tuser = 0; reg output_axis_tready = 0; +reg enable = 0; reg [1:0] select = 0; // Outputs @@ -87,6 +88,7 @@ initial begin input_3_axis_tlast, input_3_axis_tuser, output_axis_tready, + enable, select); $to_myhdl(input_0_axis_tready, input_1_axis_tready, @@ -136,6 +138,7 @@ UUT ( .output_axis_tlast(output_axis_tlast), .output_axis_tuser(output_axis_tuser), // Control + .enable(enable), .select(select) ); diff --git a/tb/test_axis_mux_64_4.py b/tb/test_axis_mux_64_4.py index b866c680b..f8349d26c 100755 --- a/tb/test_axis_mux_64_4.py +++ b/tb/test_axis_mux_64_4.py @@ -76,6 +76,7 @@ def dut_axis_mux_64_4(clk, output_axis_tlast, output_axis_tuser, + enable, select): if os.system(build_cmd): @@ -117,6 +118,7 @@ def dut_axis_mux_64_4(clk, output_axis_tlast=output_axis_tlast, output_axis_tuser=output_axis_tuser, + enable=enable, select=select) def bench(): @@ -149,6 +151,7 @@ def bench(): output_axis_tready = Signal(bool(0)) + enable = Signal(bool(0)) select = Signal(intbv(0)[2:]) # Outputs @@ -269,6 +272,7 @@ def bench(): output_axis_tlast, output_axis_tuser, + enable, select) @always(delay(4)) @@ -287,6 +291,7 @@ def bench(): yield clk.posedge yield clk.posedge + enable.next = True yield clk.posedge print("test 1: select port 0") diff --git a/tb/test_axis_mux_64_4.v b/tb/test_axis_mux_64_4.v index 31c4f0b19..3209d64ac 100644 --- a/tb/test_axis_mux_64_4.v +++ b/tb/test_axis_mux_64_4.v @@ -56,6 +56,7 @@ reg input_3_axis_tuser = 0; reg output_axis_tready = 0; +reg enable = 0; reg [1:0] select = 0; // Outputs @@ -96,6 +97,7 @@ initial begin input_3_axis_tlast, input_3_axis_tuser, output_axis_tready, + enable, select); $to_myhdl(input_0_axis_tready, input_1_axis_tready, @@ -151,6 +153,7 @@ UUT ( .output_axis_tlast(output_axis_tlast), .output_axis_tuser(output_axis_tuser), // Control + .enable(enable), .select(select) ); From d193ca5905c1293d3b8be3a1014dacc634ffef75 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 16 Nov 2014 01:58:17 -0800 Subject: [PATCH 2/3] Add LSB_PRIORITY parameter --- rtl/arbiter.v | 22 +++++++++++++++++----- rtl/priority_encoder.v | 22 +++++++++++++++++----- 2 files changed, 34 insertions(+), 10 deletions(-) diff --git a/rtl/arbiter.v b/rtl/arbiter.v index 219b4661c..d6e06303d 100644 --- a/rtl/arbiter.v +++ b/rtl/arbiter.v @@ -35,7 +35,9 @@ module arbiter # // arbitration type: "PRIORITY" or "ROUND_ROBIN" parameter TYPE = "PRIORITY", // block type: "NONE", "REQUEST", "ACKNOWLEDGE" - parameter BLOCK = "NONE" + parameter BLOCK = "NONE", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "LOW" ) ( input wire clk, @@ -62,7 +64,8 @@ wire [$clog2(PORTS)-1:0] request_index; wire [PORTS-1:0] request_mask; priority_encoder #( - .WIDTH(PORTS) + .WIDTH(PORTS), + .LSB_PRIORITY(LSB_PRIORITY) ) priority_encoder_inst ( .input_unencoded(request), @@ -78,7 +81,8 @@ wire [$clog2(PORTS)-1:0] masked_request_index; wire [PORTS-1:0] masked_request_mask; priority_encoder #( - .WIDTH(PORTS) + .WIDTH(PORTS), + .LSB_PRIORITY(LSB_PRIORITY) ) priority_encoder_masked ( .input_unencoded(request & mask_reg), @@ -113,12 +117,20 @@ always @* begin grant_valid_next = 1; grant_next = masked_request_mask; grant_encoded_next = masked_request_index; - mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index); + if (LSB_PRIORITY == "LOW") begin + mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index); + end else begin + mask_next = {PORTS{1'b1}} << (masked_request_index + 1); + end end else begin grant_valid_next = 1; grant_next = request_mask; grant_encoded_next = request_index; - mask_next = {PORTS{1'b1}} >> (PORTS - request_index); + if (LSB_PRIORITY == "LOW") begin + mask_next = {PORTS{1'b1}} >> (PORTS - request_index); + end else begin + mask_next = {PORTS{1'b1}} << (request_index + 1); + end end end end diff --git a/rtl/priority_encoder.v b/rtl/priority_encoder.v index 03af53fe9..cb380c760 100644 --- a/rtl/priority_encoder.v +++ b/rtl/priority_encoder.v @@ -31,7 +31,9 @@ THE SOFTWARE. */ module priority_encoder # ( - parameter WIDTH = 4 + parameter WIDTH = 4, + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "LOW" ) ( input wire [WIDTH-1:0] input_unencoded, @@ -48,14 +50,19 @@ generate if (WIDTH == 2) begin // two inputs - just an OR gate assign output_valid = |input_unencoded; - assign output_encoded = input_unencoded[1]; + if (LSB_PRIORITY == "LOW") begin + assign output_encoded = input_unencoded[1]; + end else begin + assign output_encoded = ~input_unencoded[0]; + end end else begin // more than two inputs - split into two parts and recurse // also pad input to correct power-of-two width wire [$clog2(W2)-1:0] out1, out2; wire valid1, valid2; priority_encoder #( - .WIDTH(W2) + .WIDTH(W2), + .LSB_PRIORITY(LSB_PRIORITY) ) priority_encoder_inst1 ( .input_unencoded(input_unencoded[W2-1:0]), @@ -63,7 +70,8 @@ generate .output_encoded(out1) ); priority_encoder #( - .WIDTH(W2) + .WIDTH(W2), + .LSB_PRIORITY(LSB_PRIORITY) ) priority_encoder_inst2 ( .input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}), @@ -72,7 +80,11 @@ generate ); // multiplexer to select part assign output_valid = valid1 | valid2; - assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1}; + if (LSB_PRIORITY == "LOW") begin + assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1}; + end else begin + assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2}; + end end endgenerate From 0c3af7d5bb20d1e0802a1309744a9917fd7aa92a Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 16 Nov 2014 02:00:27 -0800 Subject: [PATCH 3/3] Reverse priority in arbitrated mux --- rtl/axis_arb_mux.py | 7 +++-- rtl/axis_arb_mux_4.v | 7 +++-- rtl/axis_arb_mux_64.py | 7 +++-- rtl/axis_arb_mux_64_4.v | 7 +++-- tb/test_axis_arb_mux_4.py | 58 ++++++++++++++++++------------------ tb/test_axis_arb_mux_64_4.py | 58 ++++++++++++++++++------------------ 6 files changed, 78 insertions(+), 66 deletions(-) diff --git a/rtl/axis_arb_mux.py b/rtl/axis_arb_mux.py index f6c689541..9d37839d6 100755 --- a/rtl/axis_arb_mux.py +++ b/rtl/axis_arb_mux.py @@ -103,7 +103,9 @@ module {{name}} # ( parameter DATA_WIDTH = 8, // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" ) ( input wire clk, @@ -166,7 +168,8 @@ mux_inst ( arbiter #( .PORTS({{n}}), .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE") + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) ) arb_inst ( .clk(clk), diff --git a/rtl/axis_arb_mux_4.v b/rtl/axis_arb_mux_4.v index ce700a0c7..56d2afe23 100644 --- a/rtl/axis_arb_mux_4.v +++ b/rtl/axis_arb_mux_4.v @@ -33,7 +33,9 @@ module axis_arb_mux_4 # ( parameter DATA_WIDTH = 8, // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" ) ( input wire clk, @@ -131,7 +133,8 @@ mux_inst ( arbiter #( .PORTS(4), .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE") + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) ) arb_inst ( .clk(clk), diff --git a/rtl/axis_arb_mux_64.py b/rtl/axis_arb_mux_64.py index f2f7ee514..873c2e2a9 100755 --- a/rtl/axis_arb_mux_64.py +++ b/rtl/axis_arb_mux_64.py @@ -104,7 +104,9 @@ module {{name}} # parameter DATA_WIDTH = 64, parameter KEEP_WIDTH = (DATA_WIDTH/8), // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" ) ( input wire clk, @@ -171,7 +173,8 @@ mux_inst ( arbiter #( .PORTS({{n}}), .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE") + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) ) arb_inst ( .clk(clk), diff --git a/rtl/axis_arb_mux_64_4.v b/rtl/axis_arb_mux_64_4.v index 42c566f6b..b4947e2ef 100644 --- a/rtl/axis_arb_mux_64_4.v +++ b/rtl/axis_arb_mux_64_4.v @@ -34,7 +34,9 @@ module axis_arb_mux_64_4 # parameter DATA_WIDTH = 64, parameter KEEP_WIDTH = (DATA_WIDTH/8), // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" ) ( input wire clk, @@ -142,7 +144,8 @@ mux_inst ( arbiter #( .PORTS(4), .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE") + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) ) arb_inst ( .clk(clk), diff --git a/tb/test_axis_arb_mux_4.py b/tb/test_axis_arb_mux_4.py index 8cd01f7fe..e406ef368 100755 --- a/tb/test_axis_arb_mux_4.py +++ b/tb/test_axis_arb_mux_4.py @@ -366,13 +366,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -412,13 +412,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -452,13 +452,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -476,39 +476,21 @@ def bench(): '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') source_1_queue.put(test_frame1) source_2_queue.put(test_frame2) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) yield clk.posedge yield delay(800) yield clk.posedge - source_2_queue.put(test_frame2) + source_1_queue.put(test_frame1) while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid: yield clk.posedge yield clk.posedge yield clk.posedge - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame2 - - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame1 - - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame1 - rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() @@ -521,12 +503,30 @@ def bench(): assert rx_frame == test_frame2 + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() assert rx_frame == test_frame1 + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + yield delay(100) raise StopSimulation diff --git a/tb/test_axis_arb_mux_64_4.py b/tb/test_axis_arb_mux_64_4.py index 15a0e4504..4698f5f2d 100755 --- a/tb/test_axis_arb_mux_64_4.py +++ b/tb/test_axis_arb_mux_64_4.py @@ -391,13 +391,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -437,13 +437,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -477,13 +477,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -501,39 +501,21 @@ def bench(): '\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') source_1_queue.put(test_frame1) source_2_queue.put(test_frame2) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) yield clk.posedge yield delay(150) yield clk.posedge - source_2_queue.put(test_frame2) + source_1_queue.put(test_frame1) while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid: yield clk.posedge yield clk.posedge yield clk.posedge - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame2 - - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame1 - - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame1 - rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() @@ -546,12 +528,30 @@ def bench(): assert rx_frame == test_frame2 + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() assert rx_frame == test_frame1 + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + yield delay(100) raise StopSimulation