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merged changes in axis

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This commit is contained in:
Alex Forencich 2014-11-16 02:03:50 -08:00
commit e534389bf2
24 changed files with 172 additions and 84 deletions
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18
lib/axis/rtl/arbiter.v
View File

@ -35,7 +35,9 @@ module arbiter #
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter TYPE = "PRIORITY",
// block type: "NONE", "REQUEST", "ACKNOWLEDGE"
parameter BLOCK = "NONE"
parameter BLOCK = "NONE",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire clk,
@ -62,7 +64,8 @@ wire [$clog2(PORTS)-1:0] request_index;
wire [PORTS-1:0] request_mask;
priority_encoder #(
.WIDTH(PORTS)
.WIDTH(PORTS),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst (
.input_unencoded(request),
@ -78,7 +81,8 @@ wire [$clog2(PORTS)-1:0] masked_request_index;
wire [PORTS-1:0] masked_request_mask;
priority_encoder #(
.WIDTH(PORTS)
.WIDTH(PORTS),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_masked (
.input_unencoded(request & mask_reg),
@ -113,12 +117,20 @@ always @* begin
grant_valid_next = 1;
grant_next = masked_request_mask;
grant_encoded_next = masked_request_index;
if (LSB_PRIORITY == "LOW") begin
mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
end else begin
mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
end
end else begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
if (LSB_PRIORITY == "LOW") begin
mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
end else begin
mask_next = {PORTS{1'b1}} << (request_index + 1);
end
end
end
end

10
lib/axis/rtl/axis_arb_mux.py
View File

@ -103,7 +103,9 @@ module {{name}} #
(
parameter DATA_WIDTH = 8,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
@ -132,6 +134,7 @@ module {{name}} #
wire [{{n-1}}:0] request;
wire [{{n-1}}:0] acknowledge;
wire [{{n-1}}:0] grant;
wire grant_valid;
wire [{{w-1}}:0] grant_encoded;
{% for p in ports %}
assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast;
@ -157,6 +160,7 @@ mux_inst (
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
@ -164,7 +168,8 @@ mux_inst (
arbiter #(
.PORTS({{n}}),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE")
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
@ -172,6 +177,7 @@ arb_inst (
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);

10
lib/axis/rtl/axis_arb_mux_4.v
View File

@ -33,7 +33,9 @@ module axis_arb_mux_4 #
(
parameter DATA_WIDTH = 8,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
@ -79,6 +81,7 @@ module axis_arb_mux_4 #
wire [3:0] request;
wire [3:0] acknowledge;
wire [3:0] grant;
wire grant_valid;
wire [1:0] grant_encoded;
assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
@ -122,6 +125,7 @@ mux_inst (
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
@ -129,7 +133,8 @@ mux_inst (
arbiter #(
.PORTS(4),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE")
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
@ -137,6 +142,7 @@ arb_inst (
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);

10
lib/axis/rtl/axis_arb_mux_64.py
View File

@ -104,7 +104,9 @@ module {{name}} #
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
@ -135,6 +137,7 @@ module {{name}} #
wire [{{n-1}}:0] request;
wire [{{n-1}}:0] acknowledge;
wire [{{n-1}}:0] grant;
wire grant_valid;
wire [{{w-1}}:0] grant_encoded;
{% for p in ports %}
assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast;
@ -162,6 +165,7 @@ mux_inst (
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
@ -169,7 +173,8 @@ mux_inst (
arbiter #(
.PORTS({{n}}),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE")
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
@ -177,6 +182,7 @@ arb_inst (
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);

10
lib/axis/rtl/axis_arb_mux_64_4.v
View File

@ -34,7 +34,9 @@ module axis_arb_mux_64_4 #
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
@ -85,6 +87,7 @@ module axis_arb_mux_64_4 #
wire [3:0] request;
wire [3:0] acknowledge;
wire [3:0] grant;
wire grant_valid;
wire [1:0] grant_encoded;
assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
@ -133,6 +136,7 @@ mux_inst (
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
@ -140,7 +144,8 @@ mux_inst (
arbiter #(
.PORTS(4),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE")
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
@ -148,6 +153,7 @@ arb_inst (
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);

3
lib/axis/rtl/axis_demux.py
View File

@ -129,6 +129,7 @@ module {{name}} #
/*
* Control
*/
input wire enable,
input wire [{{w-1}}:0] select
);
@ -172,7 +173,7 @@ always @* begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (input_axis_tvalid & ~current_output_tvalid) begin
end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;

3
lib/axis/rtl/axis_demux_4.v
View File

@ -76,6 +76,7 @@ module axis_demux_4 #
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
@ -129,7 +130,7 @@ always @* begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (input_axis_tvalid & ~current_output_tvalid) begin
end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;

3
lib/axis/rtl/axis_demux_64.py
View File

@ -132,6 +132,7 @@ module {{name}} #
/*
* Control
*/
input wire enable,
input wire [{{w-1}}:0] select
);
@ -176,7 +177,7 @@ always @* begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (input_axis_tvalid & ~current_output_tvalid) begin
end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;

3
lib/axis/rtl/axis_demux_64_4.v
View File

@ -82,6 +82,7 @@ module axis_demux_64_4 #
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
@ -136,7 +137,7 @@ always @* begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (input_axis_tvalid & ~current_output_tvalid) begin
end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;

3
lib/axis/rtl/axis_mux.py
View File

@ -129,6 +129,7 @@ module {{name}} #
/*
* Control
*/
input wire enable,
input wire [{{w-1}}:0] select
);
@ -191,7 +192,7 @@ always @* begin
// end of frame detection
frame_next = ~current_input_tlast;
end
end else if (selected_input_tvalid) begin
end else if (enable & selected_input_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;

3
lib/axis/rtl/axis_mux_4.v
View File

@ -76,6 +76,7 @@ module axis_mux_4 #
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
@ -164,7 +165,7 @@ always @* begin
// end of frame detection
frame_next = ~current_input_tlast;
end
end else if (selected_input_tvalid) begin
end else if (enable & selected_input_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;

3
lib/axis/rtl/axis_mux_64.py
View File

@ -132,6 +132,7 @@ module {{name}} #
/*
* Control
*/
input wire enable,
input wire [{{w-1}}:0] select
);
@ -197,7 +198,7 @@ always @* begin
// end of frame detection
frame_next = ~current_input_tlast;
end
end else if (selected_input_tvalid) begin
end else if (enable & selected_input_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;

3
lib/axis/rtl/axis_mux_64_4.v
View File

@ -82,6 +82,7 @@ module axis_mux_64_4 #
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
@ -176,7 +177,7 @@ always @* begin
// end of frame detection
frame_next = ~current_input_tlast;
end
end else if (selected_input_tvalid) begin
end else if (enable & selected_input_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;

18
lib/axis/rtl/priority_encoder.v
View File

@ -31,7 +31,9 @@ THE SOFTWARE.
*/
module priority_encoder #
(
parameter WIDTH = 4
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire [WIDTH-1:0] input_unencoded,
@ -48,14 +50,19 @@ generate
if (WIDTH == 2) begin
// two inputs - just an OR gate
assign output_valid = |input_unencoded;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = input_unencoded[1];
end else begin
assign output_encoded = ~input_unencoded[0];
end
end else begin
// more than two inputs - split into two parts and recurse
// also pad input to correct power-of-two width
wire [$clog2(W2)-1:0] out1, out2;
wire valid1, valid2;
priority_encoder #(
.WIDTH(W2)
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst1 (
.input_unencoded(input_unencoded[W2-1:0]),
@ -63,7 +70,8 @@ generate
.output_encoded(out1)
);
priority_encoder #(
.WIDTH(W2)
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst2 (
.input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
@ -72,7 +80,11 @@ generate
);
// multiplexer to select part
assign output_valid = valid1 | valid2;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
end else begin
assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
end
end
endgenerate

58
lib/axis/tb/test_axis_arb_mux_4.py
View File

@ -366,13 +366,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -412,13 +412,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -452,13 +452,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -476,39 +476,21 @@ def bench():
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
yield clk.posedge
yield delay(800)
yield clk.posedge
source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1)
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
@ -521,12 +503,30 @@ def bench():
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation

58
lib/axis/tb/test_axis_arb_mux_64_4.py
View File

@ -391,13 +391,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -437,13 +437,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -477,13 +477,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -501,39 +501,21 @@ def bench():
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
yield clk.posedge
yield delay(150)
yield clk.posedge
source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1)
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
@ -546,12 +528,30 @@ def bench():
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation

5
lib/axis/tb/test_axis_demux_4.py
View File

@ -71,6 +71,7 @@ def dut_axis_demux_4(clk,
output_3_axis_tlast,
output_3_axis_tuser,
enable,
select):
if os.system(build_cmd):
@ -107,6 +108,7 @@ def dut_axis_demux_4(clk,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
enable=enable,
select=select)
def bench():
@ -126,6 +128,7 @@ def bench():
output_2_axis_tready = Signal(bool(0))
output_3_axis_tready = Signal(bool(0))
enable = Signal(bool(0))
select = Signal(intbv(0)[2:])
# Outputs
@ -247,6 +250,7 @@ def bench():
output_3_axis_tlast,
output_3_axis_tuser,
enable,
select)
@always(delay(4))
@ -265,6 +269,7 @@ def bench():
yield clk.posedge
yield clk.posedge
enable.next = True
yield clk.posedge
print("test 1: select port 0")

3
lib/axis/tb/test_axis_demux_4.v
View File

@ -43,6 +43,7 @@ reg output_1_axis_tready = 0;
reg output_2_axis_tready = 0;
reg output_3_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
@ -78,6 +79,7 @@ initial begin
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
@ -136,6 +138,7 @@ UUT (
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.enable(enable),
.select(select)
);

5
lib/axis/tb/test_axis_demux_64_4.py
View File

@ -76,6 +76,7 @@ def dut_axis_demux_64_4(clk,
output_3_axis_tlast,
output_3_axis_tuser,
enable,
select):
if os.system(build_cmd):
@ -117,6 +118,7 @@ def dut_axis_demux_64_4(clk,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
enable=enable,
select=select)
def bench():
@ -137,6 +139,7 @@ def bench():
output_2_axis_tready = Signal(bool(0))
output_3_axis_tready = Signal(bool(0))
enable = Signal(bool(0))
select = Signal(intbv(0)[2:])
# Outputs
@ -272,6 +275,7 @@ def bench():
output_3_axis_tlast,
output_3_axis_tuser,
enable,
select)
@always(delay(4))
@ -290,6 +294,7 @@ def bench():
yield clk.posedge
yield clk.posedge
enable.next = True
yield clk.posedge
print("test 1: select port 0")

3
lib/axis/tb/test_axis_demux_64_4.v
View File

@ -44,6 +44,7 @@ reg output_1_axis_tready = 0;
reg output_2_axis_tready = 0;
reg output_3_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
@ -84,6 +85,7 @@ initial begin
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
@ -151,6 +153,7 @@ UUT (
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.enable(enable),
.select(select)
);

5
lib/axis/tb/test_axis_mux_4.py
View File

@ -71,6 +71,7 @@ def dut_axis_mux_4(clk,
output_axis_tlast,
output_axis_tuser,
enable,
select):
if os.system(build_cmd):
@ -107,6 +108,7 @@ def dut_axis_mux_4(clk,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
enable=enable,
select=select)
def bench():
@ -135,6 +137,7 @@ def bench():
output_axis_tready = Signal(bool(0))
enable = Signal(bool(0))
select = Signal(intbv(0)[2:])
# Outputs
@ -244,6 +247,7 @@ def bench():
output_axis_tlast,
output_axis_tuser,
enable,
select)
@always(delay(4))
@ -262,6 +266,7 @@ def bench():
yield clk.posedge
yield clk.posedge
enable.next = True
yield clk.posedge
print("test 1: select port 0")

3
lib/axis/tb/test_axis_mux_4.v
View File

@ -52,6 +52,7 @@ reg input_3_axis_tuser = 0;
reg output_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
@ -87,6 +88,7 @@ initial begin
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
enable,
select);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
@ -136,6 +138,7 @@ UUT (
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Control
.enable(enable),
.select(select)
);

5
lib/axis/tb/test_axis_mux_64_4.py
View File

@ -76,6 +76,7 @@ def dut_axis_mux_64_4(clk,
output_axis_tlast,
output_axis_tuser,
enable,
select):
if os.system(build_cmd):
@ -117,6 +118,7 @@ def dut_axis_mux_64_4(clk,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
enable=enable,
select=select)
def bench():
@ -149,6 +151,7 @@ def bench():
output_axis_tready = Signal(bool(0))
enable = Signal(bool(0))
select = Signal(intbv(0)[2:])
# Outputs
@ -269,6 +272,7 @@ def bench():
output_axis_tlast,
output_axis_tuser,
enable,
select)
@always(delay(4))
@ -287,6 +291,7 @@ def bench():
yield clk.posedge
yield clk.posedge
enable.next = True
yield clk.posedge
print("test 1: select port 0")

3
lib/axis/tb/test_axis_mux_64_4.v
View File

@ -56,6 +56,7 @@ reg input_3_axis_tuser = 0;
reg output_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
@ -96,6 +97,7 @@ initial begin
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
enable,
select);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
@ -151,6 +153,7 @@ UUT (
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Control
.enable(enable),
.select(select)
);