From e59f5a03bd06918b2250104bf5fb765289f90c82 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 21 Jun 2023 16:26:40 -0700 Subject: [PATCH] Update example designs based on results of buffer size tests Signed-off-by: Alex Forencich --- example/common/rtl/example_core_pcie_s10.v | 2 +- example/common/tb/example_core_pcie_s10/Makefile | 2 +- .../tb/example_core_pcie_s10/test_example_core_pcie_s10.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/example/common/rtl/example_core_pcie_s10.v b/example/common/rtl/example_core_pcie_s10.v index 1ff6a0a4b..8ceadc3d7 100644 --- a/example/common/rtl/example_core_pcie_s10.v +++ b/example/common/rtl/example_core_pcie_s10.v @@ -58,7 +58,7 @@ module example_core_pcie_s10 # // Completion header flow control credit limit (read) parameter READ_CPLH_FC_LIMIT = 770, // Completion data flow control credit limit (read) - parameter READ_CPLD_FC_LIMIT = 2500, + parameter READ_CPLD_FC_LIMIT = 2400, // Operation table size (write) parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH, // In-flight transmit limit (write) diff --git a/example/common/tb/example_core_pcie_s10/Makefile b/example/common/tb/example_core_pcie_s10/Makefile index 6b629949c..f554059e4 100644 --- a/example/common/tb/example_core_pcie_s10/Makefile +++ b/example/common/tb/example_core_pcie_s10/Makefile @@ -69,7 +69,7 @@ export PARAM_IMM_WIDTH := 32 export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_READ_CPLH_FC_LIMIT := 770 -export PARAM_READ_CPLD_FC_LIMIT := 2500 +export PARAM_READ_CPLD_FC_LIMIT := 2400 export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_BAR0_APERTURE := 24 diff --git a/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py b/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py index 59929ddbf..3fb3de96e 100644 --- a/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py +++ b/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py @@ -482,7 +482,7 @@ def test_example_core_pcie_s10(request, data_width, l_tile): parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT'] parameters['READ_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH'] parameters['READ_CPLH_FC_LIMIT'] = 770 - parameters['READ_CPLD_FC_LIMIT'] = 2500 + parameters['READ_CPLD_FC_LIMIT'] = 2400 parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH'] parameters['WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH'] parameters['BAR0_APERTURE'] = 24