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Alex Forencich
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README.md
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README.md
@ -7,14 +7,14 @@ GitHub repository: https://github.com/ucsdsysnet/corundum
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Corundum is an open-source, high-performance FPGA-based NIC. Features include
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a high performance datapath, 10G/25G/100G Ethernet, PCI express gen 3, a
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custom, high performance, tightly-integrated PCIe DMA engine, many (1000+)
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transmit, receive, completion, and event queues, MSI interrupts, multiple
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interfaces, multiple ports per interface, per-port transmit scheduling
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including high precision TDMA, flow hashing, RSS, checksum offloading, and
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native IEEE 1588 PTP timestamping. A Linux driver is included that integrates
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with the Linux networking stack. Development and debugging is facilitated by
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an extensive simulation framework that covers the entire system from a
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simulation model of the driver and PCI express interface on one side to the
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Ethernet interfaces on the other side.
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transmit, receive, completion, and event queues, scatter/gather DMA, MSI
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interrupts, multiple interfaces, multiple ports per interface, per-port
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transmit scheduling including high precision TDMA, flow hashing, RSS, checksum
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offloading, and native IEEE 1588 PTP timestamping. A Linux driver is included
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that integrates with the Linux networking stack. Development and debugging is
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facilitated by an extensive simulation framework that covers the entire system
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from a simulation model of the driver and PCI express interface on one side to
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the Ethernet interfaces on the other side.
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Corundum has several unique architectural features. First, transmit, receive,
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completion, and event queue states are stored efficiently in block RAM or
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@ -24,22 +24,22 @@ have multiple ports, each with its own independent scheduler. This enables
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extremely fine-grained control over packet transmission. Coupled with PTP time
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synchronization, this enables high precision TDMA.
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Corundum currently supports Xilinx Virtex 7, Ultrascale, and Ultrascale+ series
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Corundum currently supports Xilinx Virtex 7, UltraScale, and UltraScale+ series
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devices. Designs are included for the following FPGA boards:
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* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex Ultrascale+ XCVU3P)
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* Exablaze ExaNIC X10 (Xilinx Kintex Ultrascale XCKU035)
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* Exablaze ExaNIC X25 (Xilinx Kintex Ultrascale+ XCKU3P)
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* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale+ XCVU3P)
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* Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035)
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* Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P)
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* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
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* Xilinx VCU108 (Xilinx Virtex Ultrascale XCVU095)
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* Xilinx VCU118 (Xilinx Virtex Ultrascale+ XCVU9P)
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* Xilinx VCU1525 (Xilinx Virtex Ultrascale+ XCVU9P)
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* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
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* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
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For operation at 10G and 25G, Corundum uses the open source 10G/25G MAC and
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PHY modules from the verilog-ethernet repository, no extra licenses are
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required. However, it is possible to use other MAC and/or PHY modules.
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Operation at 100G currently requires using the Xilinx CMAC core with RS-FEC
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enabled, which is covered by the free CMAC license on Xilinx Ultrascale+ parts.
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enabled, which is covered by the free CMAC license on Xilinx UltraScale+ parts.
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## Documentation
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@ -47,6 +47,8 @@ enabled, which is covered by the free CMAC license on Xilinx Ultrascale+ parts.
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Block diagram of the Corundum NIC. PCIe HIP: PCIe hard IP core; AXIL M: AXI lite master; DMA IF: DMA interface; PTP HC: PTP hardware clock; TXQ: transmit queue manager; TXCQ: transmit completion queue manager; RXQ: receive queue manager; RXCQ: receive completion queue manager; EQ: event queue manager; MAC + PHY: Ethernet media access controller (MAC) and physical interface layer (PHY).
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### Modules
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#### cmac_pad module
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@ -66,17 +68,19 @@ RAM or ultra RAM.
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#### cpl_write module
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Completion write module. Responsible for writing completion and event entries
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into host memory.
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Completion write module. Responsible for enqueuing completion and event
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records into the completion queue managers and writing records into host
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memory via DMA.
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#### desc_fetch module
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Descriptor fetch module. Responsible for reading descriptors from host memory.
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Descriptor fetch module. Responsible for dequeuing descriptors from the queue
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managers and reading descriptors from host memory via DMA.
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#### desc_op_mux module
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Descriptor operation multiplexer module. Merges descriptor fetch operations
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from different sources to enable sharing a single cpl_write module instance.
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from different sources to enable sharing a single desc_fetch module instance.
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#### event_mux module
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@ -88,7 +92,8 @@ Interface module. Contains the event queues, interface queues, and ports.
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#### port module
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Port module. Contains the transmit and receive engines
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Port module. Contains the transmit and receive datapath components, including
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transmit and receive engines and checksum and hash offloading.
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#### queue_manager module
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@ -102,9 +107,10 @@ frame payload to aid in IP checksum offloading.
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#### rx_engine module
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Receive engine. Manages receive descriptor dequeue and fetch via DMA, packet
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reception, data writeback via DMA, and completion enqueue and writeback via
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DMA. Handles PTP timestamps for inclusion in completion records.
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Receive engine. Manages receive datapath operations including descriptor
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dequeue and fetch via DMA, packet reception, data writeback via DMA, and
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completion enqueue and writeback via DMA. Handles PTP timestamps for
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inclusion in completion records.
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#### rx_hash module
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@ -113,14 +119,14 @@ headers and computes 32 bit Toeplitz flow hash.
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#### tdma_ber_ch module
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TDMA bit error ratio test channel module. Controls PRBS logic in Ethernet PHY
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and accumulates bit errors. Can be configured to bin error counts by TDMA
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timeslot.
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TDMA bit error ratio (BER) test channel module. Controls PRBS logic in
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Ethernet PHY and accumulates bit errors. Can be configured to bin error
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counts by TDMA timeslot.
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#### tdma_ber module
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TDMA bit error ratio test module. Wrapper for a tdma_scheduler and multiple
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instances of tdma_ber_ch.
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TDMA bit error ratio (BER) test module. Wrapper for a tdma_scheduler and
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multiple instances of tdma_ber_ch.
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#### tdma_scheduler module
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@ -135,9 +141,10 @@ the specified position.
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#### tx_engine module
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Transmit engine. Manages receive descriptor dequeue and fetch via DMA, packet
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data fetch via DMA, packet transmission, and completion enqueue and writeback
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via DMA. Handles PTP timestamps for inclusion in completion records.
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Transmit engine. Manages transmit datapath operations including descriptor
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dequeue and fetch via DMA, packet data fetch via DMA, packet transmission, and
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completion enqueue and writeback via DMA. Handles PTP timestamps for
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inclusion in completion records.
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#### tx_scheduler_ctrl_tdma module
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@ -189,15 +196,15 @@ individual test scripts can be run with python directly.
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tb/ip_ep.py : MyHDL IP frame endpoints
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tb/mqnic.py : MyHDL mqnic driver model
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tb/pcie.py : MyHDL PCI Express BFM
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tb/pcie_us.py : MyHDL Xilinx Ultrascale PCIe core model
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tb/pcie_usp.py : MyHDL Xilinx Ultrascale+ PCIe core model
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tb/pcie_us.py : MyHDL Xilinx UltraScale PCIe core model
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tb/pcie_usp.py : MyHDL Xilinx UltraScale+ PCIe core model
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tb/ptp.py : MyHDL PTP clock model
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tb/udp_ep.py : MyHDL UDP frame endpoints
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tb/xgmii_ep.py : MyHDL XGMII endpoints
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## Publications
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- A. Forencich, A. C. Snoeren, G. Porter, G. Papen, *Corundum: An Open-Source 100-Gbps NIC,* in FCCM'20, [Paper](https://www.cse.ucsd.edu/~snoeren/papers/corundum-fccm20.pdf)
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- A. Forencich, A. C. Snoeren, G. Porter, G. Papen, *Corundum: An Open-Source 100-Gbps NIC,* in FCCM'20, [Paper](https://www.cse.ucsd.edu/~snoeren/papers/corundum-fccm20.pdf), [Slides](http://fccm.org/....pdf)
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## Citation
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If you use Corundum in your project please cite one of the following papers
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@ -210,6 +217,14 @@ and/or link to the github project:
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booktitle = {28th IEEE International Symposium on Field-Programmable Custom Computing Machines},
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year = {2020},
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}
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@phdthesis{forencich2020thesis,
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author = {John Alexander Forencich},
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title = {System-Level Considerations for Optical Switching in Data Center Networks},
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school = {UC San Diego},
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year = {2020},
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url = {https://escholarship.org/uc/item/???},
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}
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```
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## Dependencies
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