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Code Issues Projects Releases Wiki Activity

merged changes in eth

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This commit is contained in:
Alex Forencich 2023-02-17 16:19:50 -08:00
commit e7953da0c0
91 changed files with 621 additions and 622 deletions
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2
fpga/lib/eth/.github/workflows/regression-tests.yml vendored
View File

@ -5,7 +5,7 @@ on: [push, pull_request]
jobs:
build:
name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10)
runs-on: ubuntu-20.04
runs-on: ubuntu-22.04
strategy:
matrix:

2
fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/Makefile
View File

@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/Arty/fpga/tb/fpga_core/Makefile
View File

@ -62,7 +62,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/Makefile
View File

@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/Makefile
View File

@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile
View File

@ -41,7 +41,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_crosspoint.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/Makefile
View File

@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/Makefile
View File

@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/Makefile
View File

@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/Makefile
View File

@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/Makefile
View File

@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/RV901T/fpga/tb/fpga_core/Makefile
View File

@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/Makefile
View File

@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/Makefile
View File

@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/Makefile
View File

@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/Makefile
View File

@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
#export PARAM_A ?= value
#export PARAM_A := value
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml vendored
View File

@ -5,7 +5,7 @@ on: [push, pull_request]
jobs:
build:
name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10)
runs-on: ubuntu-20.04
runs-on: ubuntu-22.04
strategy:
matrix:

25
fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile
View File

@ -32,19 +32,18 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_S_DATA_WIDTH := 8
export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH := 8
export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

28
fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile
View File

@ -38,20 +38,20 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 8
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_LAST_ENABLE ?= 1
export PARAM_UPDATE_TID ?= 1
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_S_ID_WIDTH := 8
export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_LAST_ENABLE := 1
export PARAM_UPDATE_TID := 1
export PARAM_ARB_TYPE_ROUND_ROBIN := 0
export PARAM_ARB_LSB_HIGH_PRIORITY := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

38
fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile
View File

@ -32,25 +32,25 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_RAM_PIPELINE ?= 1
export PARAM_OUTPUT_FIFO_ENABLE ?= 0
export PARAM_FRAME_FIFO ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_DEPTH := 1024
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_ENABLE := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

44
fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile
View File

@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../rtl/axis_adapter.v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_RAM_PIPELINE ?= 1
export PARAM_OUTPUT_FIFO_ENABLE ?= 0
export PARAM_FRAME_FIFO ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_DEPTH := 1024
export PARAM_S_DATA_WIDTH := 8
export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH := 8
export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_ENABLE := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile
View File

@ -36,16 +36,16 @@ VERILOG_SOURCES += $(WRAPPER).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile
View File

@ -32,7 +32,7 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
# export PARAM_APPEND_ZERO ?= 0
# export PARAM_NAME := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile
View File

@ -33,7 +33,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/axis_fifo.v
# module parameters
export PARAM_APPEND_ZERO ?= 0
export PARAM_APPEND_ZERO := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
fpga/lib/eth/lib/axis/tb/axis_demux/Makefile
View File

@ -36,17 +36,17 @@ VERILOG_SOURCES += $(WRAPPER).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_M_DEST_WIDTH ?= 8
export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())")
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_TDEST_ROUTE ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_M_DEST_WIDTH := 8
export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())")
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_TDEST_ROUTE := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

38
fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile
View File

@ -32,25 +32,25 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_RAM_PIPELINE ?= 1
export PARAM_OUTPUT_FIFO_ENABLE ?= 0
export PARAM_FRAME_FIFO ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_DEPTH := 1024
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_ENABLE := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

44
fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile
View File

@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v
VERILOG_SOURCES += ../../rtl/axis_adapter.v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_RAM_PIPELINE ?= 1
export PARAM_OUTPUT_FIFO_ENABLE ?= 0
export PARAM_FRAME_FIFO ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_DEPTH := 1024
export PARAM_S_DATA_WIDTH := 8
export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH := 8
export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_ENABLE := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_LEN_WIDTH ?= 16
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_LEN_WIDTH := 16
ifeq ($(SIM), icarus)
PLUSARGS += -fst

24
fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile
View File

@ -34,18 +34,18 @@ VERILOG_SOURCES += ../../rtl/axis_frame_length_adjust.v
VERILOG_SOURCES += ../../rtl/axis_fifo.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_LEN_WIDTH ?= 16
export PARAM_FRAME_FIFO_DEPTH ?= 1024
export PARAM_HEADER_FIFO_DEPTH ?= 8
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_LEN_WIDTH := 16
export PARAM_FRAME_FIFO_DEPTH := 1024
export PARAM_HEADER_FIFO_DEPTH := 8
ifeq ($(SIM), icarus)
PLUSARGS += -fst

18
fpga/lib/eth/lib/axis/tb/axis_mux/Makefile
View File

@ -36,15 +36,15 @@ VERILOG_SOURCES += $(WRAPPER).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile
View File

@ -32,17 +32,17 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_LENGTH ?= 2
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_LENGTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

24
fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile
View File

@ -33,18 +33,18 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/axis_register.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_REG_TYPE ?= 2
export PARAM_LENGTH ?= 2
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_REG_TYPE := 2
export PARAM_LENGTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

48
fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile
View File

@ -40,30 +40,30 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_FIFO_DEPTH ?= 4096
export PARAM_CMD_FIFO_DEPTH ?= 32
export PARAM_SPEEDUP ?= 0
export PARAM_S_DATA_WIDTH ?= 8
export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH ?= 8
export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 16
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
export PARAM_M_DEST_WIDTH ?= 8
export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_BAD_FRAME ?= 0
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_UPDATE_TID ?= 1
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
export PARAM_RAM_PIPELINE ?= 2
export PARAM_FIFO_DEPTH := 4096
export PARAM_CMD_FIFO_DEPTH := 32
export PARAM_SPEEDUP := 0
export PARAM_S_DATA_WIDTH := 8
export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
export PARAM_M_DATA_WIDTH := 8
export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_S_ID_WIDTH := 16
export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
export PARAM_M_DEST_WIDTH := 8
export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_BAD_FRAME := 0
export PARAM_DROP_WHEN_FULL := 0
export PARAM_UPDATE_TID := 1
export PARAM_ARB_TYPE_ROUND_ROBIN := 1
export PARAM_ARB_LSB_HIGH_PRIORITY := 1
export PARAM_RAM_PIPELINE := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
fpga/lib/eth/lib/axis/tb/axis_register/Makefile
View File

@ -32,17 +32,17 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_REG_TYPE ?= 2
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_REG_TYPE := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DEPTH ?= 1024
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DEPTH := 1024
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE ?= 1
export PARAM_ID_ENABLE ?= 1
export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_LAST_ENABLE := 1
export PARAM_ID_ENABLE := 1
export PARAM_ID_WIDTH := 8
export PARAM_DEST_ENABLE := 1
export PARAM_DEST_WIDTH := 8
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

30
fpga/lib/eth/lib/axis/tb/axis_switch/Makefile
View File

@ -40,21 +40,21 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE ?= 1
export PARAM_S_ID_WIDTH ?= 16
export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
export PARAM_M_DEST_WIDTH ?= 8
export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_UPDATE_TID ?= 1
export PARAM_S_REG_TYPE ?= 0
export PARAM_M_REG_TYPE ?= 2
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
export PARAM_ID_ENABLE := 1
export PARAM_S_ID_WIDTH := 16
export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")
export PARAM_M_DEST_WIDTH := 8
export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())")
export PARAM_USER_ENABLE := 1
export PARAM_USER_WIDTH := 1
export PARAM_UPDATE_TID := 1
export PARAM_S_REG_TYPE := 0
export PARAM_M_REG_TYPE := 2
export PARAM_ARB_TYPE_ROUND_ROBIN := 1
export PARAM_ARB_LSB_HIGH_PRIORITY := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

14
fpga/lib/eth/tb/arp/Makefile
View File

@ -36,13 +36,13 @@ VERILOG_SOURCES += ../../rtl/arp_cache.v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CACHE_ADDR_WIDTH ?= 2
export PARAM_REQUEST_RETRY_COUNT ?= 4
export PARAM_REQUEST_RETRY_INTERVAL ?= 300
export PARAM_REQUEST_TIMEOUT ?= 800
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CACHE_ADDR_WIDTH := 2
export PARAM_REQUEST_RETRY_COUNT := 4
export PARAM_REQUEST_RETRY_INTERVAL := 300
export PARAM_REQUEST_TIMEOUT := 800
ifeq ($(SIM), icarus)
PLUSARGS += -fst

2
fpga/lib/eth/tb/arp_cache/Makefile
View File

@ -33,7 +33,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_CACHE_ADDR_WIDTH ?= 2
export PARAM_CACHE_ADDR_WIDTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

6
fpga/lib/eth/tb/arp_eth_rx/Makefile
View File

@ -32,9 +32,9 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst

6
fpga/lib/eth/tb/arp_eth_tx/Makefile
View File

@ -32,9 +32,9 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst

12
fpga/lib/eth/tb/axis_baser_rx_64/Makefile
View File

@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH ?= 2
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
export PARAM_DATA_WIDTH := 64
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH := 2
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_WIDTH := 96
export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
fpga/lib/eth/tb/axis_baser_tx_64/Makefile
View File

@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH ?= 2
export PARAM_ENABLE_PADDING ?= 1
export PARAM_ENABLE_DIC ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH ?= 16
export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
export PARAM_DATA_WIDTH := 64
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH := 2
export PARAM_ENABLE_PADDING := 1
export PARAM_ENABLE_DIC := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_WIDTH := 96
export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH := 16
export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
ifeq ($(SIM), icarus)
PLUSARGS += -fst

10
fpga/lib/eth/tb/axis_gmii_rx/Makefile
View File

@ -33,11 +33,11 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_PTP_TS_ENABLE ?= 0
export PARAM_PTP_TS_WIDTH ?= 96
#export PARAM_USER_WIDTH ?= (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_PTP_TS_ENABLE := 0
export PARAM_PTP_TS_WIDTH := 96
#export PARAM_USER_WIDTH := (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

18
fpga/lib/eth/tb/axis_gmii_tx/Makefile
View File

@ -33,15 +33,15 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_PTP_TS_ENABLE ?= 0
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_PTP_TAG_ENABLE ?= PTP_TS_ENABLE
export PARAM_PTP_TAG_WIDTH ?= 16
#export PARAM_USER_WIDTH ?= (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1
export PARAM_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_PTP_TS_ENABLE := 0
export PARAM_PTP_TS_WIDTH := 96
export PARAM_PTP_TAG_ENABLE := PTP_TS_ENABLE
export PARAM_PTP_TAG_WIDTH := 16
#export PARAM_USER_WIDTH := (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1
export PARAM_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

12
fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile
View File

@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
export PARAM_DATA_WIDTH := 32
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_WIDTH := 96
export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
ifeq ($(SIM), icarus)
PLUSARGS += -fst

12
fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile
View File

@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
export PARAM_DATA_WIDTH := 64
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_WIDTH := 96
export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile
View File

@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 32
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_ENABLE_DIC ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH ?= 16
export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
export PARAM_DATA_WIDTH := 32
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_ENABLE_DIC := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_WIDTH := 96
export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH := 16
export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile
View File

@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_ENABLE_DIC ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH ?= 16
export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
export PARAM_DATA_WIDTH := 64
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_ENABLE_DIC := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_WIDTH := 96
export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH := 16
export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
ifeq ($(SIM), icarus)
PLUSARGS += -fst

6
fpga/lib/eth/tb/eth_axis_rx/Makefile
View File

@ -32,9 +32,9 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst

6
fpga/lib/eth/tb/eth_axis_tx/Makefile
View File

@ -32,9 +32,9 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_DATA_WIDTH := 8
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst

32
fpga/lib/eth/tb/eth_mac_10g/Makefile
View File

@ -37,22 +37,22 @@ VERILOG_SOURCES += ../../rtl/axis_xgmii_tx_64.v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_ENABLE_DIC ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_PTP_PERIOD_NS ?= 6
export PARAM_PTP_PERIOD_FNS ?= 26214
export PARAM_TX_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_WIDTH ?= 96
export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_TX_PTP_TAG_WIDTH ?= 16
export PARAM_RX_PTP_TS_ENABLE ?= 1
export PARAM_RX_PTP_TS_WIDTH ?= 96
export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 ))
export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 ))
export PARAM_DATA_WIDTH := 64
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_ENABLE_DIC := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_PTP_PERIOD_NS := 6
export PARAM_PTP_PERIOD_FNS := 26214
export PARAM_TX_PTP_TS_ENABLE := 1
export PARAM_TX_PTP_TS_WIDTH := 96
export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_TX_PTP_TAG_WIDTH := 16
export PARAM_RX_PTP_TS_ENABLE := 1
export PARAM_RX_PTP_TS_WIDTH := 96
export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 ))
export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 ))
ifeq ($(SIM), icarus)
PLUSARGS += -fst

62
fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile
View File

@ -42,37 +42,37 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_AXIS_DATA_WIDTH ?= $(PARAM_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_ENABLE_DIC ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_TX_FIFO_DEPTH ?= 16384
export PARAM_TX_FIFO_RAM_PIPELINE ?= 1
export PARAM_TX_FRAME_FIFO ?= 1
export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL ?= 0
export PARAM_RX_FIFO_DEPTH ?= 16384
export PARAM_RX_FIFO_RAM_PIPELINE ?= 1
export PARAM_RX_FRAME_FIFO ?= 1
export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_PTP_PERIOD_NS ?= 6
export PARAM_PTP_PERIOD_FNS ?= 26214
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_TX_PTP_TS_ENABLE ?= 1
export PARAM_RX_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 64
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH ?= 16
export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
export PARAM_DATA_WIDTH := 64
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_AXIS_DATA_WIDTH := $(PARAM_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_ENABLE_DIC := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1
export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL := 0
export PARAM_RX_FIFO_DEPTH := 16384
export PARAM_RX_FIFO_RAM_PIPELINE := 1
export PARAM_RX_FRAME_FIFO := 1
export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_PTP_PERIOD_NS := 6
export PARAM_PTP_PERIOD_FNS := 26214
export PARAM_PTP_USE_SAMPLE_CLOCK := 0
export PARAM_TX_PTP_TS_ENABLE := 1
export PARAM_RX_PTP_TS_ENABLE := 1
export PARAM_TX_PTP_TS_FIFO_DEPTH := 64
export PARAM_PTP_TS_WIDTH := 96
export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH := 16
export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
ifeq ($(SIM), icarus)
PLUSARGS += -fst

26
fpga/lib/eth/tb/eth_mac_1g/Makefile
View File

@ -35,19 +35,19 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 8
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_TX_PTP_TS_ENABLE ?= 0
export PARAM_TX_PTP_TS_WIDTH ?= 96
export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_TX_PTP_TAG_WIDTH ?= 16
export PARAM_RX_PTP_TS_ENABLE ?= 0
export PARAM_RX_PTP_TS_WIDTH ?= 96
# export PARAM_TX_USER_WIDTH ?= (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1
export PARAM_TX_USER_WIDTH ?= 1
# export PARAM_RX_USER_WIDTH ?= (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1
export PARAM_RX_USER_WIDTH ?= 1
export PARAM_DATA_WIDTH := 8
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_TX_PTP_TS_ENABLE := 0
export PARAM_TX_PTP_TS_WIDTH := 96
export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_TX_PTP_TAG_WIDTH := 16
export PARAM_RX_PTP_TS_ENABLE := 0
export PARAM_RX_PTP_TS_WIDTH := 96
# export PARAM_TX_USER_WIDTH := (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1
export PARAM_TX_USER_WIDTH := 1
# export PARAM_RX_USER_WIDTH := (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1
export PARAM_RX_USER_WIDTH := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst

30
fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile
View File

@ -39,21 +39,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
export PARAM_AXIS_DATA_WIDTH ?= 8
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_TX_FIFO_DEPTH ?= 16384
export PARAM_TX_FRAME_FIFO ?= 1
export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL ?= 0
export PARAM_RX_FIFO_DEPTH ?= 16384
export PARAM_RX_FRAME_FIFO ?= 1
export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_AXIS_DATA_WIDTH := 8
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FRAME_FIFO := 1
export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL := 0
export PARAM_RX_FIFO_DEPTH := 16384
export PARAM_RX_FRAME_FIFO := 1
export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
ifeq ($(SIM), icarus)
PLUSARGS += -fst

4
fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile
View File

@ -40,8 +40,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
ifeq ($(SIM), icarus)
PLUSARGS += -fst

30
fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile
View File

@ -44,21 +44,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
export PARAM_AXIS_DATA_WIDTH ?= 8
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_TX_FIFO_DEPTH ?= 16384
export PARAM_TX_FRAME_FIFO ?= 1
export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL ?= 0
export PARAM_RX_FIFO_DEPTH ?= 16384
export PARAM_RX_FRAME_FIFO ?= 1
export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_AXIS_DATA_WIDTH := 8
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FRAME_FIFO := 1
export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL := 0
export PARAM_RX_FIFO_DEPTH := 16384
export PARAM_RX_FRAME_FIFO := 1
export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
ifeq ($(SIM), icarus)
PLUSARGS += -fst

4
fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile
View File

@ -40,8 +40,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
ifeq ($(SIM), icarus)
PLUSARGS += -fst

30
fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile
View File

@ -44,21 +44,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
export PARAM_AXIS_DATA_WIDTH ?= 8
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_TX_FIFO_DEPTH ?= 16384
export PARAM_TX_FRAME_FIFO ?= 1
export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL ?= 0
export PARAM_RX_FIFO_DEPTH ?= 16384
export PARAM_RX_FRAME_FIFO ?= 1
export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_AXIS_DATA_WIDTH := 8
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FRAME_FIFO := 1
export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL := 0
export PARAM_RX_FIFO_DEPTH := 16384
export PARAM_RX_FRAME_FIFO := 1
export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
ifeq ($(SIM), icarus)
PLUSARGS += -fst

4
fpga/lib/eth/tb/eth_mac_mii/Makefile
View File

@ -38,8 +38,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
ifeq ($(SIM), icarus)
PLUSARGS += -fst

30
fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile
View File

@ -42,21 +42,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
export PARAM_AXIS_DATA_WIDTH ?= 8
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_TX_FIFO_DEPTH ?= 16384
export PARAM_TX_FRAME_FIFO ?= 1
export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL ?= 0
export PARAM_RX_FIFO_DEPTH ?= 16384
export PARAM_RX_FRAME_FIFO ?= 1
export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_AXIS_DATA_WIDTH := 8
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FRAME_FIFO := 1
export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL := 0
export PARAM_RX_FIFO_DEPTH := 16384
export PARAM_RX_FRAME_FIFO := 1
export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
ifeq ($(SIM), icarus)
PLUSARGS += -fst

48
fpga/lib/eth/tb/eth_mac_phy_10g/Makefile
View File

@ -42,30 +42,30 @@ VERILOG_SOURCES += ../../rtl/axis_baser_tx_64.v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH ?= 2
export PARAM_ENABLE_PADDING ?= 1
export PARAM_ENABLE_DIC ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_PTP_PERIOD_NS ?= 6
export PARAM_PTP_PERIOD_FNS ?= 26214
export PARAM_TX_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_WIDTH ?= 96
export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_TX_PTP_TAG_WIDTH ?= 16
export PARAM_RX_PTP_TS_ENABLE ?= 1
export PARAM_RX_PTP_TS_WIDTH ?= 96
export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 ))
export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 ))
export PARAM_BIT_REVERSE ?= 0
export PARAM_SCRAMBLER_DISABLE ?= 0
export PARAM_PRBS31_ENABLE ?= 1
export PARAM_TX_SERDES_PIPELINE ?= 2
export PARAM_RX_SERDES_PIPELINE ?= 2
export PARAM_BITSLIP_HIGH_CYCLES ?= 1
export PARAM_BITSLIP_LOW_CYCLES ?= 8
export PARAM_COUNT_125US ?= 195
export PARAM_DATA_WIDTH := 64
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH := 2
export PARAM_ENABLE_PADDING := 1
export PARAM_ENABLE_DIC := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_PTP_PERIOD_NS := 6
export PARAM_PTP_PERIOD_FNS := 26214
export PARAM_TX_PTP_TS_ENABLE := 1
export PARAM_TX_PTP_TS_WIDTH := 96
export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_TX_PTP_TAG_WIDTH := 16
export PARAM_RX_PTP_TS_ENABLE := 1
export PARAM_RX_PTP_TS_WIDTH := 96
export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 ))
export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 ))
export PARAM_BIT_REVERSE := 0
export PARAM_SCRAMBLER_DISABLE := 0
export PARAM_PRBS31_ENABLE := 1
export PARAM_TX_SERDES_PIPELINE := 2
export PARAM_RX_SERDES_PIPELINE := 2
export PARAM_BITSLIP_HIGH_CYCLES := 1
export PARAM_BITSLIP_LOW_CYCLES := 8
export PARAM_COUNT_125US := 195
ifeq ($(SIM), icarus)
PLUSARGS += -fst

78
fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile
View File

@ -47,45 +47,45 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_HDR_WIDTH ?= 2
export PARAM_AXIS_DATA_WIDTH ?= $(PARAM_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING ?= 1
export PARAM_ENABLE_DIC ?= 1
export PARAM_MIN_FRAME_LENGTH ?= 64
export PARAM_TX_FIFO_DEPTH ?= 16384
export PARAM_TX_FIFO_RAM_PIPELINE ?= 1
export PARAM_TX_FRAME_FIFO ?= 1
export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL ?= 0
export PARAM_RX_FIFO_DEPTH ?= 16384
export PARAM_RX_FIFO_RAM_PIPELINE ?= 1
export PARAM_RX_FRAME_FIFO ?= 1
export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_PTP_PERIOD_NS ?= 6
export PARAM_PTP_PERIOD_FNS ?= 26214
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_TX_PTP_TS_ENABLE ?= 1
export PARAM_RX_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 64
export PARAM_PTP_TS_WIDTH ?= 96
export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH ?= 16
export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
export PARAM_BIT_REVERSE ?= 0
export PARAM_SCRAMBLER_DISABLE ?= 0
export PARAM_PRBS31_ENABLE ?= 1
export PARAM_TX_SERDES_PIPELINE ?= 2
export PARAM_RX_SERDES_PIPELINE ?= 2
export PARAM_BITSLIP_HIGH_CYCLES ?= 1
export PARAM_BITSLIP_LOW_CYCLES ?= 8
export PARAM_COUNT_125US ?= 195
export PARAM_DATA_WIDTH := 64
export PARAM_HDR_WIDTH := 2
export PARAM_AXIS_DATA_WIDTH := $(PARAM_DATA_WIDTH)
export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PADDING := 1
export PARAM_ENABLE_DIC := 1
export PARAM_MIN_FRAME_LENGTH := 64
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1
export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL := 0
export PARAM_RX_FIFO_DEPTH := 16384
export PARAM_RX_FIFO_RAM_PIPELINE := 1
export PARAM_RX_FRAME_FIFO := 1
export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_PTP_PERIOD_NS := 6
export PARAM_PTP_PERIOD_FNS := 26214
export PARAM_PTP_USE_SAMPLE_CLOCK := 0
export PARAM_TX_PTP_TS_ENABLE := 1
export PARAM_RX_PTP_TS_ENABLE := 1
export PARAM_TX_PTP_TS_FIFO_DEPTH := 64
export PARAM_PTP_TS_WIDTH := 96
export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE)
export PARAM_PTP_TAG_WIDTH := 16
export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 ))
export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
export PARAM_BIT_REVERSE := 0
export PARAM_SCRAMBLER_DISABLE := 0
export PARAM_PRBS31_ENABLE := 1
export PARAM_TX_SERDES_PIPELINE := 2
export PARAM_RX_SERDES_PIPELINE := 2
export PARAM_BITSLIP_HIGH_CYCLES := 1
export PARAM_BITSLIP_LOW_CYCLES := 8
export PARAM_COUNT_125US := 195
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
fpga/lib/eth/tb/eth_phy_10g/Makefile
View File

@ -43,17 +43,17 @@ VERILOG_SOURCES += ../../rtl/xgmii_baser_enc_64.v
VERILOG_SOURCES += ../../rtl/lfsr.v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH ?= 2
export PARAM_BIT_REVERSE ?= 0
export PARAM_SCRAMBLER_DISABLE ?= 0
export PARAM_PRBS31_ENABLE ?= 1
export PARAM_TX_SERDES_PIPELINE ?= 2
export PARAM_RX_SERDES_PIPELINE ?= 2
export PARAM_BITSLIP_HIGH_CYCLES ?= 1
export PARAM_BITSLIP_LOW_CYCLES ?= 8
export PARAM_COUNT_125US ?= 195
export PARAM_DATA_WIDTH := 64
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH := 2
export PARAM_BIT_REVERSE := 0
export PARAM_SCRAMBLER_DISABLE := 0
export PARAM_PRBS31_ENABLE := 1
export PARAM_TX_SERDES_PIPELINE := 2
export PARAM_RX_SERDES_PIPELINE := 2
export PARAM_BITSLIP_HIGH_CYCLES := 1
export PARAM_BITSLIP_LOW_CYCLES := 8
export PARAM_COUNT_125US := 195
ifeq ($(SIM), icarus)
PLUSARGS += -fst

22
fpga/lib/eth/tb/ptp_clock/Makefile
View File

@ -32,17 +32,17 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_PERIOD_NS_WIDTH ?= 4
export PARAM_OFFSET_NS_WIDTH ?= 4
export PARAM_DRIFT_NS_WIDTH ?= 4
export PARAM_FNS_WIDTH ?= 16
export PARAM_PERIOD_NS ?= 6
export PARAM_PERIOD_FNS ?= 26214
export PARAM_DRIFT_ENABLE ?= 1
export PARAM_DRIFT_NS ?= 0
export PARAM_DRIFT_FNS ?= 2
export PARAM_DRIFT_RATE ?= 5
export PARAM_PIPELINE_OUTPUT ?= 0
export PARAM_PERIOD_NS_WIDTH := 4
export PARAM_OFFSET_NS_WIDTH := 4
export PARAM_DRIFT_NS_WIDTH := 4
export PARAM_FNS_WIDTH := 16
export PARAM_PERIOD_NS := 6
export PARAM_PERIOD_FNS := 26214
export PARAM_DRIFT_ENABLE := 1
export PARAM_DRIFT_NS := 0
export PARAM_DRIFT_FNS := 2
export PARAM_DRIFT_RATE := 5
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

12
fpga/lib/eth/tb/ptp_clock_cdc/Makefile
View File

@ -32,12 +32,12 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_TS_WIDTH ?= 96
export PARAM_NS_WIDTH ?= 4
export PARAM_FNS_WIDTH ?= 16
export PARAM_USE_SAMPLE_CLOCK ?= 1
export PARAM_LOG_RATE ?= 3
export PARAM_PIPELINE_OUTPUT ?= 0
export PARAM_TS_WIDTH := 96
export PARAM_NS_WIDTH := 4
export PARAM_FNS_WIDTH := 16
export PARAM_USE_SAMPLE_CLOCK := 1
export PARAM_LOG_RATE := 3
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

20
fpga/lib/eth/tb/ptp_perout/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_FNS_ENABLE ?= 1
export PARAM_OUT_START_S ?= 0
export PARAM_OUT_START_NS ?= 0
export PARAM_OUT_START_FNS ?= 0
export PARAM_OUT_PERIOD_S ?= 1
export PARAM_OUT_PERIOD_NS ?= 0
export PARAM_OUT_PERIOD_FNS ?= 0
export PARAM_OUT_WIDTH_S ?= 0
export PARAM_OUT_WIDTH_NS ?= 1000
export PARAM_OUT_WIDTH_FNS ?= 0
export PARAM_FNS_ENABLE := 1
export PARAM_OUT_START_S := 0
export PARAM_OUT_START_NS := 0
export PARAM_OUT_START_FNS := 0
export PARAM_OUT_PERIOD_S := 1
export PARAM_OUT_PERIOD_NS := 0
export PARAM_OUT_PERIOD_FNS := 0
export PARAM_OUT_WIDTH_S := 0
export PARAM_OUT_WIDTH_NS := 1000
export PARAM_OUT_WIDTH_FNS := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst

6
fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile
View File

@ -32,9 +32,9 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH ?= 2
export PARAM_DATA_WIDTH := 64
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst

6
fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile
View File

@ -32,9 +32,9 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_DATA_WIDTH ?= 64
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH ?= 2
export PARAM_DATA_WIDTH := 64
export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
export PARAM_HDR_WIDTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst