diff --git a/fpga/lib/eth/.github/workflows/regression-tests.yml b/fpga/lib/eth/.github/workflows/regression-tests.yml index 6acc2873c..3135aa90d 100644 --- a/fpga/lib/eth/.github/workflows/regression-tests.yml +++ b/fpga/lib/eth/.github/workflows/regression-tests.yml @@ -5,7 +5,7 @@ on: [push, pull_request] jobs: build: name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10) - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 strategy: matrix: diff --git a/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/Makefile index 8541e6ca4..36af9e16c 100644 --- a/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/Makefile index 5f583808b..6a09f4124 100644 --- a/fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ATLYS/fpga/tb/fpga_core/Makefile @@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/Arty/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/Arty/fpga/tb/fpga_core/Makefile index 1181f3bf4..72017d7d9 100644 --- a/fpga/lib/eth/example/Arty/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/Arty/fpga/tb/fpga_core/Makefile @@ -62,7 +62,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/Makefile index c6328a449..2c0f29ce3 100644 --- a/fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/C10LP/fpga/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/Makefile index 8c990bc4c..c5c8c030b 100644 --- a/fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/fpga_core/Makefile @@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile b/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile index 22a78d717..c0dda222d 100644 --- a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile @@ -41,7 +41,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_crosspoint.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/Makefile b/fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/Makefile index 5f583808b..6a09f4124 100644 --- a/fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/KC705/fpga_gmii/tb/fpga_core/Makefile @@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/Makefile b/fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/Makefile index c6328a449..2c0f29ce3 100644 --- a/fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/KC705/fpga_rgmii/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/Makefile b/fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/Makefile index 9c8aced94..8a2c204b5 100644 --- a/fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/KC705/fpga_sgmii/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/Makefile b/fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/Makefile index 5f583808b..6a09f4124 100644 --- a/fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ML605/fpga_gmii/tb/fpga_core/Makefile @@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/Makefile b/fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/Makefile index c6328a449..2c0f29ce3 100644 --- a/fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ML605/fpga_rgmii/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/Makefile b/fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/Makefile index 9c8aced94..8a2c204b5 100644 --- a/fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ML605/fpga_sgmii/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/Makefile index c6328a449..2c0f29ce3 100644 --- a/fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/NexysVideo/fpga/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/RV901T/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/RV901T/fpga/tb/fpga_core/Makefile index c6328a449..2c0f29ce3 100644 --- a/fpga/lib/eth/example/RV901T/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/RV901T/fpga/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile index 8541e6ca4..36af9e16c 100644 --- a/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/Makefile index 7641e3f0e..682ed9c2a 100644 --- a/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/Makefile @@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/Makefile b/fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/Makefile index 9c8aced94..8a2c204b5 100644 --- a/fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/VCU108/fpga_1g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/Makefile index 7641e3f0e..682ed9c2a 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/Makefile @@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/Makefile b/fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/Makefile index 9c8aced94..8a2c204b5 100644 --- a/fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/VCU118/fpga_1g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/Makefile index 7641e3f0e..682ed9c2a 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/Makefile index 87e6cf660..d840fbe00 100644 --- a/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml b/fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml index bd104f64f..2c0e252e4 100644 --- a/fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml +++ b/fpga/lib/eth/lib/axis/.github/workflows/regression-tests.yml @@ -5,7 +5,7 @@ on: [push, pull_request] jobs: build: name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10) - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 strategy: matrix: diff --git a/fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile b/fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile index 9f9110dca..3e06415e4 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile @@ -32,19 +32,18 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_S_DATA_WIDTH ?= 8 -export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_M_DATA_WIDTH ?= 8 -export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_S_DATA_WIDTH := 8 +export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) +export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_M_DATA_WIDTH := 8 +export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) +export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile b/fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile index 194d8975e..a75b88be8 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile @@ -38,20 +38,20 @@ VERILOG_SOURCES += ../../rtl/arbiter.v VERILOG_SOURCES += ../../rtl/priority_encoder.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_ID_ENABLE ?= 1 -export PARAM_S_ID_WIDTH ?= 8 -export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())") -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_LAST_ENABLE ?= 1 -export PARAM_UPDATE_TID ?= 1 -export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0 -export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_S_ID_WIDTH := 8 +export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())") +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_LAST_ENABLE := 1 +export PARAM_UPDATE_TID := 1 +export PARAM_ARB_TYPE_ROUND_ROBIN := 0 +export PARAM_ARB_LSB_HIGH_PRIORITY := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile index 792f5532c..70c29fd77 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile @@ -32,25 +32,25 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DEPTH ?= 1024 -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_RAM_PIPELINE ?= 1 -export PARAM_OUTPUT_FIFO_ENABLE ?= 0 -export PARAM_FRAME_FIFO ?= 1 -export PARAM_USER_BAD_FRAME_VALUE ?= 1 -export PARAM_USER_BAD_FRAME_MASK ?= 1 -export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO) -export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME) -export PARAM_DROP_WHEN_FULL ?= 0 +export PARAM_DEPTH := 1024 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_RAM_PIPELINE := 1 +export PARAM_OUTPUT_FIFO_ENABLE := 0 +export PARAM_FRAME_FIFO := 1 +export PARAM_USER_BAD_FRAME_VALUE := 1 +export PARAM_USER_BAD_FRAME_MASK := 1 +export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) +export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) +export PARAM_DROP_WHEN_FULL := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile b/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile index 7c7d65f93..90cca22fe 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile @@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/axis_async_fifo.v VERILOG_SOURCES += ../../rtl/axis_adapter.v # module parameters -export PARAM_DEPTH ?= 1024 -export PARAM_S_DATA_WIDTH ?= 8 -export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_M_DATA_WIDTH ?= 8 -export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_RAM_PIPELINE ?= 1 -export PARAM_OUTPUT_FIFO_ENABLE ?= 0 -export PARAM_FRAME_FIFO ?= 1 -export PARAM_USER_BAD_FRAME_VALUE ?= 1 -export PARAM_USER_BAD_FRAME_MASK ?= 1 -export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO) -export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME) -export PARAM_DROP_WHEN_FULL ?= 0 +export PARAM_DEPTH := 1024 +export PARAM_S_DATA_WIDTH := 8 +export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) +export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_M_DATA_WIDTH := 8 +export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) +export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_RAM_PIPELINE := 1 +export PARAM_OUTPUT_FIFO_ENABLE := 0 +export PARAM_FRAME_FIFO := 1 +export PARAM_USER_BAD_FRAME_VALUE := 1 +export PARAM_USER_BAD_FRAME_MASK := 1 +export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) +export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) +export PARAM_DROP_WHEN_FULL := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile b/fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile index afef17eca..51989b311 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile @@ -36,16 +36,16 @@ VERILOG_SOURCES += $(WRAPPER).v VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile b/fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile index 535c69dbe..45723c8b3 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_cobs_decode/Makefile @@ -32,7 +32,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -# export PARAM_APPEND_ZERO ?= 0 +# export PARAM_NAME := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile b/fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile index e0b47bc58..1b700a680 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_cobs_encode/Makefile @@ -33,7 +33,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/axis_fifo.v # module parameters -export PARAM_APPEND_ZERO ?= 0 +export PARAM_APPEND_ZERO := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_demux/Makefile b/fpga/lib/eth/lib/axis/tb/axis_demux/Makefile index 1a304bffc..745c2aca3 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_demux/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_demux/Makefile @@ -36,17 +36,17 @@ VERILOG_SOURCES += $(WRAPPER).v VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_M_DEST_WIDTH ?= 8 -export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())") -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_TDEST_ROUTE ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_M_DEST_WIDTH := 8 +export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())") +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_TDEST_ROUTE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile index cd64ead7e..d22bb2aa8 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile @@ -32,25 +32,25 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DEPTH ?= 1024 -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_RAM_PIPELINE ?= 1 -export PARAM_OUTPUT_FIFO_ENABLE ?= 0 -export PARAM_FRAME_FIFO ?= 1 -export PARAM_USER_BAD_FRAME_VALUE ?= 1 -export PARAM_USER_BAD_FRAME_MASK ?= 1 -export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO) -export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME) -export PARAM_DROP_WHEN_FULL ?= 0 +export PARAM_DEPTH := 1024 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_RAM_PIPELINE := 1 +export PARAM_OUTPUT_FIFO_ENABLE := 0 +export PARAM_FRAME_FIFO := 1 +export PARAM_USER_BAD_FRAME_VALUE := 1 +export PARAM_USER_BAD_FRAME_MASK := 1 +export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) +export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) +export PARAM_DROP_WHEN_FULL := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile b/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile index bda1e8c98..e53ca10b3 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile @@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v VERILOG_SOURCES += ../../rtl/axis_adapter.v # module parameters -export PARAM_DEPTH ?= 1024 -export PARAM_S_DATA_WIDTH ?= 8 -export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_M_DATA_WIDTH ?= 8 -export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_RAM_PIPELINE ?= 1 -export PARAM_OUTPUT_FIFO_ENABLE ?= 0 -export PARAM_FRAME_FIFO ?= 1 -export PARAM_USER_BAD_FRAME_VALUE ?= 1 -export PARAM_USER_BAD_FRAME_MASK ?= 1 -export PARAM_DROP_OVERSIZE_FRAME ?= $(PARAM_FRAME_FIFO) -export PARAM_DROP_BAD_FRAME ?= $(PARAM_DROP_OVERSIZE_FRAME) -export PARAM_DROP_WHEN_FULL ?= 0 +export PARAM_DEPTH := 1024 +export PARAM_S_DATA_WIDTH := 8 +export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) +export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_M_DATA_WIDTH := 8 +export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) +export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_RAM_PIPELINE := 1 +export PARAM_OUTPUT_FIFO_ENABLE := 0 +export PARAM_FRAME_FIFO := 1 +export PARAM_USER_BAD_FRAME_VALUE := 1 +export PARAM_USER_BAD_FRAME_MASK := 1 +export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) +export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) +export PARAM_DROP_WHEN_FULL := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile b/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile index 60983e25a..fe56f6089 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile @@ -32,16 +32,16 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_LEN_WIDTH ?= 16 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_LEN_WIDTH := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile index aac62b210..ba9d56f85 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile @@ -34,18 +34,18 @@ VERILOG_SOURCES += ../../rtl/axis_frame_length_adjust.v VERILOG_SOURCES += ../../rtl/axis_fifo.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_LEN_WIDTH ?= 16 -export PARAM_FRAME_FIFO_DEPTH ?= 1024 -export PARAM_HEADER_FIFO_DEPTH ?= 8 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_LEN_WIDTH := 16 +export PARAM_FRAME_FIFO_DEPTH := 1024 +export PARAM_HEADER_FIFO_DEPTH := 8 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_mux/Makefile b/fpga/lib/eth/lib/axis/tb/axis_mux/Makefile index c5d945d34..102c3dc4e 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_mux/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_mux/Makefile @@ -36,15 +36,15 @@ VERILOG_SOURCES += $(WRAPPER).v VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile index f60a41da1..43eb02ca0 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile @@ -32,17 +32,17 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_LENGTH ?= 2 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_LENGTH := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile b/fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile index a36c6995e..7de3306b9 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile @@ -33,18 +33,18 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/axis_register.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_REG_TYPE ?= 2 -export PARAM_LENGTH ?= 2 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_REG_TYPE := 2 +export PARAM_LENGTH := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile b/fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile index 674c2bed2..68398ad46 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile @@ -40,30 +40,30 @@ VERILOG_SOURCES += ../../rtl/arbiter.v VERILOG_SOURCES += ../../rtl/priority_encoder.v # module parameters -export PARAM_FIFO_DEPTH ?= 4096 -export PARAM_CMD_FIFO_DEPTH ?= 32 -export PARAM_SPEEDUP ?= 0 -export PARAM_S_DATA_WIDTH ?= 8 -export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_M_DATA_WIDTH ?= 8 -export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_ID_ENABLE ?= 1 -export PARAM_S_ID_WIDTH ?= 16 -export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())") -export PARAM_M_DEST_WIDTH ?= 8 -export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())") -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_USER_BAD_FRAME_VALUE ?= 1 -export PARAM_USER_BAD_FRAME_MASK ?= 1 -export PARAM_DROP_BAD_FRAME ?= 0 -export PARAM_DROP_WHEN_FULL ?= 0 -export PARAM_UPDATE_TID ?= 1 -export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1 -export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 -export PARAM_RAM_PIPELINE ?= 2 +export PARAM_FIFO_DEPTH := 4096 +export PARAM_CMD_FIFO_DEPTH := 32 +export PARAM_SPEEDUP := 0 +export PARAM_S_DATA_WIDTH := 8 +export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) +export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_M_DATA_WIDTH := 8 +export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) +export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_S_ID_WIDTH := 16 +export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())") +export PARAM_M_DEST_WIDTH := 8 +export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())") +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_USER_BAD_FRAME_VALUE := 1 +export PARAM_USER_BAD_FRAME_MASK := 1 +export PARAM_DROP_BAD_FRAME := 0 +export PARAM_DROP_WHEN_FULL := 0 +export PARAM_UPDATE_TID := 1 +export PARAM_ARB_TYPE_ROUND_ROBIN := 1 +export PARAM_ARB_LSB_HIGH_PRIORITY := 1 +export PARAM_RAM_PIPELINE := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile b/fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile index 858372c43..40bf6b3cc 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile @@ -32,16 +32,16 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_register/Makefile b/fpga/lib/eth/lib/axis/tb/axis_register/Makefile index 9015a57c9..7ba3d180e 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_register/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_register/Makefile @@ -32,17 +32,17 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_REG_TYPE ?= 2 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_REG_TYPE := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile index 2d25adf0d..80a2946e7 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile @@ -32,16 +32,16 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DEPTH ?= 1024 -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DEPTH := 1024 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile b/fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile index 7a6e63cf1..733fc42ee 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile @@ -32,16 +32,16 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE ?= 1 -export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 -export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_LAST_ENABLE := 1 +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_switch/Makefile b/fpga/lib/eth/lib/axis/tb/axis_switch/Makefile index 229f5f8c8..ef7b1a719 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_switch/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_switch/Makefile @@ -40,21 +40,21 @@ VERILOG_SOURCES += ../../rtl/arbiter.v VERILOG_SOURCES += ../../rtl/priority_encoder.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_ID_ENABLE ?= 1 -export PARAM_S_ID_WIDTH ?= 16 -export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())") -export PARAM_M_DEST_WIDTH ?= 8 -export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())") -export PARAM_USER_ENABLE ?= 1 -export PARAM_USER_WIDTH ?= 1 -export PARAM_UPDATE_TID ?= 1 -export PARAM_S_REG_TYPE ?= 0 -export PARAM_M_REG_TYPE ?= 2 -export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1 -export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_S_ID_WIDTH := 16 +export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())") +export PARAM_M_DEST_WIDTH := 8 +export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())") +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_UPDATE_TID := 1 +export PARAM_S_REG_TYPE := 0 +export PARAM_M_REG_TYPE := 2 +export PARAM_ARB_TYPE_ROUND_ROBIN := 1 +export PARAM_ARB_LSB_HIGH_PRIORITY := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/arp/Makefile b/fpga/lib/eth/tb/arp/Makefile index e0e93714b..c9b623cf0 100644 --- a/fpga/lib/eth/tb/arp/Makefile +++ b/fpga/lib/eth/tb/arp/Makefile @@ -36,13 +36,13 @@ VERILOG_SOURCES += ../../rtl/arp_cache.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CACHE_ADDR_WIDTH ?= 2 -export PARAM_REQUEST_RETRY_COUNT ?= 4 -export PARAM_REQUEST_RETRY_INTERVAL ?= 300 -export PARAM_REQUEST_TIMEOUT ?= 800 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CACHE_ADDR_WIDTH := 2 +export PARAM_REQUEST_RETRY_COUNT := 4 +export PARAM_REQUEST_RETRY_INTERVAL := 300 +export PARAM_REQUEST_TIMEOUT := 800 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/arp_cache/Makefile b/fpga/lib/eth/tb/arp_cache/Makefile index ccb5334b3..12b9df7cb 100644 --- a/fpga/lib/eth/tb/arp_cache/Makefile +++ b/fpga/lib/eth/tb/arp_cache/Makefile @@ -33,7 +33,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_CACHE_ADDR_WIDTH ?= 2 +export PARAM_CACHE_ADDR_WIDTH := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/arp_eth_rx/Makefile b/fpga/lib/eth/tb/arp_eth_rx/Makefile index f8fe08abd..9a46b94d7 100644 --- a/fpga/lib/eth/tb/arp_eth_rx/Makefile +++ b/fpga/lib/eth/tb/arp_eth_rx/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/arp_eth_tx/Makefile b/fpga/lib/eth/tb/arp_eth_tx/Makefile index fb605e5d6..1cce30c4d 100644 --- a/fpga/lib/eth/tb/arp_eth_tx/Makefile +++ b/fpga/lib/eth/tb/arp_eth_tx/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_baser_rx_64/Makefile b/fpga/lib/eth/tb/axis_baser_rx_64/Makefile index 654a8683e..67ece95a1 100644 --- a/fpga/lib/eth/tb/axis_baser_rx_64/Makefile +++ b/fpga/lib/eth/tb/axis_baser_rx_64/Makefile @@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_baser_tx_64/Makefile b/fpga/lib/eth/tb/axis_baser_tx_64/Makefile index 76dece3f2..26b54659c 100644 --- a/fpga/lib/eth/tb/axis_baser_tx_64/Makefile +++ b/fpga/lib/eth/tb/axis_baser_tx_64/Makefile @@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_gmii_rx/Makefile b/fpga/lib/eth/tb/axis_gmii_rx/Makefile index 2a87edb7f..1fbe4ebbb 100644 --- a/fpga/lib/eth/tb/axis_gmii_rx/Makefile +++ b/fpga/lib/eth/tb/axis_gmii_rx/Makefile @@ -33,11 +33,11 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_PTP_TS_ENABLE ?= 0 -export PARAM_PTP_TS_WIDTH ?= 96 -#export PARAM_USER_WIDTH ?= (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_PTP_TS_ENABLE := 0 +export PARAM_PTP_TS_WIDTH := 96 +#export PARAM_USER_WIDTH := (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_gmii_tx/Makefile b/fpga/lib/eth/tb/axis_gmii_tx/Makefile index f97bec4ab..a1aebdac3 100644 --- a/fpga/lib/eth/tb/axis_gmii_tx/Makefile +++ b/fpga/lib/eth/tb/axis_gmii_tx/Makefile @@ -33,15 +33,15 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_TS_ENABLE ?= 0 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_PTP_TAG_ENABLE ?= PTP_TS_ENABLE -export PARAM_PTP_TAG_WIDTH ?= 16 -#export PARAM_USER_WIDTH ?= (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_TS_ENABLE := 0 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TAG_ENABLE := PTP_TS_ENABLE +export PARAM_PTP_TAG_WIDTH := 16 +#export PARAM_USER_WIDTH := (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile b/fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile index 1e978b020..c104ad285 100644 --- a/fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_rx_32/Makefile @@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 32 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 32 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile b/fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile index 8f0d9b226..923a45d7c 100644 --- a/fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_rx_64/Makefile @@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile b/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile index 3e0a0c89a..e24b2f9a1 100644 --- a/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile @@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 32 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 32 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile b/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile index 86797aeab..7743dd38b 100644 --- a/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile @@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_axis_rx/Makefile b/fpga/lib/eth/tb/eth_axis_rx/Makefile index e13de5252..c10b54273 100644 --- a/fpga/lib/eth/tb/eth_axis_rx/Makefile +++ b/fpga/lib/eth/tb/eth_axis_rx/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_axis_tx/Makefile b/fpga/lib/eth/tb/eth_axis_tx/Makefile index e290f7f9c..3390142ac 100644 --- a/fpga/lib/eth/tb/eth_axis_tx/Makefile +++ b/fpga/lib/eth/tb/eth_axis_tx/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_10g/Makefile b/fpga/lib/eth/tb/eth_mac_10g/Makefile index a09e617c8..d9df95bc9 100644 --- a/fpga/lib/eth/tb/eth_mac_10g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_10g/Makefile @@ -37,22 +37,22 @@ VERILOG_SOURCES += ../../rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_PERIOD_NS ?= 6 -export PARAM_PTP_PERIOD_FNS ?= 26214 -export PARAM_TX_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_TX_PTP_TAG_WIDTH ?= 16 -export PARAM_RX_PTP_TS_ENABLE ?= 1 -export PARAM_RX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) -export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_PERIOD_NS := 6 +export PARAM_PTP_PERIOD_FNS := 26214 +export PARAM_TX_PTP_TS_ENABLE := 1 +export PARAM_TX_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_TX_PTP_TAG_WIDTH := 16 +export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_WIDTH := 96 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile index 18680e338..b7c4c1bf1 100644 --- a/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile @@ -42,37 +42,37 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_AXIS_DATA_WIDTH ?= $(PARAM_DATA_WIDTH) -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FIFO_RAM_PIPELINE ?= 1 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FIFO_RAM_PIPELINE ?= 1 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_PTP_PERIOD_NS ?= 6 -export PARAM_PTP_PERIOD_FNS ?= 26214 -export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0 -export PARAM_TX_PTP_TS_ENABLE ?= 1 -export PARAM_RX_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 64 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) -export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_AXIS_DATA_WIDTH := $(PARAM_DATA_WIDTH) +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FIFO_RAM_PIPELINE := 1 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FIFO_RAM_PIPELINE := 1 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_PTP_PERIOD_NS := 6 +export PARAM_PTP_PERIOD_FNS := 26214 +export PARAM_PTP_USE_SAMPLE_CLOCK := 0 +export PARAM_TX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_TX_PTP_TS_FIFO_DEPTH := 64 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_1g/Makefile b/fpga/lib/eth/tb/eth_mac_1g/Makefile index 5d88a876b..3c8e9186c 100644 --- a/fpga/lib/eth/tb/eth_mac_1g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g/Makefile @@ -35,19 +35,19 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_PTP_TS_ENABLE ?= 0 -export PARAM_TX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_TX_PTP_TAG_WIDTH ?= 16 -export PARAM_RX_PTP_TS_ENABLE ?= 0 -export PARAM_RX_PTP_TS_WIDTH ?= 96 -# export PARAM_TX_USER_WIDTH ?= (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1 -export PARAM_TX_USER_WIDTH ?= 1 -# export PARAM_RX_USER_WIDTH ?= (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1 -export PARAM_RX_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_PTP_TS_ENABLE := 0 +export PARAM_TX_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_TX_PTP_TAG_WIDTH := 16 +export PARAM_RX_PTP_TS_ENABLE := 0 +export PARAM_RX_PTP_TS_WIDTH := 96 +# export PARAM_TX_USER_WIDTH := (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1 +export PARAM_TX_USER_WIDTH := 1 +# export PARAM_RX_USER_WIDTH := (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1 +export PARAM_RX_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile index c84ed34ec..f4fef6d8e 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_fifo/Makefile @@ -39,21 +39,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_AXIS_DATA_WIDTH ?= 8 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_AXIS_DATA_WIDTH := 8 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile b/fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile index b8cbfe8e6..572a4f425 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_gmii/Makefile @@ -40,8 +40,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile index 2494ee7c3..1af7ce2d7 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_gmii_fifo/Makefile @@ -44,21 +44,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_AXIS_DATA_WIDTH ?= 8 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_AXIS_DATA_WIDTH := 8 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile b/fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile index 5fc298f0d..752a44a78 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_rgmii/Makefile @@ -40,8 +40,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile index 7c63de480..45a3c9817 100644 --- a/fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g_rgmii_fifo/Makefile @@ -44,21 +44,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_AXIS_DATA_WIDTH ?= 8 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_AXIS_DATA_WIDTH := 8 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_mii/Makefile b/fpga/lib/eth/tb/eth_mac_mii/Makefile index d24b60470..e2d0ded7f 100644 --- a/fpga/lib/eth/tb/eth_mac_mii/Makefile +++ b/fpga/lib/eth/tb/eth_mac_mii/Makefile @@ -38,8 +38,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile index 8f54d6512..ce44ec56a 100644 --- a/fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_mii_fifo/Makefile @@ -42,21 +42,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_AXIS_DATA_WIDTH ?= 8 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_AXIS_DATA_WIDTH := 8 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile b/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile index 161b0f7de..a6747924b 100644 --- a/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile @@ -42,30 +42,30 @@ VERILOG_SOURCES += ../../rtl/axis_baser_tx_64.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_PERIOD_NS ?= 6 -export PARAM_PTP_PERIOD_FNS ?= 26214 -export PARAM_TX_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_TX_PTP_TAG_WIDTH ?= 16 -export PARAM_RX_PTP_TS_ENABLE ?= 1 -export PARAM_RX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) -export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) -export PARAM_BIT_REVERSE ?= 0 -export PARAM_SCRAMBLER_DISABLE ?= 0 -export PARAM_PRBS31_ENABLE ?= 1 -export PARAM_TX_SERDES_PIPELINE ?= 2 -export PARAM_RX_SERDES_PIPELINE ?= 2 -export PARAM_BITSLIP_HIGH_CYCLES ?= 1 -export PARAM_BITSLIP_LOW_CYCLES ?= 8 -export PARAM_COUNT_125US ?= 195 +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_PERIOD_NS := 6 +export PARAM_PTP_PERIOD_FNS := 26214 +export PARAM_TX_PTP_TS_ENABLE := 1 +export PARAM_TX_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_TX_PTP_TAG_WIDTH := 16 +export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_WIDTH := 96 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) +export PARAM_BIT_REVERSE := 0 +export PARAM_SCRAMBLER_DISABLE := 0 +export PARAM_PRBS31_ENABLE := 1 +export PARAM_TX_SERDES_PIPELINE := 2 +export PARAM_RX_SERDES_PIPELINE := 2 +export PARAM_BITSLIP_HIGH_CYCLES := 1 +export PARAM_BITSLIP_LOW_CYCLES := 8 +export PARAM_COUNT_125US := 195 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile index 9da48b437..c74477c68 100644 --- a/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile @@ -47,45 +47,45 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_HDR_WIDTH ?= 2 -export PARAM_AXIS_DATA_WIDTH ?= $(PARAM_DATA_WIDTH) -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FIFO_RAM_PIPELINE ?= 1 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FIFO_RAM_PIPELINE ?= 1 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_PTP_PERIOD_NS ?= 6 -export PARAM_PTP_PERIOD_FNS ?= 26214 -export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0 -export PARAM_TX_PTP_TS_ENABLE ?= 1 -export PARAM_RX_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 64 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) -export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) -export PARAM_BIT_REVERSE ?= 0 -export PARAM_SCRAMBLER_DISABLE ?= 0 -export PARAM_PRBS31_ENABLE ?= 1 -export PARAM_TX_SERDES_PIPELINE ?= 2 -export PARAM_RX_SERDES_PIPELINE ?= 2 -export PARAM_BITSLIP_HIGH_CYCLES ?= 1 -export PARAM_BITSLIP_LOW_CYCLES ?= 8 -export PARAM_COUNT_125US ?= 195 +export PARAM_DATA_WIDTH := 64 +export PARAM_HDR_WIDTH := 2 +export PARAM_AXIS_DATA_WIDTH := $(PARAM_DATA_WIDTH) +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FIFO_RAM_PIPELINE := 1 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FIFO_RAM_PIPELINE := 1 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_PTP_PERIOD_NS := 6 +export PARAM_PTP_PERIOD_FNS := 26214 +export PARAM_PTP_USE_SAMPLE_CLOCK := 0 +export PARAM_TX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_TX_PTP_TS_FIFO_DEPTH := 64 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_BIT_REVERSE := 0 +export PARAM_SCRAMBLER_DISABLE := 0 +export PARAM_PRBS31_ENABLE := 1 +export PARAM_TX_SERDES_PIPELINE := 2 +export PARAM_RX_SERDES_PIPELINE := 2 +export PARAM_BITSLIP_HIGH_CYCLES := 1 +export PARAM_BITSLIP_LOW_CYCLES := 8 +export PARAM_COUNT_125US := 195 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_phy_10g/Makefile b/fpga/lib/eth/tb/eth_phy_10g/Makefile index 3ef854740..dbcfeec7b 100644 --- a/fpga/lib/eth/tb/eth_phy_10g/Makefile +++ b/fpga/lib/eth/tb/eth_phy_10g/Makefile @@ -43,17 +43,17 @@ VERILOG_SOURCES += ../../rtl/xgmii_baser_enc_64.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 -export PARAM_BIT_REVERSE ?= 0 -export PARAM_SCRAMBLER_DISABLE ?= 0 -export PARAM_PRBS31_ENABLE ?= 1 -export PARAM_TX_SERDES_PIPELINE ?= 2 -export PARAM_RX_SERDES_PIPELINE ?= 2 -export PARAM_BITSLIP_HIGH_CYCLES ?= 1 -export PARAM_BITSLIP_LOW_CYCLES ?= 8 -export PARAM_COUNT_125US ?= 195 +export PARAM_DATA_WIDTH := 64 +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 +export PARAM_BIT_REVERSE := 0 +export PARAM_SCRAMBLER_DISABLE := 0 +export PARAM_PRBS31_ENABLE := 1 +export PARAM_TX_SERDES_PIPELINE := 2 +export PARAM_RX_SERDES_PIPELINE := 2 +export PARAM_BITSLIP_HIGH_CYCLES := 1 +export PARAM_BITSLIP_LOW_CYCLES := 8 +export PARAM_COUNT_125US := 195 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/ptp_clock/Makefile b/fpga/lib/eth/tb/ptp_clock/Makefile index 5adaf22ef..972cfc369 100644 --- a/fpga/lib/eth/tb/ptp_clock/Makefile +++ b/fpga/lib/eth/tb/ptp_clock/Makefile @@ -32,17 +32,17 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_PERIOD_NS_WIDTH ?= 4 -export PARAM_OFFSET_NS_WIDTH ?= 4 -export PARAM_DRIFT_NS_WIDTH ?= 4 -export PARAM_FNS_WIDTH ?= 16 -export PARAM_PERIOD_NS ?= 6 -export PARAM_PERIOD_FNS ?= 26214 -export PARAM_DRIFT_ENABLE ?= 1 -export PARAM_DRIFT_NS ?= 0 -export PARAM_DRIFT_FNS ?= 2 -export PARAM_DRIFT_RATE ?= 5 -export PARAM_PIPELINE_OUTPUT ?= 0 +export PARAM_PERIOD_NS_WIDTH := 4 +export PARAM_OFFSET_NS_WIDTH := 4 +export PARAM_DRIFT_NS_WIDTH := 4 +export PARAM_FNS_WIDTH := 16 +export PARAM_PERIOD_NS := 6 +export PARAM_PERIOD_FNS := 26214 +export PARAM_DRIFT_ENABLE := 1 +export PARAM_DRIFT_NS := 0 +export PARAM_DRIFT_FNS := 2 +export PARAM_DRIFT_RATE := 5 +export PARAM_PIPELINE_OUTPUT := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/ptp_clock_cdc/Makefile b/fpga/lib/eth/tb/ptp_clock_cdc/Makefile index 62b4d3d0a..2272408ed 100644 --- a/fpga/lib/eth/tb/ptp_clock_cdc/Makefile +++ b/fpga/lib/eth/tb/ptp_clock_cdc/Makefile @@ -32,12 +32,12 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_TS_WIDTH ?= 96 -export PARAM_NS_WIDTH ?= 4 -export PARAM_FNS_WIDTH ?= 16 -export PARAM_USE_SAMPLE_CLOCK ?= 1 -export PARAM_LOG_RATE ?= 3 -export PARAM_PIPELINE_OUTPUT ?= 0 +export PARAM_TS_WIDTH := 96 +export PARAM_NS_WIDTH := 4 +export PARAM_FNS_WIDTH := 16 +export PARAM_USE_SAMPLE_CLOCK := 1 +export PARAM_LOG_RATE := 3 +export PARAM_PIPELINE_OUTPUT := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/ptp_perout/Makefile b/fpga/lib/eth/tb/ptp_perout/Makefile index 08536e377..2f3cb72aa 100644 --- a/fpga/lib/eth/tb/ptp_perout/Makefile +++ b/fpga/lib/eth/tb/ptp_perout/Makefile @@ -32,16 +32,16 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_FNS_ENABLE ?= 1 -export PARAM_OUT_START_S ?= 0 -export PARAM_OUT_START_NS ?= 0 -export PARAM_OUT_START_FNS ?= 0 -export PARAM_OUT_PERIOD_S ?= 1 -export PARAM_OUT_PERIOD_NS ?= 0 -export PARAM_OUT_PERIOD_FNS ?= 0 -export PARAM_OUT_WIDTH_S ?= 0 -export PARAM_OUT_WIDTH_NS ?= 1000 -export PARAM_OUT_WIDTH_FNS ?= 0 +export PARAM_FNS_ENABLE := 1 +export PARAM_OUT_START_S := 0 +export PARAM_OUT_START_NS := 0 +export PARAM_OUT_START_FNS := 0 +export PARAM_OUT_PERIOD_S := 1 +export PARAM_OUT_PERIOD_NS := 0 +export PARAM_OUT_PERIOD_FNS := 0 +export PARAM_OUT_WIDTH_S := 0 +export PARAM_OUT_WIDTH_NS := 1000 +export PARAM_OUT_WIDTH_FNS := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile b/fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile index 8e023a764..dd3de46b2 100644 --- a/fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile +++ b/fpga/lib/eth/tb/xgmii_baser_dec_64/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 +export PARAM_DATA_WIDTH := 64 +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile b/fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile index 57bf5ec22..d65eb2101 100644 --- a/fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile +++ b/fpga/lib/eth/tb/xgmii_baser_enc_64/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 +export PARAM_DATA_WIDTH := 64 +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst