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Update testbenches

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This commit is contained in:
Alex Forencich 2022-04-04 15:05:21 -07:00
parent 389911e126
commit e7a83364d0
14 changed files with 452 additions and 0 deletions
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106
example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py
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@ -234,6 +234,112 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await dev_pf0_bar0.write_dword(0x000000, 1)
# disable interrupts
await dev_pf0_bar0.write_dword(0x000008, 0)
# configure operation (read)
# DMA base address
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await dev_pf0_bar0.write_dword(0x001088, 0)
await dev_pf0_bar0.write_dword(0x00108c, 0)
# DMA offset mask
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001094, 0)
# DMA stride
await dev_pf0_bar0.write_dword(0x001098, 256)
await dev_pf0_bar0.write_dword(0x00109c, 0)
# RAM base address
await dev_pf0_bar0.write_dword(0x0010c0, 0)
await dev_pf0_bar0.write_dword(0x0010c4, 0)
# RAM offset address
await dev_pf0_bar0.write_dword(0x0010c8, 0)
await dev_pf0_bar0.write_dword(0x0010cc, 0)
# RAM offset mask
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0010d4, 0)
# RAM stride
await dev_pf0_bar0.write_dword(0x0010d8, 256)
await dev_pf0_bar0.write_dword(0x0010dc, 0)
# clear cycle count
await dev_pf0_bar0.write_dword(0x001008, 0)
await dev_pf0_bar0.write_dword(0x00100c, 0)
# block length
await dev_pf0_bar0.write_dword(0x001010, 256)
# block count
await dev_pf0_bar0.write_dword(0x001018, 32)
await dev_pf0_bar0.write_dword(0x00101c, 0)
# start
await dev_pf0_bar0.write_dword(0x001000, 1)
await Timer(2000, 'ns')
# configure operation (write)
# DMA base address
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await dev_pf0_bar0.write_dword(0x001188, 0)
await dev_pf0_bar0.write_dword(0x00118c, 0)
# DMA offset mask
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001194, 0)
# DMA stride
await dev_pf0_bar0.write_dword(0x001198, 256)
await dev_pf0_bar0.write_dword(0x00119c, 0)
# RAM base address
await dev_pf0_bar0.write_dword(0x0011c0, 0)
await dev_pf0_bar0.write_dword(0x0011c4, 0)
# RAM offset address
await dev_pf0_bar0.write_dword(0x0011c8, 0)
await dev_pf0_bar0.write_dword(0x0011cc, 0)
# RAM offset mask
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0011d4, 0)
# RAM stride
await dev_pf0_bar0.write_dword(0x0011d8, 256)
await dev_pf0_bar0.write_dword(0x0011dc, 0)
# clear cycle count
await dev_pf0_bar0.write_dword(0x001108, 0)
await dev_pf0_bar0.write_dword(0x00110c, 0)
# block length
await dev_pf0_bar0.write_dword(0x001110, 256)
# block count
await dev_pf0_bar0.write_dword(0x001118, 32)
await dev_pf0_bar0.write_dword(0x00111c, 0)
# start
await dev_pf0_bar0.write_dword(0x001100, 1)
await Timer(2000, 'ns')
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

20
example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
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@ -310,6 +310,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/AU200/fpga/tb/fpga_core/test_fpga_core.py
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@ -312,6 +312,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/AU250/fpga/tb/fpga_core/test_fpga_core.py
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@ -312,6 +312,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/AU280/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -310,6 +310,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/AU50/fpga/tb/fpga_core/test_fpga_core.py
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@ -310,6 +310,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -306,6 +306,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/ExaNIC_X25/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -310,6 +310,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

106
example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -234,6 +234,112 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await dev_pf0_bar0.write_dword(0x000000, 1)
# disable interrupts
await dev_pf0_bar0.write_dword(0x000008, 0)
# configure operation (read)
# DMA base address
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await dev_pf0_bar0.write_dword(0x001088, 0)
await dev_pf0_bar0.write_dword(0x00108c, 0)
# DMA offset mask
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001094, 0)
# DMA stride
await dev_pf0_bar0.write_dword(0x001098, 256)
await dev_pf0_bar0.write_dword(0x00109c, 0)
# RAM base address
await dev_pf0_bar0.write_dword(0x0010c0, 0)
await dev_pf0_bar0.write_dword(0x0010c4, 0)
# RAM offset address
await dev_pf0_bar0.write_dword(0x0010c8, 0)
await dev_pf0_bar0.write_dword(0x0010cc, 0)
# RAM offset mask
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0010d4, 0)
# RAM stride
await dev_pf0_bar0.write_dword(0x0010d8, 256)
await dev_pf0_bar0.write_dword(0x0010dc, 0)
# clear cycle count
await dev_pf0_bar0.write_dword(0x001008, 0)
await dev_pf0_bar0.write_dword(0x00100c, 0)
# block length
await dev_pf0_bar0.write_dword(0x001010, 256)
# block count
await dev_pf0_bar0.write_dword(0x001018, 32)
await dev_pf0_bar0.write_dword(0x00101c, 0)
# start
await dev_pf0_bar0.write_dword(0x001000, 1)
await Timer(2000, 'ns')
# configure operation (write)
# DMA base address
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await dev_pf0_bar0.write_dword(0x001188, 0)
await dev_pf0_bar0.write_dword(0x00118c, 0)
# DMA offset mask
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001194, 0)
# DMA stride
await dev_pf0_bar0.write_dword(0x001198, 256)
await dev_pf0_bar0.write_dword(0x00119c, 0)
# RAM base address
await dev_pf0_bar0.write_dword(0x0011c0, 0)
await dev_pf0_bar0.write_dword(0x0011c4, 0)
# RAM offset address
await dev_pf0_bar0.write_dword(0x0011c8, 0)
await dev_pf0_bar0.write_dword(0x0011cc, 0)
# RAM offset mask
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0011d4, 0)
# RAM stride
await dev_pf0_bar0.write_dword(0x0011d8, 256)
await dev_pf0_bar0.write_dword(0x0011dc, 0)
# clear cycle count
await dev_pf0_bar0.write_dword(0x001108, 0)
await dev_pf0_bar0.write_dword(0x00110c, 0)
# block length
await dev_pf0_bar0.write_dword(0x001110, 256)
# block count
await dev_pf0_bar0.write_dword(0x001118, 32)
await dev_pf0_bar0.write_dword(0x00111c, 0)
# start
await dev_pf0_bar0.write_dword(0x001100, 1)
await Timer(2000, 'ns')
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

20
example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -311,6 +311,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -317,6 +317,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/VCU1525/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -312,6 +312,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -317,6 +317,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data

20
example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -312,6 +312,26 @@ async def run_test(dut):
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test immediate write")
# write pcie write descriptor
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x44332211)
await dev_pf0_bar0.write_dword(0x000210, 0x4)
await dev_pf0_bar0.write_dword(0x000214, 0x100AA)
await Timer(2000, 'ns')
# read status
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x800100AA
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44'
tb.log.info("Test DMA block operations")
# write packet data