From e7a83364d084205ad0b0cd5c7e1c2a563a13394e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 4 Apr 2022 15:05:21 -0700 Subject: [PATCH] Update testbenches --- .../fpga/tb/fpga_core/test_fpga_core.py | 106 ++++++++++++++++++ .../fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../AU200/fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../AU250/fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../AU280/fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../AU50/fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../fpga/tb/fpga_core/test_fpga_core.py | 106 ++++++++++++++++++ .../fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ .../fb2CG/fpga/tb/fpga_core/test_fpga_core.py | 20 ++++ 14 files changed, 452 insertions(+) diff --git a/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py b/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py index 87888d60c..82f15683a 100644 --- a/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py @@ -234,6 +234,112 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + + tb.log.info("Test DMA block operations") + + # write packet data + mem[0:1024] = bytearray([x % 256 for x in range(1024)]) + + # enable DMA + await dev_pf0_bar0.write_dword(0x000000, 1) + # disable interrupts + await dev_pf0_bar0.write_dword(0x000008, 0) + + # configure operation (read) + # DMA base address + await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff) + # DMA offset address + await dev_pf0_bar0.write_dword(0x001088, 0) + await dev_pf0_bar0.write_dword(0x00108c, 0) + # DMA offset mask + await dev_pf0_bar0.write_dword(0x001090, 0x000003ff) + await dev_pf0_bar0.write_dword(0x001094, 0) + # DMA stride + await dev_pf0_bar0.write_dword(0x001098, 256) + await dev_pf0_bar0.write_dword(0x00109c, 0) + # RAM base address + await dev_pf0_bar0.write_dword(0x0010c0, 0) + await dev_pf0_bar0.write_dword(0x0010c4, 0) + # RAM offset address + await dev_pf0_bar0.write_dword(0x0010c8, 0) + await dev_pf0_bar0.write_dword(0x0010cc, 0) + # RAM offset mask + await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff) + await dev_pf0_bar0.write_dword(0x0010d4, 0) + # RAM stride + await dev_pf0_bar0.write_dword(0x0010d8, 256) + await dev_pf0_bar0.write_dword(0x0010dc, 0) + # clear cycle count + await dev_pf0_bar0.write_dword(0x001008, 0) + await dev_pf0_bar0.write_dword(0x00100c, 0) + # block length + await dev_pf0_bar0.write_dword(0x001010, 256) + # block count + await dev_pf0_bar0.write_dword(0x001018, 32) + await dev_pf0_bar0.write_dword(0x00101c, 0) + # start + await dev_pf0_bar0.write_dword(0x001000, 1) + + await Timer(2000, 'ns') + + # configure operation (write) + # DMA base address + await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff) + # DMA offset address + await dev_pf0_bar0.write_dword(0x001188, 0) + await dev_pf0_bar0.write_dword(0x00118c, 0) + # DMA offset mask + await dev_pf0_bar0.write_dword(0x001190, 0x000003ff) + await dev_pf0_bar0.write_dword(0x001194, 0) + # DMA stride + await dev_pf0_bar0.write_dword(0x001198, 256) + await dev_pf0_bar0.write_dword(0x00119c, 0) + # RAM base address + await dev_pf0_bar0.write_dword(0x0011c0, 0) + await dev_pf0_bar0.write_dword(0x0011c4, 0) + # RAM offset address + await dev_pf0_bar0.write_dword(0x0011c8, 0) + await dev_pf0_bar0.write_dword(0x0011cc, 0) + # RAM offset mask + await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff) + await dev_pf0_bar0.write_dword(0x0011d4, 0) + # RAM stride + await dev_pf0_bar0.write_dword(0x0011d8, 256) + await dev_pf0_bar0.write_dword(0x0011dc, 0) + # clear cycle count + await dev_pf0_bar0.write_dword(0x001108, 0) + await dev_pf0_bar0.write_dword(0x00110c, 0) + # block length + await dev_pf0_bar0.write_dword(0x001110, 256) + # block count + await dev_pf0_bar0.write_dword(0x001118, 32) + await dev_pf0_bar0.write_dword(0x00111c, 0) + # start + await dev_pf0_bar0.write_dword(0x001100, 1) + + await Timer(2000, 'ns') + await RisingEdge(dut.clk) await RisingEdge(dut.clk) diff --git a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py index f2c657c91..ab78dbb3c 100644 --- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py @@ -310,6 +310,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/AU200/fpga/tb/fpga_core/test_fpga_core.py b/example/AU200/fpga/tb/fpga_core/test_fpga_core.py index 429f0383f..5add2329d 100644 --- a/example/AU200/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/AU200/fpga/tb/fpga_core/test_fpga_core.py @@ -312,6 +312,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/AU250/fpga/tb/fpga_core/test_fpga_core.py b/example/AU250/fpga/tb/fpga_core/test_fpga_core.py index 429f0383f..5add2329d 100644 --- a/example/AU250/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/AU250/fpga/tb/fpga_core/test_fpga_core.py @@ -312,6 +312,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/AU280/fpga/tb/fpga_core/test_fpga_core.py b/example/AU280/fpga/tb/fpga_core/test_fpga_core.py index f2c657c91..ab78dbb3c 100644 --- a/example/AU280/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/AU280/fpga/tb/fpga_core/test_fpga_core.py @@ -310,6 +310,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/AU50/fpga/tb/fpga_core/test_fpga_core.py b/example/AU50/fpga/tb/fpga_core/test_fpga_core.py index f2c657c91..ab78dbb3c 100644 --- a/example/AU50/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/AU50/fpga/tb/fpga_core/test_fpga_core.py @@ -310,6 +310,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py index f1d721c63..f3759cb1d 100644 --- a/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py @@ -306,6 +306,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/ExaNIC_X25/fpga/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X25/fpga/tb/fpga_core/test_fpga_core.py index a4258a9a8..ea327aef7 100644 --- a/example/ExaNIC_X25/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X25/fpga/tb/fpga_core/test_fpga_core.py @@ -310,6 +310,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py b/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py index 87888d60c..82f15683a 100644 --- a/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py @@ -234,6 +234,112 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + + tb.log.info("Test DMA block operations") + + # write packet data + mem[0:1024] = bytearray([x % 256 for x in range(1024)]) + + # enable DMA + await dev_pf0_bar0.write_dword(0x000000, 1) + # disable interrupts + await dev_pf0_bar0.write_dword(0x000008, 0) + + # configure operation (read) + # DMA base address + await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff) + # DMA offset address + await dev_pf0_bar0.write_dword(0x001088, 0) + await dev_pf0_bar0.write_dword(0x00108c, 0) + # DMA offset mask + await dev_pf0_bar0.write_dword(0x001090, 0x000003ff) + await dev_pf0_bar0.write_dword(0x001094, 0) + # DMA stride + await dev_pf0_bar0.write_dword(0x001098, 256) + await dev_pf0_bar0.write_dword(0x00109c, 0) + # RAM base address + await dev_pf0_bar0.write_dword(0x0010c0, 0) + await dev_pf0_bar0.write_dword(0x0010c4, 0) + # RAM offset address + await dev_pf0_bar0.write_dword(0x0010c8, 0) + await dev_pf0_bar0.write_dword(0x0010cc, 0) + # RAM offset mask + await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff) + await dev_pf0_bar0.write_dword(0x0010d4, 0) + # RAM stride + await dev_pf0_bar0.write_dword(0x0010d8, 256) + await dev_pf0_bar0.write_dword(0x0010dc, 0) + # clear cycle count + await dev_pf0_bar0.write_dword(0x001008, 0) + await dev_pf0_bar0.write_dword(0x00100c, 0) + # block length + await dev_pf0_bar0.write_dword(0x001010, 256) + # block count + await dev_pf0_bar0.write_dword(0x001018, 32) + await dev_pf0_bar0.write_dword(0x00101c, 0) + # start + await dev_pf0_bar0.write_dword(0x001000, 1) + + await Timer(2000, 'ns') + + # configure operation (write) + # DMA base address + await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff) + # DMA offset address + await dev_pf0_bar0.write_dword(0x001188, 0) + await dev_pf0_bar0.write_dword(0x00118c, 0) + # DMA offset mask + await dev_pf0_bar0.write_dword(0x001190, 0x000003ff) + await dev_pf0_bar0.write_dword(0x001194, 0) + # DMA stride + await dev_pf0_bar0.write_dword(0x001198, 256) + await dev_pf0_bar0.write_dword(0x00119c, 0) + # RAM base address + await dev_pf0_bar0.write_dword(0x0011c0, 0) + await dev_pf0_bar0.write_dword(0x0011c4, 0) + # RAM offset address + await dev_pf0_bar0.write_dword(0x0011c8, 0) + await dev_pf0_bar0.write_dword(0x0011cc, 0) + # RAM offset mask + await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff) + await dev_pf0_bar0.write_dword(0x0011d4, 0) + # RAM stride + await dev_pf0_bar0.write_dword(0x0011d8, 256) + await dev_pf0_bar0.write_dword(0x0011dc, 0) + # clear cycle count + await dev_pf0_bar0.write_dword(0x001108, 0) + await dev_pf0_bar0.write_dword(0x00110c, 0) + # block length + await dev_pf0_bar0.write_dword(0x001110, 256) + # block count + await dev_pf0_bar0.write_dword(0x001118, 32) + await dev_pf0_bar0.write_dword(0x00111c, 0) + # start + await dev_pf0_bar0.write_dword(0x001100, 1) + + await Timer(2000, 'ns') + await RisingEdge(dut.clk) await RisingEdge(dut.clk) diff --git a/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py b/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py index 742d4efed..92afb32b3 100644 --- a/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py @@ -311,6 +311,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py index f526584c4..1f6d410c9 100644 --- a/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py @@ -317,6 +317,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/VCU1525/fpga/tb/fpga_core/test_fpga_core.py b/example/VCU1525/fpga/tb/fpga_core/test_fpga_core.py index 429f0383f..5add2329d 100644 --- a/example/VCU1525/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/VCU1525/fpga/tb/fpga_core/test_fpga_core.py @@ -312,6 +312,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py index aee89ee1d..02871d3c8 100644 --- a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py @@ -317,6 +317,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data diff --git a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py b/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py index 6c5b428d1..c316e8d3b 100644 --- a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py @@ -312,6 +312,26 @@ async def run_test(dut): assert mem[0:1024] == mem[0x1000:0x1000+1024] + tb.log.info("Test immediate write") + + # write pcie write descriptor + await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff) + await dev_pf0_bar0.write_dword(0x000208, 0x44332211) + await dev_pf0_bar0.write_dword(0x000210, 0x4) + await dev_pf0_bar0.write_dword(0x000214, 0x100AA) + + await Timer(2000, 'ns') + + # read status + val = await dev_pf0_bar0.read_dword(0x000218) + tb.log.info("Status: 0x%x", val) + assert val == 0x800100AA + + tb.log.info("%s", mem.hexdump_str(0x1000, 64)) + + assert mem[0x1000:0x1000+4] == b'\x11\x22\x33\x44' + tb.log.info("Test DMA block operations") # write packet data