mirror of
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fpga/mqnic/DE10_Agilex: Add DMA bench target for Terasic DE10-Agilex
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
9020e0f819
commit
e7dc033c78
@ -0,0 +1,135 @@
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# FPGA settings
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FPGA_TOP = fpga
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FPGA_FAMILY = "Agilex"
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FPGA_DEVICE = AGFB014R24A2E2VR0
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/eth_mac_dual_wrapper.v
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SYN_FILES += rtl/xcvr_ctrl.v
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SYN_FILES += rtl/common/mqnic_core_pcie_ptile.v
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SYN_FILES += rtl/common/mqnic_core_pcie.v
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SYN_FILES += rtl/common/mqnic_core.v
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SYN_FILES += rtl/common/mqnic_interface.v
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SYN_FILES += rtl/common/mqnic_interface_tx.v
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SYN_FILES += rtl/common/mqnic_interface_rx.v
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SYN_FILES += rtl/common/mqnic_port.v
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SYN_FILES += rtl/common/mqnic_port_tx.v
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SYN_FILES += rtl/common/mqnic_port_rx.v
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SYN_FILES += rtl/common/mqnic_egress.v
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SYN_FILES += rtl/common/mqnic_ingress.v
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SYN_FILES += rtl/common/mqnic_l2_egress.v
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SYN_FILES += rtl/common/mqnic_l2_ingress.v
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SYN_FILES += rtl/common/mqnic_rx_queue_map.v
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SYN_FILES += rtl/common/mqnic_ptp.v
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SYN_FILES += rtl/common/mqnic_ptp_clock.v
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SYN_FILES += rtl/common/mqnic_ptp_perout.v
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SYN_FILES += rtl/common/mqnic_rb_clk_info.v
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SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
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SYN_FILES += rtl/common/cpl_write.v
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SYN_FILES += rtl/common/cpl_op_mux.v
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SYN_FILES += rtl/common/desc_fetch.v
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SYN_FILES += rtl/common/desc_op_mux.v
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SYN_FILES += rtl/common/event_mux.v
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SYN_FILES += rtl/common/queue_manager.v
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SYN_FILES += rtl/common/cpl_queue_manager.v
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SYN_FILES += rtl/common/tx_fifo.v
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SYN_FILES += rtl/common/rx_fifo.v
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SYN_FILES += rtl/common/tx_req_mux.v
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SYN_FILES += rtl/common/tx_engine.v
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SYN_FILES += rtl/common/rx_engine.v
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SYN_FILES += rtl/common/tx_checksum.v
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SYN_FILES += rtl/common/rx_hash.v
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SYN_FILES += rtl/common/rx_checksum.v
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SYN_FILES += rtl/common/stats_counter.v
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SYN_FILES += rtl/common/stats_collect.v
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SYN_FILES += rtl/common/stats_pcie_if.v
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SYN_FILES += rtl/common/stats_pcie_tlp.v
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SYN_FILES += rtl/common/stats_dma_if_pcie.v
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SYN_FILES += rtl/common/stats_dma_latency.v
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SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
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SYN_FILES += rtl/common/tx_scheduler_rr.v
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SYN_FILES += rtl/common/tdma_scheduler.v
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SYN_FILES += rtl/common/avst2axis.v
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SYN_FILES += rtl/common/axis2avst.v
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SYN_FILES += rtl/common/mac_ts_insert.v
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SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
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SYN_FILES += app/dma_bench/rtl/dma_bench.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/ptp_clock.v
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SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
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SYN_FILES += lib/eth/rtl/ptp_perout.v
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SYN_FILES += lib/axi/rtl/axil_interconnect.v
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SYN_FILES += lib/axi/rtl/axil_crossbar.v
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SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
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SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
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SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
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SYN_FILES += lib/axi/rtl/axil_reg_if.v
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SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
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SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
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SYN_FILES += lib/axi/rtl/axil_register_rd.v
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SYN_FILES += lib/axi/rtl/axil_register_wr.v
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SYN_FILES += lib/axi/rtl/arbiter.v
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SYN_FILES += lib/axi/rtl/priority_encoder.v
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SYN_FILES += lib/axis/rtl/axis_adapter.v
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SYN_FILES += lib/axis/rtl/axis_arb_mux.v
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SYN_FILES += lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/axis/rtl/axis_demux.v
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SYN_FILES += lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
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SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
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SYN_FILES += lib/axis/rtl/axis_register.v
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SYN_FILES += lib/axis/rtl/sync_reset.v
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SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
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SYN_FILES += lib/pcie/rtl/pcie_msix.v
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SYN_FILES += lib/pcie/rtl/irq_rate_limit.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
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SYN_FILES += lib/pcie/rtl/dma_if_mux.v
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SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
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SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
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SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
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SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
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SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
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SYN_FILES += lib/pcie/rtl/dma_psdpram.v
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SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
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SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
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SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v
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SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v
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SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v
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SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v
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SYN_FILES += lib/pcie/rtl/pcie_ptile_fc_counter.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# IP files
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IP_TCL_FILES += ip/reset_release.tcl
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IP_TCL_FILES += ip/pcie.tcl
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IP_TCL_FILES += ip/mac_02.tcl
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IP_TCL_FILES += ip/mac_13.tcl
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# QSF files
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QSF_FILES = fpga.qsf
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# SDC files
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SDC_FILES = fpga.sdc
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/quartus_pro.mk
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program: fpga
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quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"
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@ -0,0 +1,232 @@
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# Copyright 2022, The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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# OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of The Regents of the University of California.
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set params [dict create]
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# collect build information
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set build_date [clock seconds]
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set git_hash 00000000
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set git_tag ""
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if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
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puts "Error running git or project not under version control"
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}
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if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
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puts "Error running git, project not under version control, or no tag found"
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}
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puts "Build date: ${build_date}"
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puts "Git hash: ${git_hash}"
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puts "Git tag: ${git_tag}"
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if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
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puts "Failed to extract version from git tag"
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set tag_ver 0.0.1
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}
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puts "Tag version: ${tag_ver}"
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# FW and board IDs
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set fpga_id [expr 0x034120DD]
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set fw_id [expr 0x00000000]
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set fw_ver $tag_ver
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set board_vendor_id [expr 0x1172]
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set board_device_id [expr 0xB00A]
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set board_ver 1.0
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set release_info [expr 0x00000000]
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# PCIe IDs
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set pcie_vendor_id [expr 0x1234]
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set pcie_device_id [expr 0x1001]
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set pcie_class_code [expr 0x020000]
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set pcie_revision_id [expr 0x00]
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set pcie_subsystem_vendor_id $board_vendor_id
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set pcie_subsystem_device_id $board_device_id
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dict set params FPGA_ID [format "32'h%08x" $fpga_id]
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dict set params FW_ID [format "32'h%08x" $fw_id]
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dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
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dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
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dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
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dict set params BUILD_DATE "32'd${build_date}"
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dict set params GIT_HASH "32'h${git_hash}"
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dict set params RELEASE_INFO [format "32'h%08x" $release_info]
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# Structural configuration
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dict set params IF_COUNT "2"
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dict set params PORTS_PER_IF "1"
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dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
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dict set params PORT_MASK "0"
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# Clock configuration
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dict set params CLK_PERIOD_NS_NUM "4"
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dict set params CLK_PERIOD_NS_DENOM "1"
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# PTP configuration
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dict set params PTP_CLOCK_PIPELINE "0"
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dict set params PTP_CLOCK_CDC_PIPELINE "0"
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dict set params PTP_PORT_CDC_PIPELINE "0"
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dict set params PTP_PEROUT_ENABLE "1"
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dict set params PTP_PEROUT_COUNT "1"
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# Queue manager configuration
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dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
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dict set params TX_QUEUE_OP_TABLE_SIZE "32"
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dict set params RX_QUEUE_OP_TABLE_SIZE "32"
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dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
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dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
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dict set params EVENT_QUEUE_INDEX_WIDTH "6"
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dict set params TX_QUEUE_INDEX_WIDTH "10"
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dict set params RX_QUEUE_INDEX_WIDTH "8"
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dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
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dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
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dict set params EVENT_QUEUE_PIPELINE "3"
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dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
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dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
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dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
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dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
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# TX and RX engine configuration
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dict set params TX_DESC_TABLE_SIZE "32"
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dict set params RX_DESC_TABLE_SIZE "32"
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# Scheduler configuration
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dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
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dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
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dict set params TDMA_INDEX_WIDTH "6"
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# Interface configuration
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dict set params PTP_TS_ENABLE "0"
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dict set params TX_CPL_FIFO_DEPTH "32"
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dict set params TX_CHECKSUM_ENABLE "1"
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dict set params RX_HASH_ENABLE "1"
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dict set params RX_CHECKSUM_ENABLE "1"
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dict set params TX_FIFO_DEPTH "32768"
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dict set params RX_FIFO_DEPTH "131072"
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dict set params MAX_TX_SIZE "9214"
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dict set params MAX_RX_SIZE "9214"
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dict set params TX_RAM_SIZE "131072"
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dict set params RX_RAM_SIZE "131072"
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# Application block configuration
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dict set params APP_ID "32'h12348001"
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dict set params APP_ENABLE "1"
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dict set params APP_CTRL_ENABLE "1"
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dict set params APP_DMA_ENABLE "1"
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dict set params APP_AXIS_DIRECT_ENABLE "1"
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dict set params APP_AXIS_SYNC_ENABLE "1"
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dict set params APP_AXIS_IF_ENABLE "1"
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dict set params APP_STAT_ENABLE "1"
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# DMA interface configuration
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dict set params DMA_IMM_ENABLE "0"
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dict set params DMA_IMM_WIDTH "32"
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dict set params DMA_LEN_WIDTH "16"
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dict set params DMA_TAG_WIDTH "16"
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dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
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dict set params RAM_PIPELINE "2"
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# Interrupt configuration
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dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
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# AXI lite interface configuration (control)
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dict set params AXIL_CTRL_DATA_WIDTH "32"
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dict set params AXIL_CTRL_ADDR_WIDTH "24"
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# AXI lite interface configuration (application control)
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dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
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dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
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# Ethernet interface configuration
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dict set params AXIS_ETH_TX_PIPELINE "0"
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dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
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dict set params AXIS_ETH_TX_TS_PIPELINE "0"
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dict set params AXIS_ETH_RX_PIPELINE "0"
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dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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dict set params STAT_ID_WIDTH "12"
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# PCIe IP core settings
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set pcie intel_pcie_ptile_ast_0
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set pcie_ip pcie
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set core core16
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set fp [open "update_ip_${pcie_ip}.tcl" "w"]
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puts $fp "package require qsys"
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puts $fp "load_system ip/${pcie_ip}.ip"
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# PCIe IDs
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_class_code_hwtcl} {$pcie_class_code}"
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_revision_id_hwtcl} {$pcie_revision_id}"
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
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# PCIe IP core configuration
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
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# configure BAR settings
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proc configure_bar {fp pcie core pf bar aperture} {
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if {$aperture > 0} {
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puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
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puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
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return
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}
|
||||
puts "PF${pf} BAR${bar}: disabled"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {0}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $fp $pcie $core 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $fp $pcie $core 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
puts $fp "save_system"
|
||||
close $fp
|
||||
|
||||
# apply parameters to PCIe IP core
|
||||
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
|
||||
|
||||
# apply parameters to top-level
|
||||
dict for {name value} $params {
|
||||
set_parameter -name $name $value
|
||||
}
|
||||
135
fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24B/Makefile
Normal file
135
fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24B/Makefile
Normal file
@ -0,0 +1,135 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_TOP = fpga
|
||||
FPGA_FAMILY = "Agilex"
|
||||
FPGA_DEVICE = AGFB014R24B2E2V
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/eth_mac_dual_wrapper.v
|
||||
SYN_FILES += rtl/xcvr_ctrl.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_ptile.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_port_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_port_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
|
||||
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/tx_fifo.v
|
||||
SYN_FILES += rtl/common/rx_fifo.v
|
||||
SYN_FILES += rtl/common/tx_req_mux.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_pcie_if.v
|
||||
SYN_FILES += rtl/common/stats_pcie_tlp.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_pcie.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/avst2axis.v
|
||||
SYN_FILES += rtl/common/axis2avst.v
|
||||
SYN_FILES += rtl/common/mac_ts_insert.v
|
||||
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
|
||||
SYN_FILES += app/dma_bench/rtl/dma_bench.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_demux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/irq_rate_limit.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_fc_counter.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# IP files
|
||||
IP_TCL_FILES += ip/reset_release.tcl
|
||||
IP_TCL_FILES += ip/pcie.tcl
|
||||
IP_TCL_FILES += ip/mac_02.tcl
|
||||
IP_TCL_FILES += ip/mac_13.tcl
|
||||
|
||||
# QSF files
|
||||
QSF_FILES = fpga.qsf
|
||||
|
||||
# SDC files
|
||||
SDC_FILES = fpga.sdc
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/quartus_pro.mk
|
||||
|
||||
program: fpga
|
||||
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"
|
||||
@ -0,0 +1,232 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0xC34120DD]
|
||||
set fw_id [expr 0x00000000]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x1172]
|
||||
set board_device_id [expr 0xB00A]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# PCIe IDs
|
||||
set pcie_vendor_id [expr 0x1234]
|
||||
set pcie_device_id [expr 0x1001]
|
||||
set pcie_class_code [expr 0x020000]
|
||||
set pcie_revision_id [expr 0x00]
|
||||
set pcie_subsystem_vendor_id $board_vendor_id
|
||||
set pcie_subsystem_device_id $board_device_id
|
||||
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# Structural configuration
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
|
||||
dict set params PORT_MASK "0"
|
||||
|
||||
# Clock configuration
|
||||
dict set params CLK_PERIOD_NS_NUM "4"
|
||||
dict set params CLK_PERIOD_NS_DENOM "1"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_CLOCK_PIPELINE "0"
|
||||
dict set params PTP_CLOCK_CDC_PIPELINE "0"
|
||||
dict set params PTP_PORT_CDC_PIPELINE "0"
|
||||
dict set params PTP_PEROUT_ENABLE "1"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "10"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "8"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Interface configuration
|
||||
dict set params PTP_TS_ENABLE "0"
|
||||
dict set params TX_CPL_FIFO_DEPTH "32"
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "131072"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h12348001"
|
||||
dict set params APP_ENABLE "1"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_IMM_ENABLE "0"
|
||||
dict set params DMA_IMM_WIDTH "32"
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# Interrupt configuration
|
||||
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_TX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "1"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie intel_pcie_ptile_ast_0
|
||||
set pcie_ip pcie
|
||||
set core core16
|
||||
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
|
||||
|
||||
puts $fp "package require qsys"
|
||||
puts $fp "load_system ip/${pcie_ip}.ip"
|
||||
|
||||
# PCIe IDs
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_class_code_hwtcl} {$pcie_class_code}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_revision_id_hwtcl} {$pcie_revision_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
|
||||
|
||||
# PCIe IP core configuration
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {fp pcie core pf bar aperture} {
|
||||
if {$aperture > 0} {
|
||||
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
|
||||
|
||||
return
|
||||
}
|
||||
puts "PF${pf} BAR${bar}: disabled"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {0}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $fp $pcie $core 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $fp $pcie $core 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
puts $fp "save_system"
|
||||
close $fp
|
||||
|
||||
# apply parameters to PCIe IP core
|
||||
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
|
||||
|
||||
# apply parameters to top-level
|
||||
dict for {name value} $params {
|
||||
set_parameter -name $name $value
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user