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Fix rb_drp timing constraint for write enable signal

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This commit is contained in:
Alex Forencich 2022-03-02 17:31:17 -08:00
parent 90d28ec9a2
commit e91de95955
1 changed files with 2 additions and 2 deletions
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4
fpga/common/syn/vivado/rb_drp.tcl
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@ -47,8 +47,8 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == rb_drp || REF_NAME == r
set_max_delay -from [get_cells $inst/drp_flag_reg_reg] -to [get_cells $inst/drp_flag_sync_reg_1_reg] -datapath_only $rb_clk_period
set_max_delay -from [get_cells $inst/rb_flag_reg_reg] -to [get_cells $inst/rb_flag_sync_reg_1_reg] -datapath_only $drp_clk_period
set source [get_cells -quiet -hier -regexp ".*/rb_(addr|di|we)_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
set dest [get_cells -quiet -hier -regexp ".*/drp_(addr|di|we)_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
set source [get_cells -quiet -hier -regexp ".*/rb_(addr|di|we)_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"]
set dest [get_cells -quiet -hier -regexp ".*/drp_(addr|di|we)_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"]
if {[llength $dest]} {
if {![llength $source]} {