From e91de95955f4d6d26ef6b1567a31d04a2c9d7892 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 2 Mar 2022 17:31:17 -0800 Subject: [PATCH] Fix rb_drp timing constraint for write enable signal --- fpga/common/syn/vivado/rb_drp.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/common/syn/vivado/rb_drp.tcl b/fpga/common/syn/vivado/rb_drp.tcl index 7c0c6bb6e..be6c688a7 100644 --- a/fpga/common/syn/vivado/rb_drp.tcl +++ b/fpga/common/syn/vivado/rb_drp.tcl @@ -47,8 +47,8 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == rb_drp || REF_NAME == r set_max_delay -from [get_cells $inst/drp_flag_reg_reg] -to [get_cells $inst/drp_flag_sync_reg_1_reg] -datapath_only $rb_clk_period set_max_delay -from [get_cells $inst/rb_flag_reg_reg] -to [get_cells $inst/rb_flag_sync_reg_1_reg] -datapath_only $drp_clk_period - set source [get_cells -quiet -hier -regexp ".*/rb_(addr|di|we)_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] - set dest [get_cells -quiet -hier -regexp ".*/drp_(addr|di|we)_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] + set source [get_cells -quiet -hier -regexp ".*/rb_(addr|di|we)_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"] + set dest [get_cells -quiet -hier -regexp ".*/drp_(addr|di|we)_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"] if {[llength $dest]} { if {![llength $source]} {