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Fix register definitions

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This commit is contained in:
Alex Forencich 2019-11-05 16:44:57 -08:00
parent cc592b44d7
commit e92485a41e
2 changed files with 24 additions and 24 deletions
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24
fpga/common/tb/mqnic.py
View File

@ -138,18 +138,18 @@ MQNIC_PORT_REG_TDMA_SCHED_START_FNS = 0x0110
MQNIC_PORT_REG_TDMA_SCHED_START_NS = 0x0114
MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L = 0x0118
MQNIC_PORT_REG_TDMA_SCHED_START_SEC_H = 0x011C
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS = 0x0110
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS = 0x0114
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L = 0x0118
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H = 0x011C
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS = 0x0110
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS = 0x0114
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L = 0x0118
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H = 0x011C
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS = 0x0110
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS = 0x0114
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L = 0x0118
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H = 0x011C
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS = 0x0120
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS = 0x0124
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L = 0x0128
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H = 0x012C
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS = 0x0130
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS = 0x0134
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L = 0x0138
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H = 0x013C
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS = 0x0140
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS = 0x0144
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L = 0x0148
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H = 0x014C
MQNIC_PORT_FEATURE_RSS = (1 << 0)
MQNIC_PORT_FEATURE_PTP_TS = (1 << 4)

24
modules/mqnic/mqnic_hw.h
View File

@ -143,18 +143,18 @@ either expressed or implied, of The Regents of the University of California.
#define MQNIC_PORT_REG_TDMA_SCHED_START_NS 0x0114
#define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L 0x0118
#define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_H 0x011C
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS 0x0110
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS 0x0114
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L 0x0118
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H 0x011C
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS 0x0110
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS 0x0114
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L 0x0118
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H 0x011C
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS 0x0110
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS 0x0114
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L 0x0118
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H 0x011C
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS 0x0120
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS 0x0124
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L 0x0128
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H 0x012C
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS 0x0130
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS 0x0134
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L 0x0138
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H 0x013C
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS 0x0140
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS 0x0144
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L 0x0148
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H 0x014C
#define MQNIC_PORT_FEATURE_RSS (1 << 0)
#define MQNIC_PORT_FEATURE_PTP_TS (1 << 4)