From e95c1320459e815449a7f7125d3380d7a7c08739 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Fri, 25 Mar 2022 01:26:29 -0700
Subject: [PATCH] Route PCIe user reset through BUFG

---
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v | 6 +++++-
 fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v  | 6 +++++-
 fpga/mqnic/AU200/fpga_100g/rtl/fpga.v        | 6 +++++-
 fpga/mqnic/AU200/fpga_25g/rtl/fpga.v         | 6 +++++-
 fpga/mqnic/AU250/fpga_100g/rtl/fpga.v        | 6 +++++-
 fpga/mqnic/AU250/fpga_25g/rtl/fpga.v         | 6 +++++-
 fpga/mqnic/AU280/fpga_100g/rtl/fpga.v        | 6 +++++-
 fpga/mqnic/AU280/fpga_25g/rtl/fpga.v         | 6 +++++-
 fpga/mqnic/AU50/fpga_100g/rtl/fpga.v         | 6 +++++-
 fpga/mqnic/AU50/fpga_25g/rtl/fpga.v          | 6 +++++-
 fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v        | 6 +++++-
 fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v    | 6 +++++-
 fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v      | 6 +++++-
 fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v        | 6 +++++-
 fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v       | 6 +++++-
 fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v        | 6 +++++-
 fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v      | 6 +++++-
 fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v       | 6 +++++-
 fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v       | 6 +++++-
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v        | 6 +++++-
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v         | 6 +++++-
 21 files changed, 105 insertions(+), 21 deletions(-)

diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
index f9edc0e52..de980aa87 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
@@ -715,7 +715,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 // ila_0 ila_rq (
 //     .clk(pcie_user_clk),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
index 37dae5d0d..f80f0d18e 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
@@ -723,7 +723,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 // ila_0 ila_rq (
 //     .clk(pcie_user_clk),
diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
index 90c4a4f8a..70a5f3ed8 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
@@ -865,7 +865,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
index 176e2376f..3272761b2 100644
--- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
@@ -873,7 +873,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
index 7e2206e45..eff693108 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
@@ -865,7 +865,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
index ecdcb6927..69b4ba746 100644
--- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
@@ -873,7 +873,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
index 1d98005ae..518520927 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
@@ -754,7 +754,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4c_uscale_plus_0
 pcie4c_uscale_plus_inst (
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
index 886d862f8..62b8e57f7 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
@@ -762,7 +762,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4c_uscale_plus_0
 pcie4c_uscale_plus_inst (
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
index 2d3380d09..707cde84e 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
@@ -732,7 +732,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4c_uscale_plus_0
 pcie4c_uscale_plus_inst (
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
index da4295310..a1af09fd4 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
@@ -743,7 +743,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4c_uscale_plus_0
 pcie4c_uscale_plus_inst (
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
index f501d21c0..b68924417 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
+++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
@@ -688,7 +688,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie3_ultrascale_0
 pcie3_ultrascale_inst (
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
index 55c8b0506..427f249d9 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
@@ -675,7 +675,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 // ila_0 ila_rq (
 //     .clk(pcie_user_clk),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
index a132b692b..83e3b82ba 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
@@ -781,7 +781,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie3_7x_0
 pcie3_7x_inst (
diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
index e3567ab33..d3d9e7f33 100644
--- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
+++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
@@ -717,7 +717,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie3_ultrascale_0
 pcie3_ultrascale_inst (
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
index e024920bf..27f988189 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
@@ -734,7 +734,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
index a7eb7946e..71fa09a5f 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
@@ -738,7 +738,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
index 5f560d898..92546b375 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
@@ -714,7 +714,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
index 552a80631..a521e9d89 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
@@ -718,7 +718,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
index e18537276..bf7896693 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
@@ -503,7 +503,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 pcie4_uscale_plus_0
 pcie4_uscale_plus_inst (
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
index 333cd8b81..1c08d5811 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
@@ -736,7 +736,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 // ila_0 ila_rq (
 //     .clk(pcie_user_clk),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
index 5b84f9588..514297635 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
@@ -740,7 +740,11 @@ always @(posedge pcie_user_clk) begin
     pcie_user_reset_reg_2 <= pcie_user_reset_reg_1;
 end
 
-assign pcie_user_reset = pcie_user_reset_reg_2;
+BUFG
+pcie_user_reset_bufg_inst (
+    .I(pcie_user_reset_reg_2),
+    .O(pcie_user_reset)
+);
 
 // ila_0 ila_rq (
 //     .clk(pcie_user_clk),