From e97e4ad4230889be016417fee7a4c3b1b0bf4141 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 26 Sep 2019 23:30:03 -0700 Subject: [PATCH] Parametrize tuser signal widths --- rtl/pcie_us_axi_dma.v | 171 ++++++++++++++------------- rtl/pcie_us_axi_dma_rd.v | 150 ++++++++++++----------- rtl/pcie_us_axi_dma_wr.v | 127 ++++++++++---------- rtl/pcie_us_axi_master.v | 58 +++++---- rtl/pcie_us_axi_master_rd.v | 120 ++++++++++--------- rtl/pcie_us_axi_master_wr.v | 63 +++++----- rtl/pcie_us_axil_master.v | 124 ++++++++++--------- rtl/pcie_us_axis_cq_demux.v | 92 +++++++------- rtl/pcie_us_axis_rc_demux.v | 74 ++++++------ tb/test_pcie_us_axi_dma_256.py | 6 +- tb/test_pcie_us_axi_dma_256.v | 8 +- tb/test_pcie_us_axi_dma_rd_128.py | 6 +- tb/test_pcie_us_axi_dma_rd_128.v | 8 +- tb/test_pcie_us_axi_dma_rd_256.py | 6 +- tb/test_pcie_us_axi_dma_rd_256.v | 8 +- tb/test_pcie_us_axi_dma_rd_64.py | 6 +- tb/test_pcie_us_axi_dma_rd_64.v | 8 +- tb/test_pcie_us_axi_dma_wr_128.py | 5 +- tb/test_pcie_us_axi_dma_wr_128.v | 6 +- tb/test_pcie_us_axi_dma_wr_256.py | 5 +- tb/test_pcie_us_axi_dma_wr_256.v | 6 +- tb/test_pcie_us_axi_dma_wr_64.py | 5 +- tb/test_pcie_us_axi_dma_wr_64.v | 6 +- tb/test_pcie_us_axi_master_128.py | 6 +- tb/test_pcie_us_axi_master_128.v | 8 +- tb/test_pcie_us_axi_master_256.py | 6 +- tb/test_pcie_us_axi_master_256.v | 8 +- tb/test_pcie_us_axi_master_64.py | 6 +- tb/test_pcie_us_axi_master_64.v | 8 +- tb/test_pcie_us_axi_master_rd_128.py | 6 +- tb/test_pcie_us_axi_master_rd_128.v | 8 +- tb/test_pcie_us_axi_master_rd_256.py | 6 +- tb/test_pcie_us_axi_master_rd_256.v | 8 +- tb/test_pcie_us_axi_master_rd_64.py | 6 +- tb/test_pcie_us_axi_master_rd_64.v | 8 +- tb/test_pcie_us_axi_master_wr_128.py | 3 +- tb/test_pcie_us_axi_master_wr_128.v | 4 +- tb/test_pcie_us_axi_master_wr_256.py | 3 +- tb/test_pcie_us_axi_master_wr_256.v | 4 +- tb/test_pcie_us_axi_master_wr_64.py | 3 +- tb/test_pcie_us_axi_master_wr_64.v | 4 +- tb/test_pcie_us_axil_master_128.py | 6 +- tb/test_pcie_us_axil_master_128.v | 8 +- tb/test_pcie_us_axil_master_256.py | 6 +- tb/test_pcie_us_axil_master_256.v | 8 +- tb/test_pcie_us_axil_master_64.py | 6 +- tb/test_pcie_us_axil_master_64.v | 8 +- 47 files changed, 693 insertions(+), 522 deletions(-) diff --git a/rtl/pcie_us_axi_dma.v b/rtl/pcie_us_axi_dma.v index 69c73e870..2ec779dcd 100644 --- a/rtl/pcie_us_axi_dma.v +++ b/rtl/pcie_us_axi_dma.v @@ -35,6 +35,10 @@ module pcie_us_axi_dma # parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream RC tuser signal width + parameter AXIS_PCIE_RC_USER_WIDTH = 75, + // PCIe AXI stream RQ tuser signal width + parameter AXIS_PCIE_RQ_USER_WIDTH = 60, // Width of AXI data bus in bits parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH, // Width of AXI address bus in bits @@ -61,134 +65,136 @@ module pcie_us_axi_dma # parameter TAG_WIDTH = 8 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input (RC) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tvalid, - output wire s_axis_rc_tready, - input wire s_axis_rc_tlast, - input wire [74:0] s_axis_rc_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tvalid, + output wire s_axis_rc_tready, + input wire s_axis_rc_tlast, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, /* * AXI output (RQ) */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tvalid, - input wire m_axis_rq_tready, - output wire m_axis_rq_tlast, - output wire [59:0] m_axis_rq_tuser, + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tvalid, + input wire m_axis_rq_tready, + output wire m_axis_rq_tlast, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, /* * Tag input */ - input wire [PCIE_TAG_WIDTH-1:0] s_axis_pcie_rq_tag, - input wire s_axis_pcie_rq_tag_valid, + input wire [PCIE_TAG_WIDTH-1:0] s_axis_pcie_rq_tag, + input wire s_axis_pcie_rq_tag_valid, /* * AXI read descriptor input */ - input wire [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr, - input wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr, - input wire [LEN_WIDTH-1:0] s_axis_read_desc_len, - input wire [TAG_WIDTH-1:0] s_axis_read_desc_tag, - input wire s_axis_read_desc_valid, - output wire s_axis_read_desc_ready, + input wire [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr, + input wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr, + input wire [LEN_WIDTH-1:0] s_axis_read_desc_len, + input wire [TAG_WIDTH-1:0] s_axis_read_desc_tag, + input wire s_axis_read_desc_valid, + output wire s_axis_read_desc_ready, /* * AXI read descriptor status output */ - output wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag, - output wire m_axis_read_desc_status_valid, + output wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag, + output wire m_axis_read_desc_status_valid, /* * AXI write descriptor input */ - input wire [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr, - input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr, - input wire [LEN_WIDTH-1:0] s_axis_write_desc_len, - input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag, - input wire s_axis_write_desc_valid, - output wire s_axis_write_desc_ready, + input wire [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr, + input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr, + input wire [LEN_WIDTH-1:0] s_axis_write_desc_len, + input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag, + input wire s_axis_write_desc_valid, + output wire s_axis_write_desc_ready, /* * AXI write descriptor status output */ - output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag, - output wire m_axis_write_desc_status_valid, + output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag, + output wire m_axis_write_desc_status_valid, /* * AXI master interface */ - output wire [AXI_ID_WIDTH-1:0] m_axi_awid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [7:0] m_axi_awlen, - output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, - output wire m_axi_awlock, - output wire [3:0] m_axi_awcache, - output wire [2:0] m_axi_awprot, - output wire m_axi_awvalid, - input wire m_axi_awready, - output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, - output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb, - output wire m_axi_wlast, - output wire m_axi_wvalid, - input wire m_axi_wready, - input wire [AXI_ID_WIDTH-1:0] m_axi_bid, - input wire [1:0] m_axi_bresp, - input wire m_axi_bvalid, - output wire m_axi_bready, - output wire [AXI_ID_WIDTH-1:0] m_axi_arid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, - output wire [7:0] m_axi_arlen, - output wire [2:0] m_axi_arsize, - output wire [1:0] m_axi_arburst, - output wire m_axi_arlock, - output wire [3:0] m_axi_arcache, - output wire [2:0] m_axi_arprot, - output wire m_axi_arvalid, - input wire m_axi_arready, - input wire [AXI_ID_WIDTH-1:0] m_axi_rid, - input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, - input wire [1:0] m_axi_rresp, - input wire m_axi_rlast, - input wire m_axi_rvalid, - output wire m_axi_rready, + output wire [AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [7:0] m_axi_awlen, + output wire [2:0] m_axi_awsize, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire m_axi_awvalid, + input wire m_axi_awready, + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire m_axi_wvalid, + input wire m_axi_wready, + input wire [AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [1:0] m_axi_bresp, + input wire m_axi_bvalid, + output wire m_axi_bready, + output wire [AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [7:0] m_axi_arlen, + output wire [2:0] m_axi_arsize, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire m_axi_arvalid, + input wire m_axi_arready, + input wire [AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire m_axi_rvalid, + output wire m_axi_rready, /* * Configuration */ - input wire read_enable, - input wire write_enable, - input wire ext_tag_enable, - input wire [15:0] requester_id, - input wire requester_id_enable, - input wire [2:0] max_read_request_size, - input wire [2:0] max_payload_size, + input wire read_enable, + input wire write_enable, + input wire ext_tag_enable, + input wire [15:0] requester_id, + input wire requester_id_enable, + input wire [2:0] max_read_request_size, + input wire [2:0] max_payload_size, /* * Status */ - output wire status_error_cor, - output wire status_error_uncor + output wire status_error_cor, + output wire status_error_uncor ); -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_read; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_read; -wire axis_rq_tvalid_read; -wire axis_rq_tready_read; -wire axis_rq_tlast_read; -wire [59:0] axis_rq_tuser_read; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_read; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_read; +wire axis_rq_tvalid_read; +wire axis_rq_tready_read; +wire axis_rq_tlast_read; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser_read; pcie_us_axi_dma_rd #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), @@ -290,6 +296,7 @@ pcie_us_axi_dma_rd_inst ( pcie_us_axi_dma_wr #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/rtl/pcie_us_axi_dma_rd.v b/rtl/pcie_us_axi_dma_rd.v index f7157caeb..52c33ddeb 100644 --- a/rtl/pcie_us_axi_dma_rd.v +++ b/rtl/pcie_us_axi_dma_rd.v @@ -35,6 +35,10 @@ module pcie_us_axi_dma_rd # parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream RC tuser signal width + parameter AXIS_PCIE_RC_USER_WIDTH = 75, + // PCIe AXI stream RQ tuser signal width + parameter AXIS_PCIE_RQ_USER_WIDTH = 60, // Width of AXI data bus in bits parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH, // Width of AXI address bus in bits @@ -63,88 +67,88 @@ module pcie_us_axi_dma_rd # parameter OP_TAG_WIDTH = AXI_ID_WIDTH < PCIE_TAG_WIDTH ? AXI_ID_WIDTH : PCIE_TAG_WIDTH ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input (RC) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tvalid, - output wire s_axis_rc_tready, - input wire s_axis_rc_tlast, - input wire [74:0] s_axis_rc_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tvalid, + output wire s_axis_rc_tready, + input wire s_axis_rc_tlast, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, /* * AXI output (RQ) */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tvalid, - input wire m_axis_rq_tready, - output wire m_axis_rq_tlast, - output wire [59:0] m_axis_rq_tuser, + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tvalid, + input wire m_axis_rq_tready, + output wire m_axis_rq_tlast, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, /* * Tag input */ - input wire [PCIE_TAG_WIDTH-1:0] s_axis_pcie_rq_tag, - input wire s_axis_pcie_rq_tag_valid, + input wire [PCIE_TAG_WIDTH-1:0] s_axis_pcie_rq_tag, + input wire s_axis_pcie_rq_tag_valid, /* * AXI read descriptor input */ - input wire [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr, - input wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr, - input wire [LEN_WIDTH-1:0] s_axis_read_desc_len, - input wire [TAG_WIDTH-1:0] s_axis_read_desc_tag, - input wire s_axis_read_desc_valid, - output wire s_axis_read_desc_ready, + input wire [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr, + input wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr, + input wire [LEN_WIDTH-1:0] s_axis_read_desc_len, + input wire [TAG_WIDTH-1:0] s_axis_read_desc_tag, + input wire s_axis_read_desc_valid, + output wire s_axis_read_desc_ready, /* * AXI read descriptor status output */ - output wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag, - output wire m_axis_read_desc_status_valid, + output wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag, + output wire m_axis_read_desc_status_valid, /* * AXI master interface */ - output wire [AXI_ID_WIDTH-1:0] m_axi_awid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [7:0] m_axi_awlen, - output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, - output wire m_axi_awlock, - output wire [3:0] m_axi_awcache, - output wire [2:0] m_axi_awprot, - output wire m_axi_awvalid, - input wire m_axi_awready, - output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, - output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb, - output wire m_axi_wlast, - output wire m_axi_wvalid, - input wire m_axi_wready, - input wire [AXI_ID_WIDTH-1:0] m_axi_bid, - input wire [1:0] m_axi_bresp, - input wire m_axi_bvalid, - output wire m_axi_bready, + output wire [AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [7:0] m_axi_awlen, + output wire [2:0] m_axi_awsize, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire m_axi_awvalid, + input wire m_axi_awready, + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire m_axi_wvalid, + input wire m_axi_wready, + input wire [AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [1:0] m_axi_bresp, + input wire m_axi_bvalid, + output wire m_axi_bready, /* * Configuration */ - input wire enable, - input wire ext_tag_enable, - input wire [15:0] requester_id, - input wire requester_id_enable, - input wire [2:0] max_read_request_size, + input wire enable, + input wire ext_tag_enable, + input wire [15:0] requester_id, + input wire requester_id_enable, + input wire [2:0] max_read_request_size, /* * Status */ - output wire status_error_cor, - output wire status_error_uncor + output wire status_error_cor, + output wire status_error_uncor ); parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH; @@ -173,6 +177,16 @@ initial begin $finish; end + if (AXIS_PCIE_RC_USER_WIDTH != 75) begin + $error("Error: PCIe RC tuser width must be 75 (instance %m)"); + $finish; + end + + if (AXIS_PCIE_RQ_USER_WIDTH != 60) begin + $error("Error: PCIe RQ tuser width must be 60 (instance %m)"); + $finish; + end + if (AXI_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin $error("Error: AXI interface width must match PCIe interface width (instance %m)"); $finish; @@ -314,13 +328,13 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] save_axis_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0} wire [AXI_DATA_WIDTH-1:0] shift_axis_tdata = {s_axis_rc_tdata, save_axis_tdata_reg} >> ((AXI_STRB_WIDTH-offset_reg)*AXI_WORD_SIZE); // internal datapath -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_int; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_int; -reg m_axis_rq_tvalid_int; -reg m_axis_rq_tready_int_reg = 1'b0; -reg m_axis_rq_tlast_int; -reg [59:0] m_axis_rq_tuser_int; -wire m_axis_rq_tready_int_early; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_int; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_int; +reg m_axis_rq_tvalid_int; +reg m_axis_rq_tready_int_reg = 1'b0; +reg m_axis_rq_tlast_int; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser_int; +wire m_axis_rq_tready_int_early; reg [AXI_DATA_WIDTH-1:0] m_axi_wdata_int; reg [AXI_STRB_WIDTH-1:0] m_axi_wstrb_int; @@ -473,7 +487,7 @@ always @* begin end else begin m_axis_rq_tlast_int = 1'b0; end - m_axis_rq_tuser_int = 60'd0; + m_axis_rq_tuser_int = {AXIS_PCIE_RQ_USER_WIDTH{1'b0}}; m_axis_rq_tdata_int[1:0] = 2'b0; // address type m_axis_rq_tdata_int[63:2] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:2]; // address @@ -1324,17 +1338,17 @@ always @(posedge clk) begin end // output datapath logic (PCIe TLP) -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg m_axis_rq_tvalid_reg = 1'b0, m_axis_rq_tvalid_next; -reg m_axis_rq_tlast_reg = 1'b0; -reg [59:0] m_axis_rq_tuser_reg = 60'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg m_axis_rq_tvalid_reg = 1'b0, m_axis_rq_tvalid_next; +reg m_axis_rq_tlast_reg = 1'b0; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser_reg = {AXIS_PCIE_RQ_USER_WIDTH{1'b0}}; -reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg temp_m_axis_rq_tvalid_reg = 1'b0, temp_m_axis_rq_tvalid_next; -reg temp_m_axis_rq_tlast_reg = 1'b0; -reg [59:0] temp_m_axis_rq_tuser_reg = 60'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg temp_m_axis_rq_tvalid_reg = 1'b0, temp_m_axis_rq_tvalid_next; +reg temp_m_axis_rq_tlast_reg = 1'b0; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] temp_m_axis_rq_tuser_reg = {AXIS_PCIE_RQ_USER_WIDTH{1'b0}}; // datapath control reg store_axis_rq_int_to_output; diff --git a/rtl/pcie_us_axi_dma_wr.v b/rtl/pcie_us_axi_dma_wr.v index a9efb13cf..d3624eaab 100644 --- a/rtl/pcie_us_axi_dma_wr.v +++ b/rtl/pcie_us_axi_dma_wr.v @@ -35,6 +35,8 @@ module pcie_us_axi_dma_wr # parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream RQ tuser signal width + parameter AXIS_PCIE_RQ_USER_WIDTH = 60, // Width of AXI data bus in bits parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH, // Width of AXI address bus in bits @@ -53,72 +55,72 @@ module pcie_us_axi_dma_wr # parameter TAG_WIDTH = 8 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input (RQ from read DMA) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep, - input wire s_axis_rq_tvalid, - output wire s_axis_rq_tready, - input wire s_axis_rq_tlast, - input wire [59:0] s_axis_rq_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep, + input wire s_axis_rq_tvalid, + output wire s_axis_rq_tready, + input wire s_axis_rq_tlast, + input wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] s_axis_rq_tuser, /* * AXI output (RQ) */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tvalid, - input wire m_axis_rq_tready, - output wire m_axis_rq_tlast, - output wire [59:0] m_axis_rq_tuser, + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tvalid, + input wire m_axis_rq_tready, + output wire m_axis_rq_tlast, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, /* * AXI write descriptor input */ - input wire [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr, - input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr, - input wire [LEN_WIDTH-1:0] s_axis_write_desc_len, - input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag, - input wire s_axis_write_desc_valid, - output wire s_axis_write_desc_ready, + input wire [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr, + input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr, + input wire [LEN_WIDTH-1:0] s_axis_write_desc_len, + input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag, + input wire s_axis_write_desc_valid, + output wire s_axis_write_desc_ready, /* * AXI write descriptor status output */ - output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag, - output wire m_axis_write_desc_status_valid, + output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag, + output wire m_axis_write_desc_status_valid, /* * AXI master interface */ - output wire [AXI_ID_WIDTH-1:0] m_axi_arid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, - output wire [7:0] m_axi_arlen, - output wire [2:0] m_axi_arsize, - output wire [1:0] m_axi_arburst, - output wire m_axi_arlock, - output wire [3:0] m_axi_arcache, - output wire [2:0] m_axi_arprot, - output wire m_axi_arvalid, - input wire m_axi_arready, - input wire [AXI_ID_WIDTH-1:0] m_axi_rid, - input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, - input wire [1:0] m_axi_rresp, - input wire m_axi_rlast, - input wire m_axi_rvalid, - output wire m_axi_rready, + output wire [AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [7:0] m_axi_arlen, + output wire [2:0] m_axi_arsize, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire m_axi_arvalid, + input wire m_axi_arready, + input wire [AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire m_axi_rvalid, + output wire m_axi_rready, /* * Configuration */ - input wire enable, - input wire [15:0] requester_id, - input wire requester_id_enable, - input wire [2:0] max_payload_size + input wire enable, + input wire [15:0] requester_id, + input wire requester_id_enable, + input wire [2:0] max_payload_size ); parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH; @@ -147,6 +149,11 @@ initial begin $finish; end + if (AXIS_PCIE_RQ_USER_WIDTH != 60) begin + $error("Error: PCIe RQ tuser width must be 60 (instance %m)"); + $finish; + end + if (AXI_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin $error("Error: AXI interface width must match PCIe interface width (instance %m)"); $finish; @@ -255,13 +262,13 @@ reg [AXI_DATA_WIDTH-1:0] save_axi_rdata_reg = {AXI_DATA_WIDTH{1'b0}}; wire [AXI_DATA_WIDTH-1:0] shift_axi_rdata = {m_axi_rdata, save_axi_rdata_reg} >> ((AXI_STRB_WIDTH-offset_reg)*AXI_WORD_SIZE); // internal datapath -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_int; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_int; -reg m_axis_rq_tvalid_int; -reg m_axis_rq_tready_int_reg = 1'b0; -reg m_axis_rq_tlast_int; -reg [59:0] m_axis_rq_tuser_int; -wire m_axis_rq_tready_int_early; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_int; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_int; +reg m_axis_rq_tvalid_int; +reg m_axis_rq_tready_int_reg = 1'b0; +reg m_axis_rq_tlast_int; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser_int; +wire m_axis_rq_tready_int_early; assign s_axis_rq_tready = s_axis_rq_tready_reg; @@ -461,7 +468,7 @@ always @* begin m_axis_rq_tkeep_int = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; m_axis_rq_tvalid_int = 1'b0; m_axis_rq_tlast_int = 1'b0; - m_axis_rq_tuser_int = 60'd0; + m_axis_rq_tuser_int = {AXIS_PCIE_RQ_USER_WIDTH{1'b0}}; m_axis_rq_tdata_int[1:0] = 2'b0; // address type m_axis_rq_tdata_int[63:2] = tlp_addr_reg[PCIE_ADDR_WIDTH-1:2]; // address @@ -836,17 +843,17 @@ always @(posedge clk) begin end // output datapath logic (PCIe TLP) -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg m_axis_rq_tvalid_reg = 1'b0, m_axis_rq_tvalid_next; -reg m_axis_rq_tlast_reg = 1'b0; -reg [59:0] m_axis_rq_tuser_reg = 60'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg m_axis_rq_tvalid_reg = 1'b0, m_axis_rq_tvalid_next; +reg m_axis_rq_tlast_reg = 1'b0; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser_reg = {AXIS_PCIE_RQ_USER_WIDTH{1'b0}}; -reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg temp_m_axis_rq_tvalid_reg = 1'b0, temp_m_axis_rq_tvalid_next; -reg temp_m_axis_rq_tlast_reg = 1'b0; -reg [59:0] temp_m_axis_rq_tuser_reg = 60'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg temp_m_axis_rq_tvalid_reg = 1'b0, temp_m_axis_rq_tvalid_next; +reg temp_m_axis_rq_tlast_reg = 1'b0; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] temp_m_axis_rq_tuser_reg = {AXIS_PCIE_RQ_USER_WIDTH{1'b0}}; // datapath control reg store_axis_rq_int_to_output; diff --git a/rtl/pcie_us_axi_master.v b/rtl/pcie_us_axi_master.v index 5eb9915ba..7730dcd4d 100644 --- a/rtl/pcie_us_axi_master.v +++ b/rtl/pcie_us_axi_master.v @@ -35,6 +35,10 @@ module pcie_us_axi_master # parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream CQ tuser signal width + parameter AXIS_PCIE_CQ_USER_WIDTH = 85, + // PCIe AXI stream CC tuser signal width + parameter AXIS_PCIE_CC_USER_WIDTH = 33, // Width of AXI data bus in bits parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH, // Width of AXI address bus in bits @@ -53,22 +57,22 @@ module pcie_us_axi_master # /* * AXI input (CQ) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tvalid, - output wire s_axis_cq_tready, - input wire s_axis_cq_tlast, - input wire [84:0] s_axis_cq_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tvalid, + output wire s_axis_cq_tready, + input wire s_axis_cq_tlast, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, /* * AXI output (CC) */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tvalid, - input wire m_axis_cc_tready, - output wire m_axis_cc_tlast, - output wire [32:0] m_axis_cc_tuser, + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tvalid, + input wire m_axis_cc_tready, + output wire m_axis_cc_tlast, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, /* * AXI Master output @@ -123,19 +127,19 @@ module pcie_us_axi_master # output wire status_error_uncor ); -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_read; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_read; -wire axis_cq_tvalid_read; -wire axis_cq_tready_read; -wire axis_cq_tlast_read; -wire [84:0] axis_cq_tuser_read; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_read; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_read; +wire axis_cq_tvalid_read; +wire axis_cq_tready_read; +wire axis_cq_tlast_read; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_read; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_write; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_write; -wire axis_cq_tvalid_write; -wire axis_cq_tready_write; -wire axis_cq_tlast_write; -wire [84:0] axis_cq_tuser_write; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_write; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_write; +wire axis_cq_tvalid_write; +wire axis_cq_tready_write; +wire axis_cq_tlast_write; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_write; wire [3:0] req_type; wire [1:0] select; @@ -145,7 +149,8 @@ wire [1:0] status_error_uncor_int; pcie_us_axis_cq_demux #( .M_COUNT(2), .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH) + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH) ) cq_demux_inst ( .clk(clk), @@ -182,6 +187,8 @@ assign select[0] = ~select[1]; pcie_us_axi_master_rd #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), @@ -249,6 +256,7 @@ pcie_us_axi_master_rd_inst ( pcie_us_axi_master_wr #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/rtl/pcie_us_axi_master_rd.v b/rtl/pcie_us_axi_master_rd.v index cfddc5286..d86387afb 100644 --- a/rtl/pcie_us_axi_master_rd.v +++ b/rtl/pcie_us_axi_master_rd.v @@ -35,6 +35,10 @@ module pcie_us_axi_master_rd # parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream CQ tuser signal width + parameter AXIS_PCIE_CQ_USER_WIDTH = 85, + // PCIe AXI stream CC tuser signal width + parameter AXIS_PCIE_CC_USER_WIDTH = 33, // Width of AXI data bus in bits parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH, // Width of AXI address bus in bits @@ -47,61 +51,61 @@ module pcie_us_axi_master_rd # parameter AXI_MAX_BURST_LEN = 256 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input (CQ) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tvalid, - output wire s_axis_cq_tready, - input wire s_axis_cq_tlast, - input wire [84:0] s_axis_cq_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tvalid, + output wire s_axis_cq_tready, + input wire s_axis_cq_tlast, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, /* * AXI output (CC) */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tvalid, - input wire m_axis_cc_tready, - output wire m_axis_cc_tlast, - output wire [32:0] m_axis_cc_tuser, + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tvalid, + input wire m_axis_cc_tready, + output wire m_axis_cc_tlast, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, /* * AXI master interface */ - output wire [AXI_ID_WIDTH-1:0] m_axi_arid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, - output wire [7:0] m_axi_arlen, - output wire [2:0] m_axi_arsize, - output wire [1:0] m_axi_arburst, - output wire m_axi_arlock, - output wire [3:0] m_axi_arcache, - output wire [2:0] m_axi_arprot, - output wire m_axi_arvalid, - input wire m_axi_arready, - input wire [AXI_ID_WIDTH-1:0] m_axi_rid, - input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, - input wire [1:0] m_axi_rresp, - input wire m_axi_rlast, - input wire m_axi_rvalid, - output wire m_axi_rready, + output wire [AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [7:0] m_axi_arlen, + output wire [2:0] m_axi_arsize, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire m_axi_arvalid, + input wire m_axi_arready, + input wire [AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire m_axi_rvalid, + output wire m_axi_rready, /* * Configuration */ - input wire [15:0] completer_id, - input wire completer_id_enable, - input wire [2:0] max_payload_size, + input wire [15:0] completer_id, + input wire completer_id_enable, + input wire [2:0] max_payload_size, /* * Status */ - output wire status_error_cor, - output wire status_error_uncor + output wire status_error_cor, + output wire status_error_uncor ); parameter PCIE_ADDR_WIDTH = 64; @@ -128,6 +132,16 @@ initial begin $finish; end + if (AXIS_PCIE_CQ_USER_WIDTH != 85) begin + $error("Error: PCIe CQ tuser width must be 85 (instance %m)"); + $finish; + end + + if (AXIS_PCIE_CC_USER_WIDTH != 33) begin + $error("Error: PCIe CC tuser width must be 33 (instance %m)"); + $finish; + end + if (AXI_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin $error("Error: AXI interface width must match PCIe interface width (instance %m)"); $finish; @@ -254,13 +268,13 @@ reg status_error_cor_reg = 1'b0, status_error_cor_next; reg status_error_uncor_reg = 1'b0, status_error_uncor_next; // internal datapath -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_int; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_int; -reg m_axis_cc_tvalid_int; -reg m_axis_cc_tready_int_reg = 1'b0; -reg m_axis_cc_tlast_int; -reg [59:0] m_axis_cc_tuser_int; -wire m_axis_cc_tready_int_early; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_int; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_int; +reg m_axis_cc_tvalid_int; +reg m_axis_cc_tready_int_reg = 1'b0; +reg m_axis_cc_tlast_int; +reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_int; +wire m_axis_cc_tready_int_early; assign s_axis_cq_tready = s_axis_cq_tready_reg; @@ -597,7 +611,7 @@ always @* begin m_axis_cc_tkeep_int = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; m_axis_cc_tvalid_int = 1'b0; m_axis_cc_tlast_int = 1'b0; - m_axis_cc_tuser_int = 33'd0; + m_axis_cc_tuser_int = {AXIS_PCIE_CC_USER_WIDTH{1'b0}}; m_axis_cc_tdata_int[6:0] = tlp_addr_reg; // lower address m_axis_cc_tdata_int[9:8] = at_reg; @@ -1103,17 +1117,17 @@ always @(posedge clk) begin end // output datapath logic (PCIe TLP) -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next; -reg m_axis_cc_tlast_reg = 1'b0; -reg [32:0] m_axis_cc_tuser_reg = 33'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next; +reg m_axis_cc_tlast_reg = 1'b0; +reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_reg = {AXIS_PCIE_CC_USER_WIDTH{1'b0}}; -reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg temp_m_axis_cc_tvalid_reg = 1'b0, temp_m_axis_cc_tvalid_next; -reg temp_m_axis_cc_tlast_reg = 1'b0; -reg [32:0] temp_m_axis_cc_tuser_reg = 33'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg temp_m_axis_cc_tvalid_reg = 1'b0, temp_m_axis_cc_tvalid_next; +reg temp_m_axis_cc_tlast_reg = 1'b0; +reg [AXIS_PCIE_CC_USER_WIDTH-1:0] temp_m_axis_cc_tuser_reg = {AXIS_PCIE_CC_USER_WIDTH{1'b0}}; // datapath control reg store_axis_cc_int_to_output; diff --git a/rtl/pcie_us_axi_master_wr.v b/rtl/pcie_us_axi_master_wr.v index 943c828e9..776c144c1 100644 --- a/rtl/pcie_us_axi_master_wr.v +++ b/rtl/pcie_us_axi_master_wr.v @@ -35,6 +35,8 @@ module pcie_us_axi_master_wr # parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream CQ tuser signal width + parameter AXIS_PCIE_CQ_USER_WIDTH = 85, // Width of AXI data bus in bits parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH, // Width of AXI address bus in bits @@ -47,46 +49,46 @@ module pcie_us_axi_master_wr # parameter AXI_MAX_BURST_LEN = 256 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input (CQ) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tvalid, - output wire s_axis_cq_tready, - input wire s_axis_cq_tlast, - input wire [84:0] s_axis_cq_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tvalid, + output wire s_axis_cq_tready, + input wire s_axis_cq_tlast, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, /* * AXI Master output */ - output wire [AXI_ID_WIDTH-1:0] m_axi_awid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [7:0] m_axi_awlen, - output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, - output wire m_axi_awlock, - output wire [3:0] m_axi_awcache, - output wire [2:0] m_axi_awprot, - output wire m_axi_awvalid, - input wire m_axi_awready, - output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, - output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb, - output wire m_axi_wlast, - output wire m_axi_wvalid, - input wire m_axi_wready, - input wire [AXI_ID_WIDTH-1:0] m_axi_bid, - input wire [1:0] m_axi_bresp, - input wire m_axi_bvalid, - output wire m_axi_bready, + output wire [AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [7:0] m_axi_awlen, + output wire [2:0] m_axi_awsize, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire m_axi_awvalid, + input wire m_axi_awready, + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire m_axi_wvalid, + input wire m_axi_wready, + input wire [AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [1:0] m_axi_bresp, + input wire m_axi_bvalid, + output wire m_axi_bready, /* * Status */ - output wire status_error_uncor + output wire status_error_uncor ); parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH; @@ -111,6 +113,11 @@ initial begin $finish; end + if (AXIS_PCIE_CQ_USER_WIDTH != 85) begin + $error("Error: PCIe CQ tuser width must be 85 (instance %m)"); + $finish; + end + if (AXI_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin $error("Error: AXI interface width must match PCIe interface width (instance %m)"); $finish; diff --git a/rtl/pcie_us_axil_master.v b/rtl/pcie_us_axil_master.v index dfec05b51..cecc6a3b6 100644 --- a/rtl/pcie_us_axil_master.v +++ b/rtl/pcie_us_axil_master.v @@ -35,6 +35,10 @@ module pcie_us_axil_master # parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream CQ tuser signal width + parameter AXIS_PCIE_CQ_USER_WIDTH = 85, + // PCIe AXI stream CC tuser signal width + parameter AXIS_PCIE_CC_USER_WIDTH = 33, // Width of AXI lite data bus in bits parameter AXI_DATA_WIDTH = 32, // Width of AXI lite address bus in bits @@ -45,63 +49,63 @@ module pcie_us_axil_master # parameter ENABLE_PARITY = 0 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input (CQ) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tvalid, - output wire s_axis_cq_tready, - input wire s_axis_cq_tlast, - input wire [84:0] s_axis_cq_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tvalid, + output wire s_axis_cq_tready, + input wire s_axis_cq_tlast, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, /* * AXI output (CC) */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tvalid, - input wire m_axis_cc_tready, - output wire m_axis_cc_tlast, - output wire [32:0] m_axis_cc_tuser, + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tvalid, + input wire m_axis_cc_tready, + output wire m_axis_cc_tlast, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, /* * AXI Lite Master output */ - output wire [AXI_ADDR_WIDTH-1:0] m_axil_awaddr, - output wire [2:0] m_axil_awprot, - output wire m_axil_awvalid, - input wire m_axil_awready, - output wire [AXI_DATA_WIDTH-1:0] m_axil_wdata, - output wire [AXI_STRB_WIDTH-1:0] m_axil_wstrb, - output wire m_axil_wvalid, - input wire m_axil_wready, - input wire [1:0] m_axil_bresp, - input wire m_axil_bvalid, - output wire m_axil_bready, - output wire [AXI_ADDR_WIDTH-1:0] m_axil_araddr, - output wire [2:0] m_axil_arprot, - output wire m_axil_arvalid, - input wire m_axil_arready, - input wire [AXI_DATA_WIDTH-1:0] m_axil_rdata, - input wire [1:0] m_axil_rresp, - input wire m_axil_rvalid, - output wire m_axil_rready, + output wire [AXI_ADDR_WIDTH-1:0] m_axil_awaddr, + output wire [2:0] m_axil_awprot, + output wire m_axil_awvalid, + input wire m_axil_awready, + output wire [AXI_DATA_WIDTH-1:0] m_axil_wdata, + output wire [AXI_STRB_WIDTH-1:0] m_axil_wstrb, + output wire m_axil_wvalid, + input wire m_axil_wready, + input wire [1:0] m_axil_bresp, + input wire m_axil_bvalid, + output wire m_axil_bready, + output wire [AXI_ADDR_WIDTH-1:0] m_axil_araddr, + output wire [2:0] m_axil_arprot, + output wire m_axil_arvalid, + input wire m_axil_arready, + input wire [AXI_DATA_WIDTH-1:0] m_axil_rdata, + input wire [1:0] m_axil_rresp, + input wire m_axil_rvalid, + output wire m_axil_rready, /* * Configuration */ - input wire [15:0] completer_id, - input wire completer_id_enable, + input wire [15:0] completer_id, + input wire completer_id_enable, /* * Status */ - output wire status_error_cor, - output wire status_error_uncor + output wire status_error_cor, + output wire status_error_uncor ); // bus width assertions @@ -116,6 +120,16 @@ initial begin $finish; end + if (AXIS_PCIE_CQ_USER_WIDTH != 85) begin + $error("Error: PCIe CQ tuser width must be 85 (instance %m)"); + $finish; + end + + if (AXIS_PCIE_CC_USER_WIDTH != 33) begin + $error("Error: PCIe CC tuser width must be 33 (instance %m)"); + $finish; + end + if (AXI_DATA_WIDTH != 32) begin $error("Error: AXI interface width must be 32 (instance %m)"); $finish; @@ -189,13 +203,13 @@ reg status_error_cor_reg = 1'b0, status_error_cor_next; reg status_error_uncor_reg = 1'b0, status_error_uncor_next; // internal datapath -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_int; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_int; -reg m_axis_cc_tvalid_int; -reg m_axis_cc_tready_int_reg = 1'b0; -reg m_axis_cc_tlast_int; -reg [32:0] m_axis_cc_tuser_int; -wire m_axis_cc_tready_int_early; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_int; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_int; +reg m_axis_cc_tvalid_int; +reg m_axis_cc_tready_int_reg = 1'b0; +reg m_axis_cc_tlast_int; +reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_int; +wire m_axis_cc_tready_int_early; assign s_axis_cq_tready = s_axis_cq_tready_reg; @@ -235,7 +249,7 @@ always @* begin m_axis_cc_tkeep_int = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; m_axis_cc_tvalid_int = 1'b0; m_axis_cc_tlast_int = 1'b0; - m_axis_cc_tuser_int = 33'd0; + m_axis_cc_tuser_int = {AXIS_PCIE_CC_USER_WIDTH{1'b0}}; casez (first_be_reg) 4'b0000: m_axis_cc_tdata_int[6:0] = {m_axil_addr_reg[6:2], 2'b00}; // lower address @@ -763,17 +777,17 @@ always @(posedge clk) begin end // output datapath logic -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next; -reg m_axis_cc_tlast_reg = 1'b0; -reg [32:0] m_axis_cc_tuser_reg = 33'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next; +reg m_axis_cc_tlast_reg = 1'b0; +reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_reg = {AXIS_PCIE_CC_USER_WIDTH{1'b0}}; -reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg temp_m_axis_cc_tvalid_reg = 1'b0, temp_m_axis_cc_tvalid_next; -reg temp_m_axis_cc_tlast_reg = 1'b0; -reg [32:0] temp_m_axis_cc_tuser_reg = 33'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg temp_m_axis_cc_tvalid_reg = 1'b0, temp_m_axis_cc_tvalid_next; +reg temp_m_axis_cc_tlast_reg = 1'b0; +reg [AXIS_PCIE_CC_USER_WIDTH-1:0] temp_m_axis_cc_tuser_reg = {AXIS_PCIE_CC_USER_WIDTH{1'b0}}; // datapath control reg store_axis_int_to_output; diff --git a/rtl/pcie_us_axis_cq_demux.v b/rtl/pcie_us_axis_cq_demux.v index 70df60f90..5c0e30bb4 100644 --- a/rtl/pcie_us_axis_cq_demux.v +++ b/rtl/pcie_us_axis_cq_demux.v @@ -36,47 +36,49 @@ module pcie_us_axis_cq_demux # // Width of PCIe AXI stream interfaces in bits parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream CQ tuser signal width + parameter AXIS_PCIE_CQ_USER_WIDTH = 85 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input (CQ) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tvalid, - output wire s_axis_cq_tready, - input wire s_axis_cq_tlast, - input wire [84:0] s_axis_cq_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tvalid, + output wire s_axis_cq_tready, + input wire s_axis_cq_tlast, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, /* * AXI output (CQ) */ - output wire [M_COUNT*AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cq_tdata, - output wire [M_COUNT*AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cq_tkeep, - output wire [M_COUNT-1:0] m_axis_cq_tvalid, - input wire [M_COUNT-1:0] m_axis_cq_tready, - output wire [M_COUNT-1:0] m_axis_cq_tlast, - output wire [M_COUNT*85-1:0] m_axis_cq_tuser, + output wire [M_COUNT*AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cq_tdata, + output wire [M_COUNT*AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cq_tkeep, + output wire [M_COUNT-1:0] m_axis_cq_tvalid, + input wire [M_COUNT-1:0] m_axis_cq_tready, + output wire [M_COUNT-1:0] m_axis_cq_tlast, + output wire [M_COUNT*AXIS_PCIE_CQ_USER_WIDTH-1:0] m_axis_cq_tuser, /* * Fields */ - output wire [3:0] req_type, - output wire [7:0] target_function, - output wire [2:0] bar_id, - output wire [7:0] msg_code, - output wire [2:0] msg_routing, + output wire [3:0] req_type, + output wire [7:0] target_function, + output wire [2:0] bar_id, + output wire [7:0] msg_code, + output wire [2:0] msg_routing, /* * Control */ - input wire enable, - input wire drop, - input wire [M_COUNT-1:0] select + input wire enable, + input wire drop, + input wire [M_COUNT-1:0] select ); parameter CL_M_COUNT = $clog2(M_COUNT); @@ -100,20 +102,20 @@ reg frame_reg = 1'b0, frame_ctl, frame_next; reg s_axis_cq_tready_reg = 1'b0, s_axis_cq_tready_next; -reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_s_axis_cq_tdata = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_s_axis_cq_tkeep = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg temp_s_axis_cq_tvalid = 1'b0; -reg temp_s_axis_cq_tlast = 1'b0; -reg [84:0] temp_s_axis_cq_tuser = 85'b0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_s_axis_cq_tdata = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_s_axis_cq_tkeep = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg temp_s_axis_cq_tvalid = 1'b0; +reg temp_s_axis_cq_tlast = 1'b0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] temp_s_axis_cq_tuser = {AXIS_PCIE_CQ_USER_WIDTH{1'b0}}; // internal datapath -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cq_tdata_int; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cq_tkeep_int; -reg [M_COUNT-1:0] m_axis_cq_tvalid_int; -reg m_axis_cq_tready_int_reg = 1'b0; -reg m_axis_cq_tlast_int; -reg [84:0] m_axis_cq_tuser_int; -wire m_axis_cq_tready_int_early; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cq_tdata_int; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cq_tkeep_int; +reg [M_COUNT-1:0] m_axis_cq_tvalid_int; +reg m_axis_cq_tready_int_reg = 1'b0; +reg m_axis_cq_tlast_int; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] m_axis_cq_tuser_int; +wire m_axis_cq_tready_int_early; assign s_axis_cq_tready = (s_axis_cq_tready_reg || (AXIS_PCIE_DATA_WIDTH == 64 && !temp_s_axis_cq_tvalid)) && enable; @@ -220,17 +222,17 @@ always @(posedge clk) begin end // output datapath logic -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg [M_COUNT-1:0] m_axis_cq_tvalid_reg = {M_COUNT{1'b0}}, m_axis_cq_tvalid_next; -reg m_axis_cq_tlast_reg = 1'b0; -reg [84:0] m_axis_cq_tuser_reg = 85'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg [M_COUNT-1:0] m_axis_cq_tvalid_reg = {M_COUNT{1'b0}}, m_axis_cq_tvalid_next; +reg m_axis_cq_tlast_reg = 1'b0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] m_axis_cq_tuser_reg = {AXIS_PCIE_CQ_USER_WIDTH{1'b0}}; -reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_cq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_cq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg [M_COUNT-1:0] temp_m_axis_cq_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_cq_tvalid_next; -reg temp_m_axis_cq_tlast_reg = 1'b0; -reg [84:0] temp_m_axis_cq_tuser_reg = 85'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_cq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_cq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg [M_COUNT-1:0] temp_m_axis_cq_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_cq_tvalid_next; +reg temp_m_axis_cq_tlast_reg = 1'b0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] temp_m_axis_cq_tuser_reg = {AXIS_PCIE_CQ_USER_WIDTH{1'b0}}; // datapath control reg store_axis_int_to_output; diff --git a/rtl/pcie_us_axis_rc_demux.v b/rtl/pcie_us_axis_rc_demux.v index 708855da5..55bf8965d 100644 --- a/rtl/pcie_us_axis_rc_demux.v +++ b/rtl/pcie_us_axis_rc_demux.v @@ -36,43 +36,45 @@ module pcie_us_axis_rc_demux # // Width of PCIe AXI stream interfaces in bits parameter AXIS_PCIE_DATA_WIDTH = 256, // PCIe AXI stream tkeep signal width (words per cycle) - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + // PCIe AXI stream RC tuser signal width + parameter AXIS_PCIE_RC_USER_WIDTH = 75 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input (RC) */ - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tvalid, - output wire s_axis_rc_tready, - input wire s_axis_rc_tlast, - input wire [74:0] s_axis_rc_tuser, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tvalid, + output wire s_axis_rc_tready, + input wire s_axis_rc_tlast, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, /* * AXI output (RC) */ - output wire [M_COUNT*AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata, - output wire [M_COUNT*AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep, - output wire [M_COUNT-1:0] m_axis_rc_tvalid, - input wire [M_COUNT-1:0] m_axis_rc_tready, - output wire [M_COUNT-1:0] m_axis_rc_tlast, - output wire [M_COUNT*75-1:0] m_axis_rc_tuser, + output wire [M_COUNT*AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata, + output wire [M_COUNT*AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep, + output wire [M_COUNT-1:0] m_axis_rc_tvalid, + input wire [M_COUNT-1:0] m_axis_rc_tready, + output wire [M_COUNT-1:0] m_axis_rc_tlast, + output wire [M_COUNT*AXIS_PCIE_RC_USER_WIDTH-1:0] m_axis_rc_tuser, /* * Fields */ - output wire [15:0] requester_id, + output wire [15:0] requester_id, /* * Control */ - input wire enable, - input wire drop, - input wire [M_COUNT-1:0] select + input wire enable, + input wire drop, + input wire [M_COUNT-1:0] select ); parameter CL_M_COUNT = $clog2(M_COUNT); @@ -97,13 +99,13 @@ reg frame_reg = 1'b0, frame_ctl, frame_next; reg s_axis_rc_tready_reg = 1'b0, s_axis_rc_tready_next; // internal datapath -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata_int; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep_int; -reg [M_COUNT-1:0] m_axis_rc_tvalid_int; -reg m_axis_rc_tready_int_reg = 1'b0; -reg m_axis_rc_tlast_int; -reg [74:0] m_axis_rc_tuser_int; -wire m_axis_rc_tready_int_early; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata_int; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep_int; +reg [M_COUNT-1:0] m_axis_rc_tvalid_int; +reg m_axis_rc_tready_int_reg = 1'b0; +reg m_axis_rc_tlast_int; +reg [AXIS_PCIE_RC_USER_WIDTH-1:0] m_axis_rc_tuser_int; +wire m_axis_rc_tready_int_early; assign s_axis_rc_tready = s_axis_rc_tready_reg && enable; @@ -172,17 +174,17 @@ always @(posedge clk) begin end // output datapath logic -reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg [M_COUNT-1:0] m_axis_rc_tvalid_reg = {M_COUNT{1'b0}}, m_axis_rc_tvalid_next; -reg m_axis_rc_tlast_reg = 1'b0; -reg [74:0] m_axis_rc_tuser_reg = 75'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg [M_COUNT-1:0] m_axis_rc_tvalid_reg = {M_COUNT{1'b0}}, m_axis_rc_tvalid_next; +reg m_axis_rc_tlast_reg = 1'b0; +reg [AXIS_PCIE_RC_USER_WIDTH-1:0] m_axis_rc_tuser_reg = {AXIS_PCIE_RC_USER_WIDTH{1'b0}}; -reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_rc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; -reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_rc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; -reg [M_COUNT-1:0] temp_m_axis_rc_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_rc_tvalid_next; -reg temp_m_axis_rc_tlast_reg = 1'b0; -reg [74:0] temp_m_axis_rc_tuser_reg = 75'd0; +reg [AXIS_PCIE_DATA_WIDTH-1:0] temp_m_axis_rc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}; +reg [AXIS_PCIE_KEEP_WIDTH-1:0] temp_m_axis_rc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}; +reg [M_COUNT-1:0] temp_m_axis_rc_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_rc_tvalid_next; +reg temp_m_axis_rc_tlast_reg = 1'b0; +reg [AXIS_PCIE_RC_USER_WIDTH-1:0] temp_m_axis_rc_tuser_reg = {AXIS_PCIE_RC_USER_WIDTH{1'b0}}; // datapath control reg store_axis_int_to_output; diff --git a/tb/test_pcie_us_axi_dma_256.py b/tb/test_pcie_us_axi_dma_256.py index dd016734e..188bb0490 100755 --- a/tb/test_pcie_us_axi_dma_256.py +++ b/tb/test_pcie_us_axi_dma_256.py @@ -52,6 +52,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_RC_USER_WIDTH = 75 + AXIS_PCIE_RQ_USER_WIDTH = 60 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -74,7 +76,7 @@ def bench(): s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rc_tvalid = Signal(bool(0)) s_axis_rc_tlast = Signal(bool(0)) - s_axis_rc_tuser = Signal(intbv(0)[75:]) + s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:]) m_axis_rq_tready = Signal(bool(0)) s_axis_pcie_rq_tag = Signal(intbv(0)[PCIE_TAG_WIDTH:]) s_axis_pcie_rq_tag_valid = Signal(bool(0)) @@ -113,7 +115,7 @@ def bench(): m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) m_axis_rq_tlast = Signal(bool(0)) - m_axis_rq_tuser = Signal(intbv(0)[60:]) + m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) s_axis_read_desc_ready = Signal(bool(0)) m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_read_desc_status_valid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axi_dma_256.v b/tb/test_pcie_us_axi_dma_256.v index 2fab3a153..03a174d64 100644 --- a/tb/test_pcie_us_axi_dma_256.v +++ b/tb/test_pcie_us_axi_dma_256.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_dma_256; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 256; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = 75; +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -56,7 +58,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep = 0; reg s_axis_rc_tvalid = 0; reg s_axis_rc_tlast = 0; -reg [74:0] s_axis_rc_tuser = 0; +reg [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser = 0; reg m_axis_rq_tready = 0; reg [PCIE_TAG_WIDTH-1:0] s_axis_pcie_rq_tag = 0; reg s_axis_pcie_rq_tag_valid = 0; @@ -95,7 +97,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep; wire m_axis_rq_tvalid; wire m_axis_rq_tlast; -wire [59:0] m_axis_rq_tuser; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser; wire s_axis_read_desc_ready; wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag; wire m_axis_read_desc_status_valid; @@ -221,6 +223,8 @@ end pcie_us_axi_dma #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_dma_rd_128.py b/tb/test_pcie_us_axi_dma_rd_128.py index 425ef6b17..8823aaf74 100755 --- a/tb/test_pcie_us_axi_dma_rd_128.py +++ b/tb/test_pcie_us_axi_dma_rd_128.py @@ -51,6 +51,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 128 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_RC_USER_WIDTH = 75 + AXIS_PCIE_RQ_USER_WIDTH = 60 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -73,7 +75,7 @@ def bench(): s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rc_tvalid = Signal(bool(0)) s_axis_rc_tlast = Signal(bool(0)) - s_axis_rc_tuser = Signal(intbv(0)[75:]) + s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:]) m_axis_rq_tready = Signal(bool(0)) s_axis_pcie_rq_tag = Signal(intbv(0)[PCIE_TAG_WIDTH:]) s_axis_pcie_rq_tag_valid = Signal(bool(0)) @@ -99,7 +101,7 @@ def bench(): m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) m_axis_rq_tlast = Signal(bool(0)) - m_axis_rq_tuser = Signal(intbv(0)[60:]) + m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) s_axis_read_desc_ready = Signal(bool(0)) m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_read_desc_status_valid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axi_dma_rd_128.v b/tb/test_pcie_us_axi_dma_rd_128.v index 0e7512e38..aec44308b 100644 --- a/tb/test_pcie_us_axi_dma_rd_128.v +++ b/tb/test_pcie_us_axi_dma_rd_128.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_dma_rd_128; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 128; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = 75; +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -56,7 +58,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep = 0; reg s_axis_rc_tvalid = 0; reg s_axis_rc_tlast = 0; -reg [74:0] s_axis_rc_tuser = 0; +reg [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser = 0; reg m_axis_rq_tready = 0; reg [PCIE_TAG_WIDTH-1:0] s_axis_pcie_rq_tag = 0; reg s_axis_pcie_rq_tag_valid = 0; @@ -82,7 +84,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep; wire m_axis_rq_tvalid; wire m_axis_rq_tlast; -wire [59:0] m_axis_rq_tuser; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser; wire s_axis_read_desc_ready; wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag; wire m_axis_read_desc_status_valid; @@ -169,6 +171,8 @@ end pcie_us_axi_dma_rd #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_dma_rd_256.py b/tb/test_pcie_us_axi_dma_rd_256.py index d030a52a6..0ff653cbe 100755 --- a/tb/test_pcie_us_axi_dma_rd_256.py +++ b/tb/test_pcie_us_axi_dma_rd_256.py @@ -51,6 +51,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_RC_USER_WIDTH = 75 + AXIS_PCIE_RQ_USER_WIDTH = 60 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -73,7 +75,7 @@ def bench(): s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rc_tvalid = Signal(bool(0)) s_axis_rc_tlast = Signal(bool(0)) - s_axis_rc_tuser = Signal(intbv(0)[75:]) + s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:]) m_axis_rq_tready = Signal(bool(0)) s_axis_pcie_rq_tag = Signal(intbv(0)[PCIE_TAG_WIDTH:]) s_axis_pcie_rq_tag_valid = Signal(bool(0)) @@ -99,7 +101,7 @@ def bench(): m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) m_axis_rq_tlast = Signal(bool(0)) - m_axis_rq_tuser = Signal(intbv(0)[60:]) + m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) s_axis_read_desc_ready = Signal(bool(0)) m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_read_desc_status_valid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axi_dma_rd_256.v b/tb/test_pcie_us_axi_dma_rd_256.v index e912104a2..d8164eb50 100644 --- a/tb/test_pcie_us_axi_dma_rd_256.v +++ b/tb/test_pcie_us_axi_dma_rd_256.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_dma_rd_256; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 256; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = 75; +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -56,7 +58,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep = 0; reg s_axis_rc_tvalid = 0; reg s_axis_rc_tlast = 0; -reg [74:0] s_axis_rc_tuser = 0; +reg [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser = 0; reg m_axis_rq_tready = 0; reg [PCIE_TAG_WIDTH-1:0] s_axis_pcie_rq_tag = 0; reg s_axis_pcie_rq_tag_valid = 0; @@ -82,7 +84,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep; wire m_axis_rq_tvalid; wire m_axis_rq_tlast; -wire [59:0] m_axis_rq_tuser; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser; wire s_axis_read_desc_ready; wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag; wire m_axis_read_desc_status_valid; @@ -169,6 +171,8 @@ end pcie_us_axi_dma_rd #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_dma_rd_64.py b/tb/test_pcie_us_axi_dma_rd_64.py index a564b1d40..2f0515798 100755 --- a/tb/test_pcie_us_axi_dma_rd_64.py +++ b/tb/test_pcie_us_axi_dma_rd_64.py @@ -51,6 +51,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 64 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_RC_USER_WIDTH = 75 + AXIS_PCIE_RQ_USER_WIDTH = 60 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -73,7 +75,7 @@ def bench(): s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rc_tvalid = Signal(bool(0)) s_axis_rc_tlast = Signal(bool(0)) - s_axis_rc_tuser = Signal(intbv(0)[75:]) + s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:]) m_axis_rq_tready = Signal(bool(0)) s_axis_pcie_rq_tag = Signal(intbv(0)[PCIE_TAG_WIDTH:]) s_axis_pcie_rq_tag_valid = Signal(bool(0)) @@ -99,7 +101,7 @@ def bench(): m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) m_axis_rq_tlast = Signal(bool(0)) - m_axis_rq_tuser = Signal(intbv(0)[60:]) + m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) s_axis_read_desc_ready = Signal(bool(0)) m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_read_desc_status_valid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axi_dma_rd_64.v b/tb/test_pcie_us_axi_dma_rd_64.v index a7abf0a25..16d795af5 100644 --- a/tb/test_pcie_us_axi_dma_rd_64.v +++ b/tb/test_pcie_us_axi_dma_rd_64.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_dma_rd_64; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 64; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = 75; +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -56,7 +58,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep = 0; reg s_axis_rc_tvalid = 0; reg s_axis_rc_tlast = 0; -reg [74:0] s_axis_rc_tuser = 0; +reg [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser = 0; reg m_axis_rq_tready = 0; reg [PCIE_TAG_WIDTH-1:0] s_axis_pcie_rq_tag = 0; reg s_axis_pcie_rq_tag_valid = 0; @@ -82,7 +84,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep; wire m_axis_rq_tvalid; wire m_axis_rq_tlast; -wire [59:0] m_axis_rq_tuser; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser; wire s_axis_read_desc_ready; wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag; wire m_axis_read_desc_status_valid; @@ -169,6 +171,8 @@ end pcie_us_axi_dma_rd #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_dma_wr_128.py b/tb/test_pcie_us_axi_dma_wr_128.py index 9f976be95..307e1bf34 100755 --- a/tb/test_pcie_us_axi_dma_wr_128.py +++ b/tb/test_pcie_us_axi_dma_wr_128.py @@ -48,6 +48,7 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 128 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_RQ_USER_WIDTH = 60 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -66,7 +67,7 @@ def bench(): s_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rq_tvalid = Signal(bool(0)) s_axis_rq_tlast = Signal(bool(0)) - s_axis_rq_tuser = Signal(intbv(0)[60:]) + s_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) m_axis_rq_tready = Signal(bool(0)) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) @@ -90,7 +91,7 @@ def bench(): m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) m_axis_rq_tlast = Signal(bool(0)) - m_axis_rq_tuser = Signal(intbv(0)[60:]) + m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) s_axis_write_desc_ready = Signal(bool(0)) m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_write_desc_status_valid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axi_dma_wr_128.v b/tb/test_pcie_us_axi_dma_wr_128.v index 5ee411f8c..5b6a9564a 100644 --- a/tb/test_pcie_us_axi_dma_wr_128.v +++ b/tb/test_pcie_us_axi_dma_wr_128.v @@ -34,6 +34,7 @@ module test_pcie_us_axi_dma_wr_128; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 128; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -52,7 +53,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep = 0; reg s_axis_rq_tvalid = 0; reg s_axis_rq_tlast = 0; -reg [59:0] s_axis_rq_tuser = 0; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] s_axis_rq_tuser = 0; reg m_axis_rq_tready = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0; @@ -76,7 +77,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep; wire m_axis_rq_tvalid; wire m_axis_rq_tlast; -wire [59:0] m_axis_rq_tuser; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser; wire s_axis_write_desc_ready; wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag; wire m_axis_write_desc_status_valid; @@ -149,6 +150,7 @@ end pcie_us_axi_dma_wr #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_dma_wr_256.py b/tb/test_pcie_us_axi_dma_wr_256.py index 0563d4b71..6a81001d0 100755 --- a/tb/test_pcie_us_axi_dma_wr_256.py +++ b/tb/test_pcie_us_axi_dma_wr_256.py @@ -48,6 +48,7 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_RQ_USER_WIDTH = 60 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -66,7 +67,7 @@ def bench(): s_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rq_tvalid = Signal(bool(0)) s_axis_rq_tlast = Signal(bool(0)) - s_axis_rq_tuser = Signal(intbv(0)[60:]) + s_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) m_axis_rq_tready = Signal(bool(0)) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) @@ -90,7 +91,7 @@ def bench(): m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) m_axis_rq_tlast = Signal(bool(0)) - m_axis_rq_tuser = Signal(intbv(0)[60:]) + m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) s_axis_write_desc_ready = Signal(bool(0)) m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_write_desc_status_valid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axi_dma_wr_256.v b/tb/test_pcie_us_axi_dma_wr_256.v index abe8adffe..5f14347d6 100644 --- a/tb/test_pcie_us_axi_dma_wr_256.v +++ b/tb/test_pcie_us_axi_dma_wr_256.v @@ -34,6 +34,7 @@ module test_pcie_us_axi_dma_wr_256; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 256; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -52,7 +53,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep = 0; reg s_axis_rq_tvalid = 0; reg s_axis_rq_tlast = 0; -reg [59:0] s_axis_rq_tuser = 0; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] s_axis_rq_tuser = 0; reg m_axis_rq_tready = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0; @@ -76,7 +77,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep; wire m_axis_rq_tvalid; wire m_axis_rq_tlast; -wire [59:0] m_axis_rq_tuser; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser; wire s_axis_write_desc_ready; wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag; wire m_axis_write_desc_status_valid; @@ -149,6 +150,7 @@ end pcie_us_axi_dma_wr #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_dma_wr_64.py b/tb/test_pcie_us_axi_dma_wr_64.py index f9ba5f66f..0388825d1 100755 --- a/tb/test_pcie_us_axi_dma_wr_64.py +++ b/tb/test_pcie_us_axi_dma_wr_64.py @@ -48,6 +48,7 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 64 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_RQ_USER_WIDTH = 60 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -66,7 +67,7 @@ def bench(): s_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rq_tvalid = Signal(bool(0)) s_axis_rq_tlast = Signal(bool(0)) - s_axis_rq_tuser = Signal(intbv(0)[60:]) + s_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) m_axis_rq_tready = Signal(bool(0)) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) @@ -90,7 +91,7 @@ def bench(): m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) m_axis_rq_tlast = Signal(bool(0)) - m_axis_rq_tuser = Signal(intbv(0)[60:]) + m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) s_axis_write_desc_ready = Signal(bool(0)) m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_write_desc_status_valid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axi_dma_wr_64.v b/tb/test_pcie_us_axi_dma_wr_64.v index 93d81b5bf..263ab3464 100644 --- a/tb/test_pcie_us_axi_dma_wr_64.v +++ b/tb/test_pcie_us_axi_dma_wr_64.v @@ -34,6 +34,7 @@ module test_pcie_us_axi_dma_wr_64; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 64; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -52,7 +53,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep = 0; reg s_axis_rq_tvalid = 0; reg s_axis_rq_tlast = 0; -reg [59:0] s_axis_rq_tuser = 0; +reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] s_axis_rq_tuser = 0; reg m_axis_rq_tready = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0; @@ -76,7 +77,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep; wire m_axis_rq_tvalid; wire m_axis_rq_tlast; -wire [59:0] m_axis_rq_tuser; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser; wire s_axis_write_desc_ready; wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag; wire m_axis_write_desc_status_valid; @@ -149,6 +150,7 @@ end pcie_us_axi_dma_wr #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_128.py b/tb/test_pcie_us_axi_master_128.py index 5f9fe9dfa..6922c2328 100755 --- a/tb/test_pcie_us_axi_master_128.py +++ b/tb/test_pcie_us_axi_master_128.py @@ -51,6 +51,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 128 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -66,7 +68,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axi_awready = Signal(bool(0)) m_axi_wready = Signal(bool(0)) @@ -89,7 +91,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_awlen = Signal(intbv(0)[8:]) diff --git a/tb/test_pcie_us_axi_master_128.v b/tb/test_pcie_us_axi_master_128.v index a6e1d883a..f822fa4f8 100644 --- a/tb/test_pcie_us_axi_master_128.v +++ b/tb/test_pcie_us_axi_master_128.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_master_128; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 128; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +51,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axi_awready = 0; reg m_axi_wready = 0; @@ -72,7 +74,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ID_WIDTH-1:0] m_axi_awid; wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr; wire [7:0] m_axi_awlen; @@ -170,6 +172,8 @@ end pcie_us_axi_master #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_256.py b/tb/test_pcie_us_axi_master_256.py index 553136da6..1c92e4904 100755 --- a/tb/test_pcie_us_axi_master_256.py +++ b/tb/test_pcie_us_axi_master_256.py @@ -51,6 +51,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -66,7 +68,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axi_awready = Signal(bool(0)) m_axi_wready = Signal(bool(0)) @@ -89,7 +91,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_awlen = Signal(intbv(0)[8:]) diff --git a/tb/test_pcie_us_axi_master_256.v b/tb/test_pcie_us_axi_master_256.v index 4af0cde08..1b127a076 100644 --- a/tb/test_pcie_us_axi_master_256.v +++ b/tb/test_pcie_us_axi_master_256.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_master_256; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 256; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +51,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axi_awready = 0; reg m_axi_wready = 0; @@ -72,7 +74,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ID_WIDTH-1:0] m_axi_awid; wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr; wire [7:0] m_axi_awlen; @@ -170,6 +172,8 @@ end pcie_us_axi_master #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_64.py b/tb/test_pcie_us_axi_master_64.py index 310acb643..bb1ba7c99 100755 --- a/tb/test_pcie_us_axi_master_64.py +++ b/tb/test_pcie_us_axi_master_64.py @@ -51,6 +51,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 64 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -66,7 +68,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axi_awready = Signal(bool(0)) m_axi_wready = Signal(bool(0)) @@ -89,7 +91,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_awlen = Signal(intbv(0)[8:]) diff --git a/tb/test_pcie_us_axi_master_64.v b/tb/test_pcie_us_axi_master_64.v index 5921ac7af..c2598efb1 100644 --- a/tb/test_pcie_us_axi_master_64.v +++ b/tb/test_pcie_us_axi_master_64.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_master_64; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 64; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +51,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axi_awready = 0; reg m_axi_wready = 0; @@ -72,7 +74,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ID_WIDTH-1:0] m_axi_awid; wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr; wire [7:0] m_axi_awlen; @@ -170,6 +172,8 @@ end pcie_us_axi_master #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_rd_128.py b/tb/test_pcie_us_axi_master_rd_128.py index 665f2ac6b..17fc38fb4 100755 --- a/tb/test_pcie_us_axi_master_rd_128.py +++ b/tb/test_pcie_us_axi_master_rd_128.py @@ -47,6 +47,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 128 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -62,7 +64,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axi_arready = Signal(bool(0)) m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:]) @@ -80,7 +82,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_arlen = Signal(intbv(0)[8:]) diff --git a/tb/test_pcie_us_axi_master_rd_128.v b/tb/test_pcie_us_axi_master_rd_128.v index 595ee8c2f..9361007e1 100644 --- a/tb/test_pcie_us_axi_master_rd_128.v +++ b/tb/test_pcie_us_axi_master_rd_128.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_master_rd_128; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 128; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +51,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axi_arready = 0; reg [AXI_ID_WIDTH-1:0] m_axi_rid = 0; @@ -67,7 +69,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ID_WIDTH-1:0] m_axi_arid; wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr; wire [7:0] m_axi_arlen; @@ -132,6 +134,8 @@ end pcie_us_axi_master_rd #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_rd_256.py b/tb/test_pcie_us_axi_master_rd_256.py index 718de4ebb..6945acc38 100755 --- a/tb/test_pcie_us_axi_master_rd_256.py +++ b/tb/test_pcie_us_axi_master_rd_256.py @@ -47,6 +47,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -62,7 +64,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axi_arready = Signal(bool(0)) m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:]) @@ -80,7 +82,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_arlen = Signal(intbv(0)[8:]) diff --git a/tb/test_pcie_us_axi_master_rd_256.v b/tb/test_pcie_us_axi_master_rd_256.v index e88ed851a..32d24c2be 100644 --- a/tb/test_pcie_us_axi_master_rd_256.v +++ b/tb/test_pcie_us_axi_master_rd_256.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_master_rd_256; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 256; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +51,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axi_arready = 0; reg [AXI_ID_WIDTH-1:0] m_axi_rid = 0; @@ -67,7 +69,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ID_WIDTH-1:0] m_axi_arid; wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr; wire [7:0] m_axi_arlen; @@ -132,6 +134,8 @@ end pcie_us_axi_master_rd #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_rd_64.py b/tb/test_pcie_us_axi_master_rd_64.py index 4245c0de6..2c0e5a6c3 100755 --- a/tb/test_pcie_us_axi_master_rd_64.py +++ b/tb/test_pcie_us_axi_master_rd_64.py @@ -47,6 +47,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 64 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -62,7 +64,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axi_arready = Signal(bool(0)) m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:]) @@ -80,7 +82,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_arlen = Signal(intbv(0)[8:]) diff --git a/tb/test_pcie_us_axi_master_rd_64.v b/tb/test_pcie_us_axi_master_rd_64.v index c1c7f0cb1..198a4ea91 100644 --- a/tb/test_pcie_us_axi_master_rd_64.v +++ b/tb/test_pcie_us_axi_master_rd_64.v @@ -34,6 +34,8 @@ module test_pcie_us_axi_master_rd_64; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 64; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +51,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axi_arready = 0; reg [AXI_ID_WIDTH-1:0] m_axi_rid = 0; @@ -67,7 +69,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ID_WIDTH-1:0] m_axi_arid; wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr; wire [7:0] m_axi_arlen; @@ -132,6 +134,8 @@ end pcie_us_axi_master_rd #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_wr_128.py b/tb/test_pcie_us_axi_master_wr_128.py index be709ff5e..bcee272fe 100755 --- a/tb/test_pcie_us_axi_master_wr_128.py +++ b/tb/test_pcie_us_axi_master_wr_128.py @@ -47,6 +47,7 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 128 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -62,7 +63,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axi_awready = Signal(bool(0)) m_axi_wready = Signal(bool(0)) m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:]) diff --git a/tb/test_pcie_us_axi_master_wr_128.v b/tb/test_pcie_us_axi_master_wr_128.v index eaf653eb1..fd5041802 100644 --- a/tb/test_pcie_us_axi_master_wr_128.v +++ b/tb/test_pcie_us_axi_master_wr_128.v @@ -34,6 +34,7 @@ module test_pcie_us_axi_master_wr_128; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 128; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +50,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axi_awready = 0; reg m_axi_wready = 0; reg [AXI_ID_WIDTH-1:0] m_axi_bid = 0; @@ -118,6 +119,7 @@ end pcie_us_axi_master_wr #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_wr_256.py b/tb/test_pcie_us_axi_master_wr_256.py index 5d553e13b..49a0fa3ac 100755 --- a/tb/test_pcie_us_axi_master_wr_256.py +++ b/tb/test_pcie_us_axi_master_wr_256.py @@ -47,6 +47,7 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -62,7 +63,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axi_awready = Signal(bool(0)) m_axi_wready = Signal(bool(0)) m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:]) diff --git a/tb/test_pcie_us_axi_master_wr_256.v b/tb/test_pcie_us_axi_master_wr_256.v index a7ecd6fd7..9fc687c51 100644 --- a/tb/test_pcie_us_axi_master_wr_256.v +++ b/tb/test_pcie_us_axi_master_wr_256.v @@ -34,6 +34,7 @@ module test_pcie_us_axi_master_wr_256; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 256; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +50,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axi_awready = 0; reg m_axi_wready = 0; reg [AXI_ID_WIDTH-1:0] m_axi_bid = 0; @@ -118,6 +119,7 @@ end pcie_us_axi_master_wr #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axi_master_wr_64.py b/tb/test_pcie_us_axi_master_wr_64.py index 9fe4d23e9..e8c2f0756 100755 --- a/tb/test_pcie_us_axi_master_wr_64.py +++ b/tb/test_pcie_us_axi_master_wr_64.py @@ -47,6 +47,7 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 64 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -62,7 +63,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axi_awready = Signal(bool(0)) m_axi_wready = Signal(bool(0)) m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:]) diff --git a/tb/test_pcie_us_axi_master_wr_64.v b/tb/test_pcie_us_axi_master_wr_64.v index 818514401..c45c56f0e 100644 --- a/tb/test_pcie_us_axi_master_wr_64.v +++ b/tb/test_pcie_us_axi_master_wr_64.v @@ -34,6 +34,7 @@ module test_pcie_us_axi_master_wr_64; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 64; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -49,7 +50,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axi_awready = 0; reg m_axi_wready = 0; reg [AXI_ID_WIDTH-1:0] m_axi_bid = 0; @@ -118,6 +119,7 @@ end pcie_us_axi_master_wr #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axil_master_128.py b/tb/test_pcie_us_axil_master_128.py index 188690563..0f172a2f3 100755 --- a/tb/test_pcie_us_axil_master_128.py +++ b/tb/test_pcie_us_axil_master_128.py @@ -47,6 +47,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 128 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = 32 AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -61,7 +63,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axil_awready = Signal(bool(0)) m_axil_wready = Signal(bool(0)) @@ -80,7 +82,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axil_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axil_awprot = Signal(intbv(0)[3:]) m_axil_awvalid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axil_master_128.v b/tb/test_pcie_us_axil_master_128.v index 1ff0b2988..b90fa15c8 100644 --- a/tb/test_pcie_us_axil_master_128.v +++ b/tb/test_pcie_us_axil_master_128.v @@ -34,6 +34,8 @@ module test_pcie_us_axil_master_128; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 128; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = 32; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -48,7 +50,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axil_awready = 0; reg m_axil_wready = 0; @@ -67,7 +69,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ADDR_WIDTH-1:0] m_axil_awaddr; wire [2:0] m_axil_awprot; wire m_axil_awvalid; @@ -135,6 +137,8 @@ end pcie_us_axil_master #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axil_master_256.py b/tb/test_pcie_us_axil_master_256.py index 1b6f36c35..50ad4bdbc 100755 --- a/tb/test_pcie_us_axil_master_256.py +++ b/tb/test_pcie_us_axil_master_256.py @@ -47,6 +47,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = 32 AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -61,7 +63,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axil_awready = Signal(bool(0)) m_axil_wready = Signal(bool(0)) @@ -80,7 +82,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axil_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axil_awprot = Signal(intbv(0)[3:]) m_axil_awvalid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axil_master_256.v b/tb/test_pcie_us_axil_master_256.v index 6e1976652..29e1c31f8 100644 --- a/tb/test_pcie_us_axil_master_256.v +++ b/tb/test_pcie_us_axil_master_256.v @@ -34,6 +34,8 @@ module test_pcie_us_axil_master_256; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 256; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = 32; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -48,7 +50,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axil_awready = 0; reg m_axil_wready = 0; @@ -67,7 +69,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ADDR_WIDTH-1:0] m_axil_awaddr; wire [2:0] m_axil_awprot; wire m_axil_awvalid; @@ -135,6 +137,8 @@ end pcie_us_axil_master #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH), diff --git a/tb/test_pcie_us_axil_master_64.py b/tb/test_pcie_us_axil_master_64.py index d18d663d7..d91f159be 100755 --- a/tb/test_pcie_us_axil_master_64.py +++ b/tb/test_pcie_us_axil_master_64.py @@ -47,6 +47,8 @@ def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 64 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + AXIS_PCIE_CQ_USER_WIDTH = 85 + AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = 32 AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) @@ -61,7 +63,7 @@ def bench(): s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) - s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axil_awready = Signal(bool(0)) m_axil_wready = Signal(bool(0)) @@ -80,7 +82,7 @@ def bench(): m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) - m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axil_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axil_awprot = Signal(intbv(0)[3:]) m_axil_awvalid = Signal(bool(0)) diff --git a/tb/test_pcie_us_axil_master_64.v b/tb/test_pcie_us_axil_master_64.v index a4a6cc261..80f92d28e 100644 --- a/tb/test_pcie_us_axil_master_64.v +++ b/tb/test_pcie_us_axil_master_64.v @@ -34,6 +34,8 @@ module test_pcie_us_axil_master_64; // Parameters parameter AXIS_PCIE_DATA_WIDTH = 64; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; parameter AXI_DATA_WIDTH = 32; parameter AXI_ADDR_WIDTH = 64; parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); @@ -48,7 +50,7 @@ reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0; reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0; reg s_axis_cq_tvalid = 0; reg s_axis_cq_tlast = 0; -reg [84:0] s_axis_cq_tuser = 0; +reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0; reg m_axis_cc_tready = 0; reg m_axil_awready = 0; reg m_axil_wready = 0; @@ -67,7 +69,7 @@ wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata; wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep; wire m_axis_cc_tvalid; wire m_axis_cc_tlast; -wire [32:0] m_axis_cc_tuser; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser; wire [AXI_ADDR_WIDTH-1:0] m_axil_awaddr; wire [2:0] m_axil_awprot; wire m_axil_awvalid; @@ -135,6 +137,8 @@ end pcie_us_axil_master #( .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH),