diff --git a/fpga/lib/psmake/.gitignore b/fpga/lib/psmake/.gitignore
new file mode 100644
index 000000000..c976eaec8
--- /dev/null
+++ b/fpga/lib/psmake/.gitignore
@@ -0,0 +1,5 @@
+# generic intermediate and editor backup files
+*.swp
+*.~
+.#*
+*~
diff --git a/fpga/lib/psmake/LICENSE.txt b/fpga/lib/psmake/LICENSE.txt
new file mode 100644
index 000000000..f433b1a53
--- /dev/null
+++ b/fpga/lib/psmake/LICENSE.txt
@@ -0,0 +1,177 @@
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
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+      "You" (or "Your") shall mean an individual or Legal Entity
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diff --git a/fpga/lib/psmake/README.md b/fpga/lib/psmake/README.md
new file mode 100644
index 000000000..b53591824
--- /dev/null
+++ b/fpga/lib/psmake/README.md
@@ -0,0 +1,1064 @@
+<!--
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2018-2019 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : README.md
+##  Initial Author : Stefan Wiehler <stefan.wiehler@missinglinkelectronics.com>
+##
+################################################################################
+-->
+
+# Processing System Makefiles
+
+This repository bundles convenience Makefiles for developing software targeting
+the embedded processors of SoC FPGAs or soft cores embedded in a programmable
+logic (PL) design – so called Processing Systems (PS). It features the
+following components:
+
+* PetaLinux wrapper Makefile
+* Xilinx Software Development Kit (XSDK) convenience Makefile
+* Xilinx Vitis convenience Makefile
+
+
+## PetaLinux Wrapper Makefile
+
+`petalinux.mk` is a Makefile for PetaLinux projects. It acts as convenience
+wrapper script around the PetaLinux toolchain and adds additional
+functionality.
+
+
+### Supported Platforms
+
+PetaLinux is supported from v2018.1 to v2019.1 (i.e. the last four releases).
+The Makefile should run on all underlying OSs supported by PetaLinux; however
+testing is only conducted on Ubuntu 18.04 LTS (Bionic Beaver) as of now.
+
+
+### Setup
+
+In your PetaLinux project directory, create a symlink named `Makefile` to the
+`petalinux.mk` file:
+
+    $ ln -s <path-to-your-psmake-repo>/petalinux.mk Makefile
+
+Then, execute:
+
+    $ make HDF=<path-to-your-.hdf-or-.xsa-file>
+
+to import a Hardware Description File (HDF) or a XSA file and build the
+PetaLinux project.
+
+
+### Usage
+
+The following Makefile targets are provided:
+
+`gethdf`
+: Initialize the project with a Hardware Description File (HDF) or a XSA
+file. You must provide a HDF or XSA file via the `HDF` variable.
+
+`config`
+: Configure system-level options.
+
+`config-kernel`
+: Configure the Linux kernel.
+
+`config-rootfs`
+: Configure the root filesystem.
+
+`build` (default)
+: Build the system.
+
+`sdk`
+: Build the Software Development Kit (SDK).
+
+`package-boot`
+: Package boot image. You can provide different binaries from the default ones
+for bitstream, FSBL, ATF, PMU firmware and U-Boot via the `BIT`, `FSBL`, `ATF`,
+`PMUFW` and `UBOOT` variables, respectively. To skip packaging bitstream, FSBL,
+ATF or PMU firmware, set the respective variable to `no`. Additional boot
+arguments can be specified with `BOOT_ARG_EXTRA`; run `petalinux-package --boot
+--help` for a list of options. The output path can be changed with the `BOOT`
+variable.
+
+`package-prebuilt`
+: Copy built artifacts to pre-built directory.
+
+`package-bsp`
+: Package Board Support Package (BSP). The BSP file name must be given with the
+`BSP` variable.
+
+`dts`
+: Decompile the device tree.
+
+`reset-jtag`
+: Reset board via JTAG. The hardware server URL must be provided via the
+`HW_SERVER_URL` variable.
+
+`boot-jtag-u-boot`
+: Boot board into U-Boot via JTAG. The hardware server URL must be provided via
+the `HW_SERVER_URL` variable.
+
+`boot-jtag-kernel`
+: Boot board and upload Linux kernel via JTAG. The hardware server URL must be
+provided via the `HW_SERVER_URL` variable.
+
+`boot-jtag-psinit-uboot`
+: Boot board into U-Boot via JTAG, but run `ps*_init.tcl` script instead of
+downloading and running FSBL. This can be inconvenient if the FSBL is doing
+boot mode specific jobs, e.g. loading a boot image from QSPI flash memory when
+in QSPI boot mode, although one does NOT want the FSBL to do that.  The
+hardware server URL must be provided via the `HW_SERVER_URL` variable. Only
+available on Zynq-7000 as of now.
+
+`boot-qemu`
+: Boot into QEMU.
+
+`flash-boot`
+: Flash boot image onto board via JTAG. The hardware server URL must be
+provided via the `HW_SERVER_URL` variable. The flash type must be specified
+with the `FLASH_TYPE` variable if it deviates from the default. The FSBL used
+for flashing, the boot image and the flash offset can be changed with the
+`FSBL_ELF`, `BOOT_BIN` and `BOOT_BIN_OFF` variables respectively.
+
+`flash-kernel`
+: Flash kernel image onto board via JTAG. The hardware server URL must be
+provided via the `HW_SERVER_URL` variable. The flash type must be specified
+with the `FLASH_TYPE` variable if it deviates from the default. The FSBL used
+for flashing, the kernel image and the flash offset can be changed with the
+`FSBL_ELF`, `KERNEL_IMG` and `KERNEL_IMG_OFF` variables respectively.
+
+`flash`
+: Flash boot and kernel image onto board via JTAG.
+
+`mrproper`
+: Clean all build artifacts. If this target is invoked with `CLEAN_HDF=1`, the
+HDF is deleted as well (i.e. all files in folder `project-spec/hw-description`
+except file `metadata`).
+
+
+### Networkless Builds
+
+In some circumstances, it might be desirable to perform builds without any
+network access; notably,
+- to provide long-term reproducibility in case of package sources being
+  not available online anymore.
+- to perform builds in corporate environments with restricted internet access.
+
+
+#### Setup
+
+A number of PetaLinux configuration options have to be changed to enable
+networkless builds; run `make config` and,
+
+- in Yocto Settings -> Add pre-mirror url, set the `pre-mirror url path` to
+  your local source mirror, e.g `file://${PROOT}/source-mirror` (or set
+  `CONFIG_PRE_MIRROR_URL` in `project-spec/configs/config`).
+- in Yocto Settings, uncheck `Enable Network sstate feeds`
+  (or unset `CONFIG_YOCTO_NETWORK_SSTATE_FEEDS` in
+  `project-spec/configs/config`).
+- in Yocto Settings, check `Enable BB NO NETWORK`
+  (or set `CONFIG_YOCTO_BB_NO_NETWORK` in `project-spec/configs/config`).
+
+
+#### Usage
+
+All sources that are not part of the PetaLinux installation will be stored in
+the local source mirror. To update the source mirror, run:
+
+    $ make UPDATE_MIRROR=1
+
+The local source mirror must be updated each and every time a package is added
+to the image. Notably, sources are only added to the source mirror, but never
+removed; so multiple revisions or entirely different PetaLinux projects can
+share a mirror. Cleanup of the source mirror should be performed manually when
+required.
+
+
+### Image Buildinfo
+
+Add the following snippet to `project-spec/meta-user/conf/petalinuxbsp.conf` in
+order to write build information to the target filesystem on `/etc/build`:
+
+    INHERIT += "image-buildinfo"
+    IMAGE_BUILDINFO_VARS_append = " DATETIME"
+
+`/etc/build` contains the build configuration as defined by the list of BitBake
+variables in `IMAGE_BUILINFO_VARS` and the Git revisions (branch/tag, commit ID
+and dirty flag) of all Yocto layers.
+
+Appending variables to `IMAGE_BUILDINFO_VARS` is optional; however the build
+time `DATETIME` is recommended. A list of common variables can be found in the
+[Variables Glossary of the Yocto Reference
+Manual](https://docs.yoctoproject.org/ref-manual/variables.html).
+
+
+### Image Version
+
+It is recommended to add image versioning information via
+[os-release](https://www.freedesktop.org/software/systemd/man/os-release.html)
+using the `IMAGE_ID` and `IMAGE_VERSION` variables.
+
+Add the `os-release` package to your root filesystem and extend it via
+`project-spec/meta-user/recipes-core/os-release/os-release.bbappend`. The
+following example will add the variables `BUILD_ID` (build timestamp),
+`IMAGE_ID` and `IMAGE_VERSION` to `/etc/os-release` on the target filesystem,
+identifying the image as `mle-example` and reading the semantic version from
+`version.txt` in the PetaLinux root directory.
+
+    OS_RELEASE_FIELDS += "BUILD_ID IMAGE_ID IMAGE_VERSION"
+
+    IMAGE_ID = "mle-example"
+
+    python do_compile_prepend () {
+        with open(d.getVar("TOPDIR") + "/../version.txt") as f:
+            major, minor, patch = f.readline().rstrip().split(".")
+
+        d.setVar("MAJOR_VERSION", major)
+        d.setVar("MINOR_VERSION", minor)
+        d.setVar("PATCH_VERSION", patch)
+        d.setVar("IMAGE_VERSION", "{}.{}.{}".format(major, minor, patch))
+    }
+
+
+### Open Source License Compliance
+
+There are three main areas of concern for [open source license
+compliance](http://docs.yoctoproject.org/dev-manual/common-tasks.html#maintaining-open-source-license-compliance-during-your-product-s-lifecycle).
+
+1. Source code must be provided.
+
+2. License text for the software must be provided.
+
+3. Compilation scripts and modifications to the source code must be provided.
+
+The first two points can be adressed by running:
+
+    $ make source-release SOURCE_RELEASE=<source-release-dir> MANIFESTS=<manifests-dir>
+
+This will create tarballs for packages that require the release of source code
+(i.e. GPL) in the directory `SOURCE_RELEASE` (defaulting to `source-release`).
+
+In addition, a license manifest is stored in directory `MANIFESTS` (defaulting
+to `manifests`) to assist with audits.
+
+Some licenses require the license text to accompany the binary. You can achieve
+this by adding the following to your
+`project-spec/meta-user/conf/petalinuxbsp.conf` file:
+
+    COPY_LIC_MANIFEST = "1"
+    COPY_LIC_DIRS = "1"
+    LICENSE_CREATE_PACKAGE = "1"
+
+
+### Extending
+
+If you need additional functionality in your project, put it into a file named
+`local.mk`.
+
+
+## XSDK Makefile
+
+The XSDK Makefile provides a declarative wrapper around the Xilinx Software
+Command-Line Tool (XSCT) and Bootgen to streamline the build of Xilinx Software
+Development Kit (XSDK) projects.
+
+
+### Supported Platforms
+
+XSDK is supported from v2018.1 to v2019.1 (i.e. the last four releases). The
+Makefile should run on all underlying Linux OSs supported by XSDK, but not
+Windows. However, testing is only conducted on Ubuntu 18.04 LTS (Bionic Beaver)
+as of now.
+
+
+### Build Configuration Syntax
+
+The XSDK Makefile is configured via a custom syntax as documented in the
+following sections.
+
+
+#### Hardware Platform Specification
+
+The Hardware Platform Specification captures all the information from a
+hardware design that is required to write, debug and deploy software
+applications for that hardware. In the XSDK Makefile, there is exactly one
+hardware platform specification called `hw` by default [^1]. The hardware
+platform specification is derived from the Hardware Description File (HDF)
+imported during build (see section Usage) and does not need to be configured.
+
+[^1]: The hardware platform specification name can be changed with the `HW_PRJ`
+      variable if necessary.
+
+#### Repositories
+
+A software repository is a directory that holds third-party software
+components, as well as custom drivers, libraries, and operating systems. You
+can register repositories in the workspace by adding the respective path to the
+`REPOS` variable.
+
+#### Board Support Packages
+
+A Board Support Package (BSP) is a collection of libraries and drivers that
+form the basis of software applications (see section "Applications").
+
+BSPs are registered by adding their name to the `BSP_PRJS` list. They can then
+be configured by prefixing the corresponding option with their name:
+
+    BSP_PRJS += fsbl_bsp
+    fsbl_bsp_PROC = psu_cortexa53_0
+    fsbl_bsp_IS_FSBL = yes
+    fsbl_bsp_LIBS = xilffs xilsecure xilpm
+    fsbl_bsp_POST_CREATE_TCL = configbsp -bsp fsbl_bsp use_strfunc 1
+
+    BSP_PRJS += gen_bsp
+    gen_bsp_PROC = psu_cortexa53_0
+    gen_bsp_STDOUT = psu_uart_1
+
+The following BSP options are available:
+
+`OS`
+: Operating system type. Optional, defaults to `standalone`. Run `repo -os` in
+XSCT to get a list of all OSs.
+
+`PROC`
+: Processor instance. Run `toolchain` in XSCT to get a list of supported
+processor types.
+
+`ARCH`
+: Processor architecture. Can be 32 or 64 bit. Valid only for processors
+supporting multiple architectures (e.g. A53).
+
+`PATCH`
+: List of space-separated patch file entries. Patches are applied in the base
+directory of the respective BSP project. A patch file list entry has the format
+`<patchfile>[;stripnum]`, where `stripnum` is the optional number of leading
+slashes to be stripped from each file name found in the patch file (default is
+1).
+
+`SED`
+: List of space-separated file entries to be transformed with sed (stream
+editor). Sed is run in the base directory of the respective BSP project. A sed
+list entry has the format `<srcfile>;<sedfile>`, where `<srcfile>` is the file
+to be transformed and `<sedfile>` the sed script file.
+
+`IS_FSBL`
+: If `yes`, apply non-default BSP settings for FSBL.
+
+`EXTRA_CFLAGS`
+: Additional compiler flags (default `-g -Wall -Wextra`). The default
+optimization level of `-O2` can be overriden with this variable.
+
+`STDIN`
+: Select UART for standard input.
+
+`STDOUT`
+: Select UART for standard output.
+
+`LIBS`
+: List of libraries to be added to the BSP. Run `repo -lib` in XSCT to get a
+list of available libraries.
+
+`POST_CREATE_TCL`
+: Hook for adding extra Tcl commands after the BSP has been created. Can be
+used to configure BSP settings (via the `configbsp` command) not available in
+the XSDK Makefile.
+
+
+#### Applications
+
+Software application projects are your final application containers. They can
+either be derived from a template or contain your own source files. Each
+application project must be linked to exactly one BSP.
+
+Application projects are registered by adding their name to the `APP_PRJS`
+list. They can then be configured by prefixing the corresponding option with
+their name:
+
+    APP_PRJS += fsbl
+    fsbl_TMPL = Zynq MP FSBL
+    fsbl_BSP = fsbl_bsp
+    fsbl_CPPSYMS = FSBL_DEBUG_DETAILED
+
+    APP_PRJS += helloworld
+    helloworld_TMPL = Hello World
+    helloworld_BSP = gen_bsp
+    helloworld_BCFG = Debug
+    helloworld_PATCH = helloworld.patch
+    helloworld_SED = platform.c;baud_rate.sed
+    helloworld_LIBS = helloworldlib
+
+The following application project options are available:
+
+`TMPL`
+: Name of the template to base the application project on. Run `repo -apps` in
+XSCT to get a list of available application templates.
+
+`PROC`
+: Processor instance. Run `toolchain` in XSCT to get a list of supported
+processor types.
+
+`LANG`
+: Programming language. Can be either `c` (default) or `c++`.
+
+`BSP`
+: Reference to BSP. Required.
+
+`SRC`
+: List of space-separated source files to be added to the application. For each
+list entry, a symlink in the `src` directory of the respective application
+project will be created that points towards the corresponding source file.
+
+`PATCH`
+: List of space-separated patch file entries. Patches are applied in the `src`
+directory of the respective application project. A patch file list entry has
+the format `<patchfile>[;stripnum]`, where `stripnum` is the optional number of
+leading slashes to be stripped from each file name found in the patch file
+(default is 1).
+
+`SED`
+: List of space-separated file entries to be transformed with sed (stream
+editor). Sed is run in the `src` directory of the respective application
+project. A sed list entry has the format `<srcfile>;<sedfile>`, where
+`<srcfile>` is the file to be transformed and `<sedfile>` the sed script file.
+
+`BCFG`
+: Build configuration. Can either be `Release` (default) or `Debug`.
+
+`OPT`
+: Compiler optimization level. Can either be `None (-O0)`, `Optimize (-O1)`,
+`Optimize more (-O2)` (default), `Optimize most (-O3)`, `Optimize for size
+(-Os)`.
+
+`CPPSYMS`
+: List of preprocessor symbols (e.g. `MYSYMBOL=1`).
+
+`LIBS`
+: List of library projects the application depends on. The libraries are added
+to the include and library search paths and linked against the application.
+
+`POST_CREATE_TCL`
+: Hook for adding extra Tcl commands after the application project has been
+created. Can be used to set application project configuration parameters (via
+the `configapp` command) not available in the XSDK Makefile.
+
+
+#### Libraries
+
+Software library projects are collections of commonly used functions for your
+applications. Library projects are independent of the hardware platform
+specification.
+
+Library projects are registered by adding their name to the `LIB_PRJS` list.
+They can then be configured by prefixing the corresponding option with their
+name:
+
+    LIB_PRJS += helloworldlib
+    helloworldlib_PROC = psu_cortexa53
+    helloworldlib_BCFG = Debug
+    helloworldlib_SRC = helloworldlib.c libhelloworld.h
+
+The following library project options are available:
+
+`TYPE`
+: Library type. Can be either `static` (default) or `shared`. Type `shared` can
+only be used in combination with operating system type `linux`.
+
+`PROC`
+: Processor type. Can be either `ps7_cortex9`, `microblaze`, `psu_cortexa53` or
+`psu_cortexr5`. Required.
+
+`OS`
+: Operating system type. Can be either `standalone` (default) or `linux`. Type
+`linux` can only be used in combination with library type `shared`.
+
+`LANG`
+: Programming language. Can be either `c` (default) or `c++`.
+
+`ARCH`
+: Processor architecture. Can be 32 or 64 bit. Valid only for processors
+supporting multiple architectures (e.g. A53).
+
+`SRC`
+: List of space-separated source files to be added to the library. For each
+list entry, a symlink in the `src` directory of the respective library project
+will be created that points towards the corresponding source file.
+
+`BCFG`
+: Build configuration. Can either be `Release` (default) or `Debug`.
+
+`OPT`
+: Compiler optimization level. Can either be `None (-O0)`, `Optimize (-O1)`,
+`Optimize more (-O2)` (default), `Optimize most (-O3)`, `Optimize for size
+(-Os)`.
+
+`CPPSYMS`
+: List of preprocessor symbols (e.g. `MYSYMBOL=1`).
+
+`POST_CREATE_TCL`
+: Hook for adding extra Tcl commands after the library project has been
+created. Can be used to set library project configuration parameters (via
+the `configapp` command) not available in the XSDK Makefile.
+
+Since XSDK does not support building Linux apps, the combination of library
+type `shared` and operating system type `linux` is not officially supported by
+the XSDK Makefile.
+
+
+#### Bootgen
+
+Bootgen is a Xilinx tool that merges build artifacts into a boot image
+according to a Boot Image Format (BIF) file. The XSDK Makefile can generate BIF
+files and invoke Bootgen subsequently.
+
+Bootgen projects are registered by adding their name to the `BOOTGEN_PRJS`
+list. They can then be configured by prefixing the corresponding option with
+their name:
+
+    BOOTGEN_PRJS += bootbin
+    bootbin_BIF_ARCH = zynqmp
+
+The following Bootgen project options are available:
+
+`BIF_ARCH`
+: Device architecture. Run `bootgen` and see description of `-arch` option for
+a list of supported architectures.
+
+`BIF_ARGS_EXTRA`
+: Add additional Bootgen arguments for special operations like key generation.
+
+`NO_OUTPUT`
+: If `yes`', do not write a boot image file. Required for certain operations
+like key generation.
+
+`FLASH_TYPE`
+: Flash memory type. Run `program_flash` and see description of option
+`-flash_type` to get a list of supported memory types. Only needed for `flash`
+target (see section "Usage").
+
+`FLASH_FSBL`
+: FSBL used for flashing. Only needed for `flash` target (see section "Usage").
+
+`FLASH_OFF`
+: Offset within the flash memory at which the image should be written. Only
+needed for `flash` target (see section "Usage").
+
+BIF attributes are then registered by adding their name to the `BIF_ATTRS`
+list. They can then be configured by prefixing the `BIF_ATTR` and `BIF_FILE`
+variables with the Bootgen project name and BIF attribute name:
+
+    bootbin_BIF_ATTRS = fsbl helloworld
+    bootbin_fsbl_BIF_ATTR = bootloader, destination_cpu=a53-0
+    bootbin_fsbl_BIF_FILE = fsbl/$(fsbl_BCFG)/fsbl.elf
+    bootbin_helloworld_BIF_ATTR = destination_cpu=a53-0
+    bootbin_helloworld_BIF_FILE = helloworld/$(helloworld_BCFG)/helloworld.elf
+
+This example is translated to the following BIF file:
+
+    bootbin:
+    {
+        [bootloader, destination_cpu=a53-0] fsbl/Release/fsbl.elf
+        [destination_cpu=a53-0] helloworld/Debug/helloworld.elf
+    }
+
+Prerequisites to all `BIF_FILE`s are added to the corresponding BIF generation
+rules. If, however, the concerning file is created instead of consumed by
+Bootgen (e.g. key generation) or is not a file at all, one must set the
+`BIF_FILE_NO_DEP` variable to `yes`. For example:
+
+    ...
+    generate_pem_BIF_ARGS_EXTRA = -p zu9eg -generate_keys pem
+    ...
+    generate_pem_pskfile_BIF_ATTR = pskfile
+    generate_pem_pskfile_BIF_FILE = generate_pem/psk0.pem
+    generate_pem_pskfile_BIF_FILE_NO_DEP = yes
+    ...
+
+The file name of a bitstream depends on the Vivado design and is often not
+known before the HDF has been extracted. In these cases, by convention, one
+should point the corresponding `BIF_FILE` option to a variable named like
+`BIT`:
+
+    bootbin_bit_BIF_ATTR = destination_device=pl
+    bootbin_bit_BIF_FILE = $(BIT)
+
+The `BIT` variable must then be provided on invocation:
+
+    $ make HDF=<path-to-your-hdf> BIT=hw/<bitstream>.bit
+
+Optionally, one can provide a default as well:
+
+    BIT ?= hw/design_1_wrapper.bit
+
+
+### Setup
+
+Create a symlink named `Makefile` to the `xsdk.mk` file:
+
+    $ ln -s <path-to-your-psmake-repo>/xsdk.mk Makefile
+
+Add the `build` directory to your `.gitignore`.
+
+By default, the XSDK Makefile looks for the build configuration in
+`./default.mk`. If you choose a different file name (or like to have multiple
+build configurations), you can specify the path with the `CFG` variable.
+
+Write your build configuration as documented in section "Makefile syntax".
+Instead of writing the build configuration from scratch, you can also copy
+`templates/default.mk` into your working directory.
+
+
+### Usage
+
+Import a HDF and build all projects by executing:
+
+    $ make HDF=<path-to-your-hdf>
+
+The XSDK Makefile creates a new XSDK workspace as a subfolder in directory
+`build` named `<cfg-file-name>_<date>-<time>_<git-commit-id>`. A new XSDK
+workspace is created on each invocation. If you would like to run the XSDK
+Makefile on a specific workspace instead of creating a new one, you can use the
+`O` variable:
+
+    $ make O=build/<cfg-file-name>_<date>-<time>_<git-commit-id>
+
+The XSDK Makefile dynamically creates targets according to the build
+configuration. Each BSP, application project and Bootgen project is assigned a
+build target with the same name. Additionally each BSP and application project
+feature a `clean` and `distclean` target separated by `_`.  In order to e.g.
+clean the application project `helloworld`, one would execute:
+
+    $ make helloworld_clean
+
+Bootgen projects come with a `flash` target to write the boot image onto a
+board via JTAG. In order to e.g. flash the Bootgen project `bootbin`, one would
+execute:
+
+    $ make bootbin_flash HW_SERVER_URL=<hw-server-url>
+
+In addition, the following generic Makefile targets are available:
+
+`hw`
+: Build the hardware platform specification. You must provide a HDF via the
+`HDF` variable.
+
+`hw_distclean`
+: Clean the hardware platform specification.
+
+`generate`
+: Generate all projects.
+
+`build` (default)
+: Build all projects.
+
+`metalog`
+: Show meta log.
+
+`sdklog`
+: Show XSDK log.
+
+`xsdk`
+: Run XSDK.
+
+`xsct`
+: Run XSCT.
+
+`clean`
+: Clean all projects.
+
+`distclean`
+: Remove workspace.
+
+
+### Extending
+
+The build configuration file can be extended with standard Makefile targets for
+e.g. uploading and running build artifacts via JTAG.
+
+
+## Vitis Makefile
+
+The Vitis Makefile provides a declarative wrapper around the Xilinx Software
+Command-Line Tool (XSCT) and Bootgen to streamline the build of Xilinx Vitis
+projects.
+
+
+### Supported Platforms
+
+Vitis is supported in v2020.1. So far, there is a focus on the previous XSDK
+use cases; while SDAccel/SDSoC use cases might work as well, they are not
+supported yet. The Makefile should run on all underlying Linux OSs supported by
+Vitis, but not Windows. However, testing is only conducted on Ubuntu 18.04 LTS
+(Bionic Beaver) as of now.
+
+### Known Issues
+
+- Due to a bug in the Vitis Tcl API, when building an application the
+  corresponding domain is always rebuild as well. It is therefore recommended
+  to build applications in the Vitis GUI once the workspace has been created.
+
+
+### Build Configuration Syntax
+
+The Vitis Makefile is configured via a custom Makefile syntax as documented in
+the following sections.
+
+
+#### Repositories
+
+A software repository is a directory that holds third-party software
+components, as well as custom drivers, libraries, and operating systems. You
+can register repositories in the workspace by adding the respective path to the
+`REPOS` variable. In addition, you can also register existing platforms by
+adding the respective path to the `PLATS` variable.
+
+
+#### Platform
+
+The Platform captures all the information from a hardware design that is
+required to write, debug and deploy applications for that hardware. In the
+Vitis Makefile, there is exactly one platform called `plat` by default [^1].
+The platform is either derived from
+
+- a hardware description file (XSA)
+- an existing platform via the corresponding XPFM file.
+
+See section "Usage" on how to import one of these artifacts during build.
+
+[^1]: The platform name can be changed with the `PLAT_PRJ` variable if
+      necessary.
+
+
+#### Domains (BSP)
+
+A Domain or Board Support Package (BSP) is a collection of libraries and
+drivers that form the basis of software applications (see section
+"Applications"). There can be only one domain for each processor instance (i.e.
+core).
+
+Domains are registered by adding their name to the `DOMAIN_PRJS` list. They can
+then be configured by prefixing the corresponding option with their name:
+
+    DOMAIN_PRJS += fsbl_bsp
+    fsbl_bsp_PROC = psu_cortexa53_0
+    fsbl_bsp_IS_FSBL = yes
+    fsbl_bsp_LIBS = xilffs xilsecure xilpm
+    fsbl_bsp_POST_CREATE_TCL = configbsp -bsp fsbl_bsp use_strfunc 1
+
+    DOMAIN_PRJS += gen_bsp
+    gen_bsp_PROC = psu_cortexa53_0
+    gen_bsp_EXTRA_CFLAGS = -g -Wall -Wextra -Os
+    gen_bsp_STDOUT = psu_uart_1
+
+The following domain options are available:
+
+`OS`
+: Operating system type. Optional, defaults to `standalone`. Run `repo -os` in
+XSCT to get a list of all OSs.
+
+`PROC`
+: Processor instance. Run `toolchain` in XSCT to get a list of supported
+processor types.
+
+`IS_FSBL`
+: If `yes`, apply non-default BSP settings for FSBL.
+
+`EXTRA_CFLAGS`
+: Additional compiler flags (default `-g -Wall -Wextra`). The default
+optimization level of `-O2` can be overriden with this variable.
+
+`STDIN`
+: Select UART for standard input.
+
+`STDOUT`
+: Select UART for standard output.
+
+`LIBS`
+: List of libraries to be added to the domain. Run `repo -lib` in XSCT to get a
+list of available libraries.
+
+`POST_CREATE_TCL`
+: Hook for adding extra Tcl commands after the domain has been created. Can be
+used to configure BSP settings (via the `configbsp` command) not available in
+the Vitis Makefile.
+
+
+#### Applications
+
+Application projects are your final application containers. They can
+either be derived from a template or contain your own source files. Each
+application project must be linked to exactly one Domain (BSP).
+
+Application projects are registered by adding their name to the `APP_PRJS`
+list. They can then be configured by prefixing the corresponding option with
+their name:
+
+    APP_PRJS += fsbl
+    fsbl_TMPL = Zynq MP FSBL
+    fsbl_DOMAIN = fsbl_bsp
+    fsbl_CPPSYMS = FSBL_DEBUG_DETAILED
+
+    APP_PRJS += helloworld
+    helloworld_TMPL = Hello World
+    helloworld_DOMAIN = gen_bsp
+    helloworld_BCFG = Debug
+    helloworld_PATCH = helloworld.patch
+    helloworld_SED = platform.c;baud_rate.sed
+
+The following application project options are available:
+
+`TMPL`
+: Name of the template to base the application project on. Run `repo -apps` in
+XSCT to get a list of available application templates.
+
+`PROC`
+: Processor instance. Run `toolchain` in XSCT to get a list of supported
+processor types.
+
+`DOMAIN`
+: Reference to domain (BSP). Required.
+
+`PLAT`
+: Reference to platform. Use this to base the application on a different
+platform than the default `plat`. The platform must be available in the
+platform repository; see section "Repositories". Mutually exclusive with `HW`
+option.
+
+`HW`
+: Path to hardware definition file (XSA) or platform file (XPFM). Use this to
+base the application on a hardware platform file instead of the `plat`
+platform.  Mutually exclusive with `PLAT`.
+
+`SRC`
+: List of space-separated source files or directories to be added to the
+application. For each list entry, a link entry in the application project to
+the absolute path of the respective source file or directory is created.
+
+`PATCH`
+: List of space-separated patch file entries. Patches are applied in the base
+directory of the respective application project. A patch file list entry has
+the format `<patchfile>[;stripnum]`, where `stripnum` is the optional number of
+leading slashes to be stripped from each file name found in the patch file
+(default is 1).
+
+`SED`
+: List of space-separated file entries to be transformed with sed (stream
+editor). Sed is run in the base directory of the respective application
+project. A sed list entry has the format `<srcfile>;<sedfile>`, where
+`<srcfile>` is the file to be transformed and `<sedfile>` the sed script file.
+
+`BCFG`
+: Build configuration. Can either be `Release` (default) or `Debug`.
+
+`OPT`
+: Compiler optimization level. Can either be `None (-O0)`, `Optimize (-O1)`,
+`Optimize more (-O2)` (default), `Optimize most (-O3)`, `Optimize for size
+(-Os)`.
+
+`CPPSYMS`
+: List of preprocessor symbols (e.g. `MYSYMBOL=1`).
+
+`POST_CREATE_TCL`
+: Hook for adding extra Tcl commands after the application project has been
+created. Can be used to set application project configuration parameters (via
+the `configapp` command) not available in the Vitis Makefile.
+
+
+#### Bootgen
+
+Bootgen is a Xilinx tool that merges build artifacts into a boot image
+according to a Boot Image Format (BIF) file. The Vitis Makefile can generate
+BIF files and invoke Bootgen subsequently.
+
+Bootgen projects are registered by adding their name to the `BOOTGEN_PRJS`
+list. They can then be configured by prefixing the corresponding option with
+their name:
+
+    BOOTGEN_PRJS += bootbin
+    bootbin_BIF_ARCH = zynqmp
+
+The following Bootgen project options are available:
+
+`BIF_ARCH`
+: Device architecture. Run `bootgen` and see description of `-arch` option for
+a list of supported architectures.
+
+`BIF_ARGS_EXTRA`
+: Add additional Bootgen arguments for special operations like key generation.
+
+`NO_OUTPUT`
+: If `yes`', do not write a boot image file. Required for certain operations
+like key generation.
+
+`FLASH_TYPE`
+: Flash memory type. Run `program_flash` and see description of option
+`-flash_type` to get a list of supported memory types. Only needed for `flash`
+target (see section "Usage").
+
+`FLASH_FSBL`
+: FSBL used for flashing. Only needed for `flash` target (see section "Usage").
+
+`FLASH_OFF`
+: Offset within the flash memory at which the image should be written. Only
+needed for `flash` target (see section "Usage").
+
+BIF attributes are then registered by adding their name to the `BIF_ATTRS`
+list. They can then be configured by prefixing the `BIF_ATTR` and `BIF_FILE`
+variables with the Bootgen project name and BIF attribute name:
+
+    bootbin_BIF_ATTRS = fsbl helloworld
+    bootbin_fsbl_BIF_ATTR = bootloader, destination_cpu=a53-0
+    bootbin_fsbl_BIF_FILE = fsbl/$(fsbl_BCFG)/fsbl.elf
+    bootbin_helloworld_BIF_ATTR = destination_cpu=a53-0
+    bootbin_helloworld_BIF_FILE = helloworld/$(helloworld_BCFG)/helloworld.elf
+
+This example is translated to the following BIF file:
+
+    bootbin:
+    {
+        [bootloader, destination_cpu=a53-0] fsbl/Release/fsbl.elf
+        [destination_cpu=a53-0] helloworld/Debug/helloworld.elf
+    }
+
+Prerequisites to all `BIF_FILE`s are added to the corresponding BIF generation
+rules. If, however, the concerning file is created instead of consumed by
+Bootgen (e.g. key generation) or is not a file at all, one must set the
+`BIF_FILE_NO_DEP` variable to `yes`. For example:
+
+    ...
+    generate_pem_BIF_ARGS_EXTRA = -p zu9eg -generate_keys pem
+    ...
+    generate_pem_pskfile_BIF_ATTR = pskfile
+    generate_pem_pskfile_BIF_FILE = generate_pem/psk0.pem
+    generate_pem_pskfile_BIF_FILE_NO_DEP = yes
+    ...
+
+The file name of a bitstream depends on the Vivado design and is often not
+known before the HDF has been extracted. In these cases, by convention, one
+should point the corresponding `BIF_FILE` option to a variable named like
+`BIT`:
+
+    bootbin_bit_BIF_ATTR = destination_device=pl
+    bootbin_bit_BIF_FILE = $(BIT)
+
+The `BIT` variable must then be provided on invocation:
+
+    $ make HDF=<path-to-your-hdf> BIT=hw/<bitstream>.bit
+
+Optionally, one can provide a default as well:
+
+    BIT ?= hw/design_1_wrapper.bit
+
+
+### Setup
+
+Create a symlink named `Makefile` to the `vitis.mk` file:
+
+    $ ln -s <path-to-your-psmake-repo>/vitis.mk Makefile
+
+Add the `build` directory to your `.gitignore`.
+
+By default, the Vitis Makefile looks for the build configuration in
+`./default.mk`. If you choose a different file name (or like to have multiple
+build configurations), you can specify the path with the `CFG` variable.
+
+Write your build configuration as documented in section "Makefile syntax".
+Instead of writing the build configuration from scratch, you can also copy
+`templates/vitis/default.mk` into your working directory.
+
+
+### Usage
+
+Import either a hardware description file (XSA) by executing
+
+    $ make HDF=<path-to-.xsa-file>
+
+or an existing platform via an XPFM file:
+
+    $ make XPFM=<path-to-.xpfm-file>
+
+Without specyfing a further target, all projects will be built.
+
+The Vitis Makefile creates a new Vitis workspace as a subfolder in directory
+`build` named `<cfg-file-name>_<date>-<time>_<git-commit-id>`. A new Vitis
+workspace is created on each invocation. If you would like to run the Vitis
+Makefile on a specific workspace instead of creating a new one, you can use the
+`O` variable:
+
+    $ make O=build/<cfg-file-name>_<date>-<time>_<git-commit-id>
+
+The Vitis Makefile dynamically creates Makefile targets according to the build
+configuration. Each domain, application project and Bootgen project is assigned
+a build target with the same name. Additionally each domain and application
+project feature a `clean` and `distclean` target separated by `_`.  In order to
+e.g. clean the application project `helloworld`, one would execute:
+
+    $ make helloworld_clean
+
+Bootgen projects come with a `flash` target to write the boot image onto a
+board via JTAG. In order to e.g. flash the Bootgen project `bootbin`, one would
+execute:
+
+    $ make bootbin_flash HW_SERVER_URL=<hw-server-url>
+
+In addition, the following generic Makefile targets are available:
+
+`plat`
+: Build the platform project. Either provide a path to a hardware description
+file (XSA) via the `HDF` variable, or to an existing platform file (XPFM) via
+the `XPFM` variable.
+
+`plat_distclean`
+: Clean the platform project.
+
+`generate`
+: Generate all projects.
+
+`build` (default)
+: Build all projects.
+
+`metalog`
+: Show meta log.
+
+`vitislog`
+: Show Vitis log.
+
+`vitis`
+: Run Vitis.
+
+`xsct`
+: Run XSCT.
+
+`clean`
+: Clean all projects.
+
+`distclean`
+: Remove workspace.
+
+
+### Extending
+
+The build configuration file can be extended with standard Makefile targets for
+e.g. uploading and running build artifacts via JTAG.
+
+
+## License
+
+Licensed under the [Apache License, Version 2.0](http://www.apache.org/licenses/LICENSE-2.0).
diff --git a/fpga/lib/psmake/common.mk b/fpga/lib/psmake/common.mk
new file mode 100644
index 000000000..e6734a6d9
--- /dev/null
+++ b/fpga/lib/psmake/common.mk
@@ -0,0 +1,195 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2018-2019 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : common.mk
+##  Initial Author : Stefan Wiehler <stefan.wiehler@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : XSDK/Vitis common functionality
+##
+##                   Uses: bootgen cat git mkdir patch rm sed touch
+##
+################################################################################
+
+
+################################################################################
+# VCS
+
+# user arguments
+VCS_SKIP ?=
+
+# get version control information
+ifeq ($(VCS_SKIP),)
+VCS_HEAD := $(shell git rev-parse --verify --short HEAD 2>/dev/null)
+endif
+ifneq ($(VCS_HEAD),)
+VCS_DIRTY := $(shell git diff-index --name-only HEAD | head -n 1)
+VCS_VER := _g$(VCS_HEAD)$(patsubst %,-dirty,$(VCS_DIRTY))
+else
+VCS_VER :=
+endif
+
+# get build time stamp
+BSTAMP := $(shell date +%Y%m%d-%H%M%S)
+
+# user arguments, usually provided on command line
+#  container for build directories (= xsdk workspaces)
+CNTR ?= build
+#  build directory name
+BLDN ?= $(CFG)_$(BSTAMP)$(VCS_VER)
+#  relative path to build directory
+O ?= $(CNTR)/$(BLDN)
+
+###############################################################################
+# Repositories
+
+REPOS ?=
+
+ifneq ($(strip $(REPOS)),)
+__REPOS_CCMD = $(foreach REPO,$(REPOS), \
+	repo -set {$(REPO)};)
+endif
+
+$(O)/.metadata/repos.stamp:
+ifneq ($(strip $(REPOS)),)
+	$(XSCT) -eval 'setws {$(O)}; $(__REPOS_CCMD)'
+else
+	mkdir -p $(O)/.metadata/
+endif
+	touch $@
+
+###############################################################################
+# Source symlinking, patch and sed rules
+
+# arg1: app name
+# arg2: src file name, scheme <srcfile>
+define symlink-src
+rm -f $(O)/$(1)/src/$$(notdir $(2)) && \
+ln -s ../../../../$(2) $(O)/$(1)/src/$$(notdir $(2)) &&
+endef
+
+# arg1: app name
+# arg2: patch file name, scheme <patchfile>[;<stripnum>]
+define patch-src
+patch -d $(O)/$(1)/ -p$$(subst ,1,$$(word 2,$$(subst ;, ,$(2)))) \
+	<$$(word 1,$$(subst ;, ,$(2))) &&
+endef
+
+# arg1: app name
+# arg2: src file name to edit and sed command file, scheme <srcfile>;<sedfile>
+define sed-src
+sed -i -f $$(lastword $$(subst ;, ,$(2))) \
+	$(O)/$(1)/$$(firstword $$(subst ;, ,$(2))) &&
+endef
+
+###############################################################################
+# Bootgen projects
+
+BOOTGEN ?= bootgen
+
+BOOTGEN_PRJS ?=
+
+# arg1: BIF file name
+# arg2: BIF attribute
+define gen-bif-attr
+\t[$$($(1)_$(2)_BIF_ATTR)] $$($(1)_$(2)_BIF_FILE)\n
+endef
+
+# arg1: Bootgen project
+# arg2: BIF attribute
+define gen-bootgen-dep
+$$(if $$(findstring yes,$$($(1)_$(2)_BIF_FILE_NO_DEP)),,\
+	$(O)/$$($(1)_$(2)_BIF_FILE))
+endef
+
+define gen-bif-rule
+$(1)_FLASH_TYPE ?=
+$(1)_FLASH_FSBL ?=
+$(1)_FLASH_OFF ?= 0
+$(1)_BOOTGEN_DEP = $$(foreach BIF_ATTR,$$($(1)_BIF_ATTRS),\
+	$(call gen-bootgen-dep,$(1),$$(BIF_ATTR)))
+
+$(O)/$(1)/$(1).bif: $$($(1)_BOOTGEN_DEP)
+	mkdir -p $(O)/$(1)
+	printf '$(1):\n{\n' > $(O)/$(1)/$(1).bif
+ifneq ($$(strip $$($(1)_BIF_ATTRS)),)
+	printf '$$(foreach BIF_ATTR,$$($(1)_BIF_ATTRS), \
+		$(call gen-bif-attr,$(1),$$(BIF_ATTR)))' \
+		>> $(O)/$(1)/$(1).bif
+endif
+	printf '}\n' >> $(O)/$(1)/$(1).bif
+
+$(O)/$(1)/BOOT.BIN: $(O)/$(1)/$(1).bif
+ifeq ($$($(1)_BIF_NO_OUTPUT),yes)
+	cd $(O) && $(BOOTGEN) -arch $$($(1)_BIF_ARCH) -image $(1)/$(1).bif \
+		$$($(1)_BIF_ARGS_EXTRA)
+else
+	cd $(O) && $(BOOTGEN) -arch $$($(1)_BIF_ARCH) -image $(1)/$(1).bif \
+		-o $(1)/BOOT.BIN -w $$($(1)_BIF_ARGS_EXTRA)
+endif
+
+GEN_BOOTGEN_DEP += $(O)/$(1)/$(1).bif
+BLD_BOOTGEN_DEP += $(O)/$(1)/BOOT.BIN
+
+# NOTE: Target $(1)_flash is written for QSPI flashing in mind - other types
+#       might need more or other arguments!
+$(1)_flash: $(O)/$(1)/BOOT.BIN
+	cd $(O) && \
+	program_flash \
+		-flash_type $$($(1)_FLASH_TYPE) \
+		-fsbl $$($(1)_FLASH_FSBL) \
+		-f $(1)/BOOT.BIN -offset $$($(1)_FLASH_OFF) \
+		-verify \
+		-cable type xilinx_tcf url $(HW_SERVER_URL)
+.PHONY: $(1)_flash
+
+# shortcut to build bootgen project, "make <bootgen>"
+$(1): $(O)/$(1)/BOOT.BIN
+.PHONY: $(1)
+
+$(1)_clean:
+	find $(O)/$(1)/* -not -name $(1).bif -delete
+.PHONY: $(1)_clean
+
+$(1)_distclean:
+	rm -fr $(O)/$(1)
+.PHONY: $(1)_distclean
+endef
+
+###############################################################################
+# Common targets
+
+# show logs
+metalog:
+	cat $(O)/.metadata/.log
+sdklog:
+	cat $(O)/SDK.log
+.PHONY: sdklog metalog
+
+# remove workspace
+distclean:
+	rm -fr $(O)
+.PHONY: distclean
+
+# open XSCT in interactive mode
+xsct:
+	$(XSCT) -interactive -eval 'setws $(O)'
+.PHONY: xsct
diff --git a/fpga/lib/psmake/examples/vitis/baud_rate.sed b/fpga/lib/psmake/examples/vitis/baud_rate.sed
new file mode 100644
index 000000000..235cb0fc4
--- /dev/null
+++ b/fpga/lib/psmake/examples/vitis/baud_rate.sed
@@ -0,0 +1 @@
+s/UART_BAUD 9600/UART_BAUD 115200/
diff --git a/fpga/lib/psmake/examples/vitis/default.mk b/fpga/lib/psmake/examples/vitis/default.mk
new file mode 100644
index 000000000..6e58e2580
--- /dev/null
+++ b/fpga/lib/psmake/examples/vitis/default.mk
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2019-2020 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : default.mk
+##  Initial Author : Stefan Wiehler <stefan.wiehler@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : Example for Vitis Makefile
+##
+##                   Build with default fixed platform for ZC102:
+##
+##                       $ make HW_PLAT=zcu102
+##
+##                   Also provide PLATS variable if default does not fit.
+##
+################################################################################
+
+# FSBL
+
+DOMAIN_PRJS += fsbl_bsp
+fsbl_bsp_PROC = psu_cortexa53_0
+fsbl_bsp_IS_FSBL = yes
+fsbl_bsp_LIBS = xilffs xilsecure xilpm
+fsbl_bsp_POST_CREATE_TCL = bsp config use_strfunc 1
+
+APP_PRJS += fsbl
+fsbl_TMPL = Zynq MP FSBL
+fsbl_DOMAIN = fsbl_bsp
+fsbl_CPPSYMS = FSBL_DEBUG_DETAILED
+
+################################################################################
+# Hello World
+
+DOMAIN_PRJS += gen_bsp
+gen_bsp_PROC = psu_cortexa53_0
+gen_bsp_EXTRA_CFLAGS = -g -Wall -Wextra -Os
+gen_bsp_STDOUT = psu_uart_1
+
+APP_PRJS += helloworld
+helloworld_TMPL = Hello World
+helloworld_DOMAIN = gen_bsp
+helloworld_BCFG = Debug
+helloworld_PATCH = helloworld.patch
+helloworld_SED = platform.c;baud_rate.sed
+
+APP_PRJS += example_app
+example_app_TMPL = Empty Application
+example_app_DOMAIN = gen_bsp
+example_app_BCFG = Debug
+example_app_SRC = example_app
+
+################################################################################
+# Boot image
+
+BOOTGEN_PRJS += bootbin
+
+bootbin_BIF_ARCH = zynqmp
+bootbin_BIF_ATTRS = fsbl helloworld
+bootbin_fsbl_BIF_ATTR = bootloader, destination_cpu=a53-0
+bootbin_fsbl_BIF_FILE = fsbl/$(fsbl_BCFG)/fsbl.elf
+bootbin_helloworld_BIF_ATTR = destination_cpu=a53-0
+bootbin_helloworld_BIF_FILE = helloworld/$(helloworld_BCFG)/helloworld.elf
+
+################################################################################
+# Key generation
+
+BOOTGEN_PRJS += generate_pem
+
+generate_pem_BIF_ARCH = zynqmp
+generate_pem_BIF_NO_OUTPUT = yes
+generate_pem_BIF_ARGS_EXTRA = -p zu9eg -generate_keys pem
+generate_pem_BIF_ATTRS = pskfile sskfile fsbl
+generate_pem_pskfile_BIF_ATTR = pskfile
+generate_pem_pskfile_BIF_FILE = generate_pem/psk0.pem
+generate_pem_pskfile_BIF_FILE_NO_DEP = yes
+generate_pem_sskfile_BIF_ATTR = sskfile
+generate_pem_sskfile_BIF_FILE = generate_pem/ssk0.pem
+generate_pem_sskfile_BIF_FILE_NO_DEP = yes
+generate_pem_fsbl_BIF_ATTR = bootloader, destination_cpu=a53-0
+generate_pem_fsbl_BIF_FILE = fsbl/$(fsbl_BCFG)/fsbl.elf
diff --git a/fpga/lib/psmake/examples/vitis/example_app/helloworld.c b/fpga/lib/psmake/examples/vitis/example_app/helloworld.c
new file mode 100644
index 000000000..f773f96dd
--- /dev/null
+++ b/fpga/lib/psmake/examples/vitis/example_app/helloworld.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*
+ * helloworld.c: simple test application
+ *
+ * This application configures UART 16550 to baud rate 9600.
+ * PS7 UART (Zynq) is not initialized by this application, since
+ * bootrom/bsp configures it to baud rate 115200
+ *
+ * ------------------------------------------------
+ * | UART TYPE   BAUD RATE                        |
+ * ------------------------------------------------
+ *   uartns550   9600
+ *   uartlite    Configurable only in HW design
+ *   ps7_uart    115200 (configured by bootrom/bsp)
+ */
+
+#include <stdio.h>
+#include "platform.h"
+#include "xil_printf.h"
+
+
+int main()
+{
+    init_platform();
+
+    print("Hello World Example Application\n\r");
+    print("Successfully ran Hello World application");
+    cleanup_platform();
+    return 0;
+}
diff --git a/fpga/lib/psmake/examples/vitis/example_app/platform.c b/fpga/lib/psmake/examples/vitis/example_app/platform.c
new file mode 100644
index 000000000..d8c88f5d0
--- /dev/null
+++ b/fpga/lib/psmake/examples/vitis/example_app/platform.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_cache.h"
+
+#include "platform_config.h"
+
+/*
+ * Uncomment one of the following two lines, depending on the target,
+ * if ps7/psu init source files are added in the source directory for
+ * compiling example outside of SDK.
+ */
+/*#include "ps7_init.h"*/
+/*#include "psu_init.h"*/
+
+#ifdef STDOUT_IS_16550
+ #include "xuartns550_l.h"
+
+ #define UART_BAUD 115200
+#endif
+
+void
+enable_caches()
+{
+#ifdef __PPC__
+    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
+    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
+#elif __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheEnable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheEnable();
+#endif
+#endif
+}
+
+void
+disable_caches()
+{
+#ifdef __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheDisable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheDisable();
+#endif
+#endif
+}
+
+void
+init_uart()
+{
+#ifdef STDOUT_IS_16550
+    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
+    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
+#endif
+    /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
+}
+
+void
+init_platform()
+{
+    /*
+     * If you want to run this example outside of SDK,
+     * uncomment one of the following two lines and also #include "ps7_init.h"
+     * or #include "ps7_init.h" at the top, depending on the target.
+     * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
+     * along with this example source files for compilation.
+     */
+    /* ps7_init();*/
+    /* psu_init();*/
+    enable_caches();
+    init_uart();
+}
+
+void
+cleanup_platform()
+{
+    disable_caches();
+}
diff --git a/fpga/lib/psmake/examples/vitis/example_app/platform.h b/fpga/lib/psmake/examples/vitis/example_app/platform.h
new file mode 100644
index 000000000..e273e3718
--- /dev/null
+++ b/fpga/lib/psmake/examples/vitis/example_app/platform.h
@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef __PLATFORM_H_
+#define __PLATFORM_H_
+
+#include "platform_config.h"
+
+void init_platform();
+void cleanup_platform();
+
+#endif
diff --git a/fpga/lib/psmake/examples/vitis/example_app/platform_config.h b/fpga/lib/psmake/examples/vitis/example_app/platform_config.h
new file mode 100644
index 000000000..30d16a1a6
--- /dev/null
+++ b/fpga/lib/psmake/examples/vitis/example_app/platform_config.h
@@ -0,0 +1,6 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+#define STDOUT_IS_PSU_UART
+#define UART_DEVICE_ID 1
+#endif
diff --git a/fpga/lib/psmake/examples/vitis/helloworld.patch b/fpga/lib/psmake/examples/vitis/helloworld.patch
new file mode 100644
index 000000000..64e3d5a93
--- /dev/null
+++ b/fpga/lib/psmake/examples/vitis/helloworld.patch
@@ -0,0 +1,11 @@
+--- a/helloworld.c	2020-09-01 11:44:33.249528296 +0200
++++ b/helloworld.c~	2020-09-01 12:02:34.945994392 +0200
+@@ -54,7 +54,7 @@
+ {
+     init_platform();
+ 
+-    print("Hello World\n\r");
++    print("Hello World Vitis Makefile\n\r");
+     print("Successfully ran Hello World application");
+     cleanup_platform();
+     return 0;
diff --git a/fpga/lib/psmake/examples/xsdk/baud_rate.sed b/fpga/lib/psmake/examples/xsdk/baud_rate.sed
new file mode 100644
index 000000000..235cb0fc4
--- /dev/null
+++ b/fpga/lib/psmake/examples/xsdk/baud_rate.sed
@@ -0,0 +1 @@
+s/UART_BAUD 9600/UART_BAUD 115200/
diff --git a/fpga/lib/psmake/examples/xsdk/default.mk b/fpga/lib/psmake/examples/xsdk/default.mk
new file mode 100644
index 000000000..79f7b05a5
--- /dev/null
+++ b/fpga/lib/psmake/examples/xsdk/default.mk
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2019 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : default.mk
+##  Initial Author : Stefan Wiehler <stefan.wiehler@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : Example for XSDK Makefile
+##
+################################################################################
+
+# Defaults
+
+BIT ?= hw/design_1_wrapper.bit
+
+################################################################################
+# FSBL
+
+BSP_PRJS += fsbl_bsp
+fsbl_bsp_PROC = psu_cortexa53_0
+fsbl_bsp_IS_FSBL = yes
+fsbl_bsp_LIBS = xilffs xilsecure xilpm
+fsbl_bsp_POST_CREATE_TCL = configbsp -bsp fsbl_bsp use_strfunc 1
+
+APP_PRJS += fsbl
+fsbl_TMPL = Zynq MP FSBL
+fsbl_BSP = fsbl_bsp
+fsbl_CPPSYMS = FSBL_DEBUG_DETAILED
+
+################################################################################
+# Hello World
+
+BSP_PRJS += gen_bsp
+gen_bsp_PROC = psu_cortexa53_0
+gen_bsp_EXTRA_CFLAGS = -g -Wall -Wextra -Os
+gen_bsp_STDOUT = psu_uart_1
+
+APP_PRJS += helloworld
+helloworld_TMPL = Hello World
+helloworld_BSP = gen_bsp
+helloworld_BCFG = Debug
+helloworld_PATCH = helloworld.patch
+helloworld_SED = platform.c;baud_rate.sed
+helloworld_LIBS = helloworldlib
+
+LIB_PRJS += helloworldlib
+helloworldlib_PROC = psu_cortexa53
+helloworldlib_BCFG = Debug
+helloworldlib_SRC = helloworldlib.c helloworldlib.h
+
+################################################################################
+# Boot image
+
+BOOTGEN_PRJS += bootbin
+
+bootbin_BIF_ARCH = zynqmp
+bootbin_BIF_ATTRS = fsbl bit helloworld
+bootbin_fsbl_BIF_ATTR = bootloader, destination_cpu=a53-0
+bootbin_fsbl_BIF_FILE = fsbl/$(fsbl_BCFG)/fsbl.elf
+bootbin_bit_BIF_ATTR = destination_device=pl
+bootbin_bit_BIF_FILE = $(BIT)
+bootbin_helloworld_BIF_ATTR = destination_cpu=a53-0
+bootbin_helloworld_BIF_FILE = helloworld/$(helloworld_BCFG)/helloworld.elf
+
+################################################################################
+# Key generation
+
+BOOTGEN_PRJS += generate_pem
+
+generate_pem_BIF_ARCH = zynqmp
+generate_pem_BIF_NO_OUTPUT = yes
+generate_pem_BIF_ARGS_EXTRA = -p zu9eg -generate_keys pem
+generate_pem_BIF_ATTRS = pskfile sskfile fsbl
+generate_pem_pskfile_BIF_ATTR = pskfile
+generate_pem_pskfile_BIF_FILE = generate_pem/psk0.pem
+generate_pem_pskfile_BIF_FILE_NO_DEP = yes
+generate_pem_sskfile_BIF_ATTR = sskfile
+generate_pem_sskfile_BIF_FILE = generate_pem/ssk0.pem
+generate_pem_sskfile_BIF_FILE_NO_DEP = yes
+generate_pem_fsbl_BIF_ATTR = bootloader, destination_cpu=a53-0
+generate_pem_fsbl_BIF_FILE = fsbl/$(fsbl_BCFG)/fsbl.elf
diff --git a/fpga/lib/psmake/examples/xsdk/helloworld.patch b/fpga/lib/psmake/examples/xsdk/helloworld.patch
new file mode 100644
index 000000000..a1da62769
--- /dev/null
+++ b/fpga/lib/psmake/examples/xsdk/helloworld.patch
@@ -0,0 +1,18 @@
+--- a/helloworld.c	2020-05-13 11:53:50.934001488 +0200
++++ b/helloworld.c~	2020-05-13 14:19:33.378515155 +0200
+@@ -48,13 +48,14 @@
+ #include <stdio.h>
+ #include "platform.h"
+ #include "xil_printf.h"
++#include "helloworldlib.h"
+ 
+ 
+ int main()
+ {
+     init_platform();
+ 
+-    print("Hello World\n\r");
++    helloworld();
+ 
+     cleanup_platform();
+     return 0;
diff --git a/fpga/lib/psmake/examples/xsdk/helloworldlib.c b/fpga/lib/psmake/examples/xsdk/helloworldlib.c
new file mode 100644
index 000000000..faddbd1af
--- /dev/null
+++ b/fpga/lib/psmake/examples/xsdk/helloworldlib.c
@@ -0,0 +1,6 @@
+#include <stdio.h>
+
+void helloworld(void)
+{
+	printf("Hello World\n\r");
+}
diff --git a/fpga/lib/psmake/examples/xsdk/helloworldlib.h b/fpga/lib/psmake/examples/xsdk/helloworldlib.h
new file mode 100644
index 000000000..3b4595fe7
--- /dev/null
+++ b/fpga/lib/psmake/examples/xsdk/helloworldlib.h
@@ -0,0 +1 @@
+void helloworld(void);
diff --git a/fpga/lib/psmake/petalinux.mk b/fpga/lib/psmake/petalinux.mk
new file mode 100644
index 000000000..e59506384
--- /dev/null
+++ b/fpga/lib/psmake/petalinux.mk
@@ -0,0 +1,344 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2018-2019 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : Makefile
+##  Initial Author : Joachim Foerster
+##                   <joachim.foerster@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : petalinux-* convenience wrapper
+##
+##                   Based on Makefile for PetaLinux by Stefan Wiehler.
+##
+################################################################################
+
+ifeq ($(PETALINUX_VER),)
+$(error PETALINUX_VER is unset. This Makefile must be invoked from within a PetaLinux environment)
+endif
+
+MAKEFILE_PATH = $(dir $(realpath $(firstword $(MAKEFILE_LIST))))
+
+# default target
+all: build
+
+# include Makefile snippet local to project, if one exists
+-include local.mk
+
+# tools
+ifeq ($(shell expr $(subst .,,$(PETALINUX_VER)) ">" 20191),1)
+XSDB ?= $(PETALINUX)/tools/xsct/bin/xsdb
+else
+ifeq ($(shell expr $(subst .,,$(PETALINUX_VER)) "<" 20183),1)
+XSDB ?= $(PETALINUX)/tools/hsm/bin/xsdb
+else
+# for v2018.3 and v2019.1, xsdb is automatically found via $PATH
+XSDB ?= xsdb
+endif
+endif
+
+ifeq ($(shell expr $(subst .,,$(PETALINUX_VER)) ">" 20183),1)
+SILENTCONFIG = --silentconfig
+else
+SILENTCONFIG = --oldconfig
+endif
+
+PLATFORM = $(shell cat project-spec/configs/config | \
+		grep -E '^CONFIG_SYSTEM_(MICROBLAZE|ZYNQ|ZYNQMP)=y$$' | \
+		sed -e 's/^CONFIG_SYSTEM_\(.*\)=y$$/\1/' | \
+		tr [:upper:] [:lower:])
+
+# defaults
+DEF_IMAGEUB = images/linux/image.ub
+SYSTEM_DTB ?= images/linux/system.dtb
+SYSTEM_DTS ?= images/linux/system.dts
+PETALINUX_CONFIG = project-spec/configs/config
+LOCAL_CONF = build/conf/local.conf
+SOURCE_DOWNLOADS = build/downloads
+SOURCE_MIRROR = $(shell awk 'BEGIN { FS = "file://" } /PREMIRRORS =/ { gsub(/ \\n \\/, "", $$2); print $$2 }' build/conf/plnxtool.conf)
+MANIFEST_PATH = $(lastword $(wildcard build/tmp/deploy/licenses/petalinux-image-minimal-*))
+
+# location of imported .hdf/.xsa file
+ifeq ($(HDF),)
+# if user does not specify HDF, select PRJ_HDF from existing .hdf or .xsa file
+PRJ_HDF = $(wildcard project-spec/hw-description/*.hdf project-spec/hw-description/*.xsa)
+else
+# if user specifies HDF, let PRJ_HDF depend on HDF suffix and assume "system" as prefix
+PRJ_HDF = project-spec/hw-description/system$(suffix $(HDF))
+endif
+ifeq ($(PRJ_HDF),)
+$(error missing HDF, run with argument HDF=<path-to-.hdf-or-.xsa-file>)
+endif
+
+# defaults for flash-* targets
+FLASH_TYPE ?= qspi_single
+FSBL_ELF ?= images/linux/zynqmp_fsbl.elf
+BOOT_BIN ?= images/linux/BOOT.BIN
+BOOT_BIN_OFF ?= 0
+KERNEL_IMG ?= $(DEF_IMAGEUB)
+KERNEL_IMG_OFF ?= $(shell echo $$((16 * 1024 * 1024)))
+
+# user arguments
+HDF ?=
+BIT ?=
+FSBL ?=
+ATF ?=
+PMUFW ?=
+UBOOT ?=
+BOOT ?=
+BSP ?=
+BOOT_ARG_EXTRA ?=
+UPDATE_MIRROR ?= 0
+SOURCE_RELEASE ?= source-release
+MANIFESTS ?= manifests
+
+ifneq ($(HDF),)
+TMPHDF ?= build/psmake/tmphdf/$(notdir $(HDF))/$(notdir $(HDF))
+endif
+
+# petalinux-* generic arguments
+ifeq ($(V),1)
+GEN_ARGS = -v
+endif
+# petalinux-package --boot arguments
+ifneq ($(BIT),no)
+BOOT_ARG_FPGA = --fpga
+ifneq ($(BIT),)
+BOOT_ARG_FPGA += $(BIT)
+endif
+endif
+#  no need to specify --fsbl if default is to be used
+BOOT_ARG_FSBL =
+ifneq ($(FSBL),)
+BOOT_ARG_FSBL += --fsbl $(FSBL)
+endif
+#  no need to specify --atf if default is to be used
+BOOT_ARG_ATF =
+ifneq ($(ATF),)
+BOOT_ARG_ATF += --atf $(ATF)
+endif
+#  no need to specify --pmufw if default is to be used
+BOOT_ARG_PMUFW =
+ifneq ($(PMUFW),)
+BOOT_ARG_PMUFW += --pmufw $(PMUFW)
+endif
+BOOT_ARG_UBOOT = --u-boot
+ifneq ($(UBOOT),)
+BOOT_ARG_UBOOT += $(UBOOT)
+endif
+ifneq ($(BOOT),)
+BOOT_ARG_OUT = -o $(BOOT)
+endif
+
+
+###############################################################################
+
+
+define set-update-mirror
+	sed -i 's/CONFIG_YOCTO_BB_NO_NETWORK=y/# CONFIG_YOCTO_BB_NO_NETWORK is not set/' $(PETALINUX_CONFIG)
+	printf 'BB_GENERATE_MIRROR_TARBALLS = "1"' >> $(LOCAL_CONF)
+	petalinux-config $(SILENTCONFIG)
+endef
+
+define reset-update-mirror
+	sed -i 's/# CONFIG_YOCTO_BB_NO_NETWORK is not set/CONFIG_YOCTO_BB_NO_NETWORK=y/' $(PETALINUX_CONFIG)
+	sed -i '/BB_GENERATE_MIRROR_TARBALLS/d' $(LOCAL_CONF)
+	petalinux-config $(SILENTCONFIG)
+endef
+
+# arg1: cmd
+define trap-update-mirror
+sh -c "trap 'trap - SIGINT SIGTERM ERR; \
+	sed -i \"s/# CONFIG_YOCTO_BB_NO_NETWORK is not set/CONFIG_YOCTO_BB_NO_NETWORK=y/\" $(PETALINUX_CONFIG); \
+	sed -i \"/BB_GENERATE_MIRROR_TARBALLS/d\" $(LOCAL_CONF); \
+	petalinux-config $(SILENTCONFIG); \
+	exit 1' SIGINT SIGTERM ERR; $(1)"
+endef
+
+
+define set-source-release
+	printf 'INHERIT += "archiver"\n' >> $(LOCAL_CONF)
+	printf 'ARCHIVER_MODE[src] = "original"\n' >> $(LOCAL_CONF)
+	petalinux-config $(SILENTCONFIG)
+endef
+
+define reset-source-release
+	sed -i '/INHERIT += "archiver"/d' $(LOCAL_CONF)
+	sed -i '/ARCHIVER_MODE\[src\] = "original"/d' $(LOCAL_CONF)
+	petalinux-config $(SILENTCONFIG)
+endef
+
+# arg1: cmd
+define trap-source-release
+sh -c "trap 'trap - SIGINT SIGTERM ERR; \
+	sed -i \"/INHERIT += \\\"archiver\\\"/d\" $(LOCAL_CONF); \
+	sed -i \"/ARCHIVER_MODE\\\[src\\\] = \\\"original\\\"/d\" $(LOCAL_CONF); \
+	petalinux-config $(SILENTCONFIG); \
+	exit 1' SIGINT SIGTERM ERR; $(1)"
+endef
+
+
+###############################################################################
+
+
+FORCE:
+
+
+# force only if "gethdf" is one of the targets
+$(PRJ_HDF): $(HDF) $(subst gethdf,FORCE,$(findstring gethdf,$(MAKECMDGOALS)))
+	mkdir -p $(dir $(TMPHDF))
+	ln -sf $(realpath $(HDF)) $(TMPHDF)
+	petalinux-config $(GEN_ARGS) --get-hw-description $(dir $(TMPHDF)) $(SILENTCONFIG)
+
+gethdf: $(PRJ_HDF)
+
+.PHONY: gethdf
+
+
+config: $(PRJ_HDF)
+	petalinux-config $(GEN_ARGS)
+
+config-kernel: $(PRJ_HDF)
+	DISPLAY= petalinux-config $(GEN_ARGS) -c kernel
+
+config-rootfs: $(PRJ_HDF)
+	petalinux-config $(GEN_ARGS) -c rootfs
+
+build: $(PRJ_HDF)
+ifneq ($(shell grep CONFIG_YOCTO_BB_NO_NETWORK=y project-spec/configs/config),)
+	$(call trap-update-mirror,__BLD_ARGS=\"$(GEN_ARGS)\" $(MAKE) __build)
+else
+	__BLD_ARGS="$(GEN_ARGS)" $(MAKE) __build
+endif
+
+sdk: $(PRJ_HDF)
+ifneq ($(shell grep CONFIG_YOCTO_BB_NO_NETWORK=y project-spec/configs/config),)
+	$(call trap-update-mirror,__BLD_ARGS=\"$(GEN_ARGS) -s\" $(MAKE) __build)
+else
+	__BLD_ARGS="$(GEN_ARGS) -s" $(MAKE) __build
+endif
+
+source-release: $(PRJ_HDF)
+	$(call trap-source-release,__BLD_ARGS=\"$(GEN_ARGS)\" $(MAKE) __source-release)
+	__BLD_ARGS="$(GEN_ARGS)" $(MAKE) __source-release
+
+__build:
+ifeq ($(UPDATE_MIRROR),1)
+	$(call set-update-mirror)
+endif
+	petalinux-build $(__BLD_ARGS)
+ifeq ($(UPDATE_MIRROR),1)
+	mkdir -p $(SOURCE_MIRROR)
+	find $(SOURCE_DOWNLOADS)/* -path '$(SOURCE_DOWNLOADS)/git2' -prune -or \
+		-not -name '*.done' \
+		-type f \
+		-print \
+		-exec cp -n {} $(SOURCE_MIRROR) \;
+	$(call reset-update-mirror)
+endif
+
+__source-release:
+	$(call set-source-release)
+	__BLD_ARGS="$(GEN_ARGS)" $(MAKE) __build
+	$(MAKEFILE_PATH)/source-release.sh $(SOURCE_RELEASE)
+	mkdir -p $(MANIFESTS)
+	find $(MANIFEST_PATH) -name '*.manifest' -exec cp {} $(MANIFESTS) \;
+	$(call reset-source-release)
+
+
+.PHONY: config config-kernel config-rootfs build sdk source-release
+
+
+package-boot: $(PRJ_HDF)
+	petalinux-package --boot --force \
+		$(BOOT_ARG_FPGA) $(BOOT_ARG_FSBL) $(BOOT_ARG_ATF) \
+		$(BOOT_ARG_PMUFW) $(BOOT_ARG_UBOOT) $(BOOT_ARG_EXTRA) \
+		$(BOOT_ARG_OUT)
+package-boot: $(BOOT)
+
+package-prebuilt: $(PRJ_HDF)
+	petalinux-package --prebuilt --force -a $(DEF_IMAGEUB):images
+
+$(BSP): $(PRJ_HDF)
+ifeq ($(BSP),)
+	@echo "error: missing BSP, run with argument BSP=<path-to-.bsp-file>"
+	@false
+else
+	petalinux-package --bsp --force -p $(PWD) -o $(BSP)
+endif
+package-bsp: $(BSP)
+
+dts: $(SYSTEM_DTS)
+$(SYSTEM_DTS): $(SYSTEM_DTB)
+	dtc -I dtb -O dts -o $@ $<
+
+reset-jtag: $(PRF_HDF)
+	$(XSDB) $(MAKEFILE_PATH)xsdb/$(PLATFORM)-reset.tcl
+
+boot-jtag-u-boot: reset-jtag
+	petalinux-boot --jtag --u-boot -v --fpga --hw_server-url $(HW_SERVER_URL)
+
+boot-jtag-kernel: reset-jtag
+	petalinux-boot --jtag --kernel -v --fpga --hw_server-url $(HW_SERVER_URL)
+
+boot-jtag-psinit-uboot: reset-jtag
+	$(XSDB) $(MAKEFILE_PATH)xsdb/$(PLATFORM)-boot-psinit-uboot.tcl
+
+boot-qemu: $(PRJ_HDF)
+	petalinux-boot --qemu --kernel
+
+# IMPORTANT: program_flash can be found in Xilinx Vivado toolchain, only
+#            (<= v2018.2)!
+flash-boot: reset-jtag
+	program_flash \
+		-flash_type $(FLASH_TYPE) \
+		-fsbl $(FSBL_ELF) \
+		-f $(BOOT_BIN) -offset $(BOOT_BIN_OFF) \
+		-verify \
+		-cable type xilinx_tcf url $(HW_SERVER_URL)
+
+flash-kernel: reset-jtag
+	program_flash \
+		-flash_type $(FLASH_TYPE) \
+		-fsbl $(FSBL_ELF) \
+		-f $(KERNEL_IMG) -offset $(KERNEL_IMG_OFF) \
+		-verify \
+		-cable type xilinx_tcf url $(HW_SERVER_URL)
+
+flash: flash-boot flash-kernel
+
+.PHONY: $(BOOT) $(BSP) package-boot package-prebuilt package-bsp dts \
+	reset-jtag boot-jtag-u-boot boot-jtag-kernel boot-jtag-psinit-uboot \
+	boot-qemu flash-boot flash-kernel flash
+
+mrproper:
+	petalinux-build $(GEN_ARGS) -x mrproper
+ifeq ($(CLEAN_HDF),1)
+	-cd project-spec/hw-description/ && \
+		ls -1 | grep -v -e ^metadata$$ | xargs rm -fr
+endif
+	rm -rf project-spec/meta-plnx-generated/
+	-find pre-built/ -type f -not -name 'pmu_rom_qemu_sha3.elf' \
+		-not -name 'system.dtb' \
+		-not -name 'linux-boot.*' \
+		-delete
+	rm -rf *.bsp
+
+.PHONY: mrproper
diff --git a/fpga/lib/psmake/source-release.sh b/fpga/lib/psmake/source-release.sh
new file mode 100755
index 000000000..7c4a16580
--- /dev/null
+++ b/fpga/lib/psmake/source-release.sh
@@ -0,0 +1,27 @@
+#!/bin/bash
+#
+# Script to archive a subset of packages matching specific license(s)
+# Source and license files are copied into sub folders of package folder
+#
+# Based upon example script in
+# https://www.yoctoproject.org/docs/3.1/dev-manual/dev-manual.html#maintaining-open-source-license-compliance-during-your-products-lifecycle
+
+src_release_dir="$1"
+mkdir -p $src_release_dir
+for a in build/tmp/deploy/sources/*; do
+   for d in $a/*; do
+      # Get package name from path
+      p=`basename $d`
+      p=${p%-*}
+      p=${p%-*}
+      # Only archive GPL packages (update *GPL* regex for your license check)
+      numfiles=`ls build/tmp/deploy/licenses/$p/*GPL* 2> /dev/null | wc -l`
+      if [ $numfiles -ge 1 ]; then
+         echo Archiving $p
+         mkdir -p $src_release_dir/$p/source
+         cp $d/* $src_release_dir/$p/source 2> /dev/null
+         mkdir -p $src_release_dir/$p/license
+         cp build/tmp/deploy/licenses/$p/* $src_release_dir/$p/license 2> /dev/null
+      fi
+   done
+done
diff --git a/fpga/lib/psmake/vitis.mk b/fpga/lib/psmake/vitis.mk
new file mode 100644
index 000000000..ecd0abf00
--- /dev/null
+++ b/fpga/lib/psmake/vitis.mk
@@ -0,0 +1,312 @@
+#!/usr/bin/make -f
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2019-2020 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : Makefile
+##  Initial Author : Stefan Wiehler <stefan.wiehler@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : Vitis convenience wrapper
+##
+##                   Uses: vitis xsct
+##
+################################################################################
+
+ifeq ($(XILINX_VITIS),)
+$(error XILINX_VITIS is unset. This Makefile must be invoked from within a Vitis environment)
+endif
+
+MAKEFILE_PATH := $(dir $(realpath $(lastword $(MAKEFILE_LIST))))
+
+all: build
+
+# include config
+CFG ?= default
+include $(CFG).mk
+
+include $(MAKEFILE_PATH)common.mk
+
+###############################################################################
+# Variables
+
+# platform project paths
+HDF ?=
+XPFM ?=
+
+# user arguments, defaults, usually set via config.mk
+DEF_DOMAIN_PROC ?= psu_cortexa53_0
+DEF_DOMAIN_OS ?= standalone
+DEF_APP_PROC ?= psu_cortexa53_0
+DEF_APP_TMPL ?= Empty Application
+DEF_APP_OS ?= standalone
+DEF_APP_LANG ?= C
+DEF_APP_BCFG ?= Release
+DEF_APP_OPT ?= Optimize more (-O2)
+
+DOMAIN_PRJS ?=
+APP_PRJS ?=
+
+# user arguments, rarely modified
+PLAT_PRJ ?= plat
+XSCT ?= xsct
+VITIS ?= vitis
+
+###############################################################################
+# Platform repos
+
+PLATS ?=
+
+ifneq ($(strip $(PLATS)),)
+__PLATS_CCMD = $(foreach PLAT,$(PLATS), \
+	repo -add-platforms {$(PLAT)};)
+endif
+
+$(O)/.metadata/plats.stamp:
+ifneq ($(strip $(PLATS)),)
+	$(XSCT) -eval 'setws {$(O)}; $(__PLATS_CCMD)'
+else
+	mkdir -p $(O)/.metadata/
+endif
+	touch $@
+
+###############################################################################
+# Platform
+
+# arg1: platform name
+# arg2: path to platform file
+define gen-plat-rule
+$(O)/$(1)/hw/$(1).stamp: $(O)/.metadata/repos.stamp $(O)/.metadata/plats.stamp
+ifneq ($(HDF),)
+	$(XSCT) -eval 'setws {$(O)}; \
+		platform create -name {$(1)} -hw {$(2)}'
+else
+ifneq ($(XPFM),)
+	$(XSCT) -eval 'setws {$(O)}; \
+		platform create -name {$(1)} -xpfm {$(XPFM)}'
+	touch $(O)/$(1)/xpfm.stamp
+else
+	@echo "error: missing HDF or XPFM, run either with HDF=<path-to-.xsa-file> or XPFM=<path-to-.xpfm-file>" >&2
+	@false
+endif
+endif
+	touch $$@
+
+# shortcut to create platform, "make <plat>"
+$(1): $(O)/$(1)/hw/$(1).stamp
+.PHONY: $(1)
+
+$(1)_distclean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		platform remove -name {$(1)}'
+.PHONY: $(1)_distclean
+endef
+
+###############################################################################
+# Domains
+
+# arg1: domain name
+# arg2: platform name
+define gen-domain-rule
+$(1)_PROC ?= $(DEF_DOMAIN_PROC)
+$(1)_OS ?= $(DEF_DOMAIN_OS)
+$(1)_LIBS ?=
+$(1)_EXTRA_CFLAGS ?=
+$(1)_STDIN ?=
+$(1)_STDOUT ?=
+$(1)_IS_FSBL ?=
+
+ifneq ($$strip($$($(1)_LIBS)),)
+__$(1)_LIBS_CCMD = $$(foreach LIB,$$($(1)_LIBS), \
+	bsp setlib -name {$$(LIB)};)
+endif
+__$(1)_EXTRA_CCMD =
+ifneq ($$($(1)_EXTRA_CFLAGS),)
+__$(1)_EXTRA_CCMD += \
+	bsp config extra_compiler_flags {$$($(1)_EXTRA_CFLAGS)};
+endif
+ifneq ($$($(1)_STDIN),)
+__$(1)_EXTRA_CCMD += \
+	bsp config stdin {$$($(1)_STDIN)};
+endif
+ifneq ($$($(1)_STDOUT),)
+__$(1)_EXTRA_CCMD += \
+	bsp config stdout {$$($(1)_STDOUT)};
+endif
+ifeq ($$($(1)_IS_FSBL),yes)
+# non-default BSP settings for FSBL
+__$(1)_EXTRA_CCMD += \
+	bsp config {zynqmp_fsbl_bsp} {true}; \
+	bsp config {read_only} {true}; \
+	bsp config {use_mkfs} {false}; \
+	bsp config {extra_compiler_flags} {-g -Wall -Wextra -Os -flto -ffat-lto-objects};
+endif
+
+$(O)/$(2)/$$($(1)_PROC)/$(1)/bsp/Makefile: $(O)/$(2)/hw/$(2).stamp
+	$(XSCT) -eval 'setws {$(O)}; \
+		platform active {$(2)}; \
+		domain create -name {$(1)} -proc {$$($(1)_PROC)} \
+			-os {$$($(1)_OS)}; \
+		$$(__$(1)_LIBS_CCMD) \
+		$$(__$(1)_EXTRA_CCMD) \
+		$$($(1)_POST_CREATE_TCL); \
+		bsp regenerate'
+ifneq ($$(strip $$($(1)_PATCH)),)
+	$$(foreach PATCH,$$($(1)_PATCH),$(call patch-src,$(1),$$(PATCH))) :
+endif
+ifneq ($$(strip $$($(1)_SED)),)
+	$$(foreach SED,$$($(1)_SED),$(call sed-src,$(1),$$(SED))) :
+endif
+
+
+$(O)/$(2)/export/$(2)/sw/$(2)/$(1)/bsplib/lib/libxil.a: $(O)/$(2)/$$($(1)_PROC)/$(1)/bsp/Makefile
+	$(XSCT) -eval 'setws {$(O)}; \
+		platform active {$(2)}; \
+		platform generate -domains {$(1)}'
+
+# shortcut to create domain, "make <domain>"
+$(1): $(O)/$(2)/export/$(2)/sw/$(2)/$(1)/bsplib/lib/libxil.a
+.PHONY: $(1)
+
+$(1)_distclean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		platform active {$(2)}; \
+		domain remove -name {$(1)}'
+.PHONY: $(1)_distclean
+endef
+
+###############################################################################
+# Applications
+
+# arg1: app name
+# arg2: src file/folder name, scheme <srcfile>
+# Paths are normalized because Vitis does not accept relative paths
+define import-src
+importsources -name $(1) -path [file normalize $(2)] -soft-link;
+endef
+
+# arg1: app name
+# arg2: platform name
+define gen-app-rule
+$(1)_PROC ?= $(DEF_APP_PROC)
+$(1)_TMPL ?= $(DEF_APP_TMPL)
+$(1)_OS ?= $(DEF_APP_OS)
+$(1)_LANG ?= $(DEF_APP_LANG)
+$(1)_BCFG ?= $(DEF_APP_BCFG)
+$(1)_OPT ?= $(DEF_APP_OPT)
+
+ifneq ($$strip($$($(1)_CPPSYMS)),)
+__$(1)_CPPSYMS_CCMD = $$(foreach SYM,$$($(1)_CPPSYMS), \
+	app config -name {$(1)} define-compiler-symbols {$$(SYM)};)
+endif
+ifneq ($$($(1)_HW),)
+$(O)/$(1)/src/lscript.ld:
+	$(XSCT) -eval 'setws {$(O)}; \
+		app create -name {$(1)} -hw {$$($(1)_HW)} \
+			-proc {$$($(1)_PROC)} -template {$$($(1)_TMPL)} \
+			-os {$$($(1)_OS)} -lang {$$($(1)_LANG)}'
+else
+ifneq ($$($(1)_PLAT),)
+$(O)/$(1)/src/lscript.ld:
+	$(XSCT) -eval 'setws {$(O)}; \
+		app create -name {$(1)} -platform {$$($(1)_PLAT)} \
+			-domain {$$($(1)_DOMAIN)} \
+			-proc {$$($(1)_PROC)} -template {$$($(1)_TMPL)} \
+			-os {$$($(1)_OS)} -lang {$$($(1)_LANG)}; \
+		app config -name {$(1)} build-config {$$($(1)_BCFG)}; \
+		app config -name {$(1)} compiler-optimization {$$($(1)_OPT)}; \
+		$$(__$(1)_CPPSYMS_CCMD) \
+		$$($(1)_POST_CREATE_TCL)'
+else
+$(O)/$(1)/src/lscript.ld:
+	$(XSCT) -eval 'setws {$(O)}; \
+		app create -name {$(1)} -platform {$(2)} \
+			-domain {$$($(1)_DOMAIN)} \
+			-proc {$$($(1)_PROC)} -template {$$($(1)_TMPL)} \
+			-os {$$($(1)_OS)} -lang {$$($(1)_LANG)}; \
+		app config -name {$(1)} build-config {$$($(1)_BCFG)}; \
+		app config -name {$(1)} compiler-optimization {$$($(1)_OPT)}; \
+		$$(__$(1)_CPPSYMS_CCMD) \
+		$$($(1)_POST_CREATE_TCL)'
+endif
+endif
+ifneq ($$(strip $$($(1)_SRC)),)
+	$(XSCT) -eval 'setws {$(O)}; \
+		$$(foreach SRC,$$($(1)_SRC),$(call import-src,$(1),$$(SRC)))'
+endif
+ifneq ($$(strip $$($(1)_PATCH)),)
+	$$(foreach PATCH,$$($(1)_PATCH),$(call patch-src,$(1)/src,$$(PATCH))) :
+endif
+ifneq ($$(strip $$($(1)_SED)),)
+	$$(foreach SED,$$($(1)_SED),$(call sed-src,$(1)/src,$$(SED))) :
+endif
+
+$(O)/$(1)/$$($(1)_BCFG)/$(1).elf: $(O)/$(2)/export/$(2)/sw/$(2)/$$($(1)_DOMAIN)/bsplib/lib/libxil.a \
+		$(O)/.metadata/repos.stamp $(O)/.metadata/plats.stamp $(O)/$(1)/src/lscript.ld \
+		$$($(1)_SRC)
+	$(XSCT) -eval 'setws {$(O)}; \
+		app build -name {$(1)}'
+
+GEN_APPS_DEP += $(O)/$(2)/export/$(2)/sw/$(2)/$$($(1)_DOMAIN)/bsplib/lib/libxil.a
+BLD_APPS_DEP += $(O)/$(1)/$$($(1)_BCFG)/$(1).elf
+
+# shortcut to create application, "make <app>"
+$(1): $(O)/$(1)/$$($(1)_BCFG)/$(1).elf
+.PHONY: $(1)
+
+$(1)_distclean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		app remove {$(1)}'
+.PHONY: $(1)_distclean
+
+endef
+
+###############################################################################
+# Targets
+
+# generate make rules for platform project, single
+$(eval $(call gen-plat-rule,$(PLAT_PRJ),$(HDF)))
+getdsa: $(PLAT_PRJ)
+.PHONY: gethwplat
+
+# generate make rules for domains, multiple
+$(foreach DOMAIN_PRJ,$(DOMAIN_PRJS),\
+	$(eval $(call gen-domain-rule,$(DOMAIN_PRJ),$(PLAT_PRJ))))
+
+# generate make rules for apps, multiple
+$(foreach APP_PRJ,$(APP_PRJS),\
+	$(eval $(call gen-app-rule,$(APP_PRJ),$(PLAT_PRJ))))
+
+# generate make rules for bootgen projects, multiple
+$(foreach BOOTGEN_PRJ,$(BOOTGEN_PRJS),\
+	$(eval $(call gen-bif-rule,$(BOOTGEN_PRJ))))
+
+# generate all projects
+generate: $(GEN_APPS_DEP) $(GEN_BOOTGEN_DEP)
+.PHONY: generate
+
+# build all projects
+build: $(BLD_APPS_DEP) $(BLD_BOOTGEN_DEP)
+.PHONY: build
+
+# open workspace in GUI mode
+vitis:
+	$(VITIS) -workspace $(O)
+.PHONY: vitis
diff --git a/fpga/lib/psmake/xsdb/zynq-boot-psinit-uboot.tcl b/fpga/lib/psmake/xsdb/zynq-boot-psinit-uboot.tcl
new file mode 100644
index 000000000..465b1b964
--- /dev/null
+++ b/fpga/lib/psmake/xsdb/zynq-boot-psinit-uboot.tcl
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2019 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : zynq-boot-psinit-uboot.tcl
+##  Initial Author : Joachim Foerster
+##                   <joachim.foerster@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : petalinux-* convenience wrapper
+##
+##                   TCL script for XSDB to "boot" Zynq 7000 into U-Boot via
+##                   JTAG using ps7_init TCL function instead of FSBL
+##                   executable. Thus no FSBL hook code is executed.
+##
+################################################################################
+
+
+if {![info exists ::env(HW_SERVER_URL)]} {
+	puts stderr "error: environment variable HW_SERVER_URL not set"
+	exit 1
+}
+
+# use PetaLinux built-in defaults if user does not specify certain items
+set PS7INIT "project-spec/hw-description/ps7_init.tcl"
+if {[info exists ::env(BIT)]} {
+	set BIT $::env(BIT)
+} else {
+	set BIT "images/linux/system.bit"
+}
+if {[info exists ::env(UBOOT)]} {
+	set UBOOT $::env(UBOOT)
+} else {
+	set UBOOT "images/linux/u-boot.elf"
+}
+
+if {![file exists $PS7INIT]} {
+	puts stderr "error: required file $PS7INIT does not exist"
+	exit 1
+}
+if {![file exists $BIT]} {
+	puts stderr "error: required file $BIT does not exist"
+	exit 1
+}
+if {![file exists $UBOOT]} {
+	puts stderr "error: required file $UBOOT does not exist"
+	exit 1
+}
+
+source $PS7INIT
+
+connect -url $::env(HW_SERVER_URL)
+
+puts "Execute ps7_init TCL proc ..."
+targets -set -filter {name =~ "ARM*#0"}
+ps7_init
+puts "done."
+
+puts "Download bitstream $BIT ..."
+fpga $BIT
+puts "done."
+
+puts "Execute ps7_post_config TCL proc ..."
+targets -set -filter {name =~ "ARM*#0"}
+ps7_post_config
+puts "done."
+
+puts "Download U-Boot executable $UBOOT ..."
+targets -set -filter {name =~ "ARM*#0"}
+dow $UBOOT
+puts "done."
+
+puts "Start U-Boot ..."
+con
+puts "done."
+
+disconnect
diff --git a/fpga/lib/psmake/xsdb/zynq-reset.tcl b/fpga/lib/psmake/xsdb/zynq-reset.tcl
new file mode 100644
index 000000000..cd00962e4
--- /dev/null
+++ b/fpga/lib/psmake/xsdb/zynq-reset.tcl
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2019 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : zynq-reset.tcl
+##  Initial Author : Joachim Foerster
+##                   <joachim.foerster@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : petalinux-* convenience wrapper
+##
+##                   TCL script for XSDB to "reset" Zynq 7000. PL is left
+##                   unconfigured and PS CPU cores are stopped.
+##
+################################################################################
+
+if {![info exists ::env(HW_SERVER_URL)]} {
+	puts stderr "error: environment variable HW_SERVER_URL not set"
+	exit 1
+}
+
+connect -url $::env(HW_SERVER_URL)
+
+puts "Trigger system reset on APU ..."
+targets -set -filter {name =~ "APU"}
+rst -system
+puts "done."
+
+disconnect
diff --git a/fpga/lib/psmake/xsdb/zynqmp-reset.tcl b/fpga/lib/psmake/xsdb/zynqmp-reset.tcl
new file mode 100644
index 000000000..71f80efa4
--- /dev/null
+++ b/fpga/lib/psmake/xsdb/zynqmp-reset.tcl
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2019 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : zynqmp-reset.tcl
+##  Initial Author : Stefan Wiehler <stefan.wiehler@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : petalinux-* convenience wrapper
+##
+##                   TCL script for XSDB to "reset" Zynq UltraScale+. PL is left
+##                   unconfigured and PS CPU cores are stopped.
+##
+################################################################################
+
+connect -url $::env(HW_SERVER_URL)
+
+if {$::env(PETALINUX_VER) < 2018.3} {
+	set ZYNQMP_UTILS "tools/hsm/scripts/sdk/util/zynqmp_utils.tcl"
+} elseif {$::env(PETALINUX_VER) == 2018.3} {
+	set ZYNQMP_UTILS "tools/xsct/SDK/2018.3/scripts/sdk/util/zynqmp_utils.tcl"
+} elseif {$::env(PETALINUX_VER) == 2019.1} {
+	set ZYNQMP_UTILS "tools/xsct/scripts/sdk/util/zynqmp_utils.tcl"
+} else {
+	set ZYNQMP_UTILS "tools/xsct/scripts/vitis/util/zynqmp_utils.tcl"
+}
+source $::env(PETALINUX)/$ZYNQMP_UTILS
+targets -set -nocase -filter {name =~"APU*"} -index 1
+rst -system
+after 3000
+targets -set -nocase -filter {name =~"APU*"} -index 1
+reset_apu
+targets -set -filter {level==0} -index 0
+exit
diff --git a/fpga/lib/psmake/xsdk.mk b/fpga/lib/psmake/xsdk.mk
new file mode 100644
index 000000000..903464bbb
--- /dev/null
+++ b/fpga/lib/psmake/xsdk.mk
@@ -0,0 +1,369 @@
+#!/usr/bin/make -f
+# SPDX-License-Identifier: Apache-2.0
+#
+################################################################################
+##
+## Copyright 2018-2019 Missing Link Electronics, Inc.
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##     http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+################################################################################
+##
+##  File Name      : Makefile
+##  Initial Author : Joachim Foerster
+##                   <joachim.foerster@missinglinkelectronics.com>
+##
+################################################################################
+##
+##  File Summary   : xsct/xsdk convenience wrapper
+##
+##                   Uses: xsct xsdk
+##
+################################################################################
+
+ifeq ($(XILINX_VIVADO),)
+$(error XILINX_VIVADO is unset. This Makefile must be invoked from within a Vivado/XSDK environment)
+endif
+
+MAKEFILE_PATH := $(dir $(realpath $(lastword $(MAKEFILE_LIST))))
+
+all: build
+
+# include config
+CFG ?= default
+include $(CFG).mk
+
+include $(MAKEFILE_PATH)common.mk
+
+###############################################################################
+# Variables
+
+#  path to .hdf file exported from Vivado
+HDF ?=
+
+# user arguments, defaults, usually set via config.mk
+DEF_BSP_OS ?= standalone
+DEF_APP_LANG ?= C
+DEF_APP_BCFG ?= Release
+DEF_APP_OPT ?= Optimize more (-O2)
+DEF_APP_TMPL ?= Empty Application
+DEF_LIB_TYPE ?= static
+DEF_LIB_OS ?= standalone
+DEF_LIB_LANG ?= C
+DEF_LIB_BCFG ?= Release
+DEF_LIB_OPT ?= Optimize more (-O2)
+
+BSP_PRJS ?=
+APP_PRJS ?=
+
+# user arguments, rarely modified
+HW_PRJ ?= hw
+XSCT ?= xsct
+XSDK ?= xsdk
+
+# internal settings
+# <none>
+
+###############################################################################
+# Hardware Platform Project
+
+# arg1: hw name
+# arg2: path to hdf file
+define gen-hw-rule
+$(O)/$(1)/system.hdf: $(O)/.metadata/repos.stamp
+ifeq ($(HDF),)
+	@echo "error: missing HDF, run with HDF=<path-to-hdf>" >&2
+	@false
+endif
+	$(XSCT) -eval 'setws {$(O)}; \
+		createhw -name {$(1)} -hwspec {$(2)}; \
+		$$($(1)_POST_CREATE_TCL)'
+
+# shortcut to create hw, "make <hw>"
+$(1): $(O)/$(1)/system.hdf
+.PHONY: $(1)
+
+$(1)_distclean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		deleteprojects -name {$(1)}'
+.PHONY: $(1)_distclean
+endef
+
+###############################################################################
+# Board Support Packages (BSPs)
+
+# arg1: bsp name
+# arg2: hw name
+define gen-bsp-rule
+$(1)_PROC ?=
+$(1)_OS ?= $(DEF_BSP_OS)
+ifeq ($$($(1)_PROC),psu_cortexa53_0)
+$(1)_ARCH ?= 64
+else
+$(1)_ARCH ?= 32
+endif
+$(1)_LIBS ?=
+$(1)_EXTRA_CFLAGS ?=
+$(1)_STDIN ?=
+$(1)_STDOUT ?=
+$(1)_IS_FSBL ?=
+
+ifneq ($$strip($$($(1)_LIBS)),)
+__$(1)_LIBS_CCMD = $$(foreach LIB,$$($(1)_LIBS), \
+	setlib -bsp {$(1)} -lib {$$(LIB)};)
+endif
+__$(1)_EXTRA_CCMD =
+ifneq ($$($(1)_EXTRA_CFLAGS),)
+__$(1)_EXTRA_CCMD += \
+	configbsp -bsp {$(1)} extra_compiler_flags {$$($(1)_EXTRA_CFLAGS)};
+endif
+ifneq ($$($(1)_STDIN),)
+__$(1)_EXTRA_CCMD += \
+	configbsp -bsp {$(1)} stdin {$$($(1)_STDIN)};
+endif
+ifneq ($$($(1)_STDOUT),)
+__$(1)_EXTRA_CCMD += \
+	configbsp -bsp {$(1)} stdout {$$($(1)_STDOUT)};
+endif
+ifeq ($$($(1)_IS_FSBL),yes)
+# non-default BSP settings for FSBL
+__$(1)_EXTRA_CCMD += \
+	configbsp -bsp {$(1)} {zynqmp_fsbl_bsp} {true}; \
+	configbsp -bsp {$(1)} {read_only} {true}; \
+	configbsp -bsp {$(1)} {use_mkfs} {false}; \
+	configbsp -bsp {$(1)} {extra_compiler_flags} {-g -Wall -Wextra -Os -flto -ffat-lto-objects};
+endif
+$(O)/$(1)/system.mss: $(O)/$(2)/system.hdf
+	$(XSCT) -eval 'setws {$(O)}; \
+		createbsp -name {$(1)} -proc {$$($(1)_PROC)} \
+			-hwproject {$(2)} -os {$$($(1)_OS)} \
+			-arch {$$($(1)_ARCH)}; \
+		$$(__$(1)_LIBS_CCMD) \
+		$$(__$(1)_EXTRA_CCMD) \
+		$$($(1)_POST_CREATE_TCL); \
+		regenbsp -bsp {$(1)}'
+ifneq ($$(strip $$($(1)_PATCH)),)
+	$$(foreach PATCH,$$($(1)_PATCH),$(call patch-src,$(1),$$(PATCH))) :
+endif
+ifneq ($$(strip $$($(1)_SED)),)
+	$$(foreach SED,$$($(1)_SED),$(call sed-src,$(1),$$(SED))) :
+endif
+
+$(O)/$(1)/$$($(1)_PROC)/lib/libxil.a: $(O)/$(2)/system.hdf $(O)/$(1)/system.mss
+	$(XSCT) -eval 'setws {$(O)}; \
+		projects -build -type bsp -name {$(1)}'
+
+# shortcut to build bsp, "make <bsp>"
+$(1): $(O)/$(1)/$$($(1)_PROC)/lib/libxil.a
+.PHONY: $(1)
+
+$(1)_clean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		projects -clean -type bsp -name {$(1)}'
+.PHONY: $(1)_clean
+
+$(1)_distclean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		deleteprojects -name {$(1)}'
+.PHONY: $(1)_distclean
+endef
+
+###############################################################################
+# Applications
+
+# arg1: app name
+define gen-app-proc-contents-rule
+$$($(1)_PROC)
+endef
+
+# arg1: app name
+# arg2: hw name
+define gen-app-rule
+$(1)_BSP ?=
+$(1)_PROC ?= $(call gen-app-proc-contents-rule,$$($(1)_BSP))
+$(1)_LANG ?= $(DEF_APP_LANG)
+$(1)_BCFG ?= $(DEF_APP_BCFG)
+$(1)_OPT ?= $(DEF_APP_OPT)
+$(1)_TMPL ?= $(DEF_APP_TMPL)
+$(1)_CPPSYMS ?=
+$(1)_LIBS ?=
+
+ifneq ($$strip($$($(1)_CPPSYMS)),)
+__$(1)_CPPSYMS_CCMD = $$(foreach SYM,$$($(1)_CPPSYMS), \
+	configapp -app {$(1)} define-compiler-symbols {$$(SYM)};)
+endif
+ifneq ($$(strip $$($(1)_LIBS)),)
+__$(1)_LIBS_CCMD = $$(foreach LIB,$$($(1)_LIBS), \
+	configapp -app {$(1)} include-path {../../$$(LIB)/src}; \
+	configapp -app {$(1)} library-search-path {../../$$(LIB)/$$($$(LIB)_BCFG)}; \
+	configapp -app {$(1)} libraries {$$(LIB)};)
+endif
+$(O)/$(1)/src/lscript.ld: $(O)/$$($(1)_BSP)/system.mss
+	$(XSCT) -eval 'setws {$(O)}; \
+		createapp -name {$(1)} -app {$$($(1)_TMPL)} \
+			-proc {$$($(1)_PROC)} -hwproject {$(2)} \
+			-bsp {$$($(1)_BSP)} -lang {$$($(1)_LANG)}; \
+		configapp -app {$(1)} build-config {$$($(1)_BCFG)}; \
+		configapp -app {$(1)} compiler-optimization {$$($(1)_OPT)}; \
+		$$(__$(1)_CPPSYMS_CCMD) \
+		$$(__$(1)_LIBS_CCMD) \
+		$$($(1)_POST_CREATE_TCL)'
+ifneq ($$(strip $$($(1)_SRC)),)
+	$$(foreach SRC,$$($(1)_SRC),$(call symlink-src,$(1),$$(SRC))) :
+endif
+ifneq ($$(strip $$($(1)_PATCH)),)
+	$$(foreach PATCH,$$($(1)_PATCH),$(call patch-src,$(1)/src,$$(PATCH))) :
+endif
+ifneq ($$(strip $$($(1)_SED)),)
+	$$(foreach SED,$$($(1)_SED),$(call sed-src,$(1)/src,$$(SED))) :
+endif
+
+__$(1)_SRC = $(addprefix $(O)/$(1)/src/,$$($(1)_SRC))
+$(O)/$(1)/$$($(1)_BCFG)/$(1).elf: $(O)/$$($(1)_BSP)/$$($(1)_PROC)/lib/libxil.a $(O)/$(1)/src/lscript.ld $$(__$(1)_SRC) $$($(1)_LIBS)
+	$(XSCT) -eval 'setws {$(O)}; \
+		projects -build -type app -name {$(1)}'
+
+GEN_APPS_DEP += $(O)/$(1)/src/lscript.ld
+BLD_APPS_DEP += $(O)/$(1)/$$($(1)_BCFG)/$(1).elf
+
+# shortcut to build app, "make <app>"
+$(1): $(O)/$(1)/$$($(1)_BCFG)/$(1).elf
+.PHONY: $(1)
+
+$(1)_clean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		projects -clean -type app -name {$(1)}'
+.PHONY: $(1)_clean
+
+$(1)_distclean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		deleteprojects -name {$(1)}'
+.PHONY: $(1)_distclean
+endef
+
+###############################################################################
+# Libraries
+
+# arg1: lib name
+define gen-lib-rule
+$(1)_TYPE ?= $(DEF_LIB_TYPE)
+$(1)_PROC ?= $(DEF_LIB_PROC)
+$(1)_OS ?= $(DEF_LIB_OS)
+$(1)_LANG ?= $(DEF_LIB_LANG)
+ifeq ($$($(1)_PROC),psu_cortexa53)
+$(1)_ARCH ?= 64
+else
+$(1)_ARCH ?= 32
+endif
+$(1)_BCFG ?= $(DEF_LIB_BCFG)
+$(1)_OPT ?= $(DEF_LIB_OPT)
+$(1)_CPPSYMS ?=
+
+ifneq ($$strip($$($(1)_CPPSYMS)),)
+__$(1)_CPPSYMS_CCMD = $$(foreach SYM,$$($(1)_CPPSYMS), \
+	configapp -app {$(1)} define-compiler-symbols {$$(SYM)};)
+endif
+$(O)/$(1)/src:
+	$(XSCT) -eval 'setws {$(O)}; \
+		createlib -name {$(1)} -type {$$($(1)_TYPE)} \
+			-proc {$$($(1)_PROC)} -os {$$($(1)_OS)} \
+			-lang {$$($(1)_LANG)} -arch {$$($(1)_ARCH)}; \
+		configapp -app {$(1)} build-config {$$($(1)_BCFG)}; \
+		configapp -app {$(1)} compiler-optimization {$$($(1)_OPT)}; \
+		$$(__$(1)_CPPSYMS_CCMD) \
+		$$($(1)_POST_CREATE_TCL)'
+ifneq ($$(strip $$($(1)_SRC)),)
+	$$(foreach SRC,$$($(1)_SRC),$(call symlink-src,$(1),$$(SRC))) :
+endif
+
+__$(1)_SRC = $(addprefix $(O)/$(1)/src/,$$($(1)_SRC))
+ifeq ($$($(1)_TYPE),shared)
+$(O)/$(1)/$$($(1)_BCFG)/lib$(1).so: $(O)/$(1)/src
+else
+$(O)/$(1)/$$($(1)_BCFG)/lib$(1).a: $(O)/$(1)/src
+endif
+	$(XSCT) -eval 'setws {$(O)}; \
+		projects -build -type app -name {$(1)}'
+# Workaround for missing "lib" prefix
+ifeq ($$($(1)_TYPE),shared)
+	ln -fs $(1).so $(O)/$(1)/$$($(1)_BCFG)/lib$(1).so
+endif
+
+GEN_LIBS_DEP += $(O)/$(1)/src
+ifeq ($$($(1)_TYPE),shared)
+BLD_LIBS_DEP += $(O)/$(1)/$$($(1)_BCFG)/lib$(1).so
+else
+BLD_LIBS_DEP += $(O)/$(1)/$$($(1)_BCFG)/lib$(1).a
+endif
+
+# shortcut to build lib, "make <lib>"
+ifeq ($$($(1)_TYPE),shared)
+$(1): $(O)/$(1)/$$($(1)_BCFG)/lib$(1).so
+else
+$(1): $(O)/$(1)/$$($(1)_BCFG)/lib$(1).a
+endif
+.PHONY: $(1)
+
+$(1)_clean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		projects -clean -type app -name {$(1)}'
+.PHONY: $(1)_clean
+
+$(1)_distclean:
+	-$(XSCT) -eval 'setws {$(O)}; \
+		deleteprojects -name {$(1)}'
+.PHONY: $(1)_distclean
+endef
+
+###############################################################################
+# Targets
+
+# generate make rules for hardware project, single
+$(eval $(call gen-hw-rule,$(HW_PRJ),$(HDF)))
+gethdf: $(HW_PRJ)
+.PHONY: gethdf
+
+# generate make rules for bsp projects, multiple
+$(foreach BSP_PRJ,$(BSP_PRJS),\
+	$(eval $(call gen-bsp-rule,$(BSP_PRJ),$(HW_PRJ))))
+
+# generate make rules for application projects, multiple
+$(foreach APP_PRJ,$(APP_PRJS),\
+	$(eval $(call gen-app-rule,$(APP_PRJ),$(HW_PRJ))))
+
+# generate make rules for library projects, multiple
+$(foreach LIB_PRJ,$(LIB_PRJS),\
+	$(eval $(call gen-lib-rule,$(LIB_PRJ))))
+
+# generate make rules for bootgen projects, multiple
+$(foreach BOOTGEN_PRJ,$(BOOTGEN_PRJS),\
+	$(eval $(call gen-bif-rule,$(BOOTGEN_PRJ))))
+
+# generate all (app) projects
+generate: $(GEN_APPS_DEP) $(GEN_BOOTGEN_DEP)
+.PHONY: generate
+
+# build all (app) projects
+build: $(BLD_APPS_DEP) $(BLD_BOOTGEN_DEP)
+.PHONY: build
+
+# open workspace in GUI mode
+xsdk:
+	$(XSDK) -workspace $(O)
+.PHONY: xsdk
+
+# clean all projects
+clean:
+	$(XSCT) -eval 'setws {$(O)}; \
+		projects -clean -type all'
+.PHONY: clean