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Fix state register width

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Alex Forencich 2019-08-12 15:12:21 -07:00
parent e9949f57a9
commit e9c1c5a49d
1 changed files with 1 additions and 1 deletions
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rtl/axis_xgmii_tx_32.v
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@ -121,7 +121,7 @@ localparam [3:0]
STATE_IFG = 4'd7,
STATE_WAIT_END = 4'd8;
reg [2:0] state_reg = STATE_IDLE, state_next;
reg [3:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;