From e9d52516fbf2d257a289e73db0814c0c74b451f0 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 14 Mar 2022 19:12:58 -0700 Subject: [PATCH] Unified 10G/25G design for ExaNIC X25 --- fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile | 25 - fpga/mqnic/ExaNIC_X25/fpga_10g/README.md | 24 - fpga/mqnic/ExaNIC_X25/fpga_10g/app | 1 - fpga/mqnic/ExaNIC_X25/fpga_10g/boot.xdc | 4 - .../ExaNIC_X25/fpga_10g/common/vivado.mk | 126 -- fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc | 187 --- .../ExaNIC_X25/fpga_10g/ip/eth_xcvr_gty.tcl | 129 -- .../fpga_10g/ip/pcie4_uscale_plus_0.tcl | 26 - fpga/mqnic/ExaNIC_X25/fpga_10g/lib | 1 - fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common | 1 - fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v | 1337 ----------------- .../mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v | 1298 ---------------- .../ExaNIC_X25/fpga_10g/rtl/sync_signal.v | 62 - .../ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile | 410 ----- .../ExaNIC_X25/fpga_10g/tb/fpga_core/mqnic.py | 1 - .../fpga_10g/tb/fpga_core/test_fpga_core.py | 694 --------- .../mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl | 33 + .../fpga => fpga_25g/fpga_10g}/Makefile | 0 .../fpga => fpga_25g/fpga_10g}/config.tcl | 33 + fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v | 3 +- 20 files changed, 68 insertions(+), 4327 deletions(-) delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/README.md delete mode 120000 fpga/mqnic/ExaNIC_X25/fpga_10g/app delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/boot.xdc delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gty.tcl delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.tcl delete mode 120000 fpga/mqnic/ExaNIC_X25/fpga_10g/lib delete mode 120000 fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py rename fpga/mqnic/ExaNIC_X25/{fpga_10g/fpga => fpga_25g/fpga_10g}/Makefile (100%) rename fpga/mqnic/ExaNIC_X25/{fpga_10g/fpga => fpga_25g/fpga_10g}/config.tcl (85%) diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/README.md b/fpga/mqnic/ExaNIC_X25/fpga_10g/README.md deleted file mode 100644 index 752ae9ecc..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/README.md +++ /dev/null @@ -1,24 +0,0 @@ -# Corundum mqnic for ExaNIC X25/Cisco Nexus K3P-S - -## Introduction - -This design targets the Exablaze ExaNIC X25/Cisco Nexus K3P-S FPGA board. - -FPGA: xcku3p-ffvb676-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver - -## How to build - -Run make to build. Ensure that the Xilinx Vivado toolchain components are -in PATH. - -Run make to build the driver. Ensure the headers for the running kernel are -installed, otherwise the driver cannot be compiled. - -## How to test - -Run make program to program the ExaNIC X25 board with Vivado. Then load the -driver with insmod mqnic.ko. Check dmesg for output from driver -initialization. - - diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/app b/fpga/mqnic/ExaNIC_X25/fpga_10g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/boot.xdc b/fpga/mqnic/ExaNIC_X25/fpga_10g/boot.xdc deleted file mode 100644 index 5fb323e94..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/boot.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for FPGA boot logic - -set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] -set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk b/fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk deleted file mode 100644 index df3528189..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk +++ /dev/null @@ -1,126 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES)) -CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES)) - -ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES)) -else - XDC_FILES_REL = $(FPGA_TOP).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).bit - -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(FPGA_TOP).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(FPGA_TOP).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project $*.xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp - echo "open_project $*.xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -%.bit: %.runs/impl_1/%_routed.dcp - echo "open_project $*.xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $*.bit" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - mkdir -p rev - EXT=bit; COUNT=100; \ - while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp $@ rev/$*_rev$$COUNT.$$EXT; \ - echo "Output: rev/$*_rev$$COUNT.$$EXT"; diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc deleted file mode 100644 index 38ae2396d..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc +++ /dev/null @@ -1,187 +0,0 @@ -# XDC constraints for the ExaNIC X25 -# part: xcku3p-ffvb676-2-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 31.9 [current_design] -set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 8 [current_design] -set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 4 [current_design] -set_property CONFIG_MODE BPI16 [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] - -# 10 MHz TXCO -#set_property -dict {LOC D14 IOSTANDARD LVCMOS33} [get_ports clk_10mhz] -#create_clock -period 100 -name clk_100mhz [get_ports clk_10mhz] - -# LEDs -set_property -dict {LOC J12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[0]}] -set_property -dict {LOC H12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[1]}] -set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[0]}] -set_property -dict {LOC H13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[1]}] -set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}] -set_property -dict {LOC G12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}] - -set_false_path -to [get_ports {sfp_1_led[*] sfp_2_led[*] sma_led[*]}] -set_output_delay 0 [get_ports {sfp_1_led[*] sfp_2_led[*] sma_led[*]}] - -# GPIO -#set_property -dict {LOC F9 IOSTANDARD LVCMOS18} [get_ports gpio[0]] -#set_property -dict {LOC F10 IOSTANDARD LVCMOS18} [get_ports gpio[1]] -#set_property -dict {LOC G9 IOSTANDARD LVCMOS18} [get_ports gpio[2]] -#set_property -dict {LOC G10 IOSTANDARD LVCMOS18} [get_ports gpio[3]] - -# SMA -set_property -dict {LOC A14 IOSTANDARD LVCMOS33} [get_ports sma_in] -set_property -dict {LOC A12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports sma_out] -set_property -dict {LOC A13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sma_out_en] -set_property -dict {LOC B12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sma_term_en] - -set_false_path -to [get_ports {sma_out sma_out_en sma_term_en}] -set_output_delay 0 [get_ports {sma_out sma_out_en sma_term_en}] -set_false_path -from [get_ports {sma_in}] -set_input_delay 0 [get_ports {sma_in}] - -# Config -#set_property -dict {LOC C14 IOSTANDARD LVCMOS33} [get_ports ddr_npres] - -# SFP28 Interfaces -set_property -dict {LOC D2 } [get_ports sfp_1_rx_p] ;# MGTYRXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC D1 } [get_ports sfp_1_rx_n] ;# MGTYRXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC A4 } [get_ports sfp_2_rx_p] ;# MGTYRXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC A3 } [get_ports sfp_2_rx_n] ;# MGTYRXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC F7 } [get_ports sfp_1_tx_p] ;# MGTYTXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC F6 } [get_ports sfp_1_tx_n] ;# MGTYTXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC B7 } [get_ports sfp_2_tx_p] ;# MGTYTXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC B6 } [get_ports sfp_2_tx_n] ;# MGTYTXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC K7 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_227 from X2 -set_property -dict {LOC K6 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_227 from X2 -set_property -dict {LOC AC17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable] -set_property -dict {LOC AA17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable] -set_property -dict {LOC F12 IOSTANDARD LVCMOS33 PULLUP true} [get_ports sfp_1_npres] -set_property -dict {LOC F14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports sfp_2_npres] -set_property -dict {LOC AC16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_los] -set_property -dict {LOC Y17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los] -set_property -dict {LOC G14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_1_rs] -set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_2_rs] -set_property -dict {LOC A10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl] -set_property -dict {LOC C11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda] -set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda] - -# 161.1328125 MHz MGT reference clock -create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p] - -set_false_path -to [get_ports {sfp_1_tx_disable sfp_2_tx_disable sfp_1_rs sfp_2_rs}] -set_output_delay 0 [get_ports {sfp_1_tx_disable sfp_2_tx_disable sfp_1_rs sfp_2_rs}] -set_false_path -from [get_ports {sfp_1_npres sfp_2_npres sfp_1_los sfp_2_los}] -set_input_delay 0 [get_ports {sfp_1_npres sfp_2_npres sfp_1_los sfp_2_los}] - -set_false_path -to [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}] -set_output_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}] -set_false_path -from [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}] -set_input_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}] - -# I2C interface -set_property -dict {LOC B9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl] -set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda] - -set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] -set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] -set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] -set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] - -# PCIe Interface -set_property -dict {LOC P2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC P1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC R5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC R4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC T2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC T1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC U5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC U4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC V2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC V1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC W5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC W4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC AA5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC AA4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 -set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 -set_property -dict {LOC V7 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225 -set_property -dict {LOC V6 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_225 -set_property -dict {LOC T19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] - -set_false_path -from [get_ports {pcie_reset_n}] -set_input_delay 0 [get_ports {pcie_reset_n}] - -# 100 MHz MGT reference clock -create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p] - -# BPI flash -set_property -dict {LOC AF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[0]}] -set_property -dict {LOC AE18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[1]}] -set_property -dict {LOC AF19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[2]}] -set_property -dict {LOC AF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[3]}] -set_property -dict {LOC AB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}] -set_property -dict {LOC AD19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}] -set_property -dict {LOC AB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}] -set_property -dict {LOC AE17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}] -set_property -dict {LOC AD16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}] -set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}] -set_property -dict {LOC AD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}] -set_property -dict {LOC AC21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}] -set_property -dict {LOC AE22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}] -set_property -dict {LOC AF22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}] -set_property -dict {LOC AF25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}] -set_property -dict {LOC AF24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}] -set_property -dict {LOC AE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}] -set_property -dict {LOC AE26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}] -set_property -dict {LOC AD24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}] -set_property -dict {LOC AC23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}] -set_property -dict {LOC AE23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}] -set_property -dict {LOC AD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}] -set_property -dict {LOC AC24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}] -set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}] -set_property -dict {LOC AD23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}] -set_property -dict {LOC AD21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}] -set_property -dict {LOC AB22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}] -set_property -dict {LOC AA22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}] -set_property -dict {LOC AE25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}] -set_property -dict {LOC AD26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}] -set_property -dict {LOC AB25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}] -set_property -dict {LOC AB26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}] -set_property -dict {LOC AD25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}] -set_property -dict {LOC AC26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}] -set_property -dict {LOC AB21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}] -set_property -dict {LOC AB24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}] -set_property -dict {LOC Y18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}] -set_property -dict {LOC AA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}] -set_property -dict {LOC AC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}] -set_property -dict {LOC Y20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}] -set_property -dict {LOC AF18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_ce_n}] -set_property -dict {LOC Y21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}] -set_property -dict {LOC AB20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}] -set_property -dict {LOC AF23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}] - -set_false_path -to [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}] -set_output_delay 0 [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}] -set_false_path -from [get_ports {flash_dq[*]}] -set_input_delay 0 [get_ports {flash_dq[*]}] diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gty.tcl deleted file mode 100644 index ea679b502..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gty.tcl +++ /dev/null @@ -1,129 +0,0 @@ -# Copyright 2022, The Regents of the University of California. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS -# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -# OF SUCH DAMAGE. -# -# The views and conclusions contained in the software and documentation are those -# of the authors and should not be interpreted as representing official policies, -# either expressed or implied, of The Regents of the University of California. - -set base_name {eth_xcvr_gty} - -set preset {GTY-10GBASE-R} - -set freerun_freq {125} -set line_rate {10.3125} -set sec_line_rate {0} -set refclk_freq {161.1328125} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {64} -set int_data_width $user_data_width -set rx_eq_mode {DFE} -set extra_ports [list] -set extra_pll_ports [list] -# DRP connections -lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out -lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out -# PLL reset and power down -lappend extra_pll_ports qpll0reset_in qpll1reset_in -lappend extra_pll_ports qpll0pd_in qpll1pd_in -# PLL clocking -lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out -lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out -# channel reset -lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out -lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out -# channel power down -lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in -# channel clock selection -lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in -# channel polarity -lappend extra_ports txpolarity_in rxpolarity_in -# channel TX driver -lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in -# channel CDR -lappend extra_ports rxcdrlock_out rxcdrhold_in -# channel EQ -lappend extra_ports rxlpmen_in -# channel digital monitor -lappend extra_ports dmonitorout_out -# channel PRBS -lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out -# channel eye scan -lappend extra_ports eyescandataerror_out -# channel loopback -lappend extra_ports loopback_in - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config RX_EQ_MODE $rx_eq_mode -if {$sec_line_rate != 0} { - dict set config SECONDARY_QPLL_ENABLE true - dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn - dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq -} else { - dict set config SECONDARY_QPLL_ENABLE false -} -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} -dict set config LOCATE_TX_USER_CLOCKING {CORE} -dict set config LOCATE_RX_USER_CLOCKING {CORE} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.tcl deleted file mode 100644 index 30333be04..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.tcl +++ /dev/null @@ -1,26 +0,0 @@ - -create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 - -set_property -dict [list \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ - CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ - CONFIG.axisten_if_enable_client_tag {true} \ - CONFIG.axisten_if_width {256_bit} \ - CONFIG.extended_tag_field {true} \ - CONFIG.axisten_freq {250} \ - CONFIG.PF0_CLASS_CODE {020000} \ - CONFIG.PF0_DEVICE_ID {1001} \ - CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ - CONFIG.PF0_SUBSYSTEM_ID {0009} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1ce4} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_prefetchable {true} \ - CONFIG.pf0_bar0_scale {Megabytes} \ - CONFIG.pf0_bar0_size {16} \ - CONFIG.vendor_id {1234} \ - CONFIG.en_msi_per_vec_masking {true} \ - CONFIG.mode_selection {Advanced} \ - CONFIG.en_gt_selection {true} \ - CONFIG.select_quad {GTY_Quad_225} \ -] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/lib b/fpga/mqnic/ExaNIC_X25/fpga_10g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v deleted file mode 100644 index fb475f1a1..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v +++ /dev/null @@ -1,1337 +0,0 @@ -/* - -Copyright 2019-2021, The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS -IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. - -The views and conclusions contained in the software and documentation are those -of the authors and should not be interpreted as representing official policies, -either expressed or implied, of The Regents of the University of California. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'h4A63093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h1ce4_0009, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - - // PTP configuration - parameter PTP_PEROUT_ENABLE = 1, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration (interface) - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, - - // TX and RX engine configuration (port) - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - - // Scheduler configuration (port) - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Timestamping configuration (port) - parameter PTP_TS_ENABLE = 1, - parameter TX_PTP_TS_FIFO_DEPTH = 32, - parameter RX_PTP_TS_FIFO_DEPTH = 32, - - // Interface configuration (port) - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // Application block configuration - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 256, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, - parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, - parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, - parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, - parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 64, - parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT, - parameter PCIE_DMA_READ_TX_LIMIT = 16, - parameter PCIE_DMA_READ_TX_FC_ENABLE = 1, - parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, - parameter PCIE_DMA_WRITE_TX_LIMIT = 3, - parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_TX_PIPELINE = 0, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, - parameter AXIS_ETH_TX_TS_PIPELINE = 0, - parameter AXIS_ETH_RX_PIPELINE = 0, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * GPIO - */ - output wire [1:0] sfp_1_led, - output wire [1:0] sfp_2_led, - output wire [1:0] sma_led, - - input wire sma_in, - output wire sma_out, - output wire sma_out_en, - output wire sma_term_en, - - /* - * PCI express - */ - input wire [7:0] pcie_rx_p, - input wire [7:0] pcie_rx_n, - output wire [7:0] pcie_tx_p, - output wire [7:0] pcie_tx_n, - input wire pcie_refclk_p, - input wire pcie_refclk_n, - input wire pcie_reset_n, - - /* - * Ethernet: SFP28 - */ - input wire sfp_1_rx_p, - input wire sfp_1_rx_n, - output wire sfp_1_tx_p, - output wire sfp_1_tx_n, - input wire sfp_2_rx_p, - input wire sfp_2_rx_n, - output wire sfp_2_tx_p, - output wire sfp_2_tx_n, - input wire sfp_mgt_refclk_p, - input wire sfp_mgt_refclk_n, - output wire sfp_1_tx_disable, - output wire sfp_2_tx_disable, - input wire sfp_1_npres, - input wire sfp_2_npres, - input wire sfp_1_los, - input wire sfp_2_los, - output wire sfp_1_rs, - output wire sfp_2_rs, - - inout wire sfp_i2c_scl, - inout wire sfp_1_i2c_sda, - inout wire sfp_2_i2c_sda, - - inout wire eeprom_i2c_scl, - inout wire eeprom_i2c_sda, - - /* - * BPI Flash - */ - inout wire [15:0] flash_dq, - output wire [22:0] flash_addr, - output wire flash_region, - output wire flash_ce_n, - output wire flash_oe_n, - output wire flash_we_n, - output wire flash_adv_n -); - -// PTP configuration -parameter PTP_TS_WIDTH = 96; -parameter PTP_TAG_WIDTH = 16; -parameter PTP_PERIOD_NS_WIDTH = 4; -parameter PTP_OFFSET_NS_WIDTH = 32; -parameter PTP_FNS_WIDTH = 32; -parameter PTP_PERIOD_NS = 4'd4; -parameter PTP_PERIOD_FNS = 32'd0; -parameter PTP_USE_SAMPLE_CLOCK = 0; -parameter IF_PTP_PERIOD_NS = 6'h6; -parameter IF_PTP_PERIOD_FNS = 16'h6666; - -// PCIe interface configuration -parameter MSI_COUNT = 32; - -// Ethernet interface configuration -parameter XGMII_DATA_WIDTH = 64; -parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; -parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; -parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire pcie_user_clk; -wire pcie_user_reset; - -wire clk_161mhz_int; - -wire clk_125mhz_mmcm_out; - -// Internal 125 MHz clock -wire clk_125mhz_int; -wire rst_125mhz_int; - -wire mmcm_rst = pcie_user_reset; -wire mmcm_locked; -wire mmcm_clkfb; - -// MMCM instance -// 161.13 MHz in, 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 64, D = 11 sets Fvco = 937.5 MHz (in range) -// Divide by 7.5 to get output frequency of 125 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(7.5), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(1), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(64), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(11), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_161mhz_int), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_125mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// GPIO -wire sfp_1_npres_int; -wire sfp_2_npres_int; -wire sfp_1_los_int; -wire sfp_2_los_int; -wire sfp_i2c_scl_i; -wire sfp_i2c_scl_o; -wire sfp_i2c_scl_t; -wire sfp_1_i2c_sda_i; -wire sfp_1_i2c_sda_o; -wire sfp_1_i2c_sda_t; -wire sfp_2_i2c_sda_i; -wire sfp_2_i2c_sda_o; -wire sfp_2_i2c_sda_t; -wire eeprom_i2c_scl_i; -wire eeprom_i2c_scl_o; -wire eeprom_i2c_scl_t; -wire eeprom_i2c_sda_i; -wire eeprom_i2c_sda_o; -wire eeprom_i2c_sda_t; - -reg sfp_i2c_scl_o_reg; -reg sfp_i2c_scl_t_reg; -reg sfp_1_i2c_sda_o_reg; -reg sfp_1_i2c_sda_t_reg; -reg sfp_2_i2c_sda_o_reg; -reg sfp_2_i2c_sda_t_reg; -reg eeprom_i2c_scl_o_reg; -reg eeprom_i2c_scl_t_reg; -reg eeprom_i2c_sda_o_reg; -reg eeprom_i2c_sda_t_reg; - -always @(posedge pcie_user_clk) begin - sfp_i2c_scl_o_reg <= sfp_i2c_scl_o; - sfp_i2c_scl_t_reg <= sfp_i2c_scl_t; - sfp_1_i2c_sda_o_reg <= sfp_1_i2c_sda_o; - sfp_1_i2c_sda_t_reg <= sfp_1_i2c_sda_t; - sfp_2_i2c_sda_o_reg <= sfp_2_i2c_sda_o; - sfp_2_i2c_sda_t_reg <= sfp_2_i2c_sda_t; - eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o; - eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t; - eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o; - eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t; -end - -sync_signal #( - .WIDTH(9), - .N(2) -) -sync_signal_inst ( - .clk(pcie_user_clk), - .in({sfp_1_npres, sfp_2_npres, sfp_1_los, sfp_2_los, - sfp_i2c_scl, sfp_1_i2c_sda, sfp_2_i2c_sda, - eeprom_i2c_scl, eeprom_i2c_sda}), - .out({sfp_1_npres_int, sfp_2_npres_int, sfp_1_los_int, sfp_2_los_int, - sfp_i2c_scl_i, sfp_1_i2c_sda_i, sfp_2_i2c_sda_i, - eeprom_i2c_scl_i, eeprom_i2c_sda_i}) -); - -assign sfp_i2c_scl = sfp_i2c_scl_t_reg ? 1'bz : sfp_i2c_scl_o_reg; -assign sfp_1_i2c_sda = sfp_1_i2c_sda_t_reg ? 1'bz : sfp_1_i2c_sda_o_reg; -assign sfp_2_i2c_sda = sfp_2_i2c_sda_t_reg ? 1'bz : sfp_2_i2c_sda_o_reg; -assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg; -assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg; - -// Flash -wire [15:0] flash_dq_i_int; -wire [15:0] flash_dq_o_int; -wire flash_dq_oe_int; -wire [22:0] flash_addr_int; -wire flash_region_int; -wire flash_region_oe_int; -wire flash_ce_n_int; -wire flash_oe_n_int; -wire flash_we_n_int; -wire flash_adv_n_int; - -reg [15:0] flash_dq_o_reg; -reg flash_dq_oe_reg; -reg [22:0] flash_addr_reg; -reg flash_region_reg; -reg flash_region_oe_reg; -reg flash_ce_n_reg; -reg flash_oe_n_reg; -reg flash_we_n_reg; -reg flash_adv_n_reg; - -always @(posedge pcie_user_clk) begin - flash_dq_o_reg <= flash_dq_o_int; - flash_dq_oe_reg <= flash_dq_oe_int; - flash_addr_reg <= flash_addr_int; - flash_region_reg <= flash_region_int; - flash_region_oe_reg <= flash_region_oe_int; - flash_ce_n_reg <= flash_ce_n_int; - flash_oe_n_reg <= flash_oe_n_int; - flash_we_n_reg <= flash_we_n_int; - flash_adv_n_reg <= flash_adv_n_int; -end - -assign flash_dq = flash_dq_oe_reg ? flash_dq_o_reg : 16'hzzzz; -assign flash_addr = flash_addr_reg; -assign flash_region = flash_region_oe_reg ? flash_region_reg : 1'bz; -assign flash_ce_n = flash_ce_n_reg; -assign flash_oe_n = flash_oe_n_reg; -assign flash_we_n = flash_we_n_reg; -assign flash_adv_n = flash_adv_n_reg; - -sync_signal #( - .WIDTH(16), - .N(2) -) -flash_sync_signal_inst ( - .clk(pcie_user_clk), - .in(flash_dq), - .out(flash_dq_i_int) -); - -// FPGA boot -wire fpga_boot; - -reg fpga_boot_sync_reg_0 = 1'b0; -reg fpga_boot_sync_reg_1 = 1'b0; -reg fpga_boot_sync_reg_2 = 1'b0; - -wire icap_avail; -reg [2:0] icap_state = 0; -reg icap_csib_reg = 1'b1; -reg icap_rdwrb_reg = 1'b0; -reg [31:0] icap_di_reg = 32'hffffffff; - -wire [31:0] icap_di_rev; - -assign icap_di_rev[ 7] = icap_di_reg[ 0]; -assign icap_di_rev[ 6] = icap_di_reg[ 1]; -assign icap_di_rev[ 5] = icap_di_reg[ 2]; -assign icap_di_rev[ 4] = icap_di_reg[ 3]; -assign icap_di_rev[ 3] = icap_di_reg[ 4]; -assign icap_di_rev[ 2] = icap_di_reg[ 5]; -assign icap_di_rev[ 1] = icap_di_reg[ 6]; -assign icap_di_rev[ 0] = icap_di_reg[ 7]; - -assign icap_di_rev[15] = icap_di_reg[ 8]; -assign icap_di_rev[14] = icap_di_reg[ 9]; -assign icap_di_rev[13] = icap_di_reg[10]; -assign icap_di_rev[12] = icap_di_reg[11]; -assign icap_di_rev[11] = icap_di_reg[12]; -assign icap_di_rev[10] = icap_di_reg[13]; -assign icap_di_rev[ 9] = icap_di_reg[14]; -assign icap_di_rev[ 8] = icap_di_reg[15]; - -assign icap_di_rev[23] = icap_di_reg[16]; -assign icap_di_rev[22] = icap_di_reg[17]; -assign icap_di_rev[21] = icap_di_reg[18]; -assign icap_di_rev[20] = icap_di_reg[19]; -assign icap_di_rev[19] = icap_di_reg[20]; -assign icap_di_rev[18] = icap_di_reg[21]; -assign icap_di_rev[17] = icap_di_reg[22]; -assign icap_di_rev[16] = icap_di_reg[23]; - -assign icap_di_rev[31] = icap_di_reg[24]; -assign icap_di_rev[30] = icap_di_reg[25]; -assign icap_di_rev[29] = icap_di_reg[26]; -assign icap_di_rev[28] = icap_di_reg[27]; -assign icap_di_rev[27] = icap_di_reg[28]; -assign icap_di_rev[26] = icap_di_reg[29]; -assign icap_di_rev[25] = icap_di_reg[30]; -assign icap_di_rev[24] = icap_di_reg[31]; - -always @(posedge clk_125mhz_int) begin - case (icap_state) - 0: begin - icap_state <= 0; - icap_csib_reg <= 1'b1; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - - if (fpga_boot_sync_reg_2 && icap_avail) begin - icap_state <= 1; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - end - end - 1: begin - icap_state <= 2; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hAA995566; // sync word - end - 2: begin - icap_state <= 3; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - 3: begin - icap_state <= 4; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h30008001; // write 1 word to CMD - end - 4: begin - icap_state <= 5; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h0000000F; // IPROG - end - 5: begin - icap_state <= 0; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - endcase - - fpga_boot_sync_reg_0 <= fpga_boot; - fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; - fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; -end - -ICAPE3 -icape3_inst ( - .AVAIL(icap_avail), - .CLK(clk_125mhz_int), - .CSIB(icap_csib_reg), - .I(icap_di_rev), - .O(), - .PRDONE(), - .PRERROR(), - .RDWRB(icap_rdwrb_reg) -); - -// PCIe -wire pcie_sys_clk; -wire pcie_sys_clk_gt; - -IBUFDS_GTE4 #( - .REFCLK_HROW_CK_SEL(2'b00) -) -ibufds_gte4_pcie_mgt_refclk_inst ( - .I (pcie_refclk_p), - .IB (pcie_refclk_n), - .CEB (1'b0), - .O (pcie_sys_clk_gt), - .ODIV2 (pcie_sys_clk) -); - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; -wire axis_rq_tlast; -wire axis_rq_tready; -wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; -wire axis_rq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; -wire axis_rc_tlast; -wire axis_rc_tready; -wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; -wire axis_rc_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; -wire axis_cq_tlast; -wire axis_cq_tready; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; -wire axis_cq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; -wire axis_cc_tlast; -wire axis_cc_tready; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; -wire axis_cc_tvalid; - -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; -wire pcie_rq_seq_num_vld0; -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; -wire pcie_rq_seq_num_vld1; - -wire [3:0] pcie_tfc_nph_av; -wire [3:0] pcie_tfc_npd_av; - -wire [2:0] cfg_max_payload; -wire [2:0] cfg_max_read_req; - -wire [9:0] cfg_mgmt_addr; -wire [7:0] cfg_mgmt_function_number; -wire cfg_mgmt_write; -wire [31:0] cfg_mgmt_write_data; -wire [3:0] cfg_mgmt_byte_enable; -wire cfg_mgmt_read; -wire [31:0] cfg_mgmt_read_data; -wire cfg_mgmt_read_write_done; - -wire [7:0] cfg_fc_ph; -wire [11:0] cfg_fc_pd; -wire [7:0] cfg_fc_nph; -wire [11:0] cfg_fc_npd; -wire [7:0] cfg_fc_cplh; -wire [11:0] cfg_fc_cpld; -wire [2:0] cfg_fc_sel; - -wire [3:0] cfg_interrupt_msi_enable; -wire [11:0] cfg_interrupt_msi_mmenable; -wire cfg_interrupt_msi_mask_update; -wire [31:0] cfg_interrupt_msi_data; -wire [3:0] cfg_interrupt_msi_select; -wire [31:0] cfg_interrupt_msi_int; -wire [31:0] cfg_interrupt_msi_pending_status; -wire cfg_interrupt_msi_pending_status_data_enable; -wire [3:0] cfg_interrupt_msi_pending_status_function_num; -wire cfg_interrupt_msi_sent; -wire cfg_interrupt_msi_fail; -wire [2:0] cfg_interrupt_msi_attr; -wire cfg_interrupt_msi_tph_present; -wire [1:0] cfg_interrupt_msi_tph_type; -wire [8:0] cfg_interrupt_msi_tph_st_tag; -wire [3:0] cfg_interrupt_msi_function_number; - -wire status_error_cor; -wire status_error_uncor; - -// extra register for pcie_user_reset signal -wire pcie_user_reset_int; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_2 = 1'b1; - -always @(posedge pcie_user_clk) begin - pcie_user_reset_reg_1 <= pcie_user_reset_int; - pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; -end - -assign pcie_user_reset = pcie_user_reset_reg_2; - -// ila_0 ila_rq ( -// .clk(pcie_user_clk), -// .trig_out(), -// .trig_out_ack(1'b0), -// .trig_in(1'b0), -// .trig_in_ack(), -// .probe0(axis_rq_tdata), -// .probe1(axis_rq_tkeep), -// .probe2(axis_rq_tvalid), -// .probe3(axis_rq_tready), -// .probe4({pcie_tfc_npd_av, pcie_tfc_nph_av, axis_rq_tuser}), -// .probe5(axis_rq_tlast) -// ); - -// ila_0 ila_rc ( -// .clk(pcie_user_clk), -// .trig_out(), -// .trig_out_ack(1'b0), -// .trig_in(1'b0), -// .trig_in_ack(), -// .probe0(axis_rc_tdata), -// .probe1(axis_rc_tkeep), -// .probe2(axis_rc_tvalid), -// .probe3(axis_rc_tready), -// .probe4(axis_rc_tuser), -// .probe5(axis_rc_tlast) -// ); - -pcie4_uscale_plus_0 -pcie4_uscale_plus_inst ( - .pci_exp_txn(pcie_tx_n), - .pci_exp_txp(pcie_tx_p), - .pci_exp_rxn(pcie_rx_n), - .pci_exp_rxp(pcie_rx_p), - .user_clk(pcie_user_clk), - .user_reset(pcie_user_reset_int), - .user_lnk_up(), - - .s_axis_rq_tdata(axis_rq_tdata), - .s_axis_rq_tkeep(axis_rq_tkeep), - .s_axis_rq_tlast(axis_rq_tlast), - .s_axis_rq_tready(axis_rq_tready), - .s_axis_rq_tuser(axis_rq_tuser), - .s_axis_rq_tvalid(axis_rq_tvalid), - - .m_axis_rc_tdata(axis_rc_tdata), - .m_axis_rc_tkeep(axis_rc_tkeep), - .m_axis_rc_tlast(axis_rc_tlast), - .m_axis_rc_tready(axis_rc_tready), - .m_axis_rc_tuser(axis_rc_tuser), - .m_axis_rc_tvalid(axis_rc_tvalid), - - .m_axis_cq_tdata(axis_cq_tdata), - .m_axis_cq_tkeep(axis_cq_tkeep), - .m_axis_cq_tlast(axis_cq_tlast), - .m_axis_cq_tready(axis_cq_tready), - .m_axis_cq_tuser(axis_cq_tuser), - .m_axis_cq_tvalid(axis_cq_tvalid), - - .s_axis_cc_tdata(axis_cc_tdata), - .s_axis_cc_tkeep(axis_cc_tkeep), - .s_axis_cc_tlast(axis_cc_tlast), - .s_axis_cc_tready(axis_cc_tready), - .s_axis_cc_tuser(axis_cc_tuser), - .s_axis_cc_tvalid(axis_cc_tvalid), - - .pcie_rq_seq_num0(pcie_rq_seq_num0), - .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), - .pcie_rq_seq_num1(pcie_rq_seq_num1), - .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), - .pcie_rq_tag0(), - .pcie_rq_tag1(), - .pcie_rq_tag_av(), - .pcie_rq_tag_vld0(), - .pcie_rq_tag_vld1(), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .pcie_cq_np_req(1'b1), - .pcie_cq_np_req_count(), - - .cfg_phy_link_down(), - .cfg_phy_link_status(), - .cfg_negotiated_width(), - .cfg_current_speed(), - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_function_status(), - .cfg_function_power_state(), - .cfg_vf_status(), - .cfg_vf_power_state(), - .cfg_link_power_state(), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - .cfg_mgmt_debug_access(1'b0), - - .cfg_err_cor_out(), - .cfg_err_nonfatal_out(), - .cfg_err_fatal_out(), - .cfg_local_error_valid(), - .cfg_local_error_out(), - .cfg_ltssm_state(), - .cfg_rx_pm_state(), - .cfg_tx_pm_state(), - .cfg_rcb_status(), - .cfg_obff_enable(), - .cfg_pl_status_change(), - .cfg_tph_requester_enable(), - .cfg_tph_st_mode(), - .cfg_vf_tph_requester_enable(), - .cfg_vf_tph_st_mode(), - - .cfg_msg_received(), - .cfg_msg_received_data(), - .cfg_msg_received_type(), - .cfg_msg_transmit(1'b0), - .cfg_msg_transmit_type(3'd0), - .cfg_msg_transmit_data(32'd0), - .cfg_msg_transmit_done(), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_dsn(64'd0), - - .cfg_power_state_change_ack(1'b1), - .cfg_power_state_change_interrupt(), - - .cfg_err_cor_in(status_error_cor), - .cfg_err_uncor_in(status_error_uncor), - .cfg_flr_in_process(), - .cfg_flr_done(4'd0), - .cfg_vf_flr_in_process(), - .cfg_vf_flr_func_num(8'd0), - .cfg_vf_flr_done(8'd0), - - .cfg_link_training_enable(1'b1), - - .cfg_interrupt_int(4'd0), - .cfg_interrupt_pending(4'd0), - .cfg_interrupt_sent(), - .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), - .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), - .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), - .cfg_interrupt_msi_data(cfg_interrupt_msi_data), - .cfg_interrupt_msi_select(cfg_interrupt_msi_select), - .cfg_interrupt_msi_int(cfg_interrupt_msi_int), - .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), - .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), - .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), - .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), - .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), - .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), - .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), - .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .cfg_pm_aspm_l1_entry_reject(1'b0), - .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), - - .cfg_hot_reset_out(), - - .cfg_config_space_enable(1'b1), - .cfg_req_pm_transition_l23_ready(1'b0), - .cfg_hot_reset_in(1'b0), - - .cfg_ds_port_number(8'd0), - .cfg_ds_bus_number(8'd0), - .cfg_ds_device_number(5'd0), - //.cfg_ds_function_number(3'd0), - - //.cfg_subsys_vend_id(16'h1234), - - .sys_clk(pcie_sys_clk), - .sys_clk_gt(pcie_sys_clk_gt), - .sys_reset(pcie_reset_n), - - // .int_qpll0lock_out(), - // .int_qpll0outrefclk_out(), - // .int_qpll0outclk_out(), - // .int_qpll1lock_out(), - // .int_qpll1outrefclk_out(), - // .int_qpll1outclk_out(), - .phy_rdy_out() -); - -// XGMII 10G PHY -wire sfp_1_tx_clk_int; -wire sfp_1_tx_rst_int; -wire [XGMII_DATA_WIDTH-1:0] sfp_1_txd_int; -wire [XGMII_CTRL_WIDTH-1:0] sfp_1_txc_int; -wire sfp_1_tx_prbs31_enable_int; -wire sfp_1_rx_clk_int; -wire sfp_1_rx_rst_int; -wire [XGMII_DATA_WIDTH-1:0] sfp_1_rxd_int; -wire [XGMII_CTRL_WIDTH-1:0] sfp_1_rxc_int; -wire sfp_1_rx_prbs31_enable_int; -wire [6:0] sfp_1_rx_error_count_int; - -wire sfp_2_tx_clk_int; -wire sfp_2_tx_rst_int; -wire [XGMII_DATA_WIDTH-1:0] sfp_2_txd_int; -wire [XGMII_CTRL_WIDTH-1:0] sfp_2_txc_int; -wire sfp_2_tx_prbs31_enable_int; -wire sfp_2_rx_clk_int; -wire sfp_2_rx_rst_int; -wire [XGMII_DATA_WIDTH-1:0] sfp_2_rxd_int; -wire [XGMII_CTRL_WIDTH-1:0] sfp_2_rxc_int; -wire sfp_2_rx_prbs31_enable_int; -wire [6:0] sfp_2_rx_error_count_int; - -wire sfp_drp_clk = clk_125mhz_int; -wire sfp_drp_rst = rst_125mhz_int; -wire [23:0] sfp_drp_addr; -wire [15:0] sfp_drp_di; -wire sfp_drp_en; -wire sfp_drp_we; -wire [15:0] sfp_drp_do; -wire sfp_drp_rdy; - -wire sfp_1_rx_block_lock; -wire sfp_2_rx_block_lock; - -wire sfp_gtpowergood; - -wire sfp_mgt_refclk; -wire sfp_mgt_refclk_int; -wire sfp_mgt_refclk_bufg; - -assign clk_161mhz_int = sfp_mgt_refclk_bufg; - -IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_inst ( - .I (sfp_mgt_refclk_p), - .IB (sfp_mgt_refclk_n), - .CEB (1'b0), - .O (sfp_mgt_refclk), - .ODIV2 (sfp_mgt_refclk_int) -); - -BUFG_GT bufg_gt_sfp_mgt_refclk_inst ( - .CE (sfp_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (sfp_mgt_refclk_int), - .O (sfp_mgt_refclk_bufg) -); - -wire sfp_rst; - -sync_reset #( - .N(4) -) -sfp_sync_reset_inst ( - .clk(sfp_mgt_refclk_bufg), - .rst(rst_125mhz_int), - .out(sfp_rst) -); - -eth_xcvr_phy_10g_gty_quad_wrapper #( - .COUNT(2), - .GT_1_TX_POLARITY(1'b1), - .GT_2_TX_POLARITY(1'b1), - .PRBS31_ENABLE(1) -) -sfp_phy_quad_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(sfp_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(sfp_gtpowergood), - .xcvr_ref_clk(sfp_mgt_refclk), - - /* - * DRP - */ - .drp_clk(sfp_drp_clk), - .drp_rst(sfp_drp_rst), - .drp_addr(sfp_drp_addr), - .drp_di(sfp_drp_di), - .drp_en(sfp_drp_en), - .drp_we(sfp_drp_we), - .drp_do(sfp_drp_do), - .drp_rdy(sfp_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp({sfp_2_tx_p, sfp_1_tx_p}), - .xcvr_txn({sfp_2_tx_n, sfp_1_tx_n}), - .xcvr_rxp({sfp_2_rx_p, sfp_1_rx_p}), - .xcvr_rxn({sfp_2_rx_n, sfp_1_rx_n}), - - /* - * PHY connections - */ - .phy_1_tx_clk(sfp_1_tx_clk_int), - .phy_1_tx_rst(sfp_1_tx_rst_int), - .phy_1_xgmii_txd(sfp_1_txd_int), - .phy_1_xgmii_txc(sfp_1_txc_int), - .phy_1_rx_clk(sfp_1_rx_clk_int), - .phy_1_rx_rst(sfp_1_rx_rst_int), - .phy_1_xgmii_rxd(sfp_1_rxd_int), - .phy_1_xgmii_rxc(sfp_1_rxc_int), - .phy_1_tx_bad_block(), - .phy_1_rx_error_count(sfp_1_rx_error_count_int), - .phy_1_rx_bad_block(), - .phy_1_rx_sequence_error(), - .phy_1_rx_block_lock(sfp_1_rx_block_lock), - .phy_1_rx_high_ber(), - .phy_1_tx_prbs31_enable(sfp_1_tx_prbs31_enable_int), - .phy_1_rx_prbs31_enable(sfp_1_rx_prbs31_enable_int), - - .phy_2_tx_clk(sfp_2_tx_clk_int), - .phy_2_tx_rst(sfp_2_tx_rst_int), - .phy_2_xgmii_txd(sfp_2_txd_int), - .phy_2_xgmii_txc(sfp_2_txc_int), - .phy_2_rx_clk(sfp_2_rx_clk_int), - .phy_2_rx_rst(sfp_2_rx_rst_int), - .phy_2_xgmii_rxd(sfp_2_rxd_int), - .phy_2_xgmii_rxc(sfp_2_rxc_int), - .phy_2_tx_bad_block(), - .phy_2_rx_error_count(sfp_2_rx_error_count_int), - .phy_2_rx_bad_block(), - .phy_2_rx_sequence_error(), - .phy_2_rx_block_lock(sfp_2_rx_block_lock), - .phy_2_rx_high_ber(), - .phy_2_tx_prbs31_enable(sfp_2_tx_prbs31_enable_int), - .phy_2_rx_prbs31_enable(sfp_2_rx_prbs31_enable_int) -); - -assign sfp_1_led[0] = sfp_1_rx_block_lock; -assign sfp_1_led[1] = 1'b0; -assign sfp_2_led[0] = sfp_2_rx_block_lock; -assign sfp_2_led[1] = 1'b0; - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - // PTP configuration - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH), - .PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH), - .PTP_FNS_WIDTH(PTP_FNS_WIDTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration (interface) - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), - - // TX and RX engine configuration (port) - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - - // Scheduler configuration (port) - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Timestamping configuration (port) - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH), - .RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH), - - // Interface configuration (port) - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // Application block configuration - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - .PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE), - .PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT), - .PCIE_DMA_READ_TX_FC_ENABLE(PCIE_DMA_READ_TX_FC_ENABLE), - .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), - .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), - .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), - .MSI_COUNT(MSI_COUNT), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_user_clk), - .rst_250mhz(pcie_user_reset), - - /* - * GPIO - */ - //.sfp_1_led(sfp_1_led), - //.sfp_2_led(sfp_2_led), - .sma_led(sma_led), - - .sma_in(sma_in), - .sma_out(sma_out), - .sma_out_en(sma_out_en), - .sma_term_en(sma_term_en), - - /* - * PCIe - */ - .m_axis_rq_tdata(axis_rq_tdata), - .m_axis_rq_tkeep(axis_rq_tkeep), - .m_axis_rq_tlast(axis_rq_tlast), - .m_axis_rq_tready(axis_rq_tready), - .m_axis_rq_tuser(axis_rq_tuser), - .m_axis_rq_tvalid(axis_rq_tvalid), - - .s_axis_rc_tdata(axis_rc_tdata), - .s_axis_rc_tkeep(axis_rc_tkeep), - .s_axis_rc_tlast(axis_rc_tlast), - .s_axis_rc_tready(axis_rc_tready), - .s_axis_rc_tuser(axis_rc_tuser), - .s_axis_rc_tvalid(axis_rc_tvalid), - - .s_axis_cq_tdata(axis_cq_tdata), - .s_axis_cq_tkeep(axis_cq_tkeep), - .s_axis_cq_tlast(axis_cq_tlast), - .s_axis_cq_tready(axis_cq_tready), - .s_axis_cq_tuser(axis_cq_tuser), - .s_axis_cq_tvalid(axis_cq_tvalid), - - .m_axis_cc_tdata(axis_cc_tdata), - .m_axis_cc_tkeep(axis_cc_tkeep), - .m_axis_cc_tlast(axis_cc_tlast), - .m_axis_cc_tready(axis_cc_tready), - .m_axis_cc_tuser(axis_cc_tuser), - .m_axis_cc_tvalid(axis_cc_tvalid), - - .s_axis_rq_seq_num_0(pcie_rq_seq_num0), - .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0), - .s_axis_rq_seq_num_1(pcie_rq_seq_num1), - .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), - .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), - .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), - .cfg_interrupt_msi_data(cfg_interrupt_msi_data), - .cfg_interrupt_msi_select(cfg_interrupt_msi_select), - .cfg_interrupt_msi_int(cfg_interrupt_msi_int), - .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), - .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), - .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), - .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), - .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), - .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), - .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), - .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * Ethernet: SFP+ - */ - .sfp_1_tx_clk(sfp_1_tx_clk_int), - .sfp_1_tx_rst(sfp_1_tx_rst_int), - .sfp_1_txd(sfp_1_txd_int), - .sfp_1_txc(sfp_1_txc_int), - .sfp_1_tx_prbs31_enable(sfp_1_tx_prbs31_enable_int), - .sfp_1_rx_clk(sfp_1_rx_clk_int), - .sfp_1_rx_rst(sfp_1_rx_rst_int), - .sfp_1_rxd(sfp_1_rxd_int), - .sfp_1_rxc(sfp_1_rxc_int), - .sfp_1_rx_prbs31_enable(sfp_1_rx_prbs31_enable_int), - .sfp_1_rx_error_count(sfp_1_rx_error_count_int), - - .sfp_2_tx_clk(sfp_2_tx_clk_int), - .sfp_2_tx_rst(sfp_2_tx_rst_int), - .sfp_2_txd(sfp_2_txd_int), - .sfp_2_txc(sfp_2_txc_int), - .sfp_2_tx_prbs31_enable(sfp_2_tx_prbs31_enable_int), - .sfp_2_rx_clk(sfp_2_rx_clk_int), - .sfp_2_rx_rst(sfp_2_rx_rst_int), - .sfp_2_rxd(sfp_2_rxd_int), - .sfp_2_rxc(sfp_2_rxc_int), - .sfp_2_rx_prbs31_enable(sfp_2_rx_prbs31_enable_int), - .sfp_2_rx_error_count(sfp_2_rx_error_count_int), - - .sfp_drp_clk(sfp_drp_clk), - .sfp_drp_rst(sfp_drp_rst), - .sfp_drp_addr(sfp_drp_addr), - .sfp_drp_di(sfp_drp_di), - .sfp_drp_en(sfp_drp_en), - .sfp_drp_we(sfp_drp_we), - .sfp_drp_do(sfp_drp_do), - .sfp_drp_rdy(sfp_drp_rdy), - - .sfp_1_tx_disable(sfp_1_tx_disable), - .sfp_2_tx_disable(sfp_2_tx_disable), - .sfp_1_npres(sfp_1_npres_int), - .sfp_2_npres(sfp_2_npres_int), - .sfp_1_los(sfp_1_los_int), - .sfp_2_los(sfp_2_los_int), - .sfp_1_rs(sfp_1_rs), - .sfp_2_rs(sfp_2_rs), - - .sfp_i2c_scl_i(sfp_i2c_scl_i), - .sfp_i2c_scl_o(sfp_i2c_scl_o), - .sfp_i2c_scl_t(sfp_i2c_scl_t), - .sfp_1_i2c_sda_i(sfp_1_i2c_sda_i), - .sfp_1_i2c_sda_o(sfp_1_i2c_sda_o), - .sfp_1_i2c_sda_t(sfp_1_i2c_sda_t), - .sfp_2_i2c_sda_i(sfp_2_i2c_sda_i), - .sfp_2_i2c_sda_o(sfp_2_i2c_sda_o), - .sfp_2_i2c_sda_t(sfp_2_i2c_sda_t), - - .eeprom_i2c_scl_i(eeprom_i2c_scl_i), - .eeprom_i2c_scl_o(eeprom_i2c_scl_o), - .eeprom_i2c_scl_t(eeprom_i2c_scl_t), - .eeprom_i2c_sda_i(eeprom_i2c_sda_i), - .eeprom_i2c_sda_o(eeprom_i2c_sda_o), - .eeprom_i2c_sda_t(eeprom_i2c_sda_t), - - /* - * BPI flash - */ - .fpga_boot(fpga_boot), - .flash_dq_i(flash_dq_i_int), - .flash_dq_o(flash_dq_o_int), - .flash_dq_oe(flash_dq_oe_int), - .flash_addr(flash_addr_int), - .flash_region(flash_region_int), - .flash_region_oe(flash_region_oe_int), - .flash_ce_n(flash_ce_n_int), - .flash_oe_n(flash_oe_n_int), - .flash_we_n(flash_we_n_int), - .flash_adv_n(flash_adv_n_int) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v deleted file mode 100644 index 5ace64693..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v +++ /dev/null @@ -1,1298 +0,0 @@ -/* - -Copyright 2019-2021, The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS -IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. - -The views and conclusions contained in the software and documentation are those -of the authors and should not be interpreted as representing official policies, -either expressed or implied, of The Regents of the University of California. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'h4A63093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h1ce4_0009, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - - // PTP configuration - parameter PTP_TS_WIDTH = 96, - parameter PTP_TAG_WIDTH = 16, - parameter PTP_PERIOD_NS_WIDTH = 4, - parameter PTP_OFFSET_NS_WIDTH = 32, - parameter PTP_FNS_WIDTH = 32, - parameter PTP_PERIOD_NS = 4'd4, - parameter PTP_PERIOD_FNS = 32'd0, - parameter PTP_USE_SAMPLE_CLOCK = 0, - parameter PTP_PEROUT_ENABLE = 1, - parameter PTP_PEROUT_COUNT = 1, - parameter IF_PTP_PERIOD_NS = 6'h6, - parameter IF_PTP_PERIOD_FNS = 16'h6666, - - // Queue manager configuration (interface) - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, - - // TX and RX engine configuration (port) - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - - // Scheduler configuration (port) - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Timestamping configuration (port) - parameter PTP_TS_ENABLE = 1, - parameter TX_PTP_TS_FIFO_DEPTH = 32, - parameter RX_PTP_TS_FIFO_DEPTH = 32, - - // Interface configuration (port) - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_RSS_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter ENABLE_PADDING = 1, - parameter ENABLE_DIC = 1, - parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // Application block configuration - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 256, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, - parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, - parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, - parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, - parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 64, - parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT, - parameter PCIE_DMA_READ_TX_LIMIT = 16, - parameter PCIE_DMA_READ_TX_FC_ENABLE = 1, - parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, - parameter PCIE_DMA_WRITE_TX_LIMIT = 3, - parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, - parameter MSI_COUNT = 32, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter XGMII_DATA_WIDTH = 64, - parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, - parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH, - parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 0, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, - parameter AXIS_ETH_TX_TS_PIPELINE = 0, - parameter AXIS_ETH_RX_PIPELINE = 0, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * GPIO - */ - output wire [1:0] sfp_1_led, - output wire [1:0] sfp_2_led, - output wire [1:0] sma_led, - - input wire sma_in, - output wire sma_out, - output wire sma_out_en, - output wire sma_term_en, - - /* - * PCIe - */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, - - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, - - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, - - input wire [1:0] pcie_tfc_nph_av, - input wire [1:0] pcie_tfc_npd_av, - - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, - - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - input wire [3:0] cfg_interrupt_msi_enable, - input wire [11:0] cfg_interrupt_msi_mmenable, - input wire cfg_interrupt_msi_mask_update, - input wire [31:0] cfg_interrupt_msi_data, - output wire [3:0] cfg_interrupt_msi_select, - output wire [31:0] cfg_interrupt_msi_int, - output wire [31:0] cfg_interrupt_msi_pending_status, - output wire cfg_interrupt_msi_pending_status_data_enable, - output wire [3:0] cfg_interrupt_msi_pending_status_function_num, - input wire cfg_interrupt_msi_sent, - input wire cfg_interrupt_msi_fail, - output wire [2:0] cfg_interrupt_msi_attr, - output wire cfg_interrupt_msi_tph_present, - output wire [1:0] cfg_interrupt_msi_tph_type, - output wire [8:0] cfg_interrupt_msi_tph_st_tag, - output wire [3:0] cfg_interrupt_msi_function_number, - - output wire status_error_cor, - output wire status_error_uncor, - - /* - * Ethernet: SFP28 - */ - input wire sfp_1_tx_clk, - input wire sfp_1_tx_rst, - output wire [XGMII_DATA_WIDTH-1:0] sfp_1_txd, - output wire [XGMII_CTRL_WIDTH-1:0] sfp_1_txc, - output wire sfp_1_tx_prbs31_enable, - input wire sfp_1_rx_clk, - input wire sfp_1_rx_rst, - input wire [XGMII_DATA_WIDTH-1:0] sfp_1_rxd, - input wire [XGMII_CTRL_WIDTH-1:0] sfp_1_rxc, - output wire sfp_1_rx_prbs31_enable, - input wire [6:0] sfp_1_rx_error_count, - - input wire sfp_2_tx_clk, - input wire sfp_2_tx_rst, - output wire [XGMII_DATA_WIDTH-1:0] sfp_2_txd, - output wire [XGMII_CTRL_WIDTH-1:0] sfp_2_txc, - output wire sfp_2_tx_prbs31_enable, - input wire sfp_2_rx_clk, - input wire sfp_2_rx_rst, - input wire [XGMII_DATA_WIDTH-1:0] sfp_2_rxd, - input wire [XGMII_CTRL_WIDTH-1:0] sfp_2_rxc, - output wire sfp_2_rx_prbs31_enable, - input wire [6:0] sfp_2_rx_error_count, - - input wire sfp_drp_clk, - input wire sfp_drp_rst, - output wire [23:0] sfp_drp_addr, - output wire [15:0] sfp_drp_di, - output wire sfp_drp_en, - output wire sfp_drp_we, - input wire [15:0] sfp_drp_do, - input wire sfp_drp_rdy, - - output wire sfp_1_tx_disable, - output wire sfp_2_tx_disable, - input wire sfp_1_npres, - input wire sfp_2_npres, - input wire sfp_1_los, - input wire sfp_2_los, - output wire sfp_1_rs, - output wire sfp_2_rs, - - input wire sfp_i2c_scl_i, - output wire sfp_i2c_scl_o, - output wire sfp_i2c_scl_t, - input wire sfp_1_i2c_sda_i, - output wire sfp_1_i2c_sda_o, - output wire sfp_1_i2c_sda_t, - input wire sfp_2_i2c_sda_i, - output wire sfp_2_i2c_sda_o, - output wire sfp_2_i2c_sda_t, - - input wire eeprom_i2c_scl_i, - output wire eeprom_i2c_scl_o, - output wire eeprom_i2c_scl_t, - input wire eeprom_i2c_sda_i, - output wire eeprom_i2c_sda_o, - output wire eeprom_i2c_sda_t, - - /* - * BPI Flash - */ - output wire fpga_boot, - input wire [15:0] flash_dq_i, - output wire [15:0] flash_dq_o, - output wire flash_dq_oe, - output wire [22:0] flash_addr, - output wire flash_region, - output wire flash_region_oe, - output wire flash_ce_n, - output wire flash_oe_n, - output wire flash_we_n, - output wire flash_adv_n -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -localparam RB_DRP_SFP_BASE = RB_BASE_ADDR + 16'h50; - -initial begin - if (PORT_COUNT > 2) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// AXI lite connections -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; -wire [2:0] axil_csr_awprot; -wire axil_csr_awvalid; -wire axil_csr_awready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; -wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; -wire axil_csr_wvalid; -wire axil_csr_wready; -wire [1:0] axil_csr_bresp; -wire axil_csr_bvalid; -wire axil_csr_bready; -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; -wire [2:0] axil_csr_arprot; -wire axil_csr_arvalid; -wire axil_csr_arready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; -wire [1:0] axil_csr_rresp; -wire axil_csr_rvalid; -wire axil_csr_rready; - -// PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -wire sfp_drp_reg_wr_wait; -wire sfp_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] sfp_drp_reg_rd_data; -wire sfp_drp_reg_rd_wait; -wire sfp_drp_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg sfp_1_sel_reg = 1'b0; -reg sfp_2_sel_reg = 1'b0; - -reg sfp_1_tx_disable_reg = 1'b0; -reg sfp_1_rs_reg = 1'b0; -reg sfp_2_tx_disable_reg = 1'b0; -reg sfp_2_rs_reg = 1'b0; - -reg sfp_i2c_scl_o_reg = 1'b1; -reg sfp_i2c_sda_o_reg = 1'b1; - -reg eeprom_i2c_scl_o_reg = 1'b1; -reg eeprom_i2c_sda_o_reg = 1'b1; - -reg fpga_boot_reg = 1'b0; - -reg [15:0] flash_dq_o_reg = 16'd0; -reg flash_dq_oe_reg = 1'b0; -reg [22:0] flash_addr_reg = 23'd0; -reg flash_region_reg = 1'b0; -reg flash_region_oe_reg = 1'b0; -reg flash_ce_n_reg = 1'b1; -reg flash_oe_n_reg = 1'b1; -reg flash_we_n_reg = 1'b1; -reg flash_adv_n_reg = 1'b1; - -assign ctrl_reg_wr_wait = sfp_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | sfp_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | sfp_drp_reg_rd_data; -assign ctrl_reg_rd_wait = sfp_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | sfp_drp_reg_rd_ack; - -assign sfp_1_tx_disable = !sfp_1_tx_disable_reg; -assign sfp_2_tx_disable = !sfp_2_tx_disable_reg; - -assign sfp_1_rs = sfp_1_rs_reg; -assign sfp_2_rs = sfp_2_rs_reg; - -assign sfp_i2c_scl_o = sfp_i2c_scl_o_reg; -assign sfp_i2c_scl_t = sfp_i2c_scl_o_reg; -assign sfp_1_i2c_sda_o = sfp_1_sel_reg ? sfp_i2c_sda_o_reg : 1'b1; -assign sfp_1_i2c_sda_t = sfp_1_sel_reg ? sfp_i2c_sda_o_reg : 1'b1; -assign sfp_2_i2c_sda_o = sfp_2_sel_reg ? sfp_i2c_sda_o_reg : 1'b1; -assign sfp_2_i2c_sda_t = sfp_2_sel_reg ? sfp_i2c_sda_o_reg : 1'b1; - -assign eeprom_i2c_scl_o = eeprom_i2c_scl_o_reg; -assign eeprom_i2c_scl_t = eeprom_i2c_scl_o_reg; -assign eeprom_i2c_sda_o = eeprom_i2c_sda_o_reg; -assign eeprom_i2c_sda_t = eeprom_i2c_sda_o_reg; - -assign fpga_boot = fpga_boot_reg; - -assign flash_dq_o = flash_dq_o_reg; -assign flash_dq_oe = flash_dq_oe_reg; -assign flash_addr = flash_addr_reg; -assign flash_region = flash_region_reg; -assign flash_region_oe = flash_region_oe_reg; -assign flash_ce_n = flash_ce_n_reg; -assign flash_oe_n = flash_oe_n_reg; -assign flash_we_n = flash_we_n_reg; -assign flash_adv_n = flash_adv_n_reg; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // FW ID - 8'h0C: begin - // FW ID: FPGA JTAG ID - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - // I2C 0 - RBB+8'h0C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - sfp_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - sfp_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - if (ctrl_reg_wr_strb[2]) begin - sfp_1_sel_reg <= ctrl_reg_wr_data[16]; - sfp_2_sel_reg <= ctrl_reg_wr_data[17]; - end - end - // I2C 1 - RBB+8'h1C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - eeprom_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - eeprom_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // XCVR GPIO - RBB+8'h2C: begin - // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - sfp_1_tx_disable_reg <= ctrl_reg_wr_data[5]; - sfp_1_rs_reg <= ctrl_reg_wr_data[6]; - end - if (ctrl_reg_wr_strb[1]) begin - sfp_2_tx_disable_reg <= ctrl_reg_wr_data[13]; - sfp_2_rs_reg <= ctrl_reg_wr_data[14]; - end - end - // BPI flash - RBB+8'h3C: begin - // BPI flash ctrl: format - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - RBB+8'h40: begin - // BPI flash ctrl: address - flash_addr_reg <= ctrl_reg_wr_data[22:0]; - flash_region_reg <= ctrl_reg_wr_data[23]; - end - RBB+8'h44: flash_dq_o_reg <= ctrl_reg_wr_data; // BPI flash ctrl: data - RBB+8'h48: begin - // BPI flash ctrl: control - if (ctrl_reg_wr_strb[0]) begin - flash_ce_n_reg <= ctrl_reg_wr_data[0]; - flash_oe_n_reg <= ctrl_reg_wr_data[1]; - flash_we_n_reg <= ctrl_reg_wr_data[2]; - flash_adv_n_reg <= ctrl_reg_wr_data[3]; - end - if (ctrl_reg_wr_strb[1]) begin - flash_dq_oe_reg <= ctrl_reg_wr_data[8]; - end - if (ctrl_reg_wr_strb[2]) begin - flash_region_oe_reg <= ctrl_reg_wr_data[16]; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header - RBB+8'h0C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= sfp_i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= sfp_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= (sfp_1_i2c_sda_i || !sfp_1_sel_reg) && (sfp_2_i2c_sda_i || !sfp_2_sel_reg); - ctrl_reg_rd_data_reg[9] <= sfp_i2c_sda_o_reg; - ctrl_reg_rd_data_reg[16] <= sfp_1_sel_reg; - ctrl_reg_rd_data_reg[17] <= sfp_2_sel_reg; - end - // I2C 1 - RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // I2C ctrl: Next header - RBB+8'h1C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= eeprom_i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= eeprom_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= eeprom_i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= eeprom_i2c_sda_o_reg; - end - // XCVR GPIO - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h30; // XCVR GPIO: Next header - RBB+8'h2C: begin - // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !sfp_1_npres; - ctrl_reg_rd_data_reg[2] <= sfp_1_los; - ctrl_reg_rd_data_reg[5] <= sfp_1_tx_disable_reg; - ctrl_reg_rd_data_reg[6] <= sfp_1_rs_reg; - ctrl_reg_rd_data_reg[8] <= !sfp_2_npres; - ctrl_reg_rd_data_reg[10] <= sfp_2_los; - ctrl_reg_rd_data_reg[13] <= sfp_2_tx_disable_reg; - ctrl_reg_rd_data_reg[14] <= sfp_2_rs_reg; - end - // BPI flash - RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C121; // SPI flash ctrl: Type - RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version - RBB+8'h38: ctrl_reg_rd_data_reg <= RB_DRP_SFP_BASE; // SPI flash ctrl: Next header - RBB+8'h3C: begin - // BPI flash ctrl: format - ctrl_reg_rd_data_reg[7:0] <= 1; // type (BPI) - ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments) - ctrl_reg_rd_data_reg[23:16] <= 16; // data width - ctrl_reg_rd_data_reg[31:24] <= 24; // address width - end - RBB+8'h40: begin - // BPI flash ctrl: address - ctrl_reg_rd_data_reg[22:0] <= flash_addr_reg; - ctrl_reg_rd_data_reg[23] <= flash_region_reg; - end - RBB+8'h44: ctrl_reg_rd_data_reg <= flash_dq_i; // BPI flash ctrl: data - RBB+8'h48: begin - // BPI flash ctrl: control - ctrl_reg_rd_data_reg[0] <= flash_ce_n_reg; // chip enable (inverted) - ctrl_reg_rd_data_reg[1] <= flash_oe_n_reg; // output enable (inverted) - ctrl_reg_rd_data_reg[2] <= flash_we_n_reg; // write enable (inverted) - ctrl_reg_rd_data_reg[3] <= flash_adv_n_reg; // address valid (inverted) - ctrl_reg_rd_data_reg[8] <= flash_dq_oe_reg; // data output enable - ctrl_reg_rd_data_reg[16] <= flash_region_oe_reg; // region output enable (addr bit 23) - end - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - sfp_1_sel_reg <= 1'b0; - sfp_2_sel_reg <= 1'b0; - - sfp_1_tx_disable_reg <= 1'b0; - sfp_1_rs_reg <= 1'b0; - sfp_2_tx_disable_reg <= 1'b0; - sfp_2_rs_reg <= 1'b0; - - sfp_i2c_scl_o_reg <= 1'b1; - sfp_i2c_sda_o_reg <= 1'b1; - - eeprom_i2c_scl_o_reg <= 1'b1; - eeprom_i2c_sda_o_reg <= 1'b1; - - fpga_boot_reg <= 1'b0; - - flash_dq_o_reg <= 16'd0; - flash_dq_oe_reg <= 1'b0; - flash_addr_reg <= 23'd0; - flash_region_reg <= 1'b0; - flash_region_oe_reg <= 1'b0; - flash_ce_n_reg <= 1'b1; - flash_oe_n_reg <= 1'b1; - flash_we_n_reg <= 1'b1; - flash_adv_n_reg <= 1'b1; - end -end - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd2}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_SFP_BASE), - .RB_NEXT_PTR(0) -) -sfp_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(sfp_drp_reg_wr_wait), - .reg_wr_ack(sfp_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(sfp_drp_reg_rd_data), - .reg_rd_wait(sfp_drp_reg_rd_wait), - .reg_rd_ack(sfp_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(sfp_drp_clk), - .drp_rst(sfp_drp_rst), - .drp_addr(sfp_drp_addr), - .drp_di(sfp_drp_di), - .drp_en(sfp_drp_en), - .drp_we(sfp_drp_we), - .drp_do(sfp_drp_do), - .drp_rdy(sfp_drp_rdy) -); - -reg [26:0] pps_led_counter_reg = 0; -reg pps_led_reg = 0; - -always @(posedge clk_250mhz) begin - if (ptp_pps) begin - pps_led_counter_reg <= 125000000; - end else if (pps_led_counter_reg > 0) begin - pps_led_counter_reg <= pps_led_counter_reg - 1; - end - - pps_led_reg <= pps_led_counter_reg > 0; -end - -// BER tester -tdma_ber #( - .COUNT(2), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(2)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({sfp_2_tx_clk, sfp_1_tx_clk}), - .phy_rx_clk({sfp_2_rx_clk, sfp_1_rx_clk}), - .phy_rx_error_count({sfp_2_rx_error_count, sfp_1_rx_error_count}), - .phy_tx_prbs31_enable({sfp_2_tx_prbs31_enable, sfp_1_tx_prbs31_enable}), - .phy_rx_prbs31_enable({sfp_2_rx_prbs31_enable, sfp_1_rx_prbs31_enable}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step) -); - -assign sma_out = ptp_perout_pulse; -assign sma_out_en = 1'b0; -assign sma_term_en = 1'b0; - -assign sfp_1_led = 2'b00; -assign sfp_2_led = 2'b00; -assign sma_led[0] = pps_led_reg; -assign sma_led[1] = 1'b0; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] port_xgmii_tx_clk; -wire [PORT_COUNT-1:0] port_xgmii_tx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; - -wire [PORT_COUNT-1:0] port_xgmii_rx_clk; -wire [PORT_COUNT-1:0] port_xgmii_rx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; - -// counts -// IF PORT SFP 1 SFP 2 -// 1 1 0 (0.0) -// 1 2 0 (0.0) 1 (0.1) -// 2 1 0 (0.0) 1 (1.0) - -localparam SFP_1_IND = 0; -localparam SFP_2_IND = 1; - -generate - genvar m, n; - - if (SFP_1_IND >= 0 && SFP_1_IND < PORT_COUNT) begin - assign port_xgmii_tx_clk[SFP_1_IND] = sfp_1_tx_clk; - assign port_xgmii_tx_rst[SFP_1_IND] = sfp_1_tx_rst; - assign port_xgmii_rx_clk[SFP_1_IND] = sfp_1_rx_clk; - assign port_xgmii_rx_rst[SFP_1_IND] = sfp_1_rx_rst; - assign port_xgmii_rxd[SFP_1_IND*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH] = sfp_1_rxd; - assign port_xgmii_rxc[SFP_1_IND*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH] = sfp_1_rxc; - - assign sfp_1_txd = port_xgmii_txd[SFP_1_IND*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]; - assign sfp_1_txc = port_xgmii_txc[SFP_1_IND*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]; - end else begin - assign sfp_1_txd = {XGMII_CTRL_WIDTH{8'h07}}; - assign sfp_1_txc = {XGMII_CTRL_WIDTH{1'b1}}; - end - - if (SFP_2_IND >= 0 && SFP_2_IND < PORT_COUNT) begin - assign port_xgmii_tx_clk[SFP_2_IND] = sfp_2_tx_clk; - assign port_xgmii_tx_rst[SFP_2_IND] = sfp_2_tx_rst; - assign port_xgmii_rx_clk[SFP_2_IND] = sfp_2_rx_clk; - assign port_xgmii_rx_rst[SFP_2_IND] = sfp_2_rx_rst; - assign port_xgmii_rxd[SFP_2_IND*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH] = sfp_2_rxd; - assign port_xgmii_rxc[SFP_2_IND*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH] = sfp_2_rxc; - - assign sfp_2_txd = port_xgmii_txd[SFP_2_IND*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]; - assign sfp_2_txc = port_xgmii_txc[SFP_2_IND*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]; - end else begin - assign sfp_2_txd = {XGMII_CTRL_WIDTH{8'h07}}; - assign sfp_2_txc = {XGMII_CTRL_WIDTH{1'b1}}; - end - - for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac - - assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; - assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; - assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; - assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; - - eth_mac_10g #( - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .ENABLE_PADDING(ENABLE_PADDING), - .ENABLE_DIC(ENABLE_DIC), - .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), - .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), - .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) - ) - eth_mac_inst ( - .tx_clk(port_xgmii_tx_clk[n]), - .tx_rst(port_xgmii_tx_rst[n]), - .rx_clk(port_xgmii_rx_clk[n]), - .rx_rst(port_xgmii_rx_rst[n]), - - .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), - .tx_axis_tready(axis_eth_tx_tready[n +: 1]), - .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), - .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), - - .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), - .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), - .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), - - .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]), - .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), - - .tx_error_underflow(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - - .ifg_delay(8'd12) - ); - - end - -endgenerate - -mqnic_core_pcie_us #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // PTP configuration - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH), - .PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH), - .PTP_FNS_WIDTH(PTP_FNS_WIDTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), - .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), - .PTP_SEPARATE_RX_CLOCK(0), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration (interface) - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), - - // TX and RX engine configuration (port) - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - - // Scheduler configuration (port) - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Timestamping configuration (port) - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH), - .RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH), - - // Interface configuration (port) - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // Application block configuration - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - .PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE), - .PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT), - .PCIE_DMA_READ_TX_FC_ENABLE(PCIE_DMA_READ_TX_FC_ENABLE), - .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), - .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), - .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), - .MSI_COUNT(MSI_COUNT), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * AXI input (RC) - */ - .s_axis_rc_tdata(s_axis_rc_tdata), - .s_axis_rc_tkeep(s_axis_rc_tkeep), - .s_axis_rc_tvalid(s_axis_rc_tvalid), - .s_axis_rc_tready(s_axis_rc_tready), - .s_axis_rc_tlast(s_axis_rc_tlast), - .s_axis_rc_tuser(s_axis_rc_tuser), - - /* - * AXI output (RQ) - */ - .m_axis_rq_tdata(m_axis_rq_tdata), - .m_axis_rq_tkeep(m_axis_rq_tkeep), - .m_axis_rq_tvalid(m_axis_rq_tvalid), - .m_axis_rq_tready(m_axis_rq_tready), - .m_axis_rq_tlast(m_axis_rq_tlast), - .m_axis_rq_tuser(m_axis_rq_tuser), - - /* - * AXI input (CQ) - */ - .s_axis_cq_tdata(s_axis_cq_tdata), - .s_axis_cq_tkeep(s_axis_cq_tkeep), - .s_axis_cq_tvalid(s_axis_cq_tvalid), - .s_axis_cq_tready(s_axis_cq_tready), - .s_axis_cq_tlast(s_axis_cq_tlast), - .s_axis_cq_tuser(s_axis_cq_tuser), - - /* - * AXI output (CC) - */ - .m_axis_cc_tdata(m_axis_cc_tdata), - .m_axis_cc_tkeep(m_axis_cc_tkeep), - .m_axis_cc_tvalid(m_axis_cc_tvalid), - .m_axis_cc_tready(m_axis_cc_tready), - .m_axis_cc_tlast(m_axis_cc_tlast), - .m_axis_cc_tuser(m_axis_cc_tuser), - - /* - * Transmit sequence number input - */ - .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), - .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), - .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), - .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), - - /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration inputs - */ - .cfg_max_read_req(cfg_max_read_req), - .cfg_max_payload(cfg_max_payload), - - /* - * Configuration interface - */ - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - /* - * Interrupt interface - */ - .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), - .cfg_interrupt_msi_vf_enable(8'd0), - .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), - .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), - .cfg_interrupt_msi_data(cfg_interrupt_msi_data), - .cfg_interrupt_msi_select(cfg_interrupt_msi_select), - .cfg_interrupt_msi_int(cfg_interrupt_msi_int), - .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), - .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), - .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), - .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), - .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), - .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), - .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), - .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - /* - * PCIe error outputs - */ - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(axil_csr_awaddr), - .m_axil_csr_awprot(axil_csr_awprot), - .m_axil_csr_awvalid(axil_csr_awvalid), - .m_axil_csr_awready(axil_csr_awready), - .m_axil_csr_wdata(axil_csr_wdata), - .m_axil_csr_wstrb(axil_csr_wstrb), - .m_axil_csr_wvalid(axil_csr_wvalid), - .m_axil_csr_wready(axil_csr_wready), - .m_axil_csr_bresp(axil_csr_bresp), - .m_axil_csr_bvalid(axil_csr_bvalid), - .m_axil_csr_bready(axil_csr_bready), - .m_axil_csr_araddr(axil_csr_araddr), - .m_axil_csr_arprot(axil_csr_arprot), - .m_axil_csr_arvalid(axil_csr_arvalid), - .m_axil_csr_arready(axil_csr_arready), - .m_axil_csr_rdata(axil_csr_rdata), - .m_axil_csr_rresp(axil_csr_rresp), - .m_axil_csr_rvalid(axil_csr_rvalid), - .m_axil_csr_rready(axil_csr_rready), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_sample_clk(clk_250mhz), - .ptp_pps(ptp_pps), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_ptp_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(0), - .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile deleted file mode 100644 index 60961d35e..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile +++ /dev/null @@ -1,410 +0,0 @@ -# Copyright 2020-2021, The Regents of the University of California. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS -# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -# OF SUCH DAMAGE. -# -# The views and conclusions contained in the software and documentation are those -# of the authors and should not be interpreted as representing official policies, -# either expressed or implied, of The Regents of the University of California. - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rb_drp.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT ?= 2 -export PARAM_PORTS_PER_IF ?= 1 - -# PTP configuration -export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0 -export PARAM_PTP_PEROUT_ENABLE ?= 1 -export PARAM_PTP_PEROUT_COUNT ?= 1 - -# Queue manager configuration (interface) -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 -export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE ?= 3 -export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE) - -# TX and RX engine configuration (port) -export PARAM_TX_DESC_TABLE_SIZE ?= 32 -export PARAM_RX_DESC_TABLE_SIZE ?= 32 - -# Scheduler configuration (port) -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH ?= 6 - -# Timestamping configuration (port) -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32 -export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32 - -# Interface configuration (port) -export PARAM_TX_CHECKSUM_ENABLE ?= 1 -export PARAM_RX_RSS_ENABLE ?= 1 -export PARAM_RX_HASH_ENABLE ?= 1 -export PARAM_RX_CHECKSUM_ENABLE ?= 1 -export PARAM_TX_FIFO_DEPTH ?= 32768 -export PARAM_RX_FIFO_DEPTH ?= 32768 -export PARAM_MAX_TX_SIZE ?= 9214 -export PARAM_MAX_RX_SIZE ?= 9214 -export PARAM_TX_RAM_SIZE ?= 32768 -export PARAM_RX_RAM_SIZE ?= 32768 - -# Application block configuration -export PARAM_APP_ENABLE ?= 0 -export PARAM_APP_CTRL_ENABLE ?= 1 -export PARAM_APP_DMA_ENABLE ?= 1 -export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1 -export PARAM_APP_AXIS_SYNC_ENABLE ?= 1 -export PARAM_APP_AXIS_IF_ENABLE ?= 1 -export PARAM_APP_STAT_ENABLE ?= 1 - -# DMA interface configuration -export PARAM_DMA_LEN_WIDTH ?= 16 -export PARAM_DMA_TAG_WIDTH ?= 16 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE ?= 2 - -# PCIe interface configuration -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 -export PARAM_PF_COUNT ?= 1 -export PARAM_VF_COUNT ?= 0 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16 -export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1 -export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16 -export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 -export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE ?= 0 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2 -export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 0 -export PARAM_AXIS_ETH_RX_PIPELINE ?= 0 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 2 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE ?= 1 -export PARAM_STAT_DMA_ENABLE ?= 1 -export PARAM_STAT_PCIE_ENABLE ?= 1 -export PARAM_STAT_INC_WIDTH ?= 24 -export PARAM_STAT_ID_WIDTH ?= 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).VF_COUNT=$(PARAM_VF_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT) - COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) - COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) - COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE) - COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) - COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) - COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) - COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE) - COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT) - COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE) - COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH) - COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH) - COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH) - COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH) - COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE) - COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE) - COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE) - COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE) - COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE) - COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE) - COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE) - COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE) - COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE) - COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH) - COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) - COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH) - COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH) - COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) - COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) - COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) - COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE) - COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) - COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) - COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) - COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE) - COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) - COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) - COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) - COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) - COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) - COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) - COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) - COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) - COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) - COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) - COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH) - COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT) - COMPILE_ARGS += -GVF_COUNT=$(PARAM_VF_COUNT) - COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) - COMPILE_ARGS += -GPCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE) - COMPILE_ARGS += -GPCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT) - COMPILE_ARGS += -GPCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE) - COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) - COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) - COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) - COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) - COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) - COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) - COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) - COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) - COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) - COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) - COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE) - COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE) - COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE) - COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE) - COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE) - COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH) - COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/mqnic.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 94fc2403a..000000000 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,694 +0,0 @@ -""" - -Copyright 2020-2021, The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS -IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. - -The views and conclusions contained in the software and documentation are those -of the authors and should not be interpreted as representing official policies, -either expressed or implied, of The Regents of the University of California. - -""" - -import logging -import os -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus -from cocotbext.eth import XgmiiSource, XgmiiSink -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = UltraScalePlusPcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=8, - user_clk_frequency=250e6, - alignment="dword", - cq_cc_straddle=False, - rq_rc_straddle=False, - rc_4tlp_straddle=False, - enable_pf1=False, - enable_client_tag=True, - enable_extended_tag=True, - enable_parity=False, - enable_rx_msg_interface=False, - enable_sriov=False, - enable_extended_configuration=False, - - enable_pf0_msi=True, - enable_pf1_msi=False, - - # signals - # Clock and Reset Interface - user_clk=dut.clk_250mhz, - user_reset=dut.rst_250mhz, - # user_lnk_up - # sys_clk - # sys_clk_gt - # sys_reset - # phy_rdy_out - - # Requester reQuest Interface - rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), - pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 - # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 - - # Requester Completion Interface - rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), - - # Completer reQuest Interface - cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - # pcie_cq_np_req - # pcie_cq_np_req_count - - # Completer Completion Interface - cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), - - # Transmit Flow Control Interface - # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, - # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, - - # Configuration Management Interface - cfg_mgmt_addr=dut.cfg_mgmt_addr, - cfg_mgmt_function_number=dut.cfg_mgmt_function_number, - cfg_mgmt_write=dut.cfg_mgmt_write, - cfg_mgmt_write_data=dut.cfg_mgmt_write_data, - cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, - cfg_mgmt_read=dut.cfg_mgmt_read, - cfg_mgmt_read_data=dut.cfg_mgmt_read_data, - cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, - # cfg_mgmt_debug_access - - # Configuration Status Interface - # cfg_phy_link_down - # cfg_phy_link_status - # cfg_negotiated_width - # cfg_current_speed - cfg_max_payload=dut.cfg_max_payload, - cfg_max_read_req=dut.cfg_max_read_req, - # cfg_function_status - # cfg_vf_status - # cfg_function_power_state - # cfg_vf_power_state - # cfg_link_power_state - # cfg_err_cor_out - # cfg_err_nonfatal_out - # cfg_err_fatal_out - # cfg_local_error_out - # cfg_local_error_valid - # cfg_rx_pm_state - # cfg_tx_pm_state - # cfg_ltssm_state - # cfg_rcb_status - # cfg_obff_enable - # cfg_pl_status_change - # cfg_tph_requester_enable - # cfg_tph_st_mode - # cfg_vf_tph_requester_enable - # cfg_vf_tph_st_mode - - # Configuration Received Message Interface - # cfg_msg_received - # cfg_msg_received_data - # cfg_msg_received_type - - # Configuration Transmit Message Interface - # cfg_msg_transmit - # cfg_msg_transmit_type - # cfg_msg_transmit_data - # cfg_msg_transmit_done - - # Configuration Flow Control Interface - cfg_fc_ph=dut.cfg_fc_ph, - cfg_fc_pd=dut.cfg_fc_pd, - cfg_fc_nph=dut.cfg_fc_nph, - cfg_fc_npd=dut.cfg_fc_npd, - cfg_fc_cplh=dut.cfg_fc_cplh, - cfg_fc_cpld=dut.cfg_fc_cpld, - cfg_fc_sel=dut.cfg_fc_sel, - - # Configuration Control Interface - # cfg_hot_reset_in - # cfg_hot_reset_out - # cfg_config_space_enable - # cfg_dsn - # cfg_bus_number - # cfg_ds_port_number - # cfg_ds_bus_number - # cfg_ds_device_number - # cfg_ds_function_number - # cfg_power_state_change_ack - # cfg_power_state_change_interrupt - cfg_err_cor_in=dut.status_error_cor, - cfg_err_uncor_in=dut.status_error_uncor, - # cfg_flr_in_process - # cfg_flr_done - # cfg_vf_flr_in_process - # cfg_vf_flr_func_num - # cfg_vf_flr_done - # cfg_pm_aspm_l1_entry_reject - # cfg_pm_aspm_tx_l0s_entry_disable - # cfg_req_pm_transition_l23_ready - # cfg_link_training_enable - - # Configuration Interrupt Controller Interface - # cfg_interrupt_int - # cfg_interrupt_sent - # cfg_interrupt_pending - cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, - cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, - cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, - cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, - # cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, - cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, - cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, - cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, - # cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, - cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, - cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, - # cfg_interrupt_msix_enable - # cfg_interrupt_msix_mask - # cfg_interrupt_msix_vf_enable - # cfg_interrupt_msix_vf_mask - # cfg_interrupt_msix_address - # cfg_interrupt_msix_data - # cfg_interrupt_msix_int - # cfg_interrupt_msix_vec_pending - # cfg_interrupt_msix_vec_pending_status - cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, - cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, - cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, - # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, - # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, - - # Configuration Extend Interface - # cfg_ext_read_received - # cfg_ext_write_received - # cfg_ext_register_number - # cfg_ext_function_number - # cfg_ext_write_data - # cfg_ext_write_byte_enable - # cfg_ext_read_data - # cfg_ext_read_data_valid - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - # Ethernet - cocotb.start_soon(Clock(dut.sfp_1_rx_clk, 6.4, units="ns").start()) - self.sfp_1_source = XgmiiSource(dut.sfp_1_rxd, dut.sfp_1_rxc, dut.sfp_1_rx_clk, dut.sfp_1_rx_rst) - cocotb.start_soon(Clock(dut.sfp_1_tx_clk, 6.4, units="ns").start()) - self.sfp_1_sink = XgmiiSink(dut.sfp_1_txd, dut.sfp_1_txc, dut.sfp_1_tx_clk, dut.sfp_1_tx_rst) - - cocotb.start_soon(Clock(dut.sfp_2_rx_clk, 6.4, units="ns").start()) - self.sfp_2_source = XgmiiSource(dut.sfp_2_rxd, dut.sfp_2_rxc, dut.sfp_2_rx_clk, dut.sfp_2_rx_rst) - cocotb.start_soon(Clock(dut.sfp_2_tx_clk, 6.4, units="ns").start()) - self.sfp_2_sink = XgmiiSink(dut.sfp_2_txd, dut.sfp_2_txc, dut.sfp_2_tx_clk, dut.sfp_2_tx_rst) - - cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start()) - dut.sfp_drp_rst.setimmediatevalue(0) - dut.sfp_drp_do.setimmediatevalue(0) - dut.sfp_drp_rdy.setimmediatevalue(0) - - dut.sfp_1_rx_error_count.setimmediatevalue(0) - dut.sfp_2_rx_error_count.setimmediatevalue(0) - - dut.sfp_1_npres.setimmediatevalue(0) - dut.sfp_2_npres.setimmediatevalue(0) - dut.sfp_1_los.setimmediatevalue(0) - dut.sfp_2_los.setimmediatevalue(0) - - dut.sma_in.setimmediatevalue(0) - - dut.sfp_i2c_scl_i.setimmediatevalue(1) - dut.sfp_1_i2c_sda_i.setimmediatevalue(1) - dut.sfp_2_i2c_sda_i.setimmediatevalue(1) - - dut.eeprom_i2c_scl_i.setimmediatevalue(1) - dut.eeprom_i2c_sda_i.setimmediatevalue(1) - - dut.flash_dq_i.setimmediatevalue(0) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.sfp_1_rx_rst.setimmediatevalue(0) - self.dut.sfp_1_tx_rst.setimmediatevalue(0) - self.dut.sfp_2_rx_rst.setimmediatevalue(0) - self.dut.sfp_2_tx_rst.setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.sfp_1_rx_rst.setimmediatevalue(1) - self.dut.sfp_1_tx_rst.setimmediatevalue(1) - self.dut.sfp_2_rx_rst.setimmediatevalue(1) - self.dut.sfp_2_tx_rst.setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.sfp_1_rx_rst.setimmediatevalue(0) - self.dut.sfp_1_tx_rst.setimmediatevalue(0) - self.dut.sfp_2_rx_rst.setimmediatevalue(0) - self.dut.sfp_2_tx_rst.setimmediatevalue(0) - - await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - if not self.sfp_1_sink.empty(): - await self.sfp_1_source.send(await self.sfp_1_sink.recv()) - if not self.sfp_2_sink.empty(): - await self.sfp_2_source.send(await self.sfp_2_sink.recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc, tb.dev.functions[0].pcie_id) - await tb.driver.interfaces[0].open() - # await tb.driver.interfaces[1].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].ports[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(tb.driver.interfaces[0].tx_queue_count): - await tb.driver.interfaces[0].ports[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.sfp_1_sink.recv() - tb.log.info("Packet: %s", pkt) - - await tb.sfp_1_source.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - # await tb.driver.interfaces[1].start_xmit(data, 0) - - # pkt = await tb.sfp_2_sink.recv() - # tb.log.info("Packet: %s", pkt) - - # await tb.sfp_2_source.send(pkt) - - # pkt = await tb.driver.interfaces[1].recv() - - # tb.log.info("Packet: %s", pkt) - # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.sfp_1_sink.recv() - tb.log.info("Packet: %s", pkt) - - await tb.sfp_1_source.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "rb_drp.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "tdma_scheduler.v"), - os.path.join(rtl_dir, "common", "tdma_ber.v"), - os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), - os.path.join(pcie_rtl_dir, "pcie_us_msi.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 2 - parameters['PORTS_PER_IF'] = 1 - - # PTP configuration - parameters['PTP_USE_SAMPLE_CLOCK'] = 0 - parameters['PTP_PEROUT_ENABLE'] = 1 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration (interface) - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] - - # TX and RX engine configuration (port) - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - - # Scheduler configuration (port) - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Timestamping configuration (port) - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_PTP_TS_FIFO_DEPTH'] = 32 - parameters['RX_PTP_TS_FIFO_DEPTH'] = 32 - - # Interface configuration (port) - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 32768 - - # Application block configuration - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['AXIS_PCIE_DATA_WIDTH'] = 256 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - parameters['PCIE_TAG_COUNT'] = 64 - parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT'] - parameters['PCIE_DMA_READ_TX_LIMIT'] = 16 - parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1 - parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16 - parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 - parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 0 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0 - parameters['AXIS_ETH_RX_PIPELINE'] = 0 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl index 2fe98a1f2..74b1b5e91 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl @@ -80,6 +80,15 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + # Structural configuration # counts @@ -170,6 +179,7 @@ dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" # Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] dict set params AXIS_ETH_TX_PIPELINE "0" dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" dict set params AXIS_ETH_TX_TS_PIPELINE "0" @@ -238,6 +248,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile similarity index 100% rename from fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile rename to fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/config.tcl b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl similarity index 85% rename from fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/config.tcl rename to fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl index 2fe98a1f2..6a6e73238 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/config.tcl +++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,15 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + # Structural configuration # counts @@ -170,6 +179,7 @@ dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" # Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] dict set params AXIS_ETH_TX_PIPELINE "0" dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" dict set params AXIS_ETH_TX_TS_PIPELINE "0" @@ -238,6 +248,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v index 4caa0001e..55c8b0506 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v @@ -144,6 +144,7 @@ module fpga # parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, parameter AXIS_ETH_TX_PIPELINE = 0, parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, parameter AXIS_ETH_TX_TS_PIPELINE = 0, @@ -242,7 +243,7 @@ parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1; parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;