From e9ea91b5ec3a47e86c88e5f04a9fa5cbb7038f2d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 19 Nov 2023 19:51:32 -0800 Subject: [PATCH] fpga/mqnic: Set data bus width correctly for 25G E-Tile MACs Signed-off-by: Alex Forencich --- fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v | 2 +- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v | 2 +- fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v index d1edbd1f0..3429793f1 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v @@ -209,7 +209,7 @@ parameter TX_SEQ_NUM_WIDTH = 6; parameter PCIE_TAG_COUNT = 256; // Ethernet interface configuration -parameter AXIS_ETH_DATA_WIDTH = 512; +parameter AXIS_ETH_DATA_WIDTH = MAC_100G ? 512 : 64; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE && !MAC_100G ? 2 : 1); parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v index 29b89a662..5a83dcd3a 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v @@ -202,7 +202,7 @@ parameter TX_SEQ_NUM_WIDTH = 6; parameter PCIE_TAG_COUNT = 256; // Ethernet interface configuration -parameter AXIS_ETH_DATA_WIDTH = 512; +parameter AXIS_ETH_DATA_WIDTH = MAC_100G ? 512 : 64; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE && !MAC_100G ? 2 : 1); parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v index e1ab6526d..2242cd583 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v @@ -216,7 +216,7 @@ parameter TX_SEQ_NUM_WIDTH = 6; parameter PCIE_TAG_COUNT = 256; // Ethernet interface configuration -parameter AXIS_ETH_DATA_WIDTH = 512; +parameter AXIS_ETH_DATA_WIDTH = MAC_100G ? 512 : 64; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE && !MAC_100G ? 2 : 1); parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;