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Code Issues Projects Releases Wiki Activity

Move MAC out of port module

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This commit is contained in:
Alex Forencich 2019-07-19 23:29:03 -07:00
parent 1917ed3912
commit ea7ccd182e
15 changed files with 967 additions and 1137 deletions
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fpga/common/rtl/eth_interface.v
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/*
Copyright 2019, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet interface
*/
module eth_interface #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter AXI_DATA_WIDTH = 256, // width of data bus in bits
parameter AXI_ADDR_WIDTH = 16, // width of address bus in bits
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
parameter AXI_ID_WIDTH = 8,
parameter AXI_MAX_BURST_LEN = 16,
parameter LEN_WIDTH = 20,
parameter TAG_WIDTH = 8,
parameter ENABLE_SG = 0,
parameter ENABLE_UNALIGNED = 0,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter LOGIC_PTP_PERIOD_NS = 4'h6,
parameter LOGIC_PTP_PERIOD_FNS = 16'h6666,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 1,
parameter RX_PTP_TS_ENABLE = 1,
parameter PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = 1,
parameter PTP_TAG_WIDTH = 16
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* Transmit descriptor input
*/
input wire [AXI_ADDR_WIDTH-1:0] s_axis_tx_desc_addr,
input wire [LEN_WIDTH-1:0] s_axis_tx_desc_len,
input wire [TAG_WIDTH-1:0] s_axis_tx_desc_tag,
input wire s_axis_tx_desc_user,
input wire s_axis_tx_desc_valid,
output wire s_axis_tx_desc_ready,
/*
* Transmit descriptor status output
*/
output wire [TAG_WIDTH-1:0] m_axis_tx_desc_status_tag,
output wire m_axis_tx_desc_status_valid,
/*
* Transmit timestamp tag input
*/
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* Transmit checksum input
*/
/*
* Receive descriptor input
*/
input wire [AXI_ADDR_WIDTH-1:0] s_axis_rx_desc_addr,
input wire [LEN_WIDTH-1:0] s_axis_rx_desc_len,
input wire [TAG_WIDTH-1:0] s_axis_rx_desc_tag,
input wire s_axis_rx_desc_valid,
output wire s_axis_rx_desc_ready,
/*
* Receive descriptor status output
*/
output wire [LEN_WIDTH-1:0] m_axis_rx_desc_status_len,
output wire [TAG_WIDTH-1:0] m_axis_rx_desc_status_tag,
output wire m_axis_rx_desc_status_user,
output wire m_axis_rx_desc_status_valid,
/*
* Receive timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96,
output wire m_axis_rx_ptp_ts_valid,
input wire m_axis_rx_ptp_ts_ready,
/*
* Receive checksum output
*/
output wire [15:0] m_axis_rx_csum,
output wire m_axis_rx_csum_valid,
/*
* AXI master interface
*/
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* Status
*/
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
/*
* Configuration
*/
input wire tx_enable,
input wire rx_enable,
input wire rx_abort,
input wire [7:0] ifg_delay
);
localparam KEEP_WIDTH = CTRL_WIDTH;
localparam TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
localparam RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
wire [AXI_DATA_WIDTH-1:0] tx_axis_tdata;
wire [AXI_STRB_WIDTH-1:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_axis_tuser;
wire [AXI_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXI_STRB_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_axis_tuser;
wire [AXI_DATA_WIDTH-1:0] tx_csum_axis_tdata;
wire [AXI_STRB_WIDTH-1:0] tx_csum_axis_tkeep;
wire tx_csum_axis_tvalid;
wire tx_csum_axis_tready;
wire tx_csum_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_csum_axis_tuser;
wire [AXI_DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [AXI_STRB_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [AXI_DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [AXI_STRB_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] tx_adapt_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_adapt_axis_tkeep;
wire tx_adapt_axis_tvalid;
wire tx_adapt_axis_tready;
wire tx_adapt_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_adapt_axis_tuser;
wire [DATA_WIDTH-1:0] rx_adapt_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_adapt_axis_tkeep;
wire rx_adapt_axis_tvalid;
wire rx_adapt_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_adapt_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
ptp_clock_cdc #(
.TS_WIDTH(96),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.INPUT_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.INPUT_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.OUTPUT_PERIOD_NS(PTP_PERIOD_NS),
.OUTPUT_PERIOD_FNS(PTP_PERIOD_FNS),
.USE_SAMPLE_CLOCK(0)//,
//.LOG_FIFO_DEPTH(LOG_FIFO_DEPTH),
//.LOG_RATE(LOG_RATE)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(logic_clk),
.input_ts(ptp_ts_96),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps()
);
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
ptp_clock_cdc #(
.TS_WIDTH(96),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.INPUT_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.INPUT_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.OUTPUT_PERIOD_NS(PTP_PERIOD_NS),
.OUTPUT_PERIOD_FNS(PTP_PERIOD_FNS),
.USE_SAMPLE_CLOCK(0)//,
//.LOG_FIFO_DEPTH(LOG_FIFO_DEPTH),
//.LOG_RATE(LOG_RATE)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(logic_clk),
.input_ts(ptp_ts_96),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps()
);
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
axis_async_fifo #(
.DEPTH(64),
.DATA_WIDTH(PTP_TAG_WIDTH+PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata({tx_axis_ptp_ts_tag, tx_axis_ptp_ts_96}),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata({m_axis_tx_ptp_ts_tag, m_axis_tx_ptp_ts_96}),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
wire [PTP_TS_WIDTH-1:0] rx_axis_ptp_ts_96;
wire rx_axis_ptp_ts_valid;
axis_fifo #(
.DEPTH(64),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
rx_ptp_ts_fifo (
.clk(logic_clk),
.rst(logic_rst),
// AXI input
.s_axis_tdata(rx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(m_axis_rx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_rx_ptp_ts_valid),
.m_axis_tready(m_axis_rx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
ptp_ts_extract #(
.TS_WIDTH(96),
.TS_OFFSET(1),
.USER_WIDTH(RX_USER_WIDTH)
)
rx_ptp_ts_extract (
.clk(logic_clk),
.rst(logic_rst),
// AXI stream input
.s_axis_tvalid(rx_axis_tvalid && rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Timestamp output
.m_axis_ts(rx_axis_ptp_ts_96),
.m_axis_ts_valid(rx_axis_ptp_ts_valid)
);
generate
if (RX_CHECKSUM_ENABLE) begin
rx_checksum #(
.DATA_WIDTH(AXI_DATA_WIDTH)
)
rx_checksum_inst (
.clk(logic_clk),
.rst(logic_rst),
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid & rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.m_axis_csum(m_axis_rx_csum),
.m_axis_csum_valid(m_axis_rx_csum_valid)
);
end else begin
assign m_axis_rx_csum = 16'd0;
assign m_axis_rx_csum_valid = 1'b0;
end
if (TX_CHECKSUM_ENABLE) begin
assign tx_csum_axis_tdata = tx_axis_tdata;
assign tx_csum_axis_tkeep = tx_axis_tkeep;
assign tx_csum_axis_tvalid = tx_axis_tvalid;
assign tx_axis_tready = tx_csum_axis_tready;
assign tx_csum_axis_tlast = tx_axis_tlast;
assign tx_csum_axis_tuser = tx_axis_tuser;
end else begin
assign tx_csum_axis_tdata = tx_axis_tdata;
assign tx_csum_axis_tkeep = tx_axis_tkeep;
assign tx_csum_axis_tvalid = tx_axis_tvalid;
assign tx_axis_tready = tx_csum_axis_tready;
assign tx_csum_axis_tlast = tx_axis_tlast;
assign tx_csum_axis_tuser = tx_axis_tuser;
end
endgenerate
eth_mac_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH)
)
eth_mac_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_adapt_axis_tdata),
.tx_axis_tkeep(tx_adapt_axis_tkeep),
.tx_axis_tvalid(tx_adapt_axis_tvalid),
.tx_axis_tready(tx_adapt_axis_tready),
.tx_axis_tlast(tx_adapt_axis_tlast),
.tx_axis_tuser(tx_adapt_axis_tuser),
.rx_axis_tdata(rx_adapt_axis_tdata),
.rx_axis_tkeep(rx_adapt_axis_tkeep),
.rx_axis_tvalid(rx_adapt_axis_tvalid),
.rx_axis_tlast(rx_adapt_axis_tlast),
.rx_axis_tuser(rx_adapt_axis_tuser),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_start_packet(),
.rx_start_packet(),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_adapter #(
.S_DATA_WIDTH(AXI_DATA_WIDTH),
.S_KEEP_ENABLE(1'b1),
.S_KEEP_WIDTH(AXI_STRB_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1'b1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH)
)
tx_adapter (
.clk(tx_clk),
.rst(tx_rst),
// AXI input
.s_axis_tdata(tx_fifo_axis_tdata),
.s_axis_tkeep(tx_fifo_axis_tkeep),
.s_axis_tvalid(tx_fifo_axis_tvalid),
.s_axis_tready(tx_fifo_axis_tready),
.s_axis_tlast(tx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_fifo_axis_tuser),
// AXI output
.m_axis_tdata(tx_adapt_axis_tdata),
.m_axis_tkeep(tx_adapt_axis_tkeep),
.m_axis_tvalid(tx_adapt_axis_tvalid),
.m_axis_tready(tx_adapt_axis_tready),
.m_axis_tlast(tx_adapt_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_adapt_axis_tuser)
);
axis_async_fifo #(
.DEPTH(TX_FIFO_DEPTH),
.DATA_WIDTH(AXI_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXI_STRB_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// Common reset
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(logic_clk),
.s_axis_tdata(tx_csum_axis_tdata),
.s_axis_tkeep(tx_csum_axis_tkeep),
.s_axis_tvalid(tx_csum_axis_tvalid),
.s_axis_tready(tx_csum_axis_tready),
.s_axis_tlast(tx_csum_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_csum_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_adapter #(
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXI_DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(AXI_STRB_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH)
)
rx_adapter (
.clk(rx_clk),
.rst(rx_rst),
// AXI input
.s_axis_tdata(rx_adapt_axis_tdata),
.s_axis_tkeep(rx_adapt_axis_tkeep),
.s_axis_tvalid(rx_adapt_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_adapt_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_adapt_axis_tuser),
// AXI output
.m_axis_tdata(rx_fifo_axis_tdata),
.m_axis_tkeep(rx_fifo_axis_tkeep),
.m_axis_tvalid(rx_fifo_axis_tvalid),
.m_axis_tready(1'b1),
.m_axis_tlast(rx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_fifo_axis_tuser)
);
axis_async_fifo #(
.DEPTH(RX_FIFO_DEPTH),
.DATA_WIDTH(AXI_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXI_STRB_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// Common reset
.async_rst(rx_rst | logic_rst),
// AXI input
.s_clk(rx_clk),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
axi_dma #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
.AXIS_DATA_WIDTH(AXI_DATA_WIDTH),
.AXIS_KEEP_ENABLE(1),
.AXIS_KEEP_WIDTH(AXI_STRB_WIDTH),
.AXIS_LAST_ENABLE(1),
.AXIS_ID_ENABLE(0),
.AXIS_DEST_ENABLE(0),
.AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(1),
.LEN_WIDTH(LEN_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.ENABLE_SG(ENABLE_SG),
.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
)
axi_dma_inst (
.clk(logic_clk),
.rst(logic_rst),
.s_axis_read_desc_addr(s_axis_tx_desc_addr),
.s_axis_read_desc_len(s_axis_tx_desc_len),
.s_axis_read_desc_tag(s_axis_tx_desc_tag),
.s_axis_read_desc_id(0),
.s_axis_read_desc_dest(0),
.s_axis_read_desc_user(s_axis_tx_desc_user),
.s_axis_read_desc_valid(s_axis_tx_desc_valid),
.s_axis_read_desc_ready(s_axis_tx_desc_ready),
.m_axis_read_desc_status_tag(m_axis_tx_desc_status_tag),
.m_axis_read_desc_status_valid(m_axis_tx_desc_status_valid),
.m_axis_read_data_tdata(tx_axis_tdata),
.m_axis_read_data_tkeep(tx_axis_tkeep),
.m_axis_read_data_tvalid(tx_axis_tvalid),
.m_axis_read_data_tready(tx_axis_tready),
.m_axis_read_data_tlast(tx_axis_tlast),
.m_axis_read_data_tid(),
.m_axis_read_data_tdest(),
.m_axis_read_data_tuser(tx_axis_tuser),
.s_axis_write_desc_addr(s_axis_rx_desc_addr),
.s_axis_write_desc_len(s_axis_rx_desc_len),
.s_axis_write_desc_tag(s_axis_rx_desc_tag),
.s_axis_write_desc_valid(s_axis_rx_desc_valid),
.s_axis_write_desc_ready(s_axis_rx_desc_ready),
.m_axis_write_desc_status_len(m_axis_rx_desc_status_len),
.m_axis_write_desc_status_tag(m_axis_rx_desc_status_tag),
.m_axis_write_desc_status_id(),
.m_axis_write_desc_status_dest(),
.m_axis_write_desc_status_user(m_axis_rx_desc_status_user),
.m_axis_write_desc_status_valid(m_axis_rx_desc_status_valid),
.s_axis_write_data_tdata(rx_axis_tdata),
.s_axis_write_data_tkeep(rx_axis_tkeep),
.s_axis_write_data_tvalid(rx_axis_tvalid),
.s_axis_write_data_tready(rx_axis_tready),
.s_axis_write_data_tlast(rx_axis_tlast),
.s_axis_write_data_tid(0),
.s_axis_write_data_tdest(0),
.s_axis_write_data_tuser(rx_axis_tuser),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.read_enable(tx_enable),
.write_enable(rx_enable),
.write_abort(rx_abort)
);
endmodule

99
fpga/common/rtl/interface.v
View File

@ -68,6 +68,7 @@ module interface #
parameter RAM_ADDR_WIDTH = 16,
parameter RAM_SIZE = 2**14,
parameter PTP_TS_ENABLE = 1,
parameter PTP_TS_WIDTH = 96,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter AXIL_DATA_WIDTH = 32,
@ -77,11 +78,10 @@ module interface #
parameter AXI_ADDR_WIDTH = 16,
parameter AXI_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
parameter AXI_ID_WIDTH = 8,
parameter AXI_MAX_BURST_LEN = 16,
parameter AXI_BASE_ADDR = 0,
parameter XGMII_DATA_WIDTH = 64,
parameter XGMII_CTRL_WIDTH = (XGMII_DATA_WIDTH/8),
parameter TX_FIFO_DEPTH = 4096,
parameter RX_FIFO_DEPTH = 4096
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH
)
(
input wire clk,
@ -205,16 +205,38 @@ module interface #
input wire s_axi_rready,
/*
* XGMII interface
* Transmit data output
*/
input wire [PORTS-1:0] xgmii_rx_clk,
input wire [PORTS-1:0] xgmii_rx_rst,
input wire [PORTS-1:0] xgmii_tx_clk,
input wire [PORTS-1:0] xgmii_tx_rst,
input wire [PORTS*XGMII_DATA_WIDTH-1:0] xgmii_rxd,
input wire [PORTS*XGMII_CTRL_WIDTH-1:0] xgmii_rxc,
output wire [PORTS*XGMII_DATA_WIDTH-1:0] xgmii_txd,
output wire [PORTS*XGMII_CTRL_WIDTH-1:0] xgmii_txc,
output wire [PORTS*AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
output wire [PORTS*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
output wire [PORTS-1:0] tx_axis_tvalid,
input wire [PORTS-1:0] tx_axis_tready,
output wire [PORTS-1:0] tx_axis_tlast,
output wire [PORTS-1:0] tx_axis_tuser,
/*
* Transmit timestamp input
*/
input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts_96,
input wire [PORTS-1:0] s_axis_tx_ptp_ts_valid,
output wire [PORTS-1:0] s_axis_tx_ptp_ts_ready,
/*
* Receive data input
*/
input wire [PORTS*AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
input wire [PORTS*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
input wire [PORTS-1:0] rx_axis_tvalid,
output wire [PORTS-1:0] rx_axis_tready,
input wire [PORTS-1:0] rx_axis_tlast,
input wire [PORTS-1:0] rx_axis_tuser,
/*
* Receive timestamp input
*/
input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_rx_ptp_ts_96,
input wire [PORTS-1:0] s_axis_rx_ptp_ts_valid,
output wire [PORTS-1:0] s_axis_rx_ptp_ts_ready,
/*
* PTP clock
@ -2309,6 +2331,10 @@ generate
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.QUEUE_LOG_SIZE_WIDTH(QUEUE_LOG_SIZE_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
@ -2316,11 +2342,10 @@ generate
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
.AXI_BASE_ADDR(23'h000000),
.XGMII_DATA_WIDTH(XGMII_DATA_WIDTH),
.XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH)
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
)
port_inst (
.clk(clk),
@ -2578,16 +2603,38 @@ generate
.s_axi_rready(axi_port_desc_rready[n +: 1]),
/*
* XGMII interface
* Transmit data output
*/
.xgmii_rx_clk(xgmii_rx_clk[n]),
.xgmii_rx_rst(xgmii_rx_rst[n]),
.xgmii_tx_clk(xgmii_tx_clk[n]),
.xgmii_tx_rst(xgmii_tx_rst[n]),
.xgmii_rxd(xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_rxc(xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
.xgmii_txd(xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]),
.xgmii_txc(xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]),
.tx_axis_tdata(tx_axis_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.tx_axis_tkeep(tx_axis_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.tx_axis_tvalid(tx_axis_tvalid[n +: 1]),
.tx_axis_tready(tx_axis_tready[n +: 1]),
.tx_axis_tlast(tx_axis_tlast[n +: 1]),
.tx_axis_tuser(tx_axis_tuser[n +: 1]),
/*
* Transmit timestamp input
*/
.s_axis_tx_ptp_ts_96(s_axis_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid[n +: 1]),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready[n +: 1]),
/*
* Receive data input
*/
.rx_axis_tdata(rx_axis_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.rx_axis_tkeep(rx_axis_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.rx_axis_tvalid(rx_axis_tvalid[n +: 1]),
.rx_axis_tready(rx_axis_tready[n +: 1]),
.rx_axis_tlast(rx_axis_tlast[n +: 1]),
.rx_axis_tuser(rx_axis_tuser[n +: 1]),
/*
* Receive timestamp input
*/
.s_axis_rx_ptp_ts_96(s_axis_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_rx_ptp_ts_valid(s_axis_rx_ptp_ts_valid[n +: 1]),
.s_axis_rx_ptp_ts_ready(s_axis_rx_ptp_ts_ready[n +: 1]),
/*
* PTP clock

309
fpga/common/rtl/port.v
View File

@ -58,6 +58,7 @@ module port #
parameter QUEUE_PTR_WIDTH = 16,
parameter QUEUE_LOG_SIZE_WIDTH = 4,
parameter PTP_TS_ENABLE = 1,
parameter PTP_TS_WIDTH = 96,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter AXIL_DATA_WIDTH = 32,
@ -67,11 +68,10 @@ module port #
parameter AXI_ADDR_WIDTH = 16,
parameter AXI_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
parameter AXI_ID_WIDTH = 8,
parameter AXI_MAX_BURST_LEN = 16,
parameter AXI_BASE_ADDR = 0,
parameter XGMII_DATA_WIDTH = 64,
parameter XGMII_CTRL_WIDTH = (XGMII_DATA_WIDTH/8),
parameter TX_FIFO_DEPTH = 4096,
parameter RX_FIFO_DEPTH = 4096
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH
)
(
input wire clk,
@ -329,21 +329,43 @@ module port #
input wire s_axi_rready,
/*
* XGMII interface
* Transmit data output
*/
input wire xgmii_rx_clk,
input wire xgmii_rx_rst,
input wire xgmii_tx_clk,
input wire xgmii_tx_rst,
input wire [XGMII_DATA_WIDTH-1:0] xgmii_rxd,
input wire [XGMII_CTRL_WIDTH-1:0] xgmii_rxc,
output wire [XGMII_DATA_WIDTH-1:0] xgmii_txd,
output wire [XGMII_CTRL_WIDTH-1:0] xgmii_txc,
output wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
output wire tx_axis_tvalid,
input wire tx_axis_tready,
output wire tx_axis_tlast,
output wire tx_axis_tuser,
/*
* Transmit PTP timestamp input
*/
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts_96,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
/*
* Receive data input
*/
input wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
input wire rx_axis_tvalid,
output wire rx_axis_tready,
input wire rx_axis_tlast,
input wire rx_axis_tuser,
/*
* Receive PTP timestamp input
*/
input wire [PTP_TS_WIDTH-1:0] s_axis_rx_ptp_ts_96,
input wire s_axis_rx_ptp_ts_valid,
output wire s_axis_rx_ptp_ts_ready,
/*
* PTP clock
*/
input wire [95:0] ptp_ts_96,
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step
);
@ -449,6 +471,14 @@ wire axi_rx_rlast;
wire axi_rx_rvalid;
wire axi_rx_rready;
// Checksumming
wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
wire tx_axis_tvalid_int;
wire tx_axis_tready_int;
wire tx_axis_tlast_int;
wire tx_axis_tuser_int;
// PCIe DMA
wire [PCIE_ADDR_WIDTH-1:0] tx_pcie_axi_dma_read_desc_pcie_addr;
wire [AXI_ADDR_WIDTH-1:0] tx_pcie_axi_dma_read_desc_axi_addr;
@ -501,53 +531,47 @@ wire [REQ_TAG_WIDTH-1:0] tx_req_status_tag;
wire tx_req_status_valid;
// RX engine
reg [7:0] rx_pkt_cnt_reg = 0;
reg rx_frame_reg = 0;
wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue = 0; // TODO RSS of some form
wire [REQ_TAG_WIDTH-1:0] rx_req_tag = 0;
wire rx_req_valid = rx_pkt_cnt_reg > 0;
wire rx_req_valid = rx_axis_tvalid && !rx_frame_reg;
wire rx_req_ready;
wire [REQ_TAG_WIDTH-1:0] rx_req_status_tag;
wire rx_req_status_valid;
always @(posedge clk) begin
if (rx_axis_tready && rx_axis_tvalid) begin
rx_frame_reg <= !rx_axis_tlast;
end
if (rst) begin
rx_pkt_cnt_reg <= 0;
end else begin
if (rx_pkt_cnt_reg > 0 && rx_req_ready) begin
if (!eth_rx_fifo_good_frame) begin
rx_pkt_cnt_reg <= rx_pkt_cnt_reg - 1;
end
end else begin
if (eth_rx_fifo_good_frame) begin
rx_pkt_cnt_reg <= rx_pkt_cnt_reg + 1;
end
end
rx_frame_reg <= 1'b0;
end
end
// Timestamps
wire [96:0] rx_ptp_ts_96;
wire [95:0] rx_ptp_ts_96;
wire rx_ptp_ts_valid;
wire rx_ptp_ts_ready;
wire [96:0] tx_ptp_ts_96;
wire [95:0] tx_ptp_ts_96;
wire tx_ptp_ts_valid;
wire tx_ptp_ts_ready;
// Checksums
wire [96:0] rx_csum;
wire [15:0] rx_csum;
wire rx_csum_valid;
wire [96:0] rx_fifo_csum;
wire [15:0] rx_fifo_csum;
wire rx_fifo_csum_valid;
wire rx_fifo_csum_ready;
// wire [96:0] tx_csum;
// wire [15:0] tx_csum;
// wire tx_csum_valid;
// wire [96:0] tx_fifo_csum;
// wire [15:0] tx_fifo_csum;
// wire tx_fifo_csum_valid;
// wire tx_fifo_csum_ready;
@ -965,9 +989,9 @@ tx_engine_inst (
/*
* Transmit timestamp input
*/
.s_axis_tx_ptp_ts_96(tx_ptp_ts_96),
.s_axis_tx_ptp_ts_valid(tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(tx_ptp_ts_ready),
.s_axis_tx_ptp_ts_96(s_axis_tx_ptp_ts_96),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
/*
* AXI slave interface
@ -1201,9 +1225,9 @@ rx_engine_inst (
/*
* Receive timestamp input
*/
.s_axis_rx_ptp_ts_96(rx_ptp_ts_96),
.s_axis_rx_ptp_ts_valid(rx_ptp_ts_valid),
.s_axis_rx_ptp_ts_ready(rx_ptp_ts_ready),
.s_axis_rx_ptp_ts_96(s_axis_rx_ptp_ts_96),
.s_axis_rx_ptp_ts_valid(s_axis_rx_ptp_ts_valid),
.s_axis_rx_ptp_ts_ready(s_axis_rx_ptp_ts_ready),
/*
* Receive checksum input
@ -1257,107 +1281,119 @@ rx_engine_inst (
.enable(1'b1)
);
eth_interface #(
.DATA_WIDTH(XGMII_DATA_WIDTH),
.CTRL_WIDTH(XGMII_CTRL_WIDTH),
generate
if (RX_CHECKSUM_ENABLE) begin
rx_checksum #(
.DATA_WIDTH(AXI_DATA_WIDTH)
)
rx_checksum_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid & rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.m_axis_csum(rx_csum),
.m_axis_csum_valid(rx_csum_valid)
);
end else begin
assign m_axis_rx_csum = 16'd0;
assign m_axis_rx_csum_valid = 1'b0;
end
if (TX_CHECKSUM_ENABLE) begin
assign tx_axis_tdata = tx_axis_tdata_int;
assign tx_axis_tkeep = tx_axis_tkeep_int;
assign tx_axis_tvalid = tx_axis_tvalid_int;
assign tx_axis_tready_int = tx_axis_tready;
assign tx_axis_tlast = tx_axis_tlast_int;
assign tx_axis_tuser = tx_axis_tuser_int;
end else begin
assign tx_axis_tdata = tx_axis_tdata_int;
assign tx_axis_tkeep = tx_axis_tkeep_int;
assign tx_axis_tvalid = tx_axis_tvalid_int;
assign tx_axis_tready_int = tx_axis_tready;
assign tx_axis_tlast = tx_axis_tlast_int;
assign tx_axis_tuser = tx_axis_tuser_int;
end
endgenerate
axi_dma #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(16),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE(1),
.AXIS_ID_ENABLE(0),
.AXIS_DEST_ENABLE(0),
.AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(1),
.LEN_WIDTH(AXI_DMA_LEN_WIDTH),
.TAG_WIDTH(AXI_DMA_TAG_WIDTH),
.ENABLE_SG(0),
.ENABLE_UNALIGNED(1),
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.LOGIC_PTP_PERIOD_NS(4'h4),
.LOGIC_PTP_PERIOD_FNS(16'h0000),
.PTP_PERIOD_NS(4'h6),
.PTP_PERIOD_FNS(16'h6666),
.TX_PTP_TS_ENABLE(1),
.RX_PTP_TS_ENABLE(1)//,
//.PTP_TS_WIDTH(96),
//.TX_PTP_TAG_ENABLE(1),
//.PTP_TAG_WIDTH(PTP_TAG_WIDTH)
.ENABLE_UNALIGNED(1)
)
eth_interface_inst (
.rx_clk(xgmii_rx_clk),
.rx_rst(xgmii_rx_rst),
.tx_clk(xgmii_tx_clk),
.tx_rst(xgmii_tx_rst),
.logic_clk(clk),
.logic_rst(rst),
axi_dma_inst (
.clk(clk),
.rst(rst),
/*
* Transmit descriptor input
*/
.s_axis_tx_desc_addr(dma_tx_desc_addr),
.s_axis_tx_desc_len(dma_tx_desc_len),
.s_axis_tx_desc_tag(dma_tx_desc_tag),
.s_axis_tx_desc_user(dma_tx_desc_user),
.s_axis_tx_desc_valid(dma_tx_desc_valid),
.s_axis_tx_desc_ready(dma_tx_desc_ready),
.s_axis_read_desc_addr(dma_tx_desc_addr),
.s_axis_read_desc_len(dma_tx_desc_len),
.s_axis_read_desc_tag(dma_tx_desc_tag),
.s_axis_read_desc_id(0),
.s_axis_read_desc_dest(0),
.s_axis_read_desc_user(dma_tx_desc_user),
.s_axis_read_desc_valid(dma_tx_desc_valid),
.s_axis_read_desc_ready(dma_tx_desc_ready),
/*
* Transmit descriptor status output
*/
.m_axis_tx_desc_status_tag(dma_tx_desc_status_tag),
.m_axis_tx_desc_status_valid(dma_tx_desc_status_valid),
.m_axis_read_desc_status_tag(dma_tx_desc_status_tag),
.m_axis_read_desc_status_valid(dma_tx_desc_status_valid),
/*
* Transmit timestamp tag input
*/
.s_axis_tx_ptp_ts_tag(0),
.s_axis_tx_ptp_ts_valid(1'b0),
.s_axis_tx_ptp_ts_ready(),
.m_axis_read_data_tdata(tx_axis_tdata_int),
.m_axis_read_data_tkeep(tx_axis_tkeep_int),
.m_axis_read_data_tvalid(tx_axis_tvalid_int),
.m_axis_read_data_tready(tx_axis_tready_int),
.m_axis_read_data_tlast(tx_axis_tlast_int),
.m_axis_read_data_tid(),
.m_axis_read_data_tdest(),
.m_axis_read_data_tuser(tx_axis_tuser_int),
/*
* Transmit timestamp output
*/
.m_axis_tx_ptp_ts_96(tx_ptp_ts_96),
.m_axis_tx_ptp_ts_tag(),
.m_axis_tx_ptp_ts_valid(tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(tx_ptp_ts_ready),
.s_axis_write_desc_addr(dma_rx_desc_addr),
.s_axis_write_desc_len(dma_rx_desc_len),
.s_axis_write_desc_tag(dma_rx_desc_tag),
.s_axis_write_desc_valid(dma_rx_desc_valid),
.s_axis_write_desc_ready(dma_rx_desc_ready),
/*
* Receive descriptor input
*/
.s_axis_rx_desc_addr(dma_rx_desc_addr),
.s_axis_rx_desc_len(dma_rx_desc_len),
.s_axis_rx_desc_tag(dma_rx_desc_tag),
.s_axis_rx_desc_valid(dma_rx_desc_valid),
.s_axis_rx_desc_ready(dma_rx_desc_ready),
.m_axis_write_desc_status_len(dma_rx_desc_status_len),
.m_axis_write_desc_status_tag(dma_rx_desc_status_tag),
.m_axis_write_desc_status_id(),
.m_axis_write_desc_status_dest(),
.m_axis_write_desc_status_user(dma_rx_desc_status_user),
.m_axis_write_desc_status_valid(dma_rx_desc_status_valid),
/*
* Receive descriptor status output
*/
.m_axis_rx_desc_status_len(dma_rx_desc_status_len),
.m_axis_rx_desc_status_tag(dma_rx_desc_status_tag),
.m_axis_rx_desc_status_user(dma_rx_desc_status_user),
.m_axis_rx_desc_status_valid(dma_rx_desc_status_valid),
.s_axis_write_data_tdata(rx_axis_tdata),
.s_axis_write_data_tkeep(rx_axis_tkeep),
.s_axis_write_data_tvalid(rx_axis_tvalid),
.s_axis_write_data_tready(rx_axis_tready),
.s_axis_write_data_tlast(rx_axis_tlast),
.s_axis_write_data_tid(0),
.s_axis_write_data_tdest(0),
.s_axis_write_data_tuser(rx_axis_tuser),
/*
* Receive timestamp output
*/
.m_axis_rx_ptp_ts_96(rx_ptp_ts_96),
.m_axis_rx_ptp_ts_valid(rx_ptp_ts_valid),
.m_axis_rx_ptp_ts_ready(rx_ptp_ts_ready),
/*
* Receive checksum output
*/
.m_axis_rx_csum(rx_csum),
.m_axis_rx_csum_valid(rx_csum_valid),
/*
* AXI master interface
*/
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
@ -1394,26 +1430,9 @@ eth_interface_inst (
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_fifo_overflow(eth_tx_fifo_overflow),
.tx_fifo_bad_frame(eth_tx_fifo_bad_frame),
.tx_fifo_good_frame(eth_tx_fifo_good_frame),
.rx_error_bad_frame(eth_rx_error_bad_frame),
.rx_error_bad_fcs(eth_rx_error_bad_fcs),
.rx_fifo_overflow(eth_rx_fifo_overflow),
.rx_fifo_bad_frame(eth_rx_fifo_bad_frame),
.rx_fifo_good_frame(eth_rx_fifo_good_frame),
.ptp_ts_96(ptp_ts_96),
.tx_enable(dma_enable),
.rx_enable(dma_enable),
.rx_abort(1'b0),
.ifg_delay(8'd12)
.read_enable(dma_enable),
.write_enable(dma_enable),
.write_abort(1'b0)
);
parameter RAM_COUNT = 3;

2
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
View File

@ -14,7 +14,6 @@ SYN_FILES += rtl/common/interface.v
SYN_FILES += rtl/common/port.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/eth_interface.v
SYN_FILES += rtl/common/event_queue.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
@ -25,6 +24,7 @@ SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v

211
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -259,6 +259,10 @@ parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
parameter PCIE_DMA_TAG_WIDTH = 16;
@ -278,8 +282,9 @@ parameter BOARD_VER = {16'd0, 16'd1};
// Structural parameters
parameter IF_COUNT = 2;
parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 32;
@ -301,6 +306,25 @@ parameter RX_PKT_TABLE_SIZE = 8;
parameter TX_SCHEDULER = "RR";
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
parameter LOGIC_PTP_PERIOD_NS = 6'h4;
parameter LOGIC_PTP_PERIOD_FNS = 16'h0000;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 1;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TS_FIFO_DEPTH = 32;
parameter RX_PTP_TS_FIFO_DEPTH = 32;
// Interface parameters (port)
parameter TX_CHECKSUM_ENABLE = 1;
parameter RX_CHECKSUM_ENABLE = 1;
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 32768;
parameter RX_FIFO_DEPTH = 32768;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
wire [2:0] axil_pcie_awprot;
@ -1850,17 +1874,17 @@ tdma_ber_inst (
.ptp_ts_step(ptp_ts_step)
);
wire [IF_COUNT-1:0] if_xgmii_tx_clk = {qsfp_1_tx_clk_0, qsfp_0_tx_clk_0};
wire [IF_COUNT-1:0] if_xgmii_tx_rst = {qsfp_1_tx_rst_0, qsfp_0_tx_rst_0};
wire [IF_COUNT-1:0] if_xgmii_rx_clk = {qsfp_1_rx_clk_0, qsfp_0_rx_clk_0};
wire [IF_COUNT-1:0] if_xgmii_rx_rst = {qsfp_1_rx_rst_0, qsfp_0_rx_rst_0};
wire [IF_COUNT*64-1:0] if_xgmii_txd;
wire [IF_COUNT*8-1:0] if_xgmii_txc;
wire [IF_COUNT*64-1:0] if_xgmii_rxd = {qsfp_1_rxd_0, qsfp_0_rxd_0};
wire [IF_COUNT*8-1:0] if_xgmii_rxc = {qsfp_1_rxc_0, qsfp_0_rxc_0};
wire [PORT_COUNT-1:0] port_xgmii_tx_clk = {qsfp_1_tx_clk_0, qsfp_0_tx_clk_0};
wire [PORT_COUNT-1:0] port_xgmii_tx_rst = {qsfp_1_tx_rst_0, qsfp_0_tx_rst_0};
wire [PORT_COUNT-1:0] port_xgmii_rx_clk = {qsfp_1_rx_clk_0, qsfp_0_rx_clk_0};
wire [PORT_COUNT-1:0] port_xgmii_rx_rst = {qsfp_1_rx_rst_0, qsfp_0_rx_rst_0};
wire [PORT_COUNT*64-1:0] port_xgmii_txd;
wire [PORT_COUNT*8-1:0] port_xgmii_txc;
wire [PORT_COUNT*64-1:0] port_xgmii_rxd = {qsfp_1_rxd_0, qsfp_0_rxd_0};
wire [PORT_COUNT*8-1:0] port_xgmii_rxc = {qsfp_1_rxc_0, qsfp_0_rxc_0};
assign {qsfp_1_txd_0, qsfp_0_txd_0} = if_xgmii_txd;
assign {qsfp_1_txc_0, qsfp_0_txc_0} = if_xgmii_txc;
assign {qsfp_1_txd_0, qsfp_0_txd_0} = port_xgmii_txd;
assign {qsfp_1_txc_0, qsfp_0_txc_0} = port_xgmii_txc;
// assign qsfp_0_txd_0 = 64'h0707070707070707;
// assign qsfp_0_txc_0 = 8'hff;
@ -1891,7 +1915,7 @@ wire [IF_COUNT*32-1:0] if_msi_irq;
assign msi_irq = if_msi_irq[31:0] | if_msi_irq[63:32];
generate
genvar n;
genvar m, n;
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
@ -1900,9 +1924,30 @@ generate
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
interface #
(
.PORTS(PORT_COUNT),
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
wire [PORTS_PER_IF-1:0] tx_axis_tready;
wire [PORTS_PER_IF-1:0] tx_axis_tlast;
wire [PORTS_PER_IF-1:0] tx_axis_tuser;
wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PORTS_PER_IF-1:0] tx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] tx_ptp_ts_ready;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire [PORTS_PER_IF-1:0] rx_axis_tvalid;
wire [PORTS_PER_IF-1:0] rx_axis_tready;
wire [PORTS_PER_IF-1:0] rx_axis_tlast;
wire [PORTS_PER_IF-1:0] rx_axis_tuser;
wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
@ -1925,7 +1970,10 @@ generate
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(1),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
@ -1934,10 +1982,8 @@ generate
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.XGMII_DATA_WIDTH(64),
.XGMII_CTRL_WIDTH(8),
.TX_FIFO_DEPTH(32768),
.RX_FIFO_DEPTH(32768)
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
)
interface_inst (
.clk(clk_250mhz),
@ -2061,16 +2107,38 @@ generate
.s_axi_rready(axi_if_rready[n]),
/*
* XGMII interface
* Transmit data output
*/
.xgmii_rx_clk(if_xgmii_rx_clk[n]),
.xgmii_rx_rst(if_xgmii_rx_rst[n]),
.xgmii_tx_clk(if_xgmii_tx_clk[n]),
.xgmii_tx_rst(if_xgmii_tx_rst[n]),
.xgmii_rxd(if_xgmii_rxd[n*64 +: 64]),
.xgmii_rxc(if_xgmii_rxc[n*8 +: 8]),
.xgmii_txd(if_xgmii_txd[n*64 +: 64]),
.xgmii_txc(if_xgmii_txc[n*8 +: 8]),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
/*
* Transmit timestamp input
*/
.s_axis_tx_ptp_ts_96(tx_ptp_ts_96),
.s_axis_tx_ptp_ts_valid(tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(tx_ptp_ts_ready),
/*
* Receive data input
*/
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
/*
* Receive timestamp input
*/
.s_axis_rx_ptp_ts_96(rx_ptp_ts_96),
.s_axis_rx_ptp_ts_valid(rx_ptp_ts_valid),
.s_axis_rx_ptp_ts_ready(rx_ptp_ts_ready),
/*
* PTP clock
@ -2084,6 +2152,91 @@ generate
.msi_irq(if_msi_irq[n*32 +: 32])
);
for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : mac
eth_mac_10g_fifo #(
.DATA_WIDTH(64),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FRAME_FIFO(1),
.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
.PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(0),
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(0),
.PTP_TAG_WIDTH(16)
)
eth_mac_inst (
.rx_clk(port_xgmii_rx_clk[n*PORTS_PER_IF+m]),
.rx_rst(port_xgmii_rx_rst[n*PORTS_PER_IF+m]),
.tx_clk(port_xgmii_tx_clk[n*PORTS_PER_IF+m]),
.tx_rst(port_xgmii_tx_rst[n*PORTS_PER_IF+m]),
.logic_clk(clk_250mhz),
.logic_rst(rst_250mhz),
.ptp_sample_clk(clk_250mhz),
.tx_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.tx_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.tx_axis_tvalid(tx_axis_tvalid[m +: 1]),
.tx_axis_tready(tx_axis_tready[m +: 1]),
.tx_axis_tlast(tx_axis_tlast[m +: 1]),
.tx_axis_tuser(tx_axis_tuser[m +: 1]),
.s_axis_tx_ptp_ts_tag(0),
.s_axis_tx_ptp_ts_valid(0),
.s_axis_tx_ptp_ts_ready(),
.m_axis_tx_ptp_ts_96(tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_tx_ptp_ts_tag(),
.m_axis_tx_ptp_ts_valid(tx_ptp_ts_valid[m +: 1]),
.m_axis_tx_ptp_ts_ready(tx_ptp_ts_ready[m +: 1]),
.rx_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.rx_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.rx_axis_tvalid(rx_axis_tvalid[m +: 1]),
.rx_axis_tready(rx_axis_tready[m +: 1]),
.rx_axis_tlast(rx_axis_tlast[m +: 1]),
.rx_axis_tuser(rx_axis_tuser[m +: 1]),
.m_axis_rx_ptp_ts_96(rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_rx_ptp_ts_valid(rx_ptp_ts_valid[m +: 1]),
.m_axis_rx_ptp_ts_ready(rx_ptp_ts_ready[m +: 1]),
.xgmii_rxd(port_xgmii_rxd[(n*PORTS_PER_IF+m)*64 +: 64]),
.xgmii_rxc(port_xgmii_rxc[(n*PORTS_PER_IF+m)*8 +: 8]),
.xgmii_txd(port_xgmii_txd[(n*PORTS_PER_IF+m)*64 +: 64]),
.xgmii_txc(port_xgmii_txc[(n*PORTS_PER_IF+m)*8 +: 8]),
.tx_error_underflow(),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ptp_ts_96(ptp_ts_96),
.ifg_delay(8'd12)
);
end
end
endgenerate

1
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -59,7 +59,6 @@ srcs.append("../rtl/common/rx_checksum.v")
srcs.append("../rtl/common/tx_scheduler_rr.v")
srcs.append("../rtl/common/event_queue.v")
srcs.append("../rtl/common/event_mux.v")
srcs.append("../rtl/common/eth_interface.v")
srcs.append("../rtl/common/tdma_scheduler.v")
srcs.append("../rtl/common/tdma_ber.v")
srcs.append("../rtl/common/tdma_ber_ch.v")

2
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -14,7 +14,6 @@ SYN_FILES += rtl/common/interface.v
SYN_FILES += rtl/common/port.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/eth_interface.v
SYN_FILES += rtl/common/event_queue.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
@ -23,6 +22,7 @@ SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v

208
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -197,6 +197,10 @@ parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
parameter PCIE_DMA_TAG_WIDTH = 16;
@ -216,8 +220,9 @@ parameter BOARD_VER = {16'd0, 16'd1};
// Structural parameters
parameter IF_COUNT = 2;
parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 16;
@ -239,6 +244,25 @@ parameter RX_PKT_TABLE_SIZE = 8;
parameter TX_SCHEDULER = "RR";
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
parameter LOGIC_PTP_PERIOD_NS = 6'h4;
parameter LOGIC_PTP_PERIOD_FNS = 16'h0000;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 1;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TS_FIFO_DEPTH = 32;
parameter RX_PTP_TS_FIFO_DEPTH = 32;
// Interface parameters (port)
parameter TX_CHECKSUM_ENABLE = 1;
parameter RX_CHECKSUM_ENABLE = 1;
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 16384;
parameter RX_FIFO_DEPTH = 16384;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
wire [2:0] axil_pcie_awprot;
@ -1832,17 +1856,17 @@ always @(posedge clk_250mhz) begin
pps_led_reg <= pps_led_counter_reg > 0;
end
wire [IF_COUNT-1:0] if_xgmii_tx_clk = {sfp_2_tx_clk, sfp_1_tx_clk};
wire [IF_COUNT-1:0] if_xgmii_tx_rst = {sfp_2_tx_rst, sfp_1_tx_rst};
wire [IF_COUNT-1:0] if_xgmii_rx_clk = {sfp_2_rx_clk, sfp_1_rx_clk};
wire [IF_COUNT-1:0] if_xgmii_rx_rst = {sfp_2_rx_rst, sfp_1_rx_rst};
wire [IF_COUNT*64-1:0] if_xgmii_txd;
wire [IF_COUNT*8-1:0] if_xgmii_txc;
wire [IF_COUNT*64-1:0] if_xgmii_rxd = {sfp_2_rxd, sfp_1_rxd};
wire [IF_COUNT*8-1:0] if_xgmii_rxc = {sfp_2_rxc, sfp_1_rxc};
wire [PORT_COUNT-1:0] port_xgmii_tx_clk = {sfp_2_tx_clk, sfp_1_tx_clk};
wire [PORT_COUNT-1:0] port_xgmii_tx_rst = {sfp_2_tx_rst, sfp_1_tx_rst};
wire [PORT_COUNT-1:0] port_xgmii_rx_clk = {sfp_2_rx_clk, sfp_1_rx_clk};
wire [PORT_COUNT-1:0] port_xgmii_rx_rst = {sfp_2_rx_rst, sfp_1_rx_rst};
wire [PORT_COUNT*64-1:0] port_xgmii_txd;
wire [PORT_COUNT*8-1:0] port_xgmii_txc;
wire [PORT_COUNT*64-1:0] port_xgmii_rxd = {sfp_2_rxd, sfp_1_rxd};
wire [PORT_COUNT*8-1:0] port_xgmii_rxc = {sfp_2_rxc, sfp_1_rxc};
assign {sfp_2_txd, sfp_1_txd} = if_xgmii_txd;
assign {sfp_2_txc, sfp_1_txc} = if_xgmii_txc;
assign {sfp_2_txd, sfp_1_txd} = port_xgmii_txd;
assign {sfp_2_txc, sfp_1_txc} = port_xgmii_txc;
assign sfp_1_led = 2'b00;
assign sfp_2_led = 2'b00;
@ -1854,7 +1878,7 @@ wire [IF_COUNT*32-1:0] if_msi_irq;
assign msi_irq = if_msi_irq[31:0] | if_msi_irq[63:32];
generate
genvar n;
genvar m, n;
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
@ -1863,9 +1887,31 @@ generate
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
wire [PORTS_PER_IF-1:0] tx_axis_tready;
wire [PORTS_PER_IF-1:0] tx_axis_tlast;
wire [PORTS_PER_IF-1:0] tx_axis_tuser;
wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PORTS_PER_IF-1:0] tx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] tx_ptp_ts_ready;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire [PORTS_PER_IF-1:0] rx_axis_tvalid;
wire [PORTS_PER_IF-1:0] rx_axis_tready;
wire [PORTS_PER_IF-1:0] rx_axis_tlast;
wire [PORTS_PER_IF-1:0] rx_axis_tuser;
wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
interface #
(
.PORTS(PORT_COUNT),
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
@ -1888,7 +1934,10 @@ generate
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(1),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
@ -1897,10 +1946,8 @@ generate
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.XGMII_DATA_WIDTH(64),
.XGMII_CTRL_WIDTH(8),
.TX_FIFO_DEPTH(16384),
.RX_FIFO_DEPTH(16384)
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
)
interface_inst (
.clk(clk_250mhz),
@ -2024,16 +2071,38 @@ generate
.s_axi_rready(axi_if_rready[n]),
/*
* XGMII interface
* Transmit data output
*/
.xgmii_rx_clk(if_xgmii_rx_clk[n]),
.xgmii_rx_rst(if_xgmii_rx_rst[n]),
.xgmii_tx_clk(if_xgmii_tx_clk[n]),
.xgmii_tx_rst(if_xgmii_tx_rst[n]),
.xgmii_rxd(if_xgmii_rxd[n*64 +: 64]),
.xgmii_rxc(if_xgmii_rxc[n*8 +: 8]),
.xgmii_txd(if_xgmii_txd[n*64 +: 64]),
.xgmii_txc(if_xgmii_txc[n*8 +: 8]),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
/*
* Transmit timestamp input
*/
.s_axis_tx_ptp_ts_96(tx_ptp_ts_96),
.s_axis_tx_ptp_ts_valid(tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(tx_ptp_ts_ready),
/*
* Receive data input
*/
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
/*
* Receive timestamp input
*/
.s_axis_rx_ptp_ts_96(rx_ptp_ts_96),
.s_axis_rx_ptp_ts_valid(rx_ptp_ts_valid),
.s_axis_rx_ptp_ts_ready(rx_ptp_ts_ready),
/*
* PTP clock
@ -2047,6 +2116,91 @@ generate
.msi_irq(if_msi_irq[n*32 +: 32])
);
for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : mac
eth_mac_10g_fifo #(
.DATA_WIDTH(64),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FRAME_FIFO(1),
.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
.PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(0),
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(0),
.PTP_TAG_WIDTH(16)
)
eth_mac_inst (
.rx_clk(port_xgmii_rx_clk[n*PORTS_PER_IF+m]),
.rx_rst(port_xgmii_rx_rst[n*PORTS_PER_IF+m]),
.tx_clk(port_xgmii_tx_clk[n*PORTS_PER_IF+m]),
.tx_rst(port_xgmii_tx_rst[n*PORTS_PER_IF+m]),
.logic_clk(clk_250mhz),
.logic_rst(rst_250mhz),
.ptp_sample_clk(clk_250mhz),
.tx_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.tx_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.tx_axis_tvalid(tx_axis_tvalid[m +: 1]),
.tx_axis_tready(tx_axis_tready[m +: 1]),
.tx_axis_tlast(tx_axis_tlast[m +: 1]),
.tx_axis_tuser(tx_axis_tuser[m +: 1]),
.s_axis_tx_ptp_ts_tag(0),
.s_axis_tx_ptp_ts_valid(0),
.s_axis_tx_ptp_ts_ready(),
.m_axis_tx_ptp_ts_96(tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_tx_ptp_ts_tag(),
.m_axis_tx_ptp_ts_valid(tx_ptp_ts_valid[m +: 1]),
.m_axis_tx_ptp_ts_ready(tx_ptp_ts_ready[m +: 1]),
.rx_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.rx_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.rx_axis_tvalid(rx_axis_tvalid[m +: 1]),
.rx_axis_tready(rx_axis_tready[m +: 1]),
.rx_axis_tlast(rx_axis_tlast[m +: 1]),
.rx_axis_tuser(rx_axis_tuser[m +: 1]),
.m_axis_rx_ptp_ts_96(rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_rx_ptp_ts_valid(rx_ptp_ts_valid[m +: 1]),
.m_axis_rx_ptp_ts_ready(rx_ptp_ts_ready[m +: 1]),
.xgmii_rxd(port_xgmii_rxd[(n*PORTS_PER_IF+m)*64 +: 64]),
.xgmii_rxc(port_xgmii_rxc[(n*PORTS_PER_IF+m)*8 +: 8]),
.xgmii_txd(port_xgmii_txd[(n*PORTS_PER_IF+m)*64 +: 64]),
.xgmii_txc(port_xgmii_txc[(n*PORTS_PER_IF+m)*8 +: 8]),
.tx_error_underflow(),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ptp_ts_96(ptp_ts_96),
.ifg_delay(8'd12)
);
end
end
endgenerate

1
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -60,7 +60,6 @@ srcs.append("../rtl/common/tx_scheduler_rr.v")
srcs.append("../rtl/common/tdma_scheduler.v")
srcs.append("../rtl/common/event_queue.v")
srcs.append("../rtl/common/event_mux.v")
srcs.append("../rtl/common/eth_interface.v")
srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")

2
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
View File

@ -14,7 +14,6 @@ SYN_FILES += rtl/common/interface.v
SYN_FILES += rtl/common/port.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/eth_interface.v
SYN_FILES += rtl/common/event_queue.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/tx_scheduler_tdma_rr.v
@ -25,6 +24,7 @@ SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v

211
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -259,6 +259,10 @@ parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
parameter PCIE_DMA_TAG_WIDTH = 16;
@ -278,8 +282,9 @@ parameter BOARD_VER = {16'd0, 16'd1};
// Structural parameters
parameter IF_COUNT = 2;
parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 32;
@ -301,6 +306,25 @@ parameter RX_PKT_TABLE_SIZE = 8;
parameter TX_SCHEDULER = "TDMA_RR";
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
parameter LOGIC_PTP_PERIOD_NS = 6'h4;
parameter LOGIC_PTP_PERIOD_FNS = 16'h0000;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 1;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TS_FIFO_DEPTH = 32;
parameter RX_PTP_TS_FIFO_DEPTH = 32;
// Interface parameters (port)
parameter TX_CHECKSUM_ENABLE = 1;
parameter RX_CHECKSUM_ENABLE = 1;
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 32768;
parameter RX_FIFO_DEPTH = 32768;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
wire [2:0] axil_pcie_awprot;
@ -1850,17 +1874,17 @@ tdma_ber_inst (
.ptp_ts_step(ptp_ts_step)
);
wire [IF_COUNT-1:0] if_xgmii_tx_clk = {qsfp_1_tx_clk_0, qsfp_0_tx_clk_0};
wire [IF_COUNT-1:0] if_xgmii_tx_rst = {qsfp_1_tx_rst_0, qsfp_0_tx_rst_0};
wire [IF_COUNT-1:0] if_xgmii_rx_clk = {qsfp_1_rx_clk_0, qsfp_0_rx_clk_0};
wire [IF_COUNT-1:0] if_xgmii_rx_rst = {qsfp_1_rx_rst_0, qsfp_0_rx_rst_0};
wire [IF_COUNT*64-1:0] if_xgmii_txd;
wire [IF_COUNT*8-1:0] if_xgmii_txc;
wire [IF_COUNT*64-1:0] if_xgmii_rxd = {qsfp_1_rxd_0, qsfp_0_rxd_0};
wire [IF_COUNT*8-1:0] if_xgmii_rxc = {qsfp_1_rxc_0, qsfp_0_rxc_0};
wire [PORT_COUNT-1:0] port_xgmii_tx_clk = {qsfp_1_tx_clk_0, qsfp_0_tx_clk_0};
wire [PORT_COUNT-1:0] port_xgmii_tx_rst = {qsfp_1_tx_rst_0, qsfp_0_tx_rst_0};
wire [PORT_COUNT-1:0] port_xgmii_rx_clk = {qsfp_1_rx_clk_0, qsfp_0_rx_clk_0};
wire [PORT_COUNT-1:0] port_xgmii_rx_rst = {qsfp_1_rx_rst_0, qsfp_0_rx_rst_0};
wire [PORT_COUNT*64-1:0] port_xgmii_txd;
wire [PORT_COUNT*8-1:0] port_xgmii_txc;
wire [PORT_COUNT*64-1:0] port_xgmii_rxd = {qsfp_1_rxd_0, qsfp_0_rxd_0};
wire [PORT_COUNT*8-1:0] port_xgmii_rxc = {qsfp_1_rxc_0, qsfp_0_rxc_0};
assign {qsfp_1_txd_0, qsfp_0_txd_0} = if_xgmii_txd;
assign {qsfp_1_txc_0, qsfp_0_txc_0} = if_xgmii_txc;
assign {qsfp_1_txd_0, qsfp_0_txd_0} = port_xgmii_txd;
assign {qsfp_1_txc_0, qsfp_0_txc_0} = port_xgmii_txc;
// assign qsfp_0_txd_0 = 64'h0707070707070707;
// assign qsfp_0_txc_0 = 8'hff;
@ -1891,7 +1915,7 @@ wire [IF_COUNT*32-1:0] if_msi_irq;
assign msi_irq = if_msi_irq[31:0] | if_msi_irq[63:32];
generate
genvar n;
genvar m, n;
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
@ -1900,9 +1924,30 @@ generate
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
interface #
(
.PORTS(PORT_COUNT),
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
wire [PORTS_PER_IF-1:0] tx_axis_tready;
wire [PORTS_PER_IF-1:0] tx_axis_tlast;
wire [PORTS_PER_IF-1:0] tx_axis_tuser;
wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PORTS_PER_IF-1:0] tx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] tx_ptp_ts_ready;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire [PORTS_PER_IF-1:0] rx_axis_tvalid;
wire [PORTS_PER_IF-1:0] rx_axis_tready;
wire [PORTS_PER_IF-1:0] rx_axis_tlast;
wire [PORTS_PER_IF-1:0] rx_axis_tuser;
wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
interface #(
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
@ -1925,7 +1970,10 @@ generate
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(1),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
@ -1934,10 +1982,8 @@ generate
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.XGMII_DATA_WIDTH(64),
.XGMII_CTRL_WIDTH(8),
.TX_FIFO_DEPTH(32768),
.RX_FIFO_DEPTH(32768)
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
)
interface_inst (
.clk(clk_250mhz),
@ -2061,16 +2107,38 @@ generate
.s_axi_rready(axi_if_rready[n]),
/*
* XGMII interface
* Transmit data output
*/
.xgmii_rx_clk(if_xgmii_rx_clk[n]),
.xgmii_rx_rst(if_xgmii_rx_rst[n]),
.xgmii_tx_clk(if_xgmii_tx_clk[n]),
.xgmii_tx_rst(if_xgmii_tx_rst[n]),
.xgmii_rxd(if_xgmii_rxd[n*64 +: 64]),
.xgmii_rxc(if_xgmii_rxc[n*8 +: 8]),
.xgmii_txd(if_xgmii_txd[n*64 +: 64]),
.xgmii_txc(if_xgmii_txc[n*8 +: 8]),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
/*
* Transmit timestamp input
*/
.s_axis_tx_ptp_ts_96(tx_ptp_ts_96),
.s_axis_tx_ptp_ts_valid(tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(tx_ptp_ts_ready),
/*
* Receive data input
*/
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
/*
* Receive timestamp input
*/
.s_axis_rx_ptp_ts_96(rx_ptp_ts_96),
.s_axis_rx_ptp_ts_valid(rx_ptp_ts_valid),
.s_axis_rx_ptp_ts_ready(rx_ptp_ts_ready),
/*
* PTP clock
@ -2084,6 +2152,91 @@ generate
.msi_irq(if_msi_irq[n*32 +: 32])
);
for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : mac
eth_mac_10g_fifo #(
.DATA_WIDTH(64),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FRAME_FIFO(1),
.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
.PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(0),
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(0),
.PTP_TAG_WIDTH(16)
)
eth_mac_inst (
.rx_clk(port_xgmii_rx_clk[n*PORTS_PER_IF+m]),
.rx_rst(port_xgmii_rx_rst[n*PORTS_PER_IF+m]),
.tx_clk(port_xgmii_tx_clk[n*PORTS_PER_IF+m]),
.tx_rst(port_xgmii_tx_rst[n*PORTS_PER_IF+m]),
.logic_clk(clk_250mhz),
.logic_rst(rst_250mhz),
.ptp_sample_clk(clk_250mhz),
.tx_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.tx_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.tx_axis_tvalid(tx_axis_tvalid[m +: 1]),
.tx_axis_tready(tx_axis_tready[m +: 1]),
.tx_axis_tlast(tx_axis_tlast[m +: 1]),
.tx_axis_tuser(tx_axis_tuser[m +: 1]),
.s_axis_tx_ptp_ts_tag(0),
.s_axis_tx_ptp_ts_valid(0),
.s_axis_tx_ptp_ts_ready(),
.m_axis_tx_ptp_ts_96(tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_tx_ptp_ts_tag(),
.m_axis_tx_ptp_ts_valid(tx_ptp_ts_valid[m +: 1]),
.m_axis_tx_ptp_ts_ready(tx_ptp_ts_ready[m +: 1]),
.rx_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.rx_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.rx_axis_tvalid(rx_axis_tvalid[m +: 1]),
.rx_axis_tready(rx_axis_tready[m +: 1]),
.rx_axis_tlast(rx_axis_tlast[m +: 1]),
.rx_axis_tuser(rx_axis_tuser[m +: 1]),
.m_axis_rx_ptp_ts_96(rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_rx_ptp_ts_valid(rx_ptp_ts_valid[m +: 1]),
.m_axis_rx_ptp_ts_ready(rx_ptp_ts_ready[m +: 1]),
.xgmii_rxd(port_xgmii_rxd[(n*PORTS_PER_IF+m)*64 +: 64]),
.xgmii_rxc(port_xgmii_rxc[(n*PORTS_PER_IF+m)*8 +: 8]),
.xgmii_txd(port_xgmii_txd[(n*PORTS_PER_IF+m)*64 +: 64]),
.xgmii_txc(port_xgmii_txc[(n*PORTS_PER_IF+m)*8 +: 8]),
.tx_error_underflow(),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ptp_ts_96(ptp_ts_96),
.ifg_delay(8'd12)
);
end
end
endgenerate

1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -59,7 +59,6 @@ srcs.append("../rtl/common/rx_checksum.v")
srcs.append("../rtl/common/tx_scheduler_tdma_rr.v")
srcs.append("../rtl/common/event_queue.v")
srcs.append("../rtl/common/event_mux.v")
srcs.append("../rtl/common/eth_interface.v")
srcs.append("../rtl/common/tdma_scheduler.v")
srcs.append("../rtl/common/tdma_ber.v")
srcs.append("../rtl/common/tdma_ber_ch.v")

2
fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -14,7 +14,6 @@ SYN_FILES += rtl/common/interface.v
SYN_FILES += rtl/common/port.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/eth_interface.v
SYN_FILES += rtl/common/event_queue.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/tx_scheduler_tdma_rr.v
@ -23,6 +22,7 @@ SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v

208
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -197,6 +197,10 @@ parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = 24;
// AXI stream interface parameters
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH;
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH;
// PCIe DMA parameters
parameter PCIE_DMA_LEN_WIDTH = 16;
parameter PCIE_DMA_TAG_WIDTH = 16;
@ -216,8 +220,9 @@ parameter BOARD_VER = {16'd0, 16'd1};
// Structural parameters
parameter IF_COUNT = 2;
parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 16;
@ -239,6 +244,25 @@ parameter RX_PKT_TABLE_SIZE = 8;
parameter TX_SCHEDULER = "TDMA_RR";
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
parameter LOGIC_PTP_PERIOD_NS = 6'h4;
parameter LOGIC_PTP_PERIOD_FNS = 16'h0000;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 1;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TS_FIFO_DEPTH = 32;
parameter RX_PTP_TS_FIFO_DEPTH = 32;
// Interface parameters (port)
parameter TX_CHECKSUM_ENABLE = 1;
parameter RX_CHECKSUM_ENABLE = 1;
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 16384;
parameter RX_FIFO_DEPTH = 16384;
// AXI lite connections
wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
wire [2:0] axil_pcie_awprot;
@ -1832,17 +1856,17 @@ always @(posedge clk_250mhz) begin
pps_led_reg <= pps_led_counter_reg > 0;
end
wire [IF_COUNT-1:0] if_xgmii_tx_clk = {sfp_2_tx_clk, sfp_1_tx_clk};
wire [IF_COUNT-1:0] if_xgmii_tx_rst = {sfp_2_tx_rst, sfp_1_tx_rst};
wire [IF_COUNT-1:0] if_xgmii_rx_clk = {sfp_2_rx_clk, sfp_1_rx_clk};
wire [IF_COUNT-1:0] if_xgmii_rx_rst = {sfp_2_rx_rst, sfp_1_rx_rst};
wire [IF_COUNT*64-1:0] if_xgmii_txd;
wire [IF_COUNT*8-1:0] if_xgmii_txc;
wire [IF_COUNT*64-1:0] if_xgmii_rxd = {sfp_2_rxd, sfp_1_rxd};
wire [IF_COUNT*8-1:0] if_xgmii_rxc = {sfp_2_rxc, sfp_1_rxc};
wire [PORT_COUNT-1:0] port_xgmii_tx_clk = {sfp_2_tx_clk, sfp_1_tx_clk};
wire [PORT_COUNT-1:0] port_xgmii_tx_rst = {sfp_2_tx_rst, sfp_1_tx_rst};
wire [PORT_COUNT-1:0] port_xgmii_rx_clk = {sfp_2_rx_clk, sfp_1_rx_clk};
wire [PORT_COUNT-1:0] port_xgmii_rx_rst = {sfp_2_rx_rst, sfp_1_rx_rst};
wire [PORT_COUNT*64-1:0] port_xgmii_txd;
wire [PORT_COUNT*8-1:0] port_xgmii_txc;
wire [PORT_COUNT*64-1:0] port_xgmii_rxd = {sfp_2_rxd, sfp_1_rxd};
wire [PORT_COUNT*8-1:0] port_xgmii_rxc = {sfp_2_rxc, sfp_1_rxc};
assign {sfp_2_txd, sfp_1_txd} = if_xgmii_txd;
assign {sfp_2_txc, sfp_1_txc} = if_xgmii_txc;
assign {sfp_2_txd, sfp_1_txd} = port_xgmii_txd;
assign {sfp_2_txc, sfp_1_txc} = port_xgmii_txc;
assign sfp_1_led = 2'b00;
assign sfp_2_led = 2'b00;
@ -1854,7 +1878,7 @@ wire [IF_COUNT*32-1:0] if_msi_irq;
assign msi_irq = if_msi_irq[31:0] | if_msi_irq[63:32];
generate
genvar n;
genvar m, n;
for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
@ -1863,9 +1887,31 @@ generate
wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int;
assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
wire [PORTS_PER_IF-1:0] tx_axis_tready;
wire [PORTS_PER_IF-1:0] tx_axis_tlast;
wire [PORTS_PER_IF-1:0] tx_axis_tuser;
wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PORTS_PER_IF-1:0] tx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] tx_ptp_ts_ready;
wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire [PORTS_PER_IF-1:0] rx_axis_tvalid;
wire [PORTS_PER_IF-1:0] rx_axis_tready;
wire [PORTS_PER_IF-1:0] rx_axis_tlast;
wire [PORTS_PER_IF-1:0] rx_axis_tuser;
wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
interface #
(
.PORTS(PORT_COUNT),
.PORTS(PORTS_PER_IF),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
@ -1888,7 +1934,10 @@ generate
.QUEUE_LOG_SIZE_WIDTH(4),
.RAM_ADDR_WIDTH(16),
.RAM_SIZE(2**15),
.PTP_TS_ENABLE(1),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
@ -1897,10 +1946,8 @@ generate
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(IF_AXI_ID_WIDTH),
.AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH),
.XGMII_DATA_WIDTH(64),
.XGMII_CTRL_WIDTH(8),
.TX_FIFO_DEPTH(16384),
.RX_FIFO_DEPTH(16384)
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
)
interface_inst (
.clk(clk_250mhz),
@ -2024,16 +2071,38 @@ generate
.s_axi_rready(axi_if_rready[n]),
/*
* XGMII interface
* Transmit data output
*/
.xgmii_rx_clk(if_xgmii_rx_clk[n]),
.xgmii_rx_rst(if_xgmii_rx_rst[n]),
.xgmii_tx_clk(if_xgmii_tx_clk[n]),
.xgmii_tx_rst(if_xgmii_tx_rst[n]),
.xgmii_rxd(if_xgmii_rxd[n*64 +: 64]),
.xgmii_rxc(if_xgmii_rxc[n*8 +: 8]),
.xgmii_txd(if_xgmii_txd[n*64 +: 64]),
.xgmii_txc(if_xgmii_txc[n*8 +: 8]),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
/*
* Transmit timestamp input
*/
.s_axis_tx_ptp_ts_96(tx_ptp_ts_96),
.s_axis_tx_ptp_ts_valid(tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(tx_ptp_ts_ready),
/*
* Receive data input
*/
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
/*
* Receive timestamp input
*/
.s_axis_rx_ptp_ts_96(rx_ptp_ts_96),
.s_axis_rx_ptp_ts_valid(rx_ptp_ts_valid),
.s_axis_rx_ptp_ts_ready(rx_ptp_ts_ready),
/*
* PTP clock
@ -2047,6 +2116,91 @@ generate
.msi_irq(if_msi_irq[n*32 +: 32])
);
for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : mac
eth_mac_10g_fifo #(
.DATA_WIDTH(64),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FRAME_FIFO(1),
.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
.PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(0),
.TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(0),
.PTP_TAG_WIDTH(16)
)
eth_mac_inst (
.rx_clk(port_xgmii_rx_clk[n*PORTS_PER_IF+m]),
.rx_rst(port_xgmii_rx_rst[n*PORTS_PER_IF+m]),
.tx_clk(port_xgmii_tx_clk[n*PORTS_PER_IF+m]),
.tx_rst(port_xgmii_tx_rst[n*PORTS_PER_IF+m]),
.logic_clk(clk_250mhz),
.logic_rst(rst_250mhz),
.ptp_sample_clk(clk_250mhz),
.tx_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.tx_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.tx_axis_tvalid(tx_axis_tvalid[m +: 1]),
.tx_axis_tready(tx_axis_tready[m +: 1]),
.tx_axis_tlast(tx_axis_tlast[m +: 1]),
.tx_axis_tuser(tx_axis_tuser[m +: 1]),
.s_axis_tx_ptp_ts_tag(0),
.s_axis_tx_ptp_ts_valid(0),
.s_axis_tx_ptp_ts_ready(),
.m_axis_tx_ptp_ts_96(tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_tx_ptp_ts_tag(),
.m_axis_tx_ptp_ts_valid(tx_ptp_ts_valid[m +: 1]),
.m_axis_tx_ptp_ts_ready(tx_ptp_ts_ready[m +: 1]),
.rx_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.rx_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.rx_axis_tvalid(rx_axis_tvalid[m +: 1]),
.rx_axis_tready(rx_axis_tready[m +: 1]),
.rx_axis_tlast(rx_axis_tlast[m +: 1]),
.rx_axis_tuser(rx_axis_tuser[m +: 1]),
.m_axis_rx_ptp_ts_96(rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.m_axis_rx_ptp_ts_valid(rx_ptp_ts_valid[m +: 1]),
.m_axis_rx_ptp_ts_ready(rx_ptp_ts_ready[m +: 1]),
.xgmii_rxd(port_xgmii_rxd[(n*PORTS_PER_IF+m)*64 +: 64]),
.xgmii_rxc(port_xgmii_rxc[(n*PORTS_PER_IF+m)*8 +: 8]),
.xgmii_txd(port_xgmii_txd[(n*PORTS_PER_IF+m)*64 +: 64]),
.xgmii_txc(port_xgmii_txc[(n*PORTS_PER_IF+m)*8 +: 8]),
.tx_error_underflow(),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ptp_ts_96(ptp_ts_96),
.ifg_delay(8'd12)
);
end
end
endgenerate

1
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -60,7 +60,6 @@ srcs.append("../rtl/common/tx_scheduler_tdma_rr.v")
srcs.append("../rtl/common/tdma_scheduler.v")
srcs.append("../rtl/common/event_queue.v")
srcs.append("../rtl/common/event_mux.v")
srcs.append("../rtl/common/eth_interface.v")
srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")