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More expressive flash format register

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-04-15 18:38:01 -07:00
parent 7be7b1cc9f
commit eb530475fb
25 changed files with 200 additions and 170 deletions
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27
docs/source/rb/flash_bpi.rst
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@ -4,7 +4,7 @@
BPI flash register block
========================
The BPI flash register block has a header with type 0x0000C121, version 0x00000100, and contains control registers for a BPI flash chip.
The BPI flash register block has a header with type 0x0000C121, version 0x00000200, and contains control registers for a BPI flash chip.
.. table::
@ -17,8 +17,8 @@ The BPI flash register block has a header with type 0x0000C121, version 0x000001
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------
RBB+0x0C Format AW DW config RO -
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x0C Format Format RO -
-------- ------------- ------------------------------ -------------
RBB+0x10 Address Address RW 0x00000000
-------- ------------- ------------------------------ -------------
RBB+0x14 Data Data RW 0x00000000
@ -30,27 +30,26 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
.. object:: Format
The format field contains information about the type and layout of the flash memory. AW and DW indicate the address and data interface widths in bits, and config indicates the layout of the flash.
The format field contains information about the type and layout of the flash memory. Bits 3:0 carry the number of segments. Bits 7:4 carry the index of the default segment that carries the main FPGA configuration. Bits 11:8 carry the index of the segment that contains a fallback FPGA configuration that is loaded if the configuration in the default segment fails to load. Bits 31:12 contain the size of the first segment in increments of 4096 bytes, for two-segment configurations with an uneven split. This field can be set to zero for an even split computed from the flash device size.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x0C AW DW config RO -
RBB+0x0C Format RO -
======== ====== ====== ====== ====== =============
.. table::
====== =======================
config Configuration
====== =======================
0x00 1 segment
0x01 1 segment
0x02 2 segments (even split)
0x04 4 segments (even split)
0x08 8 segments (even split)
====== =======================
====== ================================
bits Configuration
====== ================================
3:0 Segment count
7:4 Default segment
11:8 Fallback segment
31:12 First segment size
====== ================================
.. object:: Address

32
docs/source/rb/flash_spi.rst
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@ -4,7 +4,7 @@
SPI flash register block
========================
The SPI flash register block has a header with type 0x0000C120, version 0x00000100, and contains control registers for up to two SPI or QSPI flash chips.
The SPI flash register block has a header with type 0x0000C120, version 0x00000200, and contains control registers for up to two SPI or QSPI flash chips.
.. table::
@ -17,8 +17,8 @@ The SPI flash register block has a header with type 0x0000C120, version 0x000001
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------
RBB+0x0C Format AW DW config RO -
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x0C Format Format RO -
-------- ------------- ------------------------------ -------------
RBB+0x10 Control 0 CS/CLK OE D RW 0x00000000
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x14 Control 1 CS/CLK OE D RW 0x00000000
@ -28,39 +28,27 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
.. object:: Format
The format field contains information about the type and layout of the flash memory. AW and DW indicate the address and data interface widths in bits, and config indicates the layout of the flash.
The format field contains information about the type and layout of the flash memory. Bits 3:0 carry the number of segments. Bits 7:4 carry the index of the default segment that carries the main FPGA configuration. Bits 11:8 carry the index of the segment that contains a fallback FPGA configuration that is loaded if the configuration in the default segment fails to load. Bits 31:12 contain the size of the first segment in increments of 4096 bytes, for two-segment configurations with an uneven split. This field can be set to zero for an even split computed from the flash device size.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x0C AW DW config RO -
RBB+0x0C Format RO -
======== ====== ====== ====== ====== =============
.. table::
====== ================================
config Configuration
bits Configuration
====== ================================
0x00 1 segment
0x01 1 segment
0x02 2 segments (even split)
0x04 4 segments (even split)
0x08 8 segments (even split)
0x81 2 segments (split at 0x01002000)
3:0 Segment count
7:4 Default segment
11:8 Fallback segment
31:12 First segment size
====== ================================
.. table::
== ==========
DW Flash type
== ==========
1 SPI
4 QSPI
8 Dual QSPI
== ==========
.. object:: Control 0 and 1
The control 0 and 1 fields each control one SPI/QSPI flash interface. The second interface is only used in dual QSPI mode.

4
docs/source/rb/index.rst
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@ -79,8 +79,8 @@ The NIC register space is constructed from a linked list of register blocks. Ea
0x0000C081 0x00000100 :ref:`rb_phc_perout`
0x0000C100 0x00000100 :ref:`rb_gpio`
0x0000C110 0x00000100 :ref:`rb_i2c`
0x0000C120 0x00000100 :ref:`rb_flash_spi`
0x0000C121 0x00000100 :ref:`rb_flash_bpi`
0x0000C120 0x00000200 :ref:`rb_flash_spi`
0x0000C121 0x00000200 :ref:`rb_flash_bpi`
0x0000C140 0x00000100 :ref:`rb_bmc_alveo`
0x0000C141 0x00000100 :ref:`rb_bmc_gecko`
0x0000C150 0x00000100 :ref:`rb_drp`

10
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
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@ -593,14 +593,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h38: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h50; // SPI flash ctrl: Next header
RBB+8'h3C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[23:16] <= 8; // data width (dual QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h40: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -687,14 +687,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h38: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_0_BASE; // SPI flash ctrl: Next header
RBB+8'h3C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[23:16] <= 8; // data width (dual QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h40: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -606,14 +606,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 8'h81; // configuration (Alveo)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default)
end
RBB+8'h30: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
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@ -700,14 +700,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 8'h81; // configuration (Alveo)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default)
end
RBB+8'h30: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -606,14 +606,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 8'h81; // configuration (Alveo)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default)
end
RBB+8'h30: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -700,14 +700,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 8'h81; // configuration (Alveo)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default)
end
RBB+8'h30: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -507,14 +507,14 @@ always @(posedge clk_250mhz) begin
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// QSPI flash
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // SPI flash ctrl: Next header
RBB+8'h0C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 8'h81; // configuration (Alveo)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default)
end
RBB+8'h10: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -601,14 +601,14 @@ always @(posedge clk_250mhz) begin
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// QSPI flash
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // SPI flash ctrl: Next header
RBB+8'h0C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 8'h81; // configuration (Alveo)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default)
end
RBB+8'h10: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -486,14 +486,14 @@ always @(posedge clk_250mhz) begin
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// QSPI flash
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // SPI flash ctrl: Next header
RBB+8'h0C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 8'h81; // configuration (Alveo)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default)
end
RBB+8'h10: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -547,14 +547,14 @@ always @(posedge clk_250mhz) begin
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// QSPI flash
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // SPI flash ctrl: Next header
RBB+8'h0C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 8'h81; // configuration (Alveo)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default)
end
RBB+8'h10: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
View File

@ -715,14 +715,14 @@ always @(posedge clk_250mhz) begin
end
// BPI flash
RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C121; // SPI flash ctrl: Type
RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // SPI flash ctrl: Next header
RBB+8'h4C: begin
// BPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 1; // type (BPI)
ctrl_reg_rd_data_reg[15:8] <= 4; // configuration (four segments)
ctrl_reg_rd_data_reg[23:16] <= 16; // data width
ctrl_reg_rd_data_reg[31:24] <= 26; // address width
ctrl_reg_rd_data_reg[3:0] <= 4; // configuration (four segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h50: ctrl_reg_rd_data_reg <= flash_addr_reg; // BPI flash ctrl: address
RBB+8'h54: ctrl_reg_rd_data_reg <= flash_dq_i; // BPI flash ctrl: data

10
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -591,14 +591,14 @@ always @(posedge clk_250mhz) begin
end
// BPI flash
RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C121; // SPI flash ctrl: Type
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h38: ctrl_reg_rd_data_reg <= RB_DRP_SFP_BASE; // SPI flash ctrl: Next header
RBB+8'h3C: begin
// BPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 1; // type (BPI)
ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[23:16] <= 16; // data width
ctrl_reg_rd_data_reg[31:24] <= 24; // address width
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h40: begin
// BPI flash ctrl: address

10
fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
View File

@ -620,14 +620,14 @@ always @(posedge clk_250mhz) begin
end
// BPI flash
RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C121; // SPI flash ctrl: Type
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h38: ctrl_reg_rd_data_reg <= RB_DRP_SFP_BASE; // SPI flash ctrl: Next header
RBB+8'h3C: begin
// BPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 1; // type (BPI)
ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[23:16] <= 16; // data width
ctrl_reg_rd_data_reg[31:24] <= 24; // address width
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h40: begin
// BPI flash ctrl: address

10
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -578,14 +578,14 @@ always @(posedge clk_250mhz) begin
end
// BPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C121; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_BASE; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// BPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 1; // type (BPI)
ctrl_reg_rd_data_reg[15:8] <= 4; // configuration (four segments)
ctrl_reg_rd_data_reg[23:16] <= 16; // data width
ctrl_reg_rd_data_reg[31:24] <= 26; // address width
ctrl_reg_rd_data_reg[3:0] <= 4; // configuration (four segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h30: begin
// BPI flash ctrl: address

10
fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
View File

@ -569,14 +569,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= 0; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[23:16] <= 8; // data width (dual QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h30: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
View File

@ -663,14 +663,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP1_BASE; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[23:16] <= 8; // data width (dual QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h30: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
View File

@ -539,14 +539,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= 0; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h30: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
View File

@ -633,14 +633,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // SPI flash ctrl: Next header
RBB+8'h2C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split)
end
RBB+8'h30: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
View File

@ -594,14 +594,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h38: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h50; // SPI flash ctrl: Next header
RBB+8'h3C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 1; // configuration (one segment)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 1; // configuration (one segment)
ctrl_reg_rd_data_reg[7:4] <= 0; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment (none)
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (N/A)
end
RBB+8'h40: begin
// SPI flash ctrl: control 0

10
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -688,14 +688,14 @@ always @(posedge clk_250mhz) begin
end
// QSPI flash
RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // SPI flash ctrl: Version
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h38: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h50; // SPI flash ctrl: Next header
RBB+8'h3C: begin
// SPI flash ctrl: format
ctrl_reg_rd_data_reg[7:0] <= 0; // type (SPI)
ctrl_reg_rd_data_reg[15:8] <= 1; // configuration (one segment)
ctrl_reg_rd_data_reg[23:16] <= 4; // data width (QSPI)
ctrl_reg_rd_data_reg[31:24] <= 0; // address width (N/A for SPI)
ctrl_reg_rd_data_reg[3:0] <= 1; // configuration (one segment)
ctrl_reg_rd_data_reg[7:4] <= 0; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment (none)
ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (N/A)
end
RBB+8'h40: begin
// SPI flash ctrl: control 0

4
modules/mqnic/mqnic_hw.h
View File

@ -107,13 +107,13 @@
#define MQNIC_REG_GPIO_I2C_SDA_OUT 0x00000200
#define MQNIC_RB_SPI_FLASH_TYPE 0x0000C120
#define MQNIC_RB_SPI_FLASH_VER 0x00000100
#define MQNIC_RB_SPI_FLASH_VER 0x00000200
#define MQNIC_RB_SPI_FLASH_REG_FORMAT 0x0C
#define MQNIC_RB_SPI_FLASH_REG_CTRL_0 0x10
#define MQNIC_RB_SPI_FLASH_REG_CTRL_1 0x14
#define MQNIC_RB_BPI_FLASH_TYPE 0x0000C121
#define MQNIC_RB_BPI_FLASH_VER 0x00000100
#define MQNIC_RB_BPI_FLASH_VER 0x00000200
#define MQNIC_RB_BPI_FLASH_REG_FORMAT 0x0C
#define MQNIC_RB_BPI_FLASH_REG_ADDR 0x10
#define MQNIC_RB_BPI_FLASH_REG_DATA 0x14

103
utils/mqnic-fw.c
View File

@ -123,7 +123,7 @@ static void usage(char *name)
fprintf(stderr,
"usage: %s [options]\n"
" -d name device to open (/dev/mqnic0)\n"
" -s slot slot to program (default 1)\n"
" -s slot slot to program\n"
" -r file read flash to file\n"
" -w file write and verify flash from file\n"
" -e erase flash\n"
@ -659,6 +659,9 @@ int main(int argc, char *argv[])
uint8_t flash_configuration = 0;
uint8_t flash_data_width = 0;
uint8_t flash_default_segment = 0;
uint8_t flash_fallback_segment = 0;
uint32_t flash_segment0_length = 0;
printf("FPGA ID: 0x%08x\n", dev->fpga_id);
printf("FPGA part: %s\n", fpga_part);
@ -691,7 +694,7 @@ int main(int argc, char *argv[])
size_t segment_size = 0;
size_t segment_offset = 0;
if ((flash_rb = find_reg_block(dev->rb_list, MQNIC_RB_SPI_FLASH_TYPE, MQNIC_RB_SPI_FLASH_VER, 0)))
if ((flash_rb = find_reg_block(dev->rb_list, MQNIC_RB_SPI_FLASH_TYPE, 0, 0)))
{
uint32_t reg_val;
@ -701,7 +704,31 @@ int main(int argc, char *argv[])
printf("Flash type: SPI\n");
printf("Flash format: 0x%08x\n", flash_format);
flash_configuration = flash_format >> 8;
switch (flash_rb->version) {
case 0x00000100:
flash_configuration = (flash_format >> 8) & 0xff;
flash_default_segment = (flash_configuration > 1 ? 1 : 0);
flash_fallback_segment = 0;
flash_segment0_length = 0;
if (flash_configuration == 0x81)
{
// Alveo boards
flash_configuration = 2;
flash_segment0_length = 0x01002000;
}
break;
case MQNIC_RB_SPI_FLASH_VER:
flash_configuration = flash_format & 0xf;
flash_default_segment = (flash_format >> 4) & 0xf;
flash_fallback_segment = (flash_format >> 8) & 0xf;
flash_segment0_length = flash_format & 0xfffff000;
break;
default:
fprintf(stderr, "Unknown SPI flash block version\n");
ret = -1;
goto skip_flash;
}
// determine data width
flash_data_width = 0;
@ -757,7 +784,7 @@ int main(int argc, char *argv[])
flash_size = pri_flash->size;
}
}
else if ((flash_rb = find_reg_block(dev->rb_list, MQNIC_RB_BPI_FLASH_TYPE, MQNIC_RB_BPI_FLASH_VER, 0)))
else if ((flash_rb = find_reg_block(dev->rb_list, MQNIC_RB_BPI_FLASH_TYPE, 0, 0)))
{
uint32_t reg_val;
@ -767,7 +794,24 @@ int main(int argc, char *argv[])
printf("Flash type: BPI\n");
printf("Flash format: 0x%08x\n", flash_format);
flash_configuration = flash_format >> 8;
switch (flash_rb->version) {
case 0x00000100:
flash_configuration = (flash_format >> 8) & 0xff;
flash_default_segment = (flash_configuration > 1 ? 1 : 0);
flash_fallback_segment = 0;
flash_segment0_length = 0;
break;
case MQNIC_RB_BPI_FLASH_VER:
flash_configuration = flash_format & 0xf;
flash_default_segment = (flash_format >> 4) & 0xf;
flash_fallback_segment = (flash_format >> 8) & 0xf;
flash_segment0_length = flash_format & 0xfffff000;
break;
default:
fprintf(stderr, "Unknown BPI flash block version\n");
ret = -1;
goto skip_flash;
}
// determine data width
mqnic_reg_write32(flash_rb->regs, MQNIC_RB_BPI_FLASH_REG_DATA, 0xffffffff);
@ -820,11 +864,22 @@ int main(int argc, char *argv[])
flash_segment_length[0] = flash_size;
break;
case 2:
if (flash_segment0_length == 0)
{
flash_segment0_length = flash_size >> 1;
}
else if (flash_size < flash_segment0_length)
{
fprintf(stderr, "Invalid flash configuration\n");
ret = -1;
goto skip_flash;
}
flash_segment_count = 2;
flash_segment_start[0] = 0;
flash_segment_length[0] = flash_size >> 1;
flash_segment_length[0] = flash_segment0_length;
flash_segment_start[1] = flash_segment_start[0]+flash_segment_length[0];
flash_segment_length[1] = flash_size >> 1;
flash_segment_length[1] = flash_size-flash_segment_start[1];
break;
case 4:
flash_segment_count = 4;
@ -846,21 +901,6 @@ int main(int argc, char *argv[])
flash_segment_length[k] = flash_size >> 3;
}
break;
case 0x81:
// Alveo boards
if (flash_size < 0x01002000)
{
fprintf(stderr, "Invalid flash size\n");
ret = -1;
goto skip_flash;
}
flash_segment_count = 2;
flash_segment_start[0] = 0;
flash_segment_length[0] = 0x01002000;
flash_segment_start[1] = flash_segment_start[0]+flash_segment_length[0];
flash_segment_length[1] = flash_size - flash_segment_start[1];
break;
default:
fprintf(stderr, "Unknown flash configuration (0x%02x)\n", flash_configuration);
ret = -1;
@ -872,16 +912,19 @@ int main(int argc, char *argv[])
printf("Flash segment %d: start 0x%08lx length 0x%08lx\n", k, flash_segment_start[k], flash_segment_length[k]);
}
printf("Default segment: %d\n", flash_default_segment);
if (flash_fallback_segment == flash_default_segment || flash_fallback_segment >= flash_segment_count)
{
printf("Fallback segment: none\n");
}
else
{
printf("Fallback segment: %d\n", flash_fallback_segment);
}
if (slot < 0)
{
if (flash_segment_count > 1)
{
slot = 1;
}
else
{
slot = 0;
}
slot = flash_default_segment;
}
if ((action_read || action_write) && (slot < 0 || slot >= flash_segment_count))