diff --git a/fpga/common/rtl/eth_interface.v b/fpga/common/rtl/eth_interface.v index b7d32f727..0bc2425ed 100644 --- a/fpga/common/rtl/eth_interface.v +++ b/fpga/common/rtl/eth_interface.v @@ -54,11 +54,11 @@ module eth_interface # parameter ENABLE_PADDING = 1, parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_ADDR_WIDTH = 12-$clog2(AXI_STRB_WIDTH), + parameter TX_FIFO_DEPTH = 4096, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO, parameter TX_DROP_WHEN_FULL = 0, - parameter RX_FIFO_ADDR_WIDTH = 12-$clog2(AXI_STRB_WIDTH), + parameter RX_FIFO_DEPTH = 4096, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO, parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO, @@ -362,7 +362,7 @@ wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag; wire tx_axis_ptp_ts_valid; axis_async_fifo #( - .ADDR_WIDTH(6), + .DEPTH(64), .DATA_WIDTH(PTP_TAG_WIDTH+PTP_TS_WIDTH), .KEEP_ENABLE(0), .LAST_ENABLE(0), @@ -409,7 +409,7 @@ wire [PTP_TS_WIDTH-1:0] rx_axis_ptp_ts_96; wire rx_axis_ptp_ts_valid; axis_fifo #( - .ADDR_WIDTH(6), + .DEPTH(64), .DATA_WIDTH(PTP_TS_WIDTH), .KEEP_ENABLE(0), .LAST_ENABLE(0), @@ -606,7 +606,7 @@ tx_adapter ( ); axis_async_fifo #( - .ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), + .DEPTH(TX_FIFO_DEPTH), .DATA_WIDTH(AXI_DATA_WIDTH), .KEEP_ENABLE(1), .KEEP_WIDTH(AXI_STRB_WIDTH), @@ -689,7 +689,7 @@ rx_adapter ( ); axis_async_fifo #( - .ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), + .DEPTH(RX_FIFO_DEPTH), .DATA_WIDTH(AXI_DATA_WIDTH), .KEEP_ENABLE(1), .KEEP_WIDTH(AXI_STRB_WIDTH), diff --git a/fpga/common/rtl/interface.v b/fpga/common/rtl/interface.v index a046d8468..38f1b3f62 100644 --- a/fpga/common/rtl/interface.v +++ b/fpga/common/rtl/interface.v @@ -80,8 +80,8 @@ module interface # parameter AXI_BASE_ADDR = 0, parameter XGMII_DATA_WIDTH = 64, parameter XGMII_CTRL_WIDTH = (XGMII_DATA_WIDTH/8), - parameter TX_FIFO_ADDR_WIDTH = 12-$clog2(AXI_STRB_WIDTH), - parameter RX_FIFO_ADDR_WIDTH = 12-$clog2(AXI_STRB_WIDTH) + parameter TX_FIFO_DEPTH = 4096, + parameter RX_FIFO_DEPTH = 4096 ) ( input wire clk, @@ -1740,7 +1740,7 @@ event_mux_inst ( ); axis_fifo #( - .ADDR_WIDTH(4), + .DEPTH(16), .DATA_WIDTH(EVENT_SOURCE_WIDTH+EVENT_TYPE_WIDTH+EVENT_QUEUE_INDEX_WIDTH), .KEEP_ENABLE(0), .LAST_ENABLE(0), @@ -1780,7 +1780,7 @@ tx_event_fifo ( ); axis_fifo #( - .ADDR_WIDTH(4), + .DEPTH(16), .DATA_WIDTH(EVENT_SOURCE_WIDTH+EVENT_TYPE_WIDTH+EVENT_QUEUE_INDEX_WIDTH), .KEEP_ENABLE(0), .LAST_ENABLE(0), @@ -2319,8 +2319,8 @@ generate .AXI_BASE_ADDR(23'h000000), .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH) + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH) ) port_inst ( .clk(clk), diff --git a/fpga/common/rtl/port.v b/fpga/common/rtl/port.v index 9f4549a5c..e8ee97f1d 100644 --- a/fpga/common/rtl/port.v +++ b/fpga/common/rtl/port.v @@ -70,8 +70,8 @@ module port # parameter AXI_BASE_ADDR = 0, parameter XGMII_DATA_WIDTH = 64, parameter XGMII_CTRL_WIDTH = (XGMII_DATA_WIDTH/8), - parameter TX_FIFO_ADDR_WIDTH = 12-$clog2(AXI_STRB_WIDTH), - parameter RX_FIFO_ADDR_WIDTH = 12-$clog2(AXI_STRB_WIDTH) + parameter TX_FIFO_DEPTH = 4096, + parameter RX_FIFO_DEPTH = 4096 ) ( input wire clk, @@ -1015,7 +1015,7 @@ tx_engine_inst ( ); axis_fifo #( - .ADDR_WIDTH(4), + .DEPTH(16), .DATA_WIDTH(16), .KEEP_ENABLE(0), .LAST_ENABLE(0), @@ -1272,8 +1272,8 @@ eth_interface #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .LOGIC_PTP_PERIOD_NS(4'h4), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile index 209d300d3..8b577d963 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile @@ -59,6 +59,7 @@ SYN_FILES += lib/axi/rtl/arbiter.v SYN_FILES += lib/axi/rtl/priority_encoder.v SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index fb225a04c..e6cc4dd9a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -1936,8 +1936,8 @@ generate .AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH), .XGMII_DATA_WIDTH(64), .XGMII_CTRL_WIDTH(8), - .TX_FIFO_ADDR_WIDTH(15-$clog2(AXI_STRB_WIDTH)), - .RX_FIFO_ADDR_WIDTH(15-$clog2(AXI_STRB_WIDTH)) + .TX_FIFO_DEPTH(32768), + .RX_FIFO_DEPTH(32768) ) interface_inst ( .clk(clk_250mhz), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index 9771cfb49..9d8a096be 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -91,6 +91,7 @@ srcs.append("../lib/axi/rtl/priority_encoder.v") srcs.append("../lib/axis/rtl/axis_adapter.v") srcs.append("../lib/axis/rtl/axis_arb_mux.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("../lib/axis/rtl/axis_fifo.v") srcs.append("../lib/axis/rtl/axis_register.v") srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v") diff --git a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile index d38c16039..494938edd 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile +++ b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile @@ -57,6 +57,7 @@ SYN_FILES += lib/axi/rtl/arbiter.v SYN_FILES += lib/axi/rtl/priority_encoder.v SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v index 6645ebfed..7cfeb40f6 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -1899,8 +1899,8 @@ generate .AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH), .XGMII_DATA_WIDTH(64), .XGMII_CTRL_WIDTH(8), - .TX_FIFO_ADDR_WIDTH(14-$clog2(AXI_STRB_WIDTH)), - .RX_FIFO_ADDR_WIDTH(14-$clog2(AXI_STRB_WIDTH)) + .TX_FIFO_DEPTH(16384), + .RX_FIFO_DEPTH(16384) ) interface_inst ( .clk(clk_250mhz), diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py index c654d5ce8..4a07502f6 100755 --- a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -89,6 +89,7 @@ srcs.append("../lib/axi/rtl/priority_encoder.v") srcs.append("../lib/axis/rtl/axis_adapter.v") srcs.append("../lib/axis/rtl/axis_arb_mux.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("../lib/axis/rtl/axis_fifo.v") srcs.append("../lib/axis/rtl/axis_register.v") srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v") diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile index 82b793822..557a4e317 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile @@ -59,6 +59,7 @@ SYN_FILES += lib/axi/rtl/arbiter.v SYN_FILES += lib/axi/rtl/priority_encoder.v SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index c3750b7e6..5bb99236d 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -1936,8 +1936,8 @@ generate .AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH), .XGMII_DATA_WIDTH(64), .XGMII_CTRL_WIDTH(8), - .TX_FIFO_ADDR_WIDTH(15-$clog2(AXI_STRB_WIDTH)), - .RX_FIFO_ADDR_WIDTH(15-$clog2(AXI_STRB_WIDTH)) + .TX_FIFO_DEPTH(32768), + .RX_FIFO_DEPTH(32768) ) interface_inst ( .clk(clk_250mhz), diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index b0eb1bb34..56a670d25 100755 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -91,6 +91,7 @@ srcs.append("../lib/axi/rtl/priority_encoder.v") srcs.append("../lib/axis/rtl/axis_adapter.v") srcs.append("../lib/axis/rtl/axis_arb_mux.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("../lib/axis/rtl/axis_fifo.v") srcs.append("../lib/axis/rtl/axis_register.v") srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v") diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile b/fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile index d982b2cf4..97f625d64 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile @@ -57,6 +57,7 @@ SYN_FILES += lib/axi/rtl/arbiter.v SYN_FILES += lib/axi/rtl/priority_encoder.v SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v index 60e8c4e84..b6b4dc908 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -1899,8 +1899,8 @@ generate .AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH), .XGMII_DATA_WIDTH(64), .XGMII_CTRL_WIDTH(8), - .TX_FIFO_ADDR_WIDTH(14-$clog2(AXI_STRB_WIDTH)), - .RX_FIFO_ADDR_WIDTH(14-$clog2(AXI_STRB_WIDTH)) + .TX_FIFO_DEPTH(16384), + .RX_FIFO_DEPTH(16384) ) interface_inst ( .clk(clk_250mhz), diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py index 2cf8f1d77..7632eeec5 100755 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -89,6 +89,7 @@ srcs.append("../lib/axi/rtl/priority_encoder.v") srcs.append("../lib/axis/rtl/axis_adapter.v") srcs.append("../lib/axis/rtl/axis_arb_mux.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("../lib/axis/rtl/axis_fifo.v") srcs.append("../lib/axis/rtl/axis_register.v") srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")