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https://github.com/corundum/corundum.git
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Update AXI simulation model
This commit is contained in:
Alex Forencich
parent
281e1a2156
commit
ebae4e436d
292
tb/axi.py
292
tb/axi.py
@ -73,6 +73,15 @@ AWCACHE_WRITE_BACK_READ_ALLOC = 0b0111
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AWCACHE_WRITE_BACK_WRITE_ALLOC = 0b1111
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AWCACHE_WRITE_BACK_READ_AND_WRIE_ALLOC = 0b1111
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PROT_PRIVILEGED = 0b001
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PROT_NONSECURE = 0b010
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PROT_INSTRUCTION = 0b100
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RESP_OKAY = 0b00
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RESP_EXOKAY = 0b01
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RESP_SLVERR = 0b10
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RESP_DECERR = 0b11
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class AXIMaster(object):
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def __init__(self):
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self.write_command_queue = []
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@ -101,19 +110,21 @@ class AXIMaster(object):
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self.int_read_addr_sync = Signal(False)
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self.int_read_resp_command_queue = []
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self.int_read_resp_command_sync = Signal(False)
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self.int_read_resp_queue = []
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self.int_read_resp_queue_list = {}
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self.int_read_resp_sync = Signal(False)
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self.in_flight_operations = 0
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self.max_burst_len = 256
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self.has_logic = False
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self.clk = None
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def init_read(self, address, length, burst=0b01, size=None, lock=0b0, cache=0b0000, prot=0b010, qos=0b0000, region=0b0000, user=None):
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def init_read(self, address, length, burst=0b01, size=None, lock=0b0, cache=0b0011, prot=0b010, qos=0b0000, region=0b0000, user=None):
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self.read_command_queue.append((address, length, burst, size, lock, cache, prot, qos, region, user))
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self.read_command_sync.next = not self.read_command_sync
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def init_write(self, address, data, burst=0b01, size=None, lock=0b0, cache=0b0000, prot=0b010, qos=0b0000, region=0b0000, user=None):
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def init_write(self, address, data, burst=0b01, size=None, lock=0b0, cache=0b0011, prot=0b010, qos=0b0000, region=0b0000, user=None):
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self.write_command_queue.append((address, data, burst, size, lock, cache, prot, qos, region, user))
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self.write_command_sync.next = not self.write_command_sync
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@ -179,6 +190,12 @@ class AXIMaster(object):
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m_axi_ruser=None,
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m_axi_rvalid=Signal(bool(False)),
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m_axi_rready=Signal(bool(False)),
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pause=False,
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awpause=False,
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wpause=False,
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bpause=False,
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arpause=False,
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rpause=False,
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name=None
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):
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@ -186,26 +203,25 @@ class AXIMaster(object):
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raise Exception("Logic already instantiated!")
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if m_axi_wdata is not None:
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assert m_axi_awid is not None
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assert m_axi_bid is not None
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assert len(m_axi_awid) == len(m_axi_bid)
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if m_axi_awid is not None:
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assert m_axi_bid is not None
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assert len(m_axi_awid) == len(m_axi_bid)
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assert m_axi_awaddr is not None
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assert len(m_axi_wdata) % 8 == 0
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assert len(m_axi_wdata) / 8 == len(m_axi_wstrb)
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w = len(m_axi_wdata)
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if m_axi_rdata is not None:
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assert m_axi_arid is not None
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assert m_axi_rid is not None
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assert len(m_axi_arid) == len(m_axi_rid)
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if m_axi_arid is not None:
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assert m_axi_rid is not None
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assert len(m_axi_arid) == len(m_axi_rid)
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assert m_axi_araddr is not None
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assert len(m_axi_rdata) % 8 == 0
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w = len(m_axi_rdata)
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if m_axi_wdata is not None:
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assert len(m_axi_wdata) == len(m_axi_rdata)
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assert len(m_axi_awid) == len(m_axi_arid)
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assert len(m_axi_awaddr) == len(m_axi_araddr)
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assert len(m_axi_wdata) == len(m_axi_rdata)
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bw = int(w/8)
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@ -214,12 +230,28 @@ class AXIMaster(object):
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self.has_logic = True
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self.clk = clk
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m_axi_bvalid_int = Signal(bool(False))
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m_axi_bready_int = Signal(bool(False))
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m_axi_rvalid_int = Signal(bool(False))
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m_axi_rready_int = Signal(bool(False))
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@always_comb
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def pause_logic():
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m_axi_bvalid_int.next = m_axi_bvalid and not (pause or bpause)
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m_axi_bready.next = m_axi_bready_int and not (pause or bpause)
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m_axi_rvalid_int.next = m_axi_rvalid and not (pause or rpause)
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m_axi_rready.next = m_axi_rready_int and not (pause or rpause)
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@instance
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def write_logic():
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while True:
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if not self.write_command_queue:
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yield self.write_command_sync
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if m_axi_awaddr is None:
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print("Error: attempted write on read-only interface")
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raise StopSimulation
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addr, data, burst, size, lock, cache, prot, qos, region, user = self.write_command_queue.pop(0)
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self.in_flight_operations += 1
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@ -269,12 +301,17 @@ class AXIMaster(object):
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if n >= burst_length:
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transfer_count += 1
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n = 0
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burst_length = min(cycles-k, 256) # max len
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burst_length = min(burst_length, 0x1000-(cur_addr&0xfff)) # 4k align
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burst_length = min(cycles-k, min(max(self.max_burst_len, 1), 256)) # max len
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burst_length = int((min(burst_length*num_bytes, 0x1000-(cur_addr&0xfff))+num_bytes-1)/num_bytes) # 4k align
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awid = self.cur_write_id
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self.cur_write_id = (self.cur_write_id + 1) % 2**len(m_axi_awid)
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if m_axi_awid is not None:
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self.cur_write_id = (self.cur_write_id + 1) % 2**len(m_axi_awid)
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else:
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self.cur_write_id = 0
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self.int_write_addr_queue.append((cur_addr, awid, burst_length-1, size, burst, lock, cache, prot, qos, region, user))
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self.int_write_addr_sync.next = not self.int_write_addr_sync
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if name is not None:
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print("[%s] Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d" % (name, awid, cur_addr, burst_length-1, size))
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n += 1
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self.int_write_data_queue.append((val, strb, n >= burst_length))
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self.int_write_data_sync.next = not self.int_write_data_sync
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@ -299,7 +336,7 @@ class AXIMaster(object):
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while not self.int_write_resp_queue:
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yield clk.posedge
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cycle_resp = self.int_write_resp_queue.pop(0)
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cycle_id, cycle_resp, cycle_user = self.int_write_resp_queue.pop(0)
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if cycle_resp != 0:
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resp = cycle_resp
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@ -315,7 +352,8 @@ class AXIMaster(object):
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yield clk.posedge
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addr, awid, length, size, burst, lock, cache, prot, qos, region, user = self.int_write_addr_queue.pop(0)
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m_axi_awaddr.next = addr
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if m_axi_awaddr is not None:
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m_axi_awaddr.next = addr
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m_axi_awid.next = awid
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m_axi_awlen.next = length
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m_axi_awsize.next = size
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@ -327,11 +365,12 @@ class AXIMaster(object):
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m_axi_awregion.next = region
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if m_axi_awuser is not None:
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m_axi_awuser.next = user
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m_axi_awvalid.next = True
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m_axi_awvalid.next = not (pause or awpause)
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yield clk.posedge
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while m_axi_awvalid and not m_axi_awready:
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while not m_axi_awvalid or not m_axi_awready:
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m_axi_awvalid.next = m_axi_awvalid or not (pause or awpause)
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yield clk.posedge
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m_axi_awvalid.next = False
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@ -343,11 +382,12 @@ class AXIMaster(object):
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yield clk.posedge
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m_axi_wdata.next, m_axi_wstrb.next, m_axi_wlast.next = self.int_write_data_queue.pop(0)
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m_axi_wvalid.next = True
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m_axi_wvalid.next = not (pause or wpause)
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yield clk.posedge
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while m_axi_wvalid and not m_axi_wready:
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while not m_axi_wvalid or not m_axi_wready:
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m_axi_wvalid.next = m_axi_wvalid or not (pause or wpause)
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yield clk.posedge
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m_axi_wvalid.next = False
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@ -355,12 +395,21 @@ class AXIMaster(object):
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@instance
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def write_resp_interface_logic():
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while True:
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m_axi_bready.next = True
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m_axi_bready_int.next = True
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yield clk.posedge
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if m_axi_bready & m_axi_bvalid:
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self.int_write_resp_queue.append(int(m_axi_bresp))
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if m_axi_bready and m_axi_bvalid_int:
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if m_axi_bid is not None:
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bid = int(m_axi_bid)
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else:
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bid = 0
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bresp = int(m_axi_bresp)
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if m_axi_buser is not None:
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buser = int(m_axi_buser)
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else:
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buser = 0
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self.int_write_resp_queue.append((bid, bresp, buser))
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self.int_write_resp_sync.next = not self.int_write_resp_sync
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@instance
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@ -369,6 +418,10 @@ class AXIMaster(object):
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if not self.read_command_queue:
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yield self.read_command_sync
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if m_axi_araddr is None:
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print("Error: attempted read on write-only interface")
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raise StopSimulation
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addr, length, burst, size, lock, cache, prot, qos, region, user = self.read_command_queue.pop(0)
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self.in_flight_operations += 1
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@ -385,7 +438,9 @@ class AXIMaster(object):
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cycles = int((length + num_bytes-1 + (addr % num_bytes)) / num_bytes)
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self.int_read_resp_command_queue.append((addr, length, size, cycles, prot))
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burst_list = []
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self.int_read_resp_command_queue.append((addr, length, size, cycles, prot, burst_list))
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self.int_read_resp_command_sync.next = not self.int_read_resp_command_sync
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cur_addr = aligned_addr
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@ -398,22 +453,30 @@ class AXIMaster(object):
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n += 1
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if n >= burst_length:
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n = 0
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burst_length = min(cycles-k, 256) # max len
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burst_length = min(burst_length, 0x1000-((aligned_addr+k*num_bytes)&0xfff))# 4k align
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burst_length = min(cycles-k, min(max(self.max_burst_len, 1), 256)) # max len
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burst_length = int((min(burst_length*num_bytes, 0x1000-(cur_addr&0xfff))+num_bytes-1)/num_bytes) # 4k align
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arid = self.cur_read_id
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self.cur_read_id = (self.cur_read_id + 1) % 2**len(m_axi_arid)
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if m_axi_arid is not None:
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self.cur_read_id = (self.cur_read_id + 1) % 2**len(m_axi_arid)
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else:
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self.cur_read_id = 0
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burst_list.append((arid, burst_length))
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self.int_read_addr_queue.append((cur_addr, arid, burst_length-1, size, burst, lock, cache, prot, qos, region, user))
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self.int_read_addr_sync.next = not self.int_read_addr_sync
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if name is not None:
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print("[%s] Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d" % (name, arid, cur_addr, burst_length-1, size))
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cur_addr += num_bytes
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burst_list.append(None)
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@instance
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def read_resp_logic():
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while True:
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if not self.int_read_resp_command_queue:
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yield self.int_read_resp_command_sync
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addr, length, size, cycles, prot = self.int_read_resp_command_queue.pop(0)
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addr, length, size, cycles, prot, burst_list = self.int_read_resp_command_queue.pop(0)
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num_bytes = 2**size
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assert 0 <= size <= int(math.log(bw, 2))
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@ -429,29 +492,46 @@ class AXIMaster(object):
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resp = 0
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for k in range(cycles):
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if not self.int_read_resp_queue:
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yield self.int_read_resp_sync
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first = True
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cycle_data, cycle_resp, cycle_last = self.int_read_resp_queue.pop(0)
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while True:
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while not burst_list:
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yield clk.posedge
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if cycle_resp != 0:
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resp = cycle_resp
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cur_burst = burst_list.pop(0)
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start = cycle_offset
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stop = cycle_offset+num_bytes
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if cur_burst is None:
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break
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if k == 0:
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start = start_offset
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if k == cycles-1:
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stop = end_offset
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rid = cur_burst[0]
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burst_length = cur_burst[1]
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assert cycle_last == (k == cycles - 1)
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for k in range(burst_length):
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self.int_read_resp_queue_list.setdefault(rid, [])
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while not self.int_read_resp_queue_list[rid]:
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yield self.int_read_resp_sync
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for j in range(start, stop):
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data += bytearray([(cycle_data >> j*8) & 0xff])
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cycle_id, cycle_data, cycle_resp, cycle_last, cycle_user = self.int_read_resp_queue_list[rid].pop(0)
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cycle_offset = (cycle_offset + num_bytes) % bw
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if cycle_resp != 0:
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resp = cycle_resp
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start = cycle_offset
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stop = cycle_offset+num_bytes
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if first:
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start = start_offset
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assert cycle_last == (k == burst_length - 1)
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for j in range(start, stop):
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data += bytearray([(cycle_data >> j*8) & 0xff])
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cycle_offset = (cycle_offset + num_bytes) % bw
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first = False
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data = data[:length]
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if name is not None:
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print("[%s] Read data addr: 0x%08x prot: 0x%x data: %s" % (name, addr, prot, " ".join(("{:02x}".format(c) for c in bytearray(data)))))
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@ -468,7 +548,8 @@ class AXIMaster(object):
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addr, arid, length, size, burst, lock, cache, prot, qos, region, user = self.int_read_addr_queue.pop(0)
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m_axi_araddr.next = addr
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m_axi_arid.next = arid
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if m_axi_arid is not None:
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m_axi_arid.next = arid
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m_axi_arlen.next = length
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m_axi_arsize.next = size
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m_axi_arburst.next = burst
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@ -479,11 +560,12 @@ class AXIMaster(object):
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m_axi_arregion.next = region
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if m_axi_aruser is not None:
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m_axi_aruser.next = user
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m_axi_arvalid.next = True
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m_axi_arvalid.next = not (pause or arpause)
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yield clk.posedge
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while m_axi_arvalid and not m_axi_arready:
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while not m_axi_arvalid or not m_axi_arready:
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m_axi_arvalid.next = m_axi_arvalid or not (pause or arpause)
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yield clk.posedge
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m_axi_arvalid.next = False
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@ -491,12 +573,24 @@ class AXIMaster(object):
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@instance
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def read_resp_interface_logic():
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while True:
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m_axi_rready.next = True
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m_axi_rready_int.next = True
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yield clk.posedge
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if m_axi_rready & m_axi_rvalid:
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self.int_read_resp_queue.append((int(m_axi_rdata), int(m_axi_rresp), int(m_axi_rlast)))
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if m_axi_rready and m_axi_rvalid_int:
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if m_axi_rid is not None:
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rid = int(m_axi_rid)
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else:
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rid = 0
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rdata = int(m_axi_rdata)
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rresp = int(m_axi_rresp)
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rlast = int(m_axi_rlast)
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if m_axi_buser is not None:
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ruser = int(m_axi_ruser)
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else:
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ruser = 0
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self.int_read_resp_queue_list.setdefault(rid, [])
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self.int_read_resp_queue_list[rid].append((rid, rdata, rresp, rlast, ruser))
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self.int_read_resp_sync.next = not self.int_read_resp_sync
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return instances()
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@ -525,7 +619,7 @@ class AXIRam(object):
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def write_mem(self, address, data):
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self.mem.seek(address % self.size)
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self.mem.write(data)
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self.mem.write(bytes(data))
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def create_port(self,
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clk,
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@ -564,35 +658,56 @@ class AXIRam(object):
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s_axi_rlast=Signal(bool(True)),
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s_axi_rvalid=Signal(bool(False)),
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s_axi_rready=Signal(bool(False)),
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pause=False,
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awpause=False,
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wpause=False,
|
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bpause=False,
|
||||
arpause=False,
|
||||
rpause=False,
|
||||
name=None
|
||||
):
|
||||
|
||||
if s_axi_wdata is not None:
|
||||
assert s_axi_awid is not None
|
||||
assert s_axi_bid is not None
|
||||
assert len(s_axi_awid) == len(s_axi_bid)
|
||||
if s_axi_awid is not None:
|
||||
assert s_axi_bid is not None
|
||||
assert len(s_axi_awid) == len(s_axi_bid)
|
||||
assert s_axi_awaddr is not None
|
||||
assert len(s_axi_wdata) % 8 == 0
|
||||
assert len(s_axi_wdata) / 8 == len(s_axi_wstrb)
|
||||
w = len(s_axi_wdata)
|
||||
|
||||
if s_axi_rdata is not None:
|
||||
assert s_axi_arid is not None
|
||||
assert s_axi_rid is not None
|
||||
assert len(s_axi_arid) == len(s_axi_rid)
|
||||
if s_axi_arid is not None:
|
||||
assert s_axi_rid is not None
|
||||
assert len(s_axi_arid) == len(s_axi_rid)
|
||||
assert s_axi_araddr is not None
|
||||
assert len(s_axi_rdata) % 8 == 0
|
||||
w = len(s_axi_rdata)
|
||||
|
||||
if s_axi_wdata is not None:
|
||||
assert len(s_axi_wdata) == len(s_axi_rdata)
|
||||
assert len(s_axi_awid) == len(s_axi_arid)
|
||||
assert len(s_axi_awaddr) == len(s_axi_araddr)
|
||||
assert len(s_axi_wdata) == len(s_axi_rdata)
|
||||
|
||||
bw = int(w/8)
|
||||
|
||||
assert bw in (1, 2, 4, 8, 16, 32, 64, 128)
|
||||
|
||||
s_axi_awvalid_int = Signal(bool(False))
|
||||
s_axi_awready_int = Signal(bool(False))
|
||||
s_axi_wvalid_int = Signal(bool(False))
|
||||
s_axi_wready_int = Signal(bool(False))
|
||||
s_axi_arvalid_int = Signal(bool(False))
|
||||
s_axi_arready_int = Signal(bool(False))
|
||||
|
||||
@always_comb
|
||||
def pause_logic():
|
||||
s_axi_awvalid_int.next = s_axi_awvalid and not (pause or awpause)
|
||||
s_axi_awready.next = s_axi_awready_int and not (pause or awpause)
|
||||
s_axi_wvalid_int.next = s_axi_wvalid and not (pause or wpause)
|
||||
s_axi_wready.next = s_axi_wready_int and not (pause or wpause)
|
||||
s_axi_arvalid_int.next = s_axi_arvalid and not (pause or arpause)
|
||||
s_axi_arready.next = s_axi_arready_int and not (pause or arpause)
|
||||
|
||||
@instance
|
||||
def write_logic():
|
||||
while True:
|
||||
@ -601,6 +716,9 @@ class AXIRam(object):
|
||||
|
||||
addr, awid, length, size, burst, lock, cache, prot = self.int_write_addr_queue.pop(0)
|
||||
|
||||
if name is not None:
|
||||
print("[%s] Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d" % (name, awid, addr, length, size))
|
||||
|
||||
num_bytes = 2**size
|
||||
assert 0 < num_bytes <= bw
|
||||
|
||||
@ -622,25 +740,28 @@ class AXIRam(object):
|
||||
for n in range(length):
|
||||
cur_word_addr = int(cur_addr/bw)*bw
|
||||
|
||||
self.mem.seek(cur_word_addr % self.size)
|
||||
|
||||
if not self.int_write_data_queue:
|
||||
yield self.int_write_data_sync
|
||||
|
||||
wdata, strb, last = self.int_write_data_queue.pop(0)
|
||||
|
||||
self.mem.seek(cur_word_addr % self.size)
|
||||
|
||||
data = bytearray()
|
||||
for i in range(bw):
|
||||
data.extend(bytearray([wdata & 0xff]))
|
||||
wdata >>= 8
|
||||
for i in range(bw):
|
||||
if strb & (1 << i):
|
||||
self.mem.write(data[i:i+1])
|
||||
self.mem.write(bytes(data[i:i+1]))
|
||||
else:
|
||||
self.mem.seek(1, 1)
|
||||
if n == length-1:
|
||||
self.int_write_resp_queue.append((awid, 0b00))
|
||||
self.int_write_resp_sync.next = not self.int_write_resp_sync
|
||||
if last != (n == length-1):
|
||||
print("Error: bad last assert")
|
||||
raise StopSimulation
|
||||
assert last == (n == length-1)
|
||||
if name is not None:
|
||||
print("[%s] Write word id: %d addr: 0x%08x prot: 0x%x wstrb: 0x%02x data: %s" % (name, awid, cur_addr, prot, s_axi_wstrb, " ".join(("{:02x}".format(c) for c in bytearray(data)))))
|
||||
@ -655,13 +776,16 @@ class AXIRam(object):
|
||||
@instance
|
||||
def write_addr_interface_logic():
|
||||
while True:
|
||||
s_axi_awready.next = True
|
||||
s_axi_awready_int.next = True
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
if s_axi_awready & s_axi_awvalid:
|
||||
if s_axi_awready and s_axi_awvalid_int:
|
||||
addr = int(s_axi_awaddr)
|
||||
awid = int(s_axi_awid)
|
||||
if s_axi_awid is not None:
|
||||
awid = int(s_axi_awid)
|
||||
else:
|
||||
awid = 0
|
||||
length = int(s_axi_awlen)
|
||||
size = int(s_axi_awsize)
|
||||
burst = int(s_axi_awburst)
|
||||
@ -674,11 +798,11 @@ class AXIRam(object):
|
||||
@instance
|
||||
def write_data_interface_logic():
|
||||
while True:
|
||||
s_axi_wready.next = True
|
||||
s_axi_wready_int.next = True
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
if s_axi_wready & s_axi_wvalid:
|
||||
if s_axi_wready and s_axi_wvalid_int:
|
||||
data = int(s_axi_wdata)
|
||||
strb = int(s_axi_wstrb)
|
||||
last = bool(s_axi_wlast)
|
||||
@ -691,12 +815,16 @@ class AXIRam(object):
|
||||
while not self.int_write_resp_queue:
|
||||
yield clk.posedge
|
||||
|
||||
s_axi_bid.next, s_axi_bresp.next = self.int_write_resp_queue.pop(0)
|
||||
s_axi_bvalid.next = True
|
||||
bid, bresp = self.int_write_resp_queue.pop(0)
|
||||
if s_axi_bid is not None:
|
||||
s_axi_bid.next = bid
|
||||
s_axi_bresp.next = bresp
|
||||
s_axi_bvalid.next = not (pause or bpause)
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
while s_axi_bvalid and not s_axi_bready:
|
||||
while not s_axi_bvalid or not s_axi_bready:
|
||||
s_axi_bvalid.next = s_axi_bvalid or not (pause or bpause)
|
||||
yield clk.posedge
|
||||
|
||||
s_axi_bvalid.next = False
|
||||
@ -709,6 +837,9 @@ class AXIRam(object):
|
||||
|
||||
addr, arid, length, size, burst, lock, cache, prot = self.int_read_addr_queue.pop(0)
|
||||
|
||||
if name is not None:
|
||||
print("[%s] Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d" % (name, arid, addr, length, size))
|
||||
|
||||
num_bytes = 2**size
|
||||
assert 0 < num_bytes <= bw
|
||||
|
||||
@ -752,13 +883,16 @@ class AXIRam(object):
|
||||
@instance
|
||||
def read_addr_interface_logic():
|
||||
while True:
|
||||
s_axi_arready.next = True
|
||||
s_axi_arready_int.next = True
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
if s_axi_arready & s_axi_arvalid:
|
||||
if s_axi_arready and s_axi_arvalid_int:
|
||||
addr = int(s_axi_araddr)
|
||||
arid = int(s_axi_arid)
|
||||
if s_axi_arid is not None:
|
||||
arid = int(s_axi_arid)
|
||||
else:
|
||||
arid = 0
|
||||
length = int(s_axi_arlen)
|
||||
size = int(s_axi_arsize)
|
||||
burst = int(s_axi_arburst)
|
||||
@ -774,12 +908,18 @@ class AXIRam(object):
|
||||
while not self.int_read_resp_queue:
|
||||
yield clk.posedge
|
||||
|
||||
s_axi_rid.next, s_axi_rdata.next, s_axi_rresp.next, s_axi_rlast.next = self.int_read_resp_queue.pop(0)
|
||||
s_axi_rvalid.next = True
|
||||
rid, rdata, rresp, rlast = self.int_read_resp_queue.pop(0)
|
||||
if s_axi_rid is not None:
|
||||
s_axi_rid.next = rid
|
||||
s_axi_rdata.next = rdata
|
||||
s_axi_rresp.next = rresp
|
||||
s_axi_rlast.next = rlast
|
||||
s_axi_rvalid.next = not (pause or rpause)
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
while s_axi_rvalid and not s_axi_rready:
|
||||
while not s_axi_rvalid or not s_axi_rready:
|
||||
s_axi_rvalid.next = s_axi_rvalid or not (pause or rpause)
|
||||
yield clk.posedge
|
||||
|
||||
s_axi_rvalid.next = False
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user