diff --git a/rtl/axis_baser_rx_64.v b/rtl/axis_baser_rx_64.v
index 12cfb21d5..30c04522a 100644
--- a/rtl/axis_baser_rx_64.v
+++ b/rtl/axis_baser_rx_64.v
@@ -596,9 +596,6 @@ always @(posedge clk) begin
         error_bad_fcs_reg <= 1'b0;
         rx_bad_block_reg <= 1'b0;
 
-        crc_state <= 32'hFFFFFFFF;
-        crc_state3 <= 32'hFFFFFFFF;
-
         input_type_d0 <= INPUT_TYPE_IDLE;
         input_type_d1 <= INPUT_TYPE_IDLE;
 
diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v
index 915bdb8ae..6d9a5d6d2 100644
--- a/rtl/axis_baser_tx_64.v
+++ b/rtl/axis_baser_tx_64.v
@@ -884,8 +884,6 @@ always @(posedge clk) begin
     if (rst) begin
         state_reg <= STATE_IDLE;
 
-        frame_ptr_reg <= 16'd0;
-
         ifg_count_reg <= 8'd0;
         deficit_idle_count_reg <= 2'd0;
 
@@ -903,8 +901,6 @@ always @(posedge clk) begin
         start_packet_reg <= 2'b00;
         error_underflow_reg <= 1'b0;
 
-        crc_state <= 32'hFFFFFFFF;
-
         lanes_swapped <= 1'b0;
 
         delay_type_valid <= 1'b0;
diff --git a/rtl/axis_gmii_rx.v b/rtl/axis_gmii_rx.v
index cdddc5b01..6203b2b27 100644
--- a/rtl/axis_gmii_rx.v
+++ b/rtl/axis_gmii_rx.v
@@ -327,8 +327,6 @@ always @(posedge clk) begin
         error_bad_frame_reg <= 1'b0;
         error_bad_fcs_reg <= 1'b0;
 
-        crc_state <= 32'hFFFFFFFF;
-
         mii_locked <= 1'b0;
         mii_odd <= 1'b0;
 
diff --git a/rtl/axis_gmii_tx.v b/rtl/axis_gmii_tx.v
index 1b0972726..a76aa5d24 100644
--- a/rtl/axis_gmii_tx.v
+++ b/rtl/axis_gmii_tx.v
@@ -428,8 +428,6 @@ always @(posedge clk) begin
     if (rst) begin
         state_reg <= STATE_IDLE;
 
-        frame_ptr_reg <= 16'd0;
-
         s_axis_tready_reg <= 1'b0;
 
         m_axis_ptp_ts_valid_reg <= 1'b0;
@@ -439,8 +437,6 @@ always @(posedge clk) begin
 
         start_packet_reg <= 1'b0;
         error_underflow_reg <= 1'b0;
-
-        crc_state <= 32'hFFFFFFFF;
     end
 end
 
diff --git a/rtl/axis_xgmii_rx_32.v b/rtl/axis_xgmii_rx_32.v
index d110c5688..2873135d6 100644
--- a/rtl/axis_xgmii_rx_32.v
+++ b/rtl/axis_xgmii_rx_32.v
@@ -421,8 +421,6 @@ always @(posedge clk) begin
         error_bad_frame_reg <= 1'b0;
         error_bad_fcs_reg <= 1'b0;
 
-        crc_state <= 32'hFFFFFFFF;
-
         xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}};
         xgmii_rxc_d1 <= {CTRL_WIDTH{1'b0}};
     end
diff --git a/rtl/axis_xgmii_rx_64.v b/rtl/axis_xgmii_rx_64.v
index ba7b118d4..acd749992 100644
--- a/rtl/axis_xgmii_rx_64.v
+++ b/rtl/axis_xgmii_rx_64.v
@@ -539,9 +539,6 @@ always @(posedge clk) begin
         error_bad_frame_reg <= 1'b0;
         error_bad_fcs_reg <= 1'b0;
 
-        crc_state <= 32'hFFFFFFFF;
-        crc_state3 <= 32'hFFFFFFFF;
-
         xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}};
         xgmii_rxc_d1 <= {CTRL_WIDTH{1'b0}};
 
diff --git a/rtl/axis_xgmii_tx_32.v b/rtl/axis_xgmii_tx_32.v
index 3050db971..9f081052c 100644
--- a/rtl/axis_xgmii_tx_32.v
+++ b/rtl/axis_xgmii_tx_32.v
@@ -607,8 +607,6 @@ always @(posedge clk) begin
     if (rst) begin
         state_reg <= STATE_IDLE;
 
-        frame_ptr_reg <= 16'd0;
-
         ifg_count_reg <= 8'd0;
         deficit_idle_count_reg <= 2'd0;
 
@@ -621,8 +619,6 @@ always @(posedge clk) begin
 
         start_packet_reg <= 1'b0;
         error_underflow_reg <= 1'b0;
-
-        crc_state <= 32'hFFFFFFFF;
     end
 end
 
diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v
index 7f0cc3fc9..fd83bdc63 100644
--- a/rtl/axis_xgmii_tx_64.v
+++ b/rtl/axis_xgmii_tx_64.v
@@ -758,8 +758,6 @@ always @(posedge clk) begin
     if (rst) begin
         state_reg <= STATE_IDLE;
 
-        frame_ptr_reg <= 16'd0;
-
         ifg_count_reg <= 8'd0;
         deficit_idle_count_reg <= 2'd0;
 
@@ -774,8 +772,6 @@ always @(posedge clk) begin
         start_packet_reg <= 2'b00;
         error_underflow_reg <= 1'b0;
 
-        crc_state <= 32'hFFFFFFFF;
-
         lanes_swapped <= 1'b0;
     end
 end