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Remove unnecessary resets

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-07-24 10:14:54 -07:00
parent c1e947dc3d
commit ebd5f04e2d
8 changed files with 0 additions and 26 deletions
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3
rtl/axis_baser_rx_64.v
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@ -596,9 +596,6 @@ always @(posedge clk) begin
error_bad_fcs_reg <= 1'b0; error_bad_fcs_reg <= 1'b0;
rx_bad_block_reg <= 1'b0; rx_bad_block_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
input_type_d0 <= INPUT_TYPE_IDLE; input_type_d0 <= INPUT_TYPE_IDLE;
input_type_d1 <= INPUT_TYPE_IDLE; input_type_d1 <= INPUT_TYPE_IDLE;

4
rtl/axis_baser_tx_64.v
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@ -884,8 +884,6 @@ always @(posedge clk) begin
if (rst) begin if (rst) begin
state_reg <= STATE_IDLE; state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
ifg_count_reg <= 8'd0; ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0; deficit_idle_count_reg <= 2'd0;
@ -903,8 +901,6 @@ always @(posedge clk) begin
start_packet_reg <= 2'b00; start_packet_reg <= 2'b00;
error_underflow_reg <= 1'b0; error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
lanes_swapped <= 1'b0; lanes_swapped <= 1'b0;
delay_type_valid <= 1'b0; delay_type_valid <= 1'b0;

2
rtl/axis_gmii_rx.v
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@ -327,8 +327,6 @@ always @(posedge clk) begin
error_bad_frame_reg <= 1'b0; error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0; error_bad_fcs_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
mii_locked <= 1'b0; mii_locked <= 1'b0;
mii_odd <= 1'b0; mii_odd <= 1'b0;

4
rtl/axis_gmii_tx.v
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@ -428,8 +428,6 @@ always @(posedge clk) begin
if (rst) begin if (rst) begin
state_reg <= STATE_IDLE; state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
s_axis_tready_reg <= 1'b0; s_axis_tready_reg <= 1'b0;
m_axis_ptp_ts_valid_reg <= 1'b0; m_axis_ptp_ts_valid_reg <= 1'b0;
@ -439,8 +437,6 @@ always @(posedge clk) begin
start_packet_reg <= 1'b0; start_packet_reg <= 1'b0;
error_underflow_reg <= 1'b0; error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
end end
end end

2
rtl/axis_xgmii_rx_32.v
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@ -421,8 +421,6 @@ always @(posedge clk) begin
error_bad_frame_reg <= 1'b0; error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0; error_bad_fcs_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}}; xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}};
xgmii_rxc_d1 <= {CTRL_WIDTH{1'b0}}; xgmii_rxc_d1 <= {CTRL_WIDTH{1'b0}};
end end

3
rtl/axis_xgmii_rx_64.v
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@ -539,9 +539,6 @@ always @(posedge clk) begin
error_bad_frame_reg <= 1'b0; error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0; error_bad_fcs_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}}; xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}};
xgmii_rxc_d1 <= {CTRL_WIDTH{1'b0}}; xgmii_rxc_d1 <= {CTRL_WIDTH{1'b0}};

4
rtl/axis_xgmii_tx_32.v
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@ -607,8 +607,6 @@ always @(posedge clk) begin
if (rst) begin if (rst) begin
state_reg <= STATE_IDLE; state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
ifg_count_reg <= 8'd0; ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0; deficit_idle_count_reg <= 2'd0;
@ -621,8 +619,6 @@ always @(posedge clk) begin
start_packet_reg <= 1'b0; start_packet_reg <= 1'b0;
error_underflow_reg <= 1'b0; error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
end end
end end

4
rtl/axis_xgmii_tx_64.v
View File

@ -758,8 +758,6 @@ always @(posedge clk) begin
if (rst) begin if (rst) begin
state_reg <= STATE_IDLE; state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
ifg_count_reg <= 8'd0; ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0; deficit_idle_count_reg <= 2'd0;
@ -774,8 +772,6 @@ always @(posedge clk) begin
start_packet_reg <= 2'b00; start_packet_reg <= 2'b00;
error_underflow_reg <= 1'b0; error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
lanes_swapped <= 1'b0; lanes_swapped <= 1'b0;
end end
end end