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Add stretched PTP PPS output

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-07-18 22:25:58 -07:00
parent 676f3edd2d
commit ef5b2449dc
36 changed files with 124 additions and 360 deletions
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1
fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
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@ -296,6 +296,7 @@ module mqnic_app_block #
input wire ptp_rst,
input wire ptp_sample_clk,
input wire ptp_pps,
input wire ptp_pps_str,
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
input wire ptp_sync_pps,

1
fpga/app/template/rtl/mqnic_app_block.v
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@ -296,6 +296,7 @@ module mqnic_app_block #
input wire ptp_rst,
input wire ptp_sample_clk,
input wire ptp_pps,
input wire ptp_pps_str,
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
input wire ptp_sync_pps,

3
fpga/common/rtl/mqnic_core.v
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@ -360,6 +360,7 @@ module mqnic_core #
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
@ -701,6 +702,7 @@ mqnic_ptp_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
@ -3131,6 +3133,7 @@ if (APP_ENABLE) begin : app
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

2
fpga/common/rtl/mqnic_core_axi.v
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@ -321,6 +321,7 @@ module mqnic_core_axi #
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
@ -1091,6 +1092,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

2
fpga/common/rtl/mqnic_core_pcie.v
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@ -345,6 +345,7 @@ module mqnic_core_pcie #
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
@ -1760,6 +1761,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

2
fpga/common/rtl/mqnic_core_pcie_s10.v
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@ -283,6 +283,7 @@ module mqnic_core_pcie_s10 #
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
@ -914,6 +915,7 @@ core_pcie_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

2
fpga/common/rtl/mqnic_core_pcie_us.v
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@ -342,6 +342,7 @@ module mqnic_core_pcie_us #
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
@ -1029,6 +1030,7 @@ core_pcie_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

2
fpga/common/rtl/mqnic_ptp.v
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@ -81,6 +81,7 @@ module mqnic_ptp #
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [95:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
@ -193,6 +194,7 @@ ptp_clock_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

21
fpga/common/rtl/mqnic_ptp_clock.v
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@ -81,6 +81,7 @@ module mqnic_ptp_clock #
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [95:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
@ -330,6 +331,26 @@ ptp_clock_inst (
.output_pps(ptp_pps)
);
// stretched PPS output
localparam PPS_CNT_PERIOD = (64'd500_000_000*PTP_CLK_PERIOD_NS_DENOM)/PTP_CLK_PERIOD_NS_NUM;
reg [$clog2(PPS_CNT_PERIOD)-1:0] pps_counter_reg = 0;
reg pps_str_reg = 0;
always @(posedge ptp_clk) begin
pps_str_reg <= 1'b0;
if (ptp_pps) begin
pps_counter_reg <= PPS_CNT_PERIOD;
pps_str_reg <= 1'b1;
end else if (pps_counter_reg > 0) begin
pps_counter_reg <= pps_counter_reg - 1;
pps_str_reg <= 1'b1;
end
end
assign ptp_pps_str = pps_str_reg;
// sync to core clock domain
ptp_clock_cdc #(
.TS_WIDTH(96),

19
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
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@ -403,6 +403,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -661,23 +662,10 @@ always @(posedge clk_250mhz) begin
end
end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign user_led_g[0] = 1'b1;
assign user_led_g[1] = !pps_led_reg;
assign user_led_g[1] = !ptp_pps_str;
assign user_led_r = 1'b1;
assign front_led[0] = !pps_led_reg;
assign front_led[0] = !ptp_pps_str;
assign front_led[1] = 1'b0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1128,6 +1116,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

19
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
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@ -492,6 +492,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -846,19 +847,6 @@ qsfp_1_rb_drp_inst (
.drp_rdy(qsfp_1_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -935,9 +923,9 @@ end
endgenerate
assign user_led_g[0] = 1'b1;
assign user_led_g[1] = !pps_led_reg;
assign user_led_g[1] = !ptp_pps_str;
assign user_led_r = 1'b1;
assign front_led[0] = !pps_led_reg;
assign front_led[0] = !ptp_pps_str;
assign front_led[1] = 1'b0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1394,6 +1382,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
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@ -420,6 +420,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -672,20 +673,7 @@ always @(posedge clk_250mhz) begin
end
end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign led[0] = pps_led_reg;
assign led[0] = ptp_pps_str;
assign led[2:1] = 0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1136,6 +1124,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
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@ -509,6 +509,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -857,19 +858,6 @@ qsfp1_rb_drp_inst (
.drp_rdy(qsfp1_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -946,7 +934,7 @@ end
endgenerate
assign led[0] = pps_led_reg;
assign led[0] = ptp_pps_str;
assign led[2:1] = 0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1403,6 +1391,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
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@ -420,6 +420,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -672,20 +673,7 @@ always @(posedge clk_250mhz) begin
end
end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign led[0] = pps_led_reg;
assign led[0] = ptp_pps_str;
assign led[2:1] = 0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1136,6 +1124,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
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@ -509,6 +509,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -857,19 +858,6 @@ qsfp1_rb_drp_inst (
.drp_rdy(qsfp1_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -946,7 +934,7 @@ end
endgenerate
assign led[0] = pps_led_reg;
assign led[0] = ptp_pps_str;
assign led[2:1] = 0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1403,6 +1391,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -392,6 +392,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -1012,6 +1013,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

2
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -481,6 +481,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -1279,6 +1280,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -369,6 +369,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -541,20 +542,7 @@ always @(posedge clk_250mhz) begin
end
end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign qsfp_led_act = pps_led_reg;
assign qsfp_led_act = ptp_pps_str;
assign qsfp_led_stat_g = 1'b0;
assign qsfp_led_stat_y = 1'b0;
@ -1002,6 +990,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -429,6 +429,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -649,19 +650,6 @@ qsfp_rb_drp_inst (
.drp_rdy(qsfp_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -730,7 +718,7 @@ end
endgenerate
assign qsfp_led_act = pps_led_reg;
assign qsfp_led_act = ptp_pps_str;
assign qsfp_led_stat_g = 1'b0;
assign qsfp_led_stat_y = 1'b0;
@ -1188,6 +1176,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
View File

@ -499,6 +499,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -871,19 +872,6 @@ qsfp1_rb_drp_inst (
.drp_rdy(qsfp1_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 78125000;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -961,7 +949,7 @@ end
endgenerate
assign user_led[6:0] = 0;
assign user_led[7] = pps_led_reg;
assign user_led[7] = ptp_pps_str;
assign qsfp0_leg_green = 1'b0;
assign qsfp0_leg_red = 1'b0;
@ -1422,6 +1410,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -380,6 +380,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -550,24 +551,11 @@ always @(posedge clk_250mhz) begin
end
end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 78125000;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign sfp_1_led = 2'b00;
assign sfp_2_led = 2'b00;
assign sfp_3_led = 2'b00;
assign sfp_4_led = 2'b00;
assign led[0] = pps_led_reg;
assign led[0] = ptp_pps_str;
assign led[1] = 1'b0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1024,6 +1012,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
View File

@ -382,6 +382,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -702,26 +703,13 @@ sfp_rb_drp_inst (
.drp_rdy(sfp_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign sma_out = ptp_perout_pulse;
assign sma_out_en = 1'b0;
assign sma_term_en = 1'b0;
assign sfp_1_led = 2'b00;
assign sfp_2_led = 2'b00;
assign sma_led[0] = pps_led_reg;
assign sma_led[0] = ptp_pps_str;
assign sma_led[1] = 1'b0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1178,6 +1166,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
View File

@ -506,6 +506,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -905,19 +906,6 @@ qsfp_1_rb_drp_inst (
.drp_rdy(qsfp_1_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -1001,7 +989,7 @@ assign qsfp_0_led_green = 1'b0;
assign qsfp_0_led_orange = 1'b0;
assign qsfp_1_led_green = 1'b0;
assign qsfp_1_led_orange = 1'b0;
assign sma_led_green = pps_led_reg;
assign sma_led_green = ptp_pps_str;
assign sma_led_red = 1'b0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1458,6 +1446,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
View File

@ -417,6 +417,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -737,19 +738,6 @@ sfp_rb_drp_inst (
.drp_rdy(sfp_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -819,7 +807,7 @@ assign sma_term_en = 1'b0;
assign sfp_1_led = 2'b00;
assign sfp_2_led = 2'b00;
assign sma_led[0] = pps_led_reg;
assign sma_led[0] = ptp_pps_str;
assign sma_led[1] = 1'b0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1276,6 +1264,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

19
fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
View File

@ -381,6 +381,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -582,19 +583,6 @@ always @(posedge clk_250mhz) begin
end
end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 78125000;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
// // BER tester
// tdma_ber #(
// .COUNT(8),
@ -643,10 +631,10 @@ end
// .ptp_ts_step(ptp_ts_step)
// );
assign user_led[0] = pps_led_reg;
assign user_led[0] = 1'b0;
assign user_led[1] = 1'b0;
assign user_led[2] = 1'b0;
assign user_led[3] = 1'b0;
assign user_led[3] = ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
@ -1043,6 +1031,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -426,6 +426,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -686,19 +687,6 @@ qsfp_rb_drp_inst (
.drp_rdy(qsfp_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 78125000;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -772,7 +760,7 @@ assign pmod1[0] = ptp_perout_pulse;
assign pmod1[7:1] = 0;
assign led[6:0] = 0;
assign led[7] = pps_led_reg;
assign led[7] = ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
@ -1228,6 +1216,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

19
fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
View File

@ -406,6 +406,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -635,26 +636,13 @@ always @(posedge clk_250mhz) begin
end
end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 78125000;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign pmod0[0] = ptp_perout_pulse;
assign pmod0[7:1] = 0;
assign pmod1[0] = ptp_perout_pulse;
assign pmod1[7:1] = 0;
assign led[0] = pps_led_reg;
assign led[2:1] = 0;
assign led[6:0] = 0;
assign led[7] = ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
@ -1104,6 +1092,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

19
fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
View File

@ -495,6 +495,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -820,19 +821,6 @@ qsfp2_rb_drp_inst (
.drp_rdy(qsfp2_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 78125000;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -914,8 +902,8 @@ assign pmod0[7:1] = 0;
assign pmod1[0] = ptp_perout_pulse;
assign pmod1[7:1] = 0;
assign led[0] = pps_led_reg;
assign led[2:1] = 0;
assign led[6:0] = 0;
assign led[7] = ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
@ -1371,6 +1359,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
View File

@ -395,6 +395,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -595,20 +596,7 @@ always @(posedge clk_250mhz) begin
end
end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign led[0] = pps_led_reg;
assign led[0] = ptp_pps_str;
assign led[2:1] = 0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1059,6 +1047,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

18
fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
View File

@ -484,6 +484,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -780,19 +781,6 @@ qsfp1_rb_drp_inst (
.drp_rdy(qsfp1_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -869,7 +857,7 @@ end
endgenerate
assign led[0] = pps_led_reg;
assign led[0] = ptp_pps_str;
assign led[2:1] = 0;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1325,7 +1313,7 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
View File

@ -490,6 +490,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -843,21 +844,8 @@ always @(posedge clk_250mhz) begin
end
end
reg [27:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 161132812;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign led[2:0] = 3'b111;
assign led[3] = !pps_led_reg;
assign led[3] = !ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
@ -1315,6 +1303,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

17
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
View File

@ -638,6 +638,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -1183,19 +1184,6 @@ qsfp3_rb_drp_inst (
.drp_rdy(qsfp3_drp_rdy)
);
reg [27:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 161132812;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -1289,7 +1277,7 @@ end
endgenerate
assign led[2:0] = 3'b111;
assign led[3] = !pps_led_reg;
assign led[3] = !ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
@ -1745,6 +1733,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

19
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
View File

@ -387,6 +387,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -553,19 +554,6 @@ sfp_rb_drp_inst (
.drp_rdy(sfp_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 78125000;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -629,8 +617,8 @@ end
endgenerate
assign led[0] = pps_led_reg;
assign led[7:1] = 0;
assign led[6:0] = 0;
assign led[7] = ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
@ -1082,6 +1070,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

19
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
View File

@ -376,6 +376,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -510,19 +511,6 @@ sfp_rb_drp_inst (
.drp_rdy(sfp_drp_rdy)
);
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 78125000;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -586,8 +574,8 @@ end
endgenerate
assign led[0] = pps_led_reg;
assign led[7:1] = 0;
assign led[6:0] = 0;
assign led[7] = ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
@ -1018,6 +1006,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

19
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
View File

@ -410,6 +410,7 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -693,24 +694,11 @@ bmc_spi_inst (
assign pps_out = ptp_perout_pulse[0];
assign pps_out_en = 1'b1;
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
assign led_red = 8'd0;
assign led_green = 8'd0;
assign led_bmc[0] = pps_led_reg;
assign led_bmc[0] = ptp_pps_str;
assign led_bmc[1] = 0;
assign led_exp[0] = !pps_led_reg;
assign led_exp[0] = !ptp_pps_str;
assign led_exp[1] = 1'b1;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1161,6 +1149,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),

19
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -499,6 +499,7 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
@ -878,19 +879,6 @@ qsfp_1_rb_drp_inst (
assign pps_out = ptp_perout_pulse[0];
assign pps_out_en = 1'b1;
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
pps_led_reg <= pps_led_counter_reg > 0;
end
generate
if (TDMA_BER_ENABLE) begin
@ -968,9 +956,9 @@ endgenerate
assign led_red = 8'd0;
assign led_green = 8'd0;
assign led_bmc[0] = pps_led_reg;
assign led_bmc[0] = ptp_pps_str;
assign led_bmc[1] = 0;
assign led_exp[0] = !pps_led_reg;
assign led_exp[0] = !ptp_pps_str;
assign led_exp[1] = 1'b1;
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -1427,6 +1415,7 @@ core_inst (
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),