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Add IO delay false paths to HTG-9200 constraints file

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-07-20 21:15:20 -07:00
parent 4a65e3594c
commit efb3747967
1 changed files with 51 additions and 19 deletions
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32
example/HTG9200/fpga_25g/fpga.xdc
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@ -41,6 +41,11 @@ set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}] #set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}]
#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}] #set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}]
set_false_path -to [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}]
set_output_delay 0 [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}]
set_false_path -from [get_ports {clk_gty2_intr_n clk_gty2_lol_n}]
set_input_delay 0 [get_ports {clk_gty2_intr_n clk_gty2_lol_n}]
# LEDs # LEDs
set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
set_property -dict {LOC BB24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] set_property -dict {LOC BB24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
@ -51,10 +56,16 @@ set_property -dict {LOC BD25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
set_property -dict {LOC BC26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] set_property -dict {LOC BC26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}]
set_property -dict {LOC BC27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] set_property -dict {LOC BC27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}]
set_false_path -to [get_ports {led[*]}]
set_output_delay 0 [get_ports {led[*]}]
# Push buttons # Push buttons
set_property -dict {LOC B31 IOSTANDARD LVCMOS12} [get_ports {btn[0]}] set_property -dict {LOC B31 IOSTANDARD LVCMOS12} [get_ports {btn[0]}]
set_property -dict {LOC C31 IOSTANDARD LVCMOS12} [get_ports {btn[1]}] set_property -dict {LOC C31 IOSTANDARD LVCMOS12} [get_ports {btn[1]}]
set_false_path -from [get_ports {btn[*]}]
set_input_delay 0 [get_ports {btn[*]}]
# DIP switches # DIP switches
set_property -dict {LOC P33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] set_property -dict {LOC P33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
set_property -dict {LOC K34 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] set_property -dict {LOC K34 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
@ -65,6 +76,9 @@ set_property -dict {LOC D36 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
set_property -dict {LOC E37 IOSTANDARD LVCMOS12} [get_ports {sw[6]}] set_property -dict {LOC E37 IOSTANDARD LVCMOS12} [get_ports {sw[6]}]
set_property -dict {LOC F38 IOSTANDARD LVCMOS12} [get_ports {sw[7]}] set_property -dict {LOC F38 IOSTANDARD LVCMOS12} [get_ports {sw[7]}]
set_false_path -from [get_ports {sw[*]}]
set_input_delay 0 [get_ports {sw[*]}]
# GPIO # GPIO
#set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {gpio[0]}] #set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {gpio[0]}]
#set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {gpio[1]}] #set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {gpio[1]}]
@ -75,6 +89,9 @@ set_property -dict {LOC F38 IOSTANDARD LVCMOS12} [get_ports {sw[7]}]
#set_property -dict {LOC AU25 IOSTANDARD LVCMOS18} [get_ports {gpio[6]}] #set_property -dict {LOC AU25 IOSTANDARD LVCMOS18} [get_ports {gpio[6]}]
#set_property -dict {LOC AR26 IOSTANDARD LVCMOS18} [get_ports {gpio[7]}] #set_property -dict {LOC AR26 IOSTANDARD LVCMOS18} [get_ports {gpio[7]}]
#set_false_path -to [get_ports {gpio[*]}]
#set_output_delay 0 [get_ports {gpio[*]}]
# UART # UART
set_property -dict {LOC BB27 IOSTANDARD LVCMOS18} [get_ports uart_txd] set_property -dict {LOC BB27 IOSTANDARD LVCMOS18} [get_ports uart_txd]
set_property -dict {LOC AY27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rxd] set_property -dict {LOC AY27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rxd]
@ -87,11 +104,21 @@ set_property -dict {LOC BB26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports u
#set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[2]}] #set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[2]}]
#set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[3]}] #set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[3]}]
set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}]
set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}]
set_false_path -from [get_ports {uart_txd uart_rts}]
set_input_delay 0 [get_ports {uart_txd uart_rts}]
# I2C # I2C
set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl] set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl]
set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda] set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda]
set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n] set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n]
set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}]
set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}]
set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}]
set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}]
# QSPI flash # QSPI flash
#set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}] #set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}]
#set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}] #set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}]
@ -99,6 +126,11 @@ set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i
#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}] #set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}]
#set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}] #set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}]
#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
#set_false_path -from [get_ports {qspi_1_dq}]
#set_input_delay 0 [get_ports {qspi_1_dq}]
# DDR4 A # DDR4 A
# set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[0]}] # set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[0]}]
# set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[1]}] # set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[1]}]