From efbeecde35744292f77f11be459c83de7b457ea9 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 21 Sep 2022 15:19:49 -0700 Subject: [PATCH] fpga/common: Clean up parameters Signed-off-by: Alex Forencich --- fpga/common/rtl/mqnic_interface.v | 59 ++++++++++++++-------------- fpga/common/rtl/mqnic_interface_rx.v | 10 ++--- fpga/common/rtl/mqnic_interface_tx.v | 10 ++--- fpga/common/rtl/rx_engine.v | 20 +++++----- fpga/common/rtl/tx_engine.v | 25 +++++------- 5 files changed, 56 insertions(+), 68 deletions(-) diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index 513454ba9..20527428d 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -509,12 +509,17 @@ parameter EVENT_TYPE_WIDTH = 16; parameter MAX_DESC_TABLE_SIZE = TX_DESC_TABLE_SIZE > RX_DESC_TABLE_SIZE ? TX_DESC_TABLE_SIZE : RX_DESC_TABLE_SIZE; -parameter REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + $clog2(SCHEDULERS); -parameter REQ_TAG_WIDTH_INT = REQ_TAG_WIDTH - $clog2(SCHEDULERS); +parameter REQ_TAG_WIDTH_INT = $clog2(MAX_DESC_TABLE_SIZE); +parameter REQ_TAG_WIDTH = REQ_TAG_WIDTH_INT + $clog2(SCHEDULERS); -parameter DESC_REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + 1 + $clog2(PORTS+1); +parameter DESC_REQ_TAG_WIDTH_INT = $clog2(MAX_DESC_TABLE_SIZE); +parameter DESC_REQ_TAG_WIDTH = DESC_REQ_TAG_WIDTH_INT + $clog2(2); -parameter QUEUE_REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + 1 + $clog2(PORTS+1); +parameter CPL_REQ_TAG_WIDTH_INT = $clog2(MAX_DESC_TABLE_SIZE); +parameter CPL_REQ_TAG_WIDTH = CPL_REQ_TAG_WIDTH_INT + $clog2(3); + +parameter QUEUE_REQ_TAG_WIDTH = DESC_REQ_TAG_WIDTH; +parameter CPL_QUEUE_REQ_TAG_WIDTH = CPL_REQ_TAG_WIDTH; parameter QUEUE_OP_TAG_WIDTH = 6; parameter DMA_TAG_WIDTH_INT = DMA_TAG_WIDTH - $clog2(PORTS); @@ -523,8 +528,6 @@ parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH; parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH; parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH; -parameter DESC_REQ_TAG_WIDTH_INT = DESC_REQ_TAG_WIDTH - $clog2(3); - parameter AXIL_CSR_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); parameter AXIL_CTRL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); parameter AXIL_EQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8); @@ -706,12 +709,12 @@ wire [SCHEDULERS-1:0] axil_sched_rready; // Queue management wire [CPL_QUEUE_INDEX_WIDTH-1:0] event_enqueue_req_queue; -wire [QUEUE_REQ_TAG_WIDTH-1:0] event_enqueue_req_tag; +wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] event_enqueue_req_tag; wire event_enqueue_req_valid; wire event_enqueue_req_ready; wire [DMA_ADDR_WIDTH-1:0] event_enqueue_resp_addr; -wire [QUEUE_REQ_TAG_WIDTH-1:0] event_enqueue_resp_tag; +wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] event_enqueue_resp_tag; wire [QUEUE_OP_TAG_WIDTH-1:0] event_enqueue_resp_op_tag; wire event_enqueue_resp_full; wire event_enqueue_resp_error; @@ -747,12 +750,12 @@ wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_doorbell_queue; wire tx_doorbell_valid; wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_cpl_enqueue_req_queue; -wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_req_tag; +wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_req_tag; wire tx_cpl_enqueue_req_valid; wire tx_cpl_enqueue_req_ready; wire [DMA_ADDR_WIDTH-1:0] tx_cpl_enqueue_resp_addr; -wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_tag; +wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_tag; wire [QUEUE_OP_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_op_tag; wire tx_cpl_enqueue_resp_full; wire tx_cpl_enqueue_resp_error; @@ -785,12 +788,12 @@ wire rx_desc_dequeue_commit_valid; wire rx_desc_dequeue_commit_ready; wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_cpl_enqueue_req_queue; -wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_req_tag; +wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_req_tag; wire rx_cpl_enqueue_req_valid; wire rx_cpl_enqueue_req_ready; wire [DMA_ADDR_WIDTH-1:0] rx_cpl_enqueue_resp_addr; -wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_tag; +wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_tag; wire [QUEUE_OP_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_op_tag; wire rx_cpl_enqueue_resp_full; wire rx_cpl_enqueue_resp_error; @@ -883,36 +886,36 @@ wire cpl_req_status_valid; wire [1:0] event_cpl_req_sel = 2'd2; wire [QUEUE_INDEX_WIDTH-1:0] event_cpl_req_queue; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] event_cpl_req_tag; +wire [CPL_REQ_TAG_WIDTH_INT-1:0] event_cpl_req_tag; wire [CPL_SIZE*8-1:0] event_cpl_req_data; wire event_cpl_req_valid; wire event_cpl_req_ready; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] event_cpl_req_status_tag; +wire [CPL_REQ_TAG_WIDTH_INT-1:0] event_cpl_req_status_tag; wire event_cpl_req_status_full; wire event_cpl_req_status_error; wire event_cpl_req_status_valid; wire [1:0] rx_cpl_req_sel = 2'd1; wire [QUEUE_INDEX_WIDTH-1:0] rx_cpl_req_queue; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_tag; +wire [CPL_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_tag; wire [CPL_SIZE*8-1:0] rx_cpl_req_data; wire rx_cpl_req_valid; wire rx_cpl_req_ready; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_status_tag; +wire [CPL_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_status_tag; wire rx_cpl_req_status_full; wire rx_cpl_req_status_error; wire rx_cpl_req_status_valid; wire [1:0] tx_cpl_req_sel = 2'd0; wire [QUEUE_INDEX_WIDTH-1:0] tx_cpl_req_queue; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_tag; +wire [CPL_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_tag; wire [CPL_SIZE*8-1:0] tx_cpl_req_data; wire tx_cpl_req_valid; wire tx_cpl_req_ready; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_status_tag; +wire [CPL_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_status_tag; wire tx_cpl_req_status_full; wire tx_cpl_req_status_error; wire tx_cpl_req_status_valid; @@ -1265,7 +1268,7 @@ axil_crossbar_inst ( cpl_queue_manager #( .ADDR_WIDTH(DMA_ADDR_WIDTH), - .REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), + .REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), .OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), @@ -1435,7 +1438,7 @@ tx_queue_manager_inst ( cpl_queue_manager #( .ADDR_WIDTH(DMA_ADDR_WIDTH), - .REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), + .REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), .OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), @@ -1605,7 +1608,7 @@ rx_queue_manager_inst ( cpl_queue_manager #( .ADDR_WIDTH(DMA_ADDR_WIDTH), - .REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), + .REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), .OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), @@ -1896,8 +1899,8 @@ cpl_op_mux #( .PORTS(3), .SELECT_WIDTH(2), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), - .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), + .S_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH_INT), + .M_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH), .CPL_SIZE(CPL_SIZE), .ARB_TYPE_ROUND_ROBIN(1), .ARB_LSB_HIGH_PRIORITY(1) @@ -1955,8 +1958,8 @@ cpl_write #( .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), - .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), + .REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH), + .QUEUE_REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), .CPL_SIZE(CPL_SIZE), @@ -2402,8 +2405,7 @@ mqnic_interface_tx #( .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), .REQ_TAG_WIDTH(REQ_TAG_WIDTH), .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), - .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), - .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), + .CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), @@ -2591,8 +2593,7 @@ mqnic_interface_rx #( .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), - .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), - .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), + .CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH), // TX and RX engine configuration .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_interface_rx.v b/fpga/common/rtl/mqnic_interface_rx.v index 859e8124d..b58c05ab4 100644 --- a/fpga/common/rtl/mqnic_interface_rx.v +++ b/fpga/common/rtl/mqnic_interface_rx.v @@ -65,8 +65,7 @@ module mqnic_interface_rx # parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8, parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8, parameter DESC_REQ_TAG_WIDTH = 8, - parameter QUEUE_REQ_TAG_WIDTH = 8, - parameter QUEUE_OP_TAG_WIDTH = 8, + parameter CPL_REQ_TAG_WIDTH = 8, // TX and RX engine configuration parameter RX_DESC_TABLE_SIZE = 32, @@ -158,7 +157,7 @@ module mqnic_interface_rx # * Completion request output */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, - output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, + output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, output wire m_axis_cpl_req_valid, input wire m_axis_cpl_req_ready, @@ -166,7 +165,7 @@ module mqnic_interface_rx # /* * Completion request status input */ - input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, + input wire [CPL_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, input wire s_axis_cpl_req_status_full, input wire s_axis_cpl_req_status_error, input wire s_axis_cpl_req_status_valid, @@ -341,10 +340,9 @@ rx_engine #( .DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), .REQ_TAG_WIDTH(REQ_TAG_WIDTH), .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), + .CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), .DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH), - .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), - .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), diff --git a/fpga/common/rtl/mqnic_interface_tx.v b/fpga/common/rtl/mqnic_interface_tx.v index 2047c872a..7b10b35d2 100644 --- a/fpga/common/rtl/mqnic_interface_tx.v +++ b/fpga/common/rtl/mqnic_interface_tx.v @@ -66,8 +66,7 @@ module mqnic_interface_tx # parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8, parameter REQ_TAG_WIDTH = 8, parameter DESC_REQ_TAG_WIDTH = 8, - parameter QUEUE_REQ_TAG_WIDTH = 8, - parameter QUEUE_OP_TAG_WIDTH = 8, + parameter CPL_REQ_TAG_WIDTH = 8, // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -152,7 +151,7 @@ module mqnic_interface_tx # * Completion request output */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, - output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, + output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, output wire m_axis_cpl_req_valid, input wire m_axis_cpl_req_ready, @@ -160,7 +159,7 @@ module mqnic_interface_tx # /* * Completion request status input */ - input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, + input wire [CPL_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, input wire s_axis_cpl_req_status_full, input wire s_axis_cpl_req_status_error, input wire s_axis_cpl_req_status_valid, @@ -297,10 +296,9 @@ tx_engine #( .DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), .REQ_TAG_WIDTH(REQ_TAG_WIDTH), .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), + .CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), .DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH), - .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), - .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), diff --git a/fpga/common/rtl/rx_engine.v b/fpga/common/rtl/rx_engine.v index 4f2a58b99..9c71daa31 100644 --- a/fpga/common/rtl/rx_engine.v +++ b/fpga/common/rtl/rx_engine.v @@ -66,14 +66,12 @@ module rx_engine # parameter REQ_TAG_WIDTH = 8, // Descriptor request tag field width parameter DESC_REQ_TAG_WIDTH = 8, + // Completion request tag field width + parameter CPL_REQ_TAG_WIDTH = 8, // DMA tag field width parameter DMA_TAG_WIDTH = 8, // DMA client tag field width parameter DMA_CLIENT_TAG_WIDTH = 8, - // Queue request tag field width - parameter QUEUE_REQ_TAG_WIDTH = 8, - // Queue operation tag field width - parameter QUEUE_OP_TAG_WIDTH = 8, // Queue index width parameter QUEUE_INDEX_WIDTH = 4, // Queue element pointer width @@ -184,7 +182,7 @@ module rx_engine # * Completion request output */ output wire [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, - output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, + output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, output wire m_axis_cpl_req_valid, input wire m_axis_cpl_req_ready, @@ -192,7 +190,7 @@ module rx_engine # /* * Completion request status input */ - input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, + input wire [CPL_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, input wire s_axis_cpl_req_status_full, input wire s_axis_cpl_req_status_error, input wire s_axis_cpl_req_status_valid, @@ -279,13 +277,13 @@ initial begin $finish; end - if (QUEUE_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin - $error("Error: QUEUE_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)"); + if (DESC_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin + $error("Error: DESC_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)"); $finish; end - if (DESC_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin - $error("Error: DESC_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)"); + if (CPL_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin + $error("Error: CPL_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)"); $finish; end @@ -308,7 +306,7 @@ reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next; reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next; reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next; -reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next; +reg [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {CPL_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next; reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next; reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next; diff --git a/fpga/common/rtl/tx_engine.v b/fpga/common/rtl/tx_engine.v index 1ccb9adb0..74ad20335 100644 --- a/fpga/common/rtl/tx_engine.v +++ b/fpga/common/rtl/tx_engine.v @@ -56,14 +56,12 @@ module tx_engine # parameter REQ_TAG_WIDTH = 8, // Descriptor request tag field width parameter DESC_REQ_TAG_WIDTH = 8, + // Completion request tag field width + parameter CPL_REQ_TAG_WIDTH = 8, // DMA tag field width parameter DMA_TAG_WIDTH = 8, // DMA client tag field width parameter DMA_CLIENT_TAG_WIDTH = 8, - // Queue request tag field width - parameter QUEUE_REQ_TAG_WIDTH = 8, - // Queue operation tag field width - parameter QUEUE_OP_TAG_WIDTH = 8, // Queue index width parameter QUEUE_INDEX_WIDTH = 4, // Queue element pointer width @@ -161,7 +159,7 @@ module tx_engine # * Completion request output */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, - output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, + output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, output wire m_axis_cpl_req_valid, input wire m_axis_cpl_req_ready, @@ -169,7 +167,7 @@ module tx_engine # /* * Completion request status input */ - input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, + input wire [CPL_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, input wire s_axis_cpl_req_status_full, input wire s_axis_cpl_req_status_error, input wire s_axis_cpl_req_status_valid, @@ -256,18 +254,13 @@ initial begin $finish; end - if (QUEUE_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin - $error("Error: QUEUE_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)"); + if (DESC_REQ_TAG_WIDTH < REQ_TAG_WIDTH) begin + $error("Error: DESC_REQ_TAG_WIDTH must be at least REQ_TAG_WIDTH (instance %m)"); $finish; end - if (DESC_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin - $error("Error: DESC_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)"); - $finish; - end - - if (QUEUE_REQ_TAG_WIDTH < REQ_TAG_WIDTH) begin - $error("Error: QUEUE_REQ_TAG_WIDTH must be at least REQ_TAG_WIDTH (instance %m)"); + if (CPL_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin + $error("Error: CPL_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)"); $finish; end @@ -295,7 +288,7 @@ reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next; reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next; reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next; -reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next; +reg [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {CPL_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next; reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next; reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next;