diff --git a/README.md b/README.md index 6def17258..c90805824 100644 --- a/README.md +++ b/README.md @@ -30,6 +30,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * NetFPGA SUME (Xilinx Virtex 7 XC7V690T) * BittWare 250-SoC (Xilinx Zynq UltraScale+ XCZU19EG) +* BittWare XUSP3S (Xilinx Virtex UltraScale XCVU095) * BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P) * Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100) * Intel Stratix 10 DX dev kit (Intel Stratix 10 DX 2800) diff --git a/docs/source/devicelist.rst b/docs/source/devicelist.rst index 812bdf32b..0e7673875 100644 --- a/docs/source/devicelist.rst +++ b/docs/source/devicelist.rst @@ -23,6 +23,7 @@ This section details PCIe form-factor targets, which interface with a separate h Cisco Nexus K3P-Q XCKU3P-2FFVB676E 0x1ce4000a Silicom fb2CG\@KU15P XCKU15P-2FFVE1760E 0x1c2ca00e Digilent NetFPGA SUME XC7V690T-3FFG1761 0x10ee7028 + BittWare XUSP3S XCVU095-2FFVB2104E 0x12ba8823 BittWare XUP-P3R XCVU9P-2FLGB2104E 0x12ba9823 BittWare 250-SoC XCZU19EG-2FFVD1760E 0x198a250e Intel DK-DEV-1SMX-H-A 1SM21BHU2F53E1VG 0x11720001 @@ -53,6 +54,7 @@ This section details PCIe form-factor targets, which interface with a separate h fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2666 (4x 512M x72) \- NetFPGA SUME Gen 3 x8 4x SFP+ 8 GB DDR3 1866 (2x 512M x64) \- 250-SoC Gen 3 x16 2x QSFP28 4 GB DDR4 2666 (512M x72) \- + XUSP3S Gen 3 x8 4x QSFP28 2x 4GB DDR4 512M x72, 2x SODIMM \- XUP-P3R Gen 3 x16 4x QSFP28 4x DDR4 2400 DIMM (4x x72) \- DK-DEV-1SMX-H-A Gen 3 x16 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 8 GB DK-DEV-1SMC-H-A Gen 3 x16 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 16 GB @@ -82,6 +84,7 @@ This section details PCIe form-factor targets, which interface with a separate h fb2CG\@KU15P Y Y Y NetFPGA SUME Y N :sup:`7` N :sup:`8` 250-SoC Y N N :sup:`9` + XUSP3S Y Y Y XUP-P3R Y Y Y DK-DEV-1SMX-H-A Y N :sup:`7` N DK-DEV-1SMC-H-A Y N :sup:`7` N @@ -135,6 +138,8 @@ This section details PCIe form-factor targets, which interface with a separate h 250-SoC mqnic/fpga_25g/fpga 2x1 256/8K 25G Y RR 250-SoC mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G Y RR 250-SoC mqnic/fpga_100g/fpga 2x1 256/8K 100G Y RR + XUSP3S mqnic/fpga_25g/fpga 2x1 256/512 25G Y RR + XUSP3S mqnic/fpga_25g/fpga_10g 2x1 256/512 10G Y RR XUP-P3R mqnic/fpga_25g/fpga 4x1 256/8K 25G Y RR XUP-P3R mqnic/fpga_25g/fpga_10g 4x1 256/8K 10G Y RR XUP-P3R mqnic/fpga_100g/fpga 4x1 256/8K 100G Y RR diff --git a/docs/source/index.rst b/docs/source/index.rst index 069a50b5f..91b94c792 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -22,6 +22,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s * Silicom fb2CG\@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * NetFPGA SUME (Xilinx Virtex 7 XC7V690T) * BittWare 250-SoC (Xilinx Zynq UltraScale+ XCZU19EG) +* BittWare XUSP3S (Xilinx Virtex UltraScale+ XCVU095) * BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P) * Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100) * Intel Stratix 10 DX dev kit (Intel Stratix 10 DX 2800) diff --git a/fpga/mqnic/XUSP3S/fpga_25g/README.md b/fpga/mqnic/XUSP3S/fpga_25g/README.md new file mode 100644 index 000000000..e45bc8a8a --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/README.md @@ -0,0 +1,23 @@ +# Corundum mqnic for XUSP3S + +## Introduction + +This design targets the BittWare XUSP3S FPGA board. + +* FPGA: xcvu095-ffvb2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* RAM: 8 GB DDR4 2400 (2x 512M x72) + 2x SODIMM + +## Quick start + +### Build FPGA bitstream + +Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. + +### Build driver and userspace tools + +On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. + +### Testing + +Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/XUSP3S/fpga_25g/app b/fpga/mqnic/XUSP3S/fpga_25g/app new file mode 120000 index 000000000..4d46690fb --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/app @@ -0,0 +1 @@ +../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/XUSP3S/fpga_25g/boot.xdc b/fpga/mqnic/XUSP3S/fpga_25g/boot.xdc new file mode 100644 index 000000000..5fb323e94 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/boot.xdc @@ -0,0 +1,4 @@ +# Timing constraints for FPGA boot logic + +set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] +set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/common/vivado.mk b/fpga/mqnic/XUSP3S/fpga_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga.xdc b/fpga/mqnic/XUSP3S/fpga_25g/fpga.xdc new file mode 100644 index 000000000..1ce87ae51 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga.xdc @@ -0,0 +1,894 @@ +# XDC constraints for the BittWare XUSP3S board +# part: xcvu095-ffvb2104-2-e + +# General configuration +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 90 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# 48 MHz system clock +set_property -dict {LOC AV23 IOSTANDARD LVCMOS33} [get_ports clk_48mhz] +create_clock -period 20.833 -name clk_48mhz [get_ports clk_48mhz] + +# 322.265625 MHz clock from Si5338 B ch 1 +#set_property -dict {LOC AY23 IOSTANDARD LVPECL} [get_ports clk_b1_p] +#set_property -dict {LOC BA23 IOSTANDARD LVPECL} [get_ports clk_b1_n] +#create_clock -period 3.103 -name clk_b1 [get_ports clk_b1_p] + +# 322.265625 MHz clock from Si5338 B ch 2 +#set_property -dict {LOC BB9 IOSTANDARD DIFF_SSTL15_DCI ODT RTT_48} [get_ports clk_b2_p] +#set_property -dict {LOC BC9 IOSTANDARD DIFF_SSTL15_DCI ODT RTT_48} [get_ports clk_b2_n] +#create_clock -period 3.103 -name clk_b2 [get_ports clk_b2_p] + +# 100 MHz DDR4 SODIMM 1 clock from Si5338 A ch 0 +set_property -dict {LOC AV18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_sodimm1_p] +set_property -dict {LOC AW18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_sodimm1_n] +#create_clock -period 10.000 -name clk_ddr_sodimm1 [get_ports clk_ddr_sodimm1_p] + +# 100 MHz DDR4 A clock from Si5338 A ch 1 +set_property -dict {LOC BB36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_a_p] +set_property -dict {LOC BC36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_a_n] +#create_clock -period 10.000 -name clk_ddr_a [get_ports clk_ddr_a_p] + +# 100 MHz DDR4 B clock from Si5338 A ch 2 +set_property -dict {LOC E38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_b_p] +set_property -dict {LOC D38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_b_n] +#create_clock -period 10.000 -name clk_ddr_b [get_ports clk_ddr_b_p] + +# 100 MHz DDR4 SODIMM 2 clock from Si5338 A ch 3 +set_property -dict {LOC K18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_sodimm2_p] +set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_sodimm2_n] +#create_clock -period 10.000 -name clk_ddr_sodimm2 [get_ports clk_ddr_sodimm2_p] + +# LEDs +set_property -dict {LOC AR22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC AT22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC AR23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[2]}] +set_property -dict {LOC AV22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[3]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Timing +set_property -dict {LOC AU22 IOSTANDARD LVCMOS33} [get_ports ext_pps_in] ;# from J1 +set_property -dict {LOC AV24 IOSTANDARD LVCMOS33} [get_ports ext_clk_in] ;# from J2 + +create_clock -period 100.000 -name ext_clk_in [get_ports ext_clk_in] + +set_false_path -from [get_ports {ext_pps_in ext_clk_in}] +set_input_delay 0 [get_ports {ext_pps_in ext_clk_in}] + +# Reset +#set_property -dict {LOC AT23 IOSTANDARD LVCMOS33} [get_ports sys_rst_l] + +#set_false_path -from [get_ports {sys_rst_l}] +#set_input_delay 0 [get_ports {sys_rst_l}] + +# UART +#set_property -dict {LOC AM24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd] +#set_property -dict {LOC AL24 IOSTANDARD LVCMOS33} [get_ports uart_rxd] + +#set_false_path -to [get_ports {uart_txd}] +#set_output_delay 0 [get_ports {uart_txd}] +#set_false_path -from [get_ports {uart_rxd}] +#set_input_delay 0 [get_ports {uart_rxd}] + +# EEPROM I2C interface +set_property -dict {LOC AN24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports eeprom_i2c_scl] +set_property -dict {LOC AP23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports eeprom_i2c_sda] + +set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] +set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] +set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] +set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] + +# I2C-related signals +set_property -dict {LOC AT24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_i2c_master_l] +set_property -dict {LOC AN23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_ctl_en] + +set_false_path -to [get_ports {fpga_i2c_master_l qsfp_ctl_en}] +set_output_delay 0 [get_ports {fpga_i2c_master_l qsfp_ctl_en}] + +# QSFP28 Interfaces +set_property -dict {LOC BC45} [get_ports qsfp0_rx1_p] ;# MGTHRXP0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BC46} [get_ports qsfp0_rx1_n] ;# MGTHRXN0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BF42} [get_ports qsfp0_tx1_p] ;# MGTHTXP0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BF43} [get_ports qsfp0_tx1_n] ;# MGTHTXN0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA45} [get_ports qsfp0_rx2_p] ;# MGTHRXP1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA46} [get_ports qsfp0_rx2_n] ;# MGTHRXN1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD42} [get_ports qsfp0_tx2_p] ;# MGTHTXP1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD43} [get_ports qsfp0_tx2_n] ;# MGTHTXN1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW45} [get_ports qsfp0_rx3_p] ;# MGTHRXP2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW46} [get_ports qsfp0_rx3_n] ;# MGTHRXN2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB42} [get_ports qsfp0_tx3_p] ;# MGTHTXP2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB43} [get_ports qsfp0_tx3_n] ;# MGTHTXN2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV43} [get_ports qsfp0_rx4_p] ;# MGTHRXP3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV44} [get_ports qsfp0_rx4_n] ;# MGTHRXN3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW40} [get_ports qsfp0_tx4_p] ;# MGTHTXP3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW41} [get_ports qsfp0_tx4_n] ;# MGTHTXN3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA40} [get_ports qsfp0_mgt_refclk_b0_p] ;# MGTREFCLK0P_124 from Si5338 B ch 0 +set_property -dict {LOC BA41} [get_ports qsfp0_mgt_refclk_b0_n] ;# MGTREFCLK0N_124 from Si5338 B ch 0 +#set_property -dict {LOC AY38} [get_ports qsfp0_mgt_refclk_b1_p] ;# MGTREFCLK1P_124 from Si5338 B ch 1 +#set_property -dict {LOC AY39} [get_ports qsfp0_mgt_refclk_b1_n] ;# MGTREFCLK1N_124 from Si5338 B ch 1 +set_property -dict {LOC BD24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] +set_property -dict {LOC BD23 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp0_modprsl] +set_property -dict {LOC BE23 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp0_intl] +set_property -dict {LOC BC24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] +set_property -dict {LOC BF24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl] +set_property -dict {LOC BF23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda] + +# 322.265625 MHz MGT reference clock (from Si5338 B ch 0) +create_clock -period 3.103 -name qsfp0_mgt_refclk_b0 [get_ports qsfp0_mgt_refclk_b0_p] + +# 322.265625 MHz MGT reference clock (from Si5338 B ch 1) +#create_clock -period 3.103 -name qsfp0_mgt_refclk_b1 [get_ports qsfp0_mgt_refclk_b1_p] + +set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}] +set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}] +set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] +set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] + +set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}] +set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}] +set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}] +set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}] + +set_property -dict {LOC AN45} [get_ports qsfp1_rx1_p] ;# MGTHRXP0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN46} [get_ports qsfp1_rx1_n] ;# MGTHRXN0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN40} [get_ports qsfp1_tx1_p] ;# MGTHTXP0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN41} [get_ports qsfp1_tx1_n] ;# MGTHTXN0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM43} [get_ports qsfp1_rx2_p] ;# MGTHRXP1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM44} [get_ports qsfp1_rx2_n] ;# MGTHRXN1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM38} [get_ports qsfp1_tx2_p] ;# MGTHTXP1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM39} [get_ports qsfp1_tx2_n] ;# MGTHTXN1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL45} [get_ports qsfp1_rx3_p] ;# MGTHRXP2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL46} [get_ports qsfp1_rx3_n] ;# MGTHRXN2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL40} [get_ports qsfp1_tx3_p] ;# MGTHTXP2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL41} [get_ports qsfp1_tx3_n] ;# MGTHTXN2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK43} [get_ports qsfp1_rx4_p] ;# MGTHRXP3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK44} [get_ports qsfp1_rx4_n] ;# MGTHRXN3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK38} [get_ports qsfp1_tx4_p] ;# MGTHTXP3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK39} [get_ports qsfp1_tx4_n] ;# MGTHTXN3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AR36} [get_ports qsfp1_mgt_refclk_b0_p] ;# MGTREFCLK0P_126 from Si5338 B ch 0 +set_property -dict {LOC AR37} [get_ports qsfp1_mgt_refclk_b0_n] ;# MGTREFCLK0N_126 from Si5338 B ch 0 +#set_property -dict {LOC AN36} [get_ports qsfp1_mgt_refclk_b1_p] ;# MGTREFCLK1P_126 from Si5338 B ch 1 +#set_property -dict {LOC AN37} [get_ports qsfp1_mgt_refclk_b1_n] ;# MGTREFCLK1N_126 from Si5338 B ch 1 +set_property -dict {LOC BE20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] +set_property -dict {LOC BD21 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp1_modprsl] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp1_intl] +set_property -dict {LOC BD20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] +set_property -dict {LOC BE22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl] +set_property -dict {LOC BF22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda] + +# 322.265625 MHz MGT reference clock (from Si5338 B ch 0) +create_clock -period 3.103 -name qsfp1_mgt_refclk_b0 [get_ports qsfp1_mgt_refclk_b0_p] + +# 322.265625 MHz MGT reference clock (from Si5338 B ch 1) +#create_clock -period 3.103 -name qsfp1_mgt_refclk_b1 [get_ports qsfp1_mgt_refclk_b1_p] + +set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}] +set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}] +set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] +set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] + +set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}] +set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}] +set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}] +set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}] + +set_property -dict {LOC AA45} [get_ports qsfp2_rx1_p] ;# MGTHRXP0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA46} [get_ports qsfp2_rx1_n] ;# MGTHRXN0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA40} [get_ports qsfp2_tx1_p] ;# MGTHTXP0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA41} [get_ports qsfp2_tx1_n] ;# MGTHTXN0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y43 } [get_ports qsfp2_rx2_p] ;# MGTHRXP1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y44 } [get_ports qsfp2_rx2_n] ;# MGTHRXN1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y38 } [get_ports qsfp2_tx2_p] ;# MGTHTXP1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y39 } [get_ports qsfp2_tx2_n] ;# MGTHTXN1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W45 } [get_ports qsfp2_rx3_p] ;# MGTHRXP2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W46 } [get_ports qsfp2_rx3_n] ;# MGTHRXN2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W40 } [get_ports qsfp2_tx3_p] ;# MGTHTXP2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W41 } [get_ports qsfp2_tx3_n] ;# MGTHTXN2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V43 } [get_ports qsfp2_rx4_p] ;# MGTHRXP3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V44 } [get_ports qsfp2_rx4_n] ;# MGTHRXN3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V38 } [get_ports qsfp2_tx4_p] ;# MGTHTXP3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V39 } [get_ports qsfp2_tx4_n] ;# MGTHTXN3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AC36} [get_ports qsfp2_mgt_refclk_b0_p] ;# MGTREFCLK0P_129 from Si5338 B ch 0 +set_property -dict {LOC AC37} [get_ports qsfp2_mgt_refclk_b0_n] ;# MGTREFCLK0N_129 from Si5338 B ch 0 +#set_property -dict {LOC AA36} [get_ports qsfp2_mgt_refclk_b2_p] ;# MGTREFCLK1P_129 from Si5338 B ch 2 +#set_property -dict {LOC AA37} [get_ports qsfp2_mgt_refclk_b2_n] ;# MGTREFCLK1N_129 from Si5338 B ch 2 +set_property -dict {LOC BB22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp2_resetl] +set_property -dict {LOC BB20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp2_modprsl] +set_property -dict {LOC BB21 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp2_intl] +set_property -dict {LOC BC21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode] +set_property -dict {LOC BF20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp2_i2c_scl] +set_property -dict {LOC BA20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp2_i2c_sda] + +# 322.265625 MHz MGT reference clock (from Si5338 B ch 0) +create_clock -period 3.103 -name qsfp2_mgt_refclk_b0 [get_ports qsfp2_mgt_refclk_b0_p] + +# 322.265625 MHz MGT reference clock (from Si5338 B ch 2) +#create_clock -period 3.103 -name qsfp2_mgt_refclk_b2 [get_ports qsfp2_mgt_refclk_b2_p] + +set_false_path -to [get_ports {qsfp2_resetl qsfp2_lpmode}] +set_output_delay 0 [get_ports {qsfp2_resetl qsfp2_lpmode}] +set_false_path -from [get_ports {qsfp2_modprsl qsfp2_intl}] +set_input_delay 0 [get_ports {qsfp2_modprsl qsfp2_intl}] + +set_false_path -to [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}] +set_output_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}] +set_false_path -from [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}] +set_input_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}] + +set_property -dict {LOC N45 } [get_ports qsfp3_rx1_p] ;# MGTHRXP0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N46 } [get_ports qsfp3_rx1_n] ;# MGTHRXN0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N40 } [get_ports qsfp3_tx1_p] ;# MGTHTXP0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N41 } [get_ports qsfp3_tx1_n] ;# MGTHTXN0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M43 } [get_ports qsfp3_rx2_p] ;# MGTHRXP1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M44 } [get_ports qsfp3_rx2_n] ;# MGTHRXN1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M38 } [get_ports qsfp3_tx2_p] ;# MGTHTXP1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M39 } [get_ports qsfp3_tx2_n] ;# MGTHTXN1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L45 } [get_ports qsfp3_rx3_p] ;# MGTHRXP2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L46 } [get_ports qsfp3_rx3_n] ;# MGTHRXN2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L40 } [get_ports qsfp3_tx3_p] ;# MGTHTXP2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L41 } [get_ports qsfp3_tx3_n] ;# MGTHTXN2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K43 } [get_ports qsfp3_rx4_p] ;# MGTHRXP3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K44 } [get_ports qsfp3_rx4_n] ;# MGTHRXN3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J40 } [get_ports qsfp3_tx4_p] ;# MGTHTXP3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J41 } [get_ports qsfp3_tx4_n] ;# MGTHTXN3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC R36 } [get_ports qsfp3_mgt_refclk_b0_p] ;# MGTREFCLK0P_131 from Si5338 B ch 0 +set_property -dict {LOC R37 } [get_ports qsfp3_mgt_refclk_b0_n] ;# MGTREFCLK0N_131 from Si5338 B ch 0 +#set_property -dict {LOC N36 } [get_ports qsfp3_mgt_refclk_b3_p] ;# MGTREFCLK1P_131 from Si5338 B ch 3 +#set_property -dict {LOC N37 } [get_ports qsfp3_mgt_refclk_b3_n] ;# MGTREFCLK1N_131 from Si5338 B ch 3 +set_property -dict {LOC BC23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp3_resetl] +set_property -dict {LOC BB24 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp3_modprsl] +set_property -dict {LOC AY22 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp3_intl] +set_property -dict {LOC BA22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp3_lpmode] +set_property -dict {LOC BC22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp3_i2c_scl] +set_property -dict {LOC BA24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp3_i2c_sda] + +# 322.265625 MHz MGT reference clock (from Si5338 B ch 0) +create_clock -period 3.103 -name qsfp3_mgt_refclk_b0 [get_ports qsfp3_mgt_refclk_b0_p] + +# 322.265625 MHz MGT reference clock (from Si5338 B ch 2) +#create_clock -period 3.103 -name qsfp3_mgt_refclk_b3 [get_ports qsfp3_mgt_refclk_b3_p] + +set_false_path -to [get_ports {qsfp3_resetl qsfp3_lpmode}] +set_output_delay 0 [get_ports {qsfp3_resetl qsfp3_lpmode}] +set_false_path -from [get_ports {qsfp3_modprsl qsfp3_intl}] +set_input_delay 0 [get_ports {qsfp3_modprsl qsfp3_intl}] + +set_false_path -to [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}] +set_output_delay 0 [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}] +set_false_path -from [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}] +set_input_delay 0 [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}] + +# PCIe Interface +set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTHRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTHRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTHTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTHTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTHRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTHRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTHTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTHTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AT11 } [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_225 +set_property -dict {LOC AT10 } [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_225 +#set_property -dict {LOC AM11 } [get_ports pcie_refclk_b1_p] ;# MGTREFCLK0P_226 from Si5338 B ch 1 +#set_property -dict {LOC AM10 } [get_ports pcie_refclk_b1_n] ;# MGTREFCLK0N_226 from Si5338 B ch 1 +#set_property -dict {LOC AH11 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227 +#set_property -dict {LOC AH10 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227 +set_property -dict {LOC AR26 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p] +#create_clock -period 10 -name pcie_mgt_refclk_b1 [get_ports pcie_refclk_b1_p] +#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] + +set_false_path -from [get_ports {pcie_reset_n}] +set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 A (U5, U6, U7, U8, U9, U32, U33, U34, U35) +# 9x MT40A512M8RH-083E +set_property -dict {LOC AY33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[0]}] +set_property -dict {LOC BA33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[1]}] +set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[2]}] +set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[3]}] +set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[4]}] +set_property -dict {LOC AW33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[5]}] +set_property -dict {LOC AU34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[6]}] +set_property -dict {LOC AT33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[7]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[8]}] +set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[9]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[10]}] +set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[11]}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[12]}] +set_property -dict {LOC AL32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[13]}] +set_property -dict {LOC AM32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[14]}] +set_property -dict {LOC AL34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[15]}] +set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[16]}] +set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_ba[0]}] +set_property -dict {LOC BB34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_ba[1]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_bg[0]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_bg[1]}] +set_property -dict {LOC AW35 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_a_ck_t[0]}] +set_property -dict {LOC AW36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_a_ck_c[0]}] +set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_cke[0]}] +set_property -dict {LOC BE35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_cs_n[0]}] +set_property -dict {LOC BF35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_act_n}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_odt[0]}] +set_property -dict {LOC BB35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_par}] +set_property -dict {LOC BC34 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_a_reset_n}] + +set_property -dict {LOC W34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[0]}] +set_property -dict {LOC W33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[1]}] +set_property -dict {LOC Y33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[2]}] +set_property -dict {LOC Y32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[3]}] +set_property -dict {LOC Y30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[4]}] +set_property -dict {LOC W30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[5]}] +set_property -dict {LOC AB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[6]}] +set_property -dict {LOC AA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[7]}] +set_property -dict {LOC AD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[8]}] +set_property -dict {LOC AC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[9]}] +set_property -dict {LOC AC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[10]}] +set_property -dict {LOC AC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[11]}] +set_property -dict {LOC AF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[12]}] +set_property -dict {LOC AE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[13]}] +set_property -dict {LOC AE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[14]}] +set_property -dict {LOC AD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[15]}] +set_property -dict {LOC AF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[16]}] +set_property -dict {LOC AF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[17]}] +set_property -dict {LOC AG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[18]}] +set_property -dict {LOC AG31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[19]}] +set_property -dict {LOC AG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[20]}] +set_property -dict {LOC AF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[21]}] +set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[22]}] +set_property -dict {LOC AH33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[23]}] +set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[24]}] +set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[25]}] +set_property -dict {LOC AG30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[26]}] +set_property -dict {LOC AG29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[27]}] +set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[28]}] +set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[29]}] +set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[30]}] +set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[32]}] +set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[33]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[34]}] +set_property -dict {LOC AM31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[35]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[36]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[37]}] +set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[38]}] +set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[39]}] +set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[40]}] +set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[41]}] +set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[42]}] +set_property -dict {LOC AU30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[43]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[44]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[45]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[46]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[47]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[48]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[49]}] +set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[50]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[51]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[52]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[53]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[54]}] +set_property -dict {LOC BB30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[55]}] +set_property -dict {LOC BD29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[56]}] +set_property -dict {LOC BC29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[58]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[59]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[60]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[61]}] +set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[62]}] +set_property -dict {LOC BE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[63]}] +set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[64]}] +set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[65]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[66]}] +set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[69]}] +set_property -dict {LOC BF38 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[70]}] +set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[71]}] +set_property -dict {LOC W31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[0]}] +set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[0]}] +set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[1]}] +set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[1]}] +set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[2]}] +set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[2]}] +set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[3]}] +set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[3]}] +set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[4]}] +set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[4]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[5]}] +set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[5]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[6]}] +set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[6]}] +set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[7]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[7]}] +set_property -dict {LOC BD40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[8]}] +set_property -dict {LOC BE40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[8]}] +set_property -dict {LOC AA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[0]}] +set_property -dict {LOC AE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[1]}] +set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[2]}] +set_property -dict {LOC AJ27 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[3]}] +set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[4]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[5]}] +set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[6]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[7]}] +set_property -dict {LOC BF39 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[8]}] + +# DDR4 B (U22, U23, U24, U25, U26, U79, U80, U81, U82) +# 9x MT40A512M8RH-083E +set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[0]}] +set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[2]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[3]}] +set_property -dict {LOC E35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[4]}] +set_property -dict {LOC D35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[5]}] +set_property -dict {LOC E37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[6]}] +set_property -dict {LOC B34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[7]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[8]}] +set_property -dict {LOC D34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[9]}] +set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[10]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[11]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[12]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[13]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[14]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[15]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[16]}] +set_property -dict {LOC C36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_ba[0]}] +set_property -dict {LOC C37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_ba[1]}] +set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_bg[0]}] +set_property -dict {LOC D36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_bg[1]}] +set_property -dict {LOC B36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_b_ck_t[0]}] +set_property -dict {LOC B37 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_b_ck_c[0]}] +set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_cke[0]}] +set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_cs_n[0]}] +set_property -dict {LOC F38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_act_n}] +set_property -dict {LOC A39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_odt[0]}] +set_property -dict {LOC C39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_par}] +set_property -dict {LOC E40 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_b_reset_n}] + +set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[0]}] +set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[1]}] +set_property -dict {LOC E32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[2]}] +set_property -dict {LOC F32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[3]}] +set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[4]}] +set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[5]}] +set_property -dict {LOC G31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[6]}] +set_property -dict {LOC H31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[7]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[8]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[9]}] +set_property -dict {LOC J31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[10]}] +set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[11]}] +set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[12]}] +set_property -dict {LOC M30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[13]}] +set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[14]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[15]}] +set_property -dict {LOC N33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[16]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[17]}] +set_property -dict {LOC N31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[18]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[19]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[20]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[21]}] +set_property -dict {LOC R32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[22]}] +set_property -dict {LOC R31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[23]}] +set_property -dict {LOC T30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[24]}] +set_property -dict {LOC U30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[25]}] +set_property -dict {LOC U31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[26]}] +set_property -dict {LOC V31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[27]}] +set_property -dict {LOC T32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[28]}] +set_property -dict {LOC U32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[29]}] +set_property -dict {LOC R33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[30]}] +set_property -dict {LOC T33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[31]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[32]}] +set_property -dict {LOC B30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[33]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[34]}] +set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[35]}] +set_property -dict {LOC D30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[36]}] +set_property -dict {LOC E30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[37]}] +set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[38]}] +set_property -dict {LOC D29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[39]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[40]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[41]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[42]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[43]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[44]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[45]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[46]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[47]}] +set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[48]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[49]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[50]}] +set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[51]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[52]}] +set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[53]}] +set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[54]}] +set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[55]}] +set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[56]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[57]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[58]}] +set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[59]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[60]}] +set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[61]}] +set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[62]}] +set_property -dict {LOC T27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[63]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[64]}] +set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[65]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[66]}] +set_property -dict {LOC H34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[67]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[68]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[69]}] +set_property -dict {LOC F37 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[70]}] +set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[71]}] +set_property -dict {LOC J33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[0]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[0]}] +set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[1]}] +set_property -dict {LOC J30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[1]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[2]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[2]}] +set_property -dict {LOC V32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[3]}] +set_property -dict {LOC V33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[3]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[4]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[4]}] +set_property -dict {LOC F28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[5]}] +set_property -dict {LOC F29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[5]}] +set_property -dict {LOC K26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[6]}] +set_property -dict {LOC K27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[6]}] +set_property -dict {LOC P29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[7]}] +set_property -dict {LOC N29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[7]}] +set_property -dict {LOC H36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[8]}] +set_property -dict {LOC G36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[8]}] +set_property -dict {LOC G30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[0]}] +set_property -dict {LOC M31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[1]}] +set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[2]}] +set_property -dict {LOC U34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[3]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[4]}] +set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[5]}] +set_property -dict {LOC M29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[6]}] +set_property -dict {LOC T28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[7]}] +set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[8]}] + +# DDR4 SODIMM 1 +set_property -dict {LOC AT18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[0]}] +set_property -dict {LOC AU17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[1]}] +set_property -dict {LOC AP18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[2]}] +set_property -dict {LOC AR18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[3]}] +set_property -dict {LOC AP20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[4]}] +set_property -dict {LOC AR20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[5]}] +set_property -dict {LOC AU21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[6]}] +set_property -dict {LOC AN18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[7]}] +set_property -dict {LOC AN17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[8]}] +set_property -dict {LOC AN19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[9]}] +set_property -dict {LOC AP19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[10]}] +set_property -dict {LOC AM16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[11]}] +set_property -dict {LOC AN16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[12]}] +set_property -dict {LOC AL19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[13]}] +set_property -dict {LOC AM19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[14]}] +set_property -dict {LOC AL20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[15]}] +set_property -dict {LOC AM20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[16]}] +set_property -dict {LOC AT19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_ba[0]}] +set_property -dict {LOC AU19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_ba[1]}] +set_property -dict {LOC AT20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_bg[0]}] +set_property -dict {LOC AU20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_bg[1]}] +set_property -dict {LOC AR17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm1_ck_t[0]}] +set_property -dict {LOC AT17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm1_ck_c[0]}] +#set_property -dict {LOC AM17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm1_ck_t[1]}] +#set_property -dict {LOC AL17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm1_ck_c[1]}] +set_property -dict {LOC AY20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cke[0]}] +#set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cke[1]}] +set_property -dict {LOC BA18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cs_n[0]}] +#set_property -dict {LOC AW20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cs_n[1]}] +#set_property -dict {LOC AP16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cs_n[2]}] +#set_property -dict {LOC AY17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cs_n[3]}] +set_property -dict {LOC AV17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_act_n}] +set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_odt[0]}] +#set_property -dict {LOC AV19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_odt[1]}] +set_property -dict {LOC AW19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_par}] +set_property -dict {LOC BA17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_sodimm1_reset_n}] +set_property -dict {LOC AY18 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm1_alert_n}] + +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[0]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[1]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[2]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[3]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[4]}] +set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[5]}] +set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[6]}] +set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[7]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[8]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[9]}] +set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[10]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[11]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[12]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[13]}] +set_property -dict {LOC AW15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[14]}] +set_property -dict {LOC AW16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[15]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[16]}] +set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[17]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[18]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[19]}] +set_property -dict {LOC AY15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[20]}] +set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[21]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[22]}] +set_property -dict {LOC AY12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[23]}] +set_property -dict {LOC BC13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[24]}] +set_property -dict {LOC BC14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[25]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[26]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[27]}] +set_property -dict {LOC BE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[28]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[29]}] +set_property -dict {LOC BF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[30]}] +set_property -dict {LOC BE15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[31]}] +set_property -dict {LOC AL28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[32]}] +set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[33]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[34]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[35]}] +set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[36]}] +set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[37]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[38]}] +set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[39]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[40]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[41]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[42]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[43]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[44]}] +set_property -dict {LOC AU26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[45]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[46]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[47]}] +set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[48]}] +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[49]}] +set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[50]}] +set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[51]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[52]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[53]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[54]}] +set_property -dict {LOC BB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[55]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[56]}] +set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[57]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[58]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[59]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[60]}] +set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[61]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[62]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[63]}] +#set_property -dict {LOC BC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[64]}] +#set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[65]}] +#set_property -dict {LOC BC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[66]}] +#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[67]}] +#set_property -dict {LOC BE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[68]}] +#set_property -dict {LOC BD18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[69]}] +#set_property -dict {LOC BF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[70]}] +#set_property -dict {LOC BF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[71]}] +set_property -dict {LOC AP13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[0]}] +set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[0]}] +set_property -dict {LOC AU14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[1]}] +set_property -dict {LOC AV14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[1]}] +set_property -dict {LOC BB15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[2]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[2]}] +set_property -dict {LOC BD13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[3]}] +set_property -dict {LOC BE13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[3]}] +set_property -dict {LOC AM26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[4]}] +set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[4]}] +set_property -dict {LOC AR25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[5]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[5]}] +set_property -dict {LOC AW25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[6]}] +set_property -dict {LOC AY25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[6]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[7]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[7]}] +#set_property -dict {LOC BC19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[8]}] +#set_property -dict {LOC BD19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[8]}] +set_property -dict {LOC AR16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[0]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[1]}] +set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[2]}] +set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[3]}] +set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[4]}] +set_property -dict {LOC AV26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[5]}] +set_property -dict {LOC BA25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[6]}] +set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[7]}] +#set_property -dict {LOC BE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[8]}] + +# DDR4 SODIMM 2 (J10) +set_property -dict {LOC F20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[0]}] +set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[1]}] +set_property -dict {LOC E21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[2]}] +set_property -dict {LOC E20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[3]}] +set_property -dict {LOC F18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[4]}] +set_property -dict {LOC F17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[5]}] +set_property -dict {LOC G21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[6]}] +set_property -dict {LOC D19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[7]}] +set_property -dict {LOC C19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[8]}] +set_property -dict {LOC D21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[9]}] +set_property -dict {LOC D20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[10]}] +set_property -dict {LOC C21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[11]}] +set_property -dict {LOC B21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[12]}] +set_property -dict {LOC B19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[13]}] +set_property -dict {LOC A19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[14]}] +set_property -dict {LOC B20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[15]}] +set_property -dict {LOC A20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[16]}] +set_property -dict {LOC H19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_ba[0]}] +set_property -dict {LOC H18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_ba[1]}] +set_property -dict {LOC G20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_bg[0]}] +set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_bg[1]}] +set_property -dict {LOC E18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm2_ck_t[0]}] +set_property -dict {LOC E17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm2_ck_c[0]}] +#set_property -dict {LOC C18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm2_ck_t[1]}] +#set_property -dict {LOC D18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm2_ck_c[1]}] +set_property -dict {LOC K20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cke[0]}] +#set_property -dict {LOC J21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cke[1]}] +set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cs_n[0]}] +#set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cs_n[1]}] +#set_property -dict {LOC A18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cs_n[2]}] +#set_property -dict {LOC L17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cs_n[3]}] +set_property -dict {LOC K21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_act_n}] +set_property -dict {LOC H21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_odt[0]}] +#set_property -dict {LOC J20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_odt[1]}] +set_property -dict {LOC J19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_par}] +set_property -dict {LOC K17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_sodimm2_reset_n}] +set_property -dict {LOC L19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm2_alert_n}] + +set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[0]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[1]}] +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[2]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[3]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[4]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[5]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[6]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[7]}] +set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[8]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[9]}] +set_property -dict {LOC D23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[10]}] +set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[11]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[12]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[13]}] +set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[14]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[15]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[16]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[17]}] +set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[18]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[19]}] +set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[20]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[21]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[22]}] +set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[23]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[24]}] +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[25]}] +set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[26]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[27]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[28]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[29]}] +set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[30]}] +set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[31]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[32]}] +set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[33]}] +set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[34]}] +set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[35]}] +set_property -dict {LOC A13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[36]}] +set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[37]}] +set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[38]}] +set_property -dict {LOC C14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[39]}] +set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[40]}] +set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[41]}] +set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[42]}] +set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[43]}] +set_property -dict {LOC E13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[44]}] +set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[45]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[46]}] +set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[47]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[48]}] +set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[49]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[50]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[51]}] +set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[52]}] +set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[53]}] +set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[54]}] +set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[55]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[56]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[57]}] +set_property -dict {LOC L14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[58]}] +set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[59]}] +set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[60]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[61]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[62]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[63]}] +#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[64]}] +#set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[65]}] +#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[66]}] +#set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[67]}] +#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[68]}] +#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[69]}] +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[70]}] +#set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[71]}] +set_property -dict {LOC A23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[0]}] +set_property -dict {LOC A22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[0]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[1]}] +set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[1]}] +set_property -dict {LOC K25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[2]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[2]}] +set_property -dict {LOC P24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[3]}] +set_property -dict {LOC N24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[3]}] +set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[4]}] +set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[4]}] +set_property -dict {LOC G17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[5]}] +set_property -dict {LOC G16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[5]}] +set_property -dict {LOC H17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[6]}] +set_property -dict {LOC H16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[6]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[7]}] +set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[7]}] +#set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[8]}] +#set_property -dict {LOC N19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[8]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[0]}] +set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[1]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[2]}] +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[3]}] +set_property -dict {LOC D13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[4]}] +set_property -dict {LOC G14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[5]}] +set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[6]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[7]}] +#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[8]}] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile new file mode 100644 index 000000000..49846b400 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile @@ -0,0 +1,268 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2019-2023 The Regents of the University of California + +# FPGA settings +FPGA_PART = xcvu095-ffvb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = VirtexUltrascale + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/common/mqnic_core_pcie_us.v +SYN_FILES += rtl/common/mqnic_core_pcie.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_port_tx.v +SYN_FILES += rtl/common/mqnic_port_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_rx_queue_map.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v +SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/rb_drp.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_pcie_if.v +SYN_FILES += rtl/common/stats_pcie_tlp.v +SYN_FILES += rtl/common/stats_dma_if_pcie.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v +SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v +SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += placement.xdc +XDC_FILES += boot.xdc +XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl +XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl +XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl + +# IP +IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gty.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_sodimm_0.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +%_fallback.bit: %.bit + echo "open_project $*.xpr" > generate_fallback_bit.tcl + echo "open_run impl_1" >> generate_fallback_bit.tcl + echo "startgroup" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl + echo "endgroup" >> generate_fallback_bit.tcl + echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl + echo "undo" >> generate_fallback_bit.tcl + echo "exit" >> generate_fallback_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl + mkdir -p rev + EXT=bit; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT"; + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +%_fallback.mcs %_fallback.prm: %_fallback.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl + echo "exit" >> generate_fallback_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \ + echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done; + +%_full.mcs %_full.prm: %_fallback.bit %.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl + echo "exit" >> generate_full_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \ + echo "Output: rev/$*_full_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + +flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm + echo "open_hw" > flash$*.tcl + echo "connect_hw_server" >> flash$*.tcl + echo "open_hw_target" >> flash$*.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl + echo "program_hw_devices [current_hw_device]" >> flash$*.tcl + echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl + echo "boot_hw_device [current_hw_device]" >> flash$*.tcl + echo "exit" >> flash$*.tcl + vivado -nojournal -nolog -mode batch -source flash$*.tcl + diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..1f974eb44 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga/config.tcl @@ -0,0 +1,308 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2021-2023 The Regents of the University of California + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x3842093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x12ba] +set board_device_id [expr 0x8823] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_vendor_id $board_vendor_id +set pcie_subsystem_device_id $board_device_id + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +dict set params TDMA_BER_ENABLE "0" + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +# Structural configuration +dict set params IF_COUNT "2" +dict set params PORTS_PER_IF "1" +dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] +dict set params PORT_MASK "0" + +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +dict set params PTP_CLOCK_PIPELINE "0" +dict set params PTP_CLOCK_CDC_PIPELINE "0" +dict set params PTP_PORT_CDC_PIPELINE "0" +dict set params PTP_PEROUT_ENABLE "0" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" +dict set params TX_QUEUE_INDEX_WIDTH "9" +dict set params RX_QUEUE_INDEX_WIDTH "8" +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] + +# TX and RX engine configuration +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] + +# Scheduler configuration +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Interface configuration +dict set params PTP_TS_ENABLE "0" +dict set params TX_CPL_FIFO_DEPTH "32" +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "0" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + +# Application block configuration +dict set params APP_ID "32'h00000000" +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# DMA interface configuration +dict set params DMA_IMM_ENABLE "0" +dict set params DMA_IMM_WIDTH "32" +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" + +# Interrupt configuration +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_WIDTH "32" +dict set params AXIL_CTRL_ADDR_WIDTH "24" + +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + +# Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] +dict set params AXIS_ETH_TX_PIPELINE "0" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" +dict set params AXIS_ETH_TX_TS_PIPELINE "0" +dict set params AXIS_ETH_RX_PIPELINE "0" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_PCIE_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + # components (DDR4 A, DDR4 B) + set ddr4 [get_ips ddr4_0] + + # performance-related configuration + set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4 + set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4 + set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4 + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] + + if {[dict get $params DDR_CH] > 2} { + # SO-DIMMs (DDR4 SODMM 1, DDR4 SODIMM 2) + set ddr4 [get_ips ddr4_sodimm_0] + + # performance-related configuration + set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4 + set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4 + set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4 + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]] + } +} + +# PCIe IP core settings +set pcie [get_ips pcie3_ultrascale_0] + +# Internal interface settings +dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] + +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +# set_property generic $param_list [current_fileset] +set_property generic $param_list [get_filesets sources_1] + +# set implementation strategy +set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..49846b400 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,268 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2019-2023 The Regents of the University of California + +# FPGA settings +FPGA_PART = xcvu095-ffvb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = VirtexUltrascale + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/common/mqnic_core_pcie_us.v +SYN_FILES += rtl/common/mqnic_core_pcie.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_port_tx.v +SYN_FILES += rtl/common/mqnic_port_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_rx_queue_map.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v +SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/rb_drp.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_pcie_if.v +SYN_FILES += rtl/common/stats_pcie_tlp.v +SYN_FILES += rtl/common/stats_dma_if_pcie.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v +SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v +SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += placement.xdc +XDC_FILES += boot.xdc +XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl +XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl +XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl + +# IP +IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gty.tcl +#IP_TCL_FILES += ip/ddr4_0.tcl +#IP_TCL_FILES += ip/ddr4_sodimm_0.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +%_fallback.bit: %.bit + echo "open_project $*.xpr" > generate_fallback_bit.tcl + echo "open_run impl_1" >> generate_fallback_bit.tcl + echo "startgroup" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl + echo "endgroup" >> generate_fallback_bit.tcl + echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl + echo "undo" >> generate_fallback_bit.tcl + echo "exit" >> generate_fallback_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl + mkdir -p rev + EXT=bit; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT"; + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +%_fallback.mcs %_fallback.prm: %_fallback.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl + echo "exit" >> generate_fallback_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \ + echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done; + +%_full.mcs %_full.prm: %_fallback.bit %.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl + echo "exit" >> generate_full_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \ + echo "Output: rev/$*_full_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + +flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm + echo "open_hw" > flash$*.tcl + echo "connect_hw_server" >> flash$*.tcl + echo "open_hw_target" >> flash$*.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl + echo "program_hw_devices [current_hw_device]" >> flash$*.tcl + echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl + echo "boot_hw_device [current_hw_device]" >> flash$*.tcl + echo "exit" >> flash$*.tcl + vivado -nojournal -nolog -mode batch -source flash$*.tcl + diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..13ed1bfd3 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,308 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2021-2023 The Regents of the University of California + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x3842093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x12ba] +set board_device_id [expr 0x8823] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_vendor_id $board_vendor_id +set pcie_subsystem_device_id $board_device_id + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +dict set params TDMA_BER_ENABLE "0" + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +# Structural configuration +dict set params IF_COUNT "2" +dict set params PORTS_PER_IF "1" +dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] +dict set params PORT_MASK "0" + +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +dict set params PTP_CLOCK_PIPELINE "0" +dict set params PTP_CLOCK_CDC_PIPELINE "0" +dict set params PTP_PORT_CDC_PIPELINE "0" +dict set params PTP_PEROUT_ENABLE "0" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" +dict set params TX_QUEUE_INDEX_WIDTH "9" +dict set params RX_QUEUE_INDEX_WIDTH "8" +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] + +# TX and RX engine configuration +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] + +# Scheduler configuration +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Interface configuration +dict set params PTP_TS_ENABLE "1" +dict set params TX_CPL_FIFO_DEPTH "32" +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "0" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + +# Application block configuration +dict set params APP_ID "32'h00000000" +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# DMA interface configuration +dict set params DMA_IMM_ENABLE "0" +dict set params DMA_IMM_WIDTH "32" +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" + +# Interrupt configuration +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_WIDTH "32" +dict set params AXIL_CTRL_ADDR_WIDTH "24" + +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + +# Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] +dict set params AXIS_ETH_TX_PIPELINE "0" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" +dict set params AXIS_ETH_TX_TS_PIPELINE "0" +dict set params AXIS_ETH_RX_PIPELINE "0" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_PCIE_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + # components (DDR4 A, DDR4 B) + set ddr4 [get_ips ddr4_0] + + # performance-related configuration + set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4 + set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4 + set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4 + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] + + if {[dict get $params DDR_CH] > 2} { + # SO-DIMMs (DDR4 SODMM 1, DDR4 SODIMM 2) + set ddr4 [get_ips ddr4_sodimm_0] + + # performance-related configuration + set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4 + set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4 + set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4 + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]] + } +} + +# PCIe IP core settings +set pcie [get_ips pcie3_ultrascale_0] + +# Internal interface settings +dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] + +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +# set_property generic $param_list [current_fileset] +set_property generic $param_list [get_filesets sources_1] + +# set implementation strategy +set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile new file mode 100644 index 000000000..a22295564 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile @@ -0,0 +1,278 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2019-2023 The Regents of the University of California + +# FPGA settings +FPGA_PART = xcvu095-ffvb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = VirtexUltrascale + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/common/mqnic_core_pcie_us.v +SYN_FILES += rtl/common/mqnic_core_pcie.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_port_tx.v +SYN_FILES += rtl/common/mqnic_port_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_rx_queue_map.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v +SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/rb_drp.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_pcie_if.v +SYN_FILES += rtl/common/stats_pcie_tlp.v +SYN_FILES += rtl/common/stats_dma_if_pcie.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v +SYN_FILES += app/dma_bench/rtl/dma_bench.v +SYN_FILES += app/dma_bench/rtl/dram_test_ch.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v +SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v +SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v +SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v +SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += placement.xdc +XDC_FILES += boot.xdc +XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl +XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl +XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl +XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl +XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl +XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl + +# IP +IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl +IP_TCL_FILES += ip/ddr4_sodimm_0.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +%_fallback.bit: %.bit + echo "open_project $*.xpr" > generate_fallback_bit.tcl + echo "open_run impl_1" >> generate_fallback_bit.tcl + echo "startgroup" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl + echo "endgroup" >> generate_fallback_bit.tcl + echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl + echo "undo" >> generate_fallback_bit.tcl + echo "exit" >> generate_fallback_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl + mkdir -p rev + EXT=bit; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT"; + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +%_fallback.mcs %_fallback.prm: %_fallback.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl + echo "exit" >> generate_fallback_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \ + echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done; + +%_full.mcs %_full.prm: %_fallback.bit %.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl + echo "exit" >> generate_full_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \ + echo "Output: rev/$*_full_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + +flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm + echo "open_hw" > flash$*.tcl + echo "connect_hw_server" >> flash$*.tcl + echo "open_hw_target" >> flash$*.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl + echo "program_hw_devices [current_hw_device]" >> flash$*.tcl + echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl + echo "boot_hw_device [current_hw_device]" >> flash$*.tcl + echo "exit" >> flash$*.tcl + vivado -nojournal -nolog -mode batch -source flash$*.tcl + diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl new file mode 100644 index 000000000..c87ab4c04 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/config.tcl @@ -0,0 +1,308 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2021-2023 The Regents of the University of California + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x3842093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x12ba] +set board_device_id [expr 0x8823] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_vendor_id $board_vendor_id +set pcie_subsystem_device_id $board_device_id + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +dict set params TDMA_BER_ENABLE "0" + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +# Structural configuration +dict set params IF_COUNT "1" +dict set params PORTS_PER_IF "2" +dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] +dict set params PORT_MASK "0" + +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +dict set params PTP_CLOCK_PIPELINE "0" +dict set params PTP_CLOCK_CDC_PIPELINE "0" +dict set params PTP_PORT_CDC_PIPELINE "0" +dict set params PTP_PEROUT_ENABLE "0" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" +dict set params TX_QUEUE_INDEX_WIDTH "9" +dict set params RX_QUEUE_INDEX_WIDTH "8" +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] + +# TX and RX engine configuration +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] + +# Scheduler configuration +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Interface configuration +dict set params PTP_TS_ENABLE "0" +dict set params TX_CPL_FIFO_DEPTH "32" +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + +# Application block configuration +dict set params APP_ID "32'h12348001" +dict set params APP_ENABLE "1" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# DMA interface configuration +dict set params DMA_IMM_ENABLE "0" +dict set params DMA_IMM_WIDTH "32" +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" + +# Interrupt configuration +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_WIDTH "32" +dict set params AXIL_CTRL_ADDR_WIDTH "24" + +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + +# Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] +dict set params AXIS_ETH_TX_PIPELINE "0" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" +dict set params AXIS_ETH_TX_TS_PIPELINE "0" +dict set params AXIS_ETH_RX_PIPELINE "0" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_PCIE_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + # components (DDR4 A, DDR4 B) + set ddr4 [get_ips ddr4_0] + + # performance-related configuration + set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4 + set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4 + set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4 + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] + + if {[dict get $params DDR_CH] > 2} { + # SO-DIMMs (DDR4 SODMM 1, DDR4 SODIMM 2) + set ddr4 [get_ips ddr4_sodimm_0] + + # performance-related configuration + set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4 + set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4 + set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4 + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]] + } +} + +# PCIe IP core settings +set pcie [get_ips pcie3_ultrascale_0] + +# Internal interface settings +dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] + +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +# set_property generic $param_list [current_fileset] +set_property generic $param_list [get_filesets sources_1] + +# set implementation strategy +set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..7d154dc5b --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,18 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {9996} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M8HX-083} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_sodimm_0.tcl b/fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_sodimm_0.tcl new file mode 100644 index 000000000..8b7d7d84b --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/ip/ddr4_sodimm_0.tcl @@ -0,0 +1,18 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_sodimm_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {1072} \ + CONFIG.C0.DDR4_InputClockPeriod {10004} \ + CONFIG.C0.DDR4_MemoryType {SODIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA8ATF1G64HZ-2G3} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {13} \ + CONFIG.C0.DDR4_CasWriteLatency {10} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_sodimm_0] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/XUSP3S/fpga_25g/ip/eth_xcvr_gty.tcl new file mode 100644 index 000000000..c7e049079 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/ip/eth_xcvr_gty.tcl @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2022-2023 The Regents of the University of California + +set base_name {eth_xcvr_gty} + +set preset {GTY-10GBASE-R} + +set freerun_freq {125} +set line_rate {25.78125} +set sec_line_rate {10.3125} +set refclk_freq {322.265625} +set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set user_data_width {64} +set int_data_width $user_data_width +set rx_eq_mode {DFE} +set extra_ports [list] +set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in +# channel polarity +lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in +# channel EQ +lappend extra_ports rxlpmen_in +# channel digital monitor +lappend extra_ports dmonitorout_out +# channel PRBS +lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out +# channel eye scan +lappend extra_ports eyescandataerror_out +# channel loopback +lappend extra_ports loopback_in + +set config [dict create] + +dict set config TX_LINE_RATE $line_rate +dict set config TX_REFCLK_FREQUENCY $refclk_freq +dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config TX_USER_DATA_WIDTH $user_data_width +dict set config TX_INT_DATA_WIDTH $int_data_width +dict set config RX_LINE_RATE $line_rate +dict set config RX_REFCLK_FREQUENCY $refclk_freq +dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config RX_USER_DATA_WIDTH $user_data_width +dict set config RX_INT_DATA_WIDTH $int_data_width +dict set config RX_EQ_MODE $rx_eq_mode +if {$sec_line_rate != 0} { + dict set config SECONDARY_QPLL_ENABLE true + dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn + dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq +} else { + dict set config SECONDARY_QPLL_ENABLE false +} +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} +dict set config LOCATE_TX_USER_CLOCKING {CORE} +dict set config LOCATE_RX_USER_CLOCKING {CORE} +dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} +dict set config FREERUN_FREQUENCY $freerun_freq +dict set config DISABLE_LOC_XDC {1} + +proc create_gtwizard_ip {name preset config} { + create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name + set ip [get_ips $name] + set_property CONFIG.preset $preset $ip + set config_list {} + dict for {name value} $config { + lappend config_list "CONFIG.${name}" $value + } + set_property -dict $config_list $ip +} + +# variant with channel and common +dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] +dict set config LOCATE_COMMON {CORE} + +create_gtwizard_ip "${base_name}_full" $preset $config + +# variant with channel only +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {EXAMPLE_DESIGN} + +create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/XUSP3S/fpga_25g/ip/pcie3_ultrascale_0.tcl b/fpga/mqnic/XUSP3S/fpga_25g/ip/pcie3_ultrascale_0.tcl new file mode 100644 index 000000000..e0d9987f9 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/ip/pcie3_ultrascale_0.tcl @@ -0,0 +1,31 @@ + +create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.AXISTEN_IF_RC_STRADDLE {true} \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.extended_tag_field {true} \ + CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ + CONFIG.axisten_freq {250} \ + CONFIG.pf0_class_code_base {02} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_class_code_interface {00} \ + CONFIG.PF0_DEVICE_ID {1001} \ + CONFIG.PF0_SUBSYSTEM_ID {8823} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {12ba} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_msi_enabled {false} \ + CONFIG.pf0_msix_enabled {true} \ + CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ + CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ + CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ + CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ + CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ + CONFIG.vendor_id {1234} \ + CONFIG.mode_selection {Advanced} \ +] [get_ips pcie3_ultrascale_0] diff --git a/fpga/mqnic/XUSP3S/fpga_25g/lib b/fpga/mqnic/XUSP3S/fpga_25g/lib new file mode 120000 index 000000000..9512b3d5e --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/lib @@ -0,0 +1 @@ +../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/XUSP3S/fpga_25g/placement.xdc b/fpga/mqnic/XUSP3S/fpga_25g/placement.xdc new file mode 100644 index 000000000..7e880e367 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/placement.xdc @@ -0,0 +1,19 @@ +# Placement constraints +create_pblock pblock_pcie +# add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie3_ultrascale_inst"] +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"] +resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X3Y0:CLOCKREGION_X4Y1} + +create_pblock pblock_eth +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_phy_quad_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp2_phy_quad_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp3_phy_quad_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"] +resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y0:CLOCKREGION_X1Y7} diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/common b/fpga/mqnic/XUSP3S/fpga_25g/rtl/common new file mode 120000 index 000000000..449c9409c --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/rtl/common @@ -0,0 +1 @@ +../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v new file mode 100644 index 000000000..3b59f6d2b --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v @@ -0,0 +1,3084 @@ +// SPDX-License-Identifier: BSD-2-Clause-Views +/* + * Copyright (c) 2019-2023 The Regents of the University of California + */ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // FW and board IDs + parameter FPGA_ID = 32'h3842093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h12ba_8823, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 1, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 11, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 0, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_WIDTH = 256, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, + parameter AXIS_ETH_TX_PIPELINE = 0, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, + parameter AXIS_ETH_TX_TS_PIPELINE = 0, + parameter AXIS_ETH_RX_PIPELINE = 0, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 48MHz + */ + input wire clk_48mhz, + input wire clk_ddr_a_p, + input wire clk_ddr_a_n, + input wire clk_ddr_b_p, + input wire clk_ddr_b_n, + input wire clk_ddr_sodimm1_p, + input wire clk_ddr_sodimm1_n, + input wire clk_ddr_sodimm2_p, + input wire clk_ddr_sodimm2_n, + + /* + * GPIO + */ + output wire [3:0] led, + input wire ext_pps_in, + input wire ext_clk_in, + + /* + * I2C and related signals + */ + inout wire eeprom_i2c_scl, + inout wire eeprom_i2c_sda, + output wire fpga_i2c_master_l, + output wire qsfp_ctl_en, + + /* + * PCI express + */ + input wire [7:0] pcie_rx_p, + input wire [7:0] pcie_rx_n, + output wire [7:0] pcie_tx_p, + output wire [7:0] pcie_tx_n, + input wire pcie_refclk_0_p, + input wire pcie_refclk_0_n, + // input wire pcie_refclk_b1_p, + // input wire pcie_refclk_b1_n, + // input wire pcie_refclk_1_p, + // input wire pcie_refclk_1_n, + input wire pcie_reset_n, + + /* + * Ethernet: QSFP28 + */ + output wire qsfp0_tx1_p, + output wire qsfp0_tx1_n, + input wire qsfp0_rx1_p, + input wire qsfp0_rx1_n, + output wire qsfp0_tx2_p, + output wire qsfp0_tx2_n, + input wire qsfp0_rx2_p, + input wire qsfp0_rx2_n, + output wire qsfp0_tx3_p, + output wire qsfp0_tx3_n, + input wire qsfp0_rx3_p, + input wire qsfp0_rx3_n, + output wire qsfp0_tx4_p, + output wire qsfp0_tx4_n, + input wire qsfp0_rx4_p, + input wire qsfp0_rx4_n, + input wire qsfp0_mgt_refclk_b0_p, + input wire qsfp0_mgt_refclk_b0_n, + // input wire qsfp0_mgt_refclk_b1_p, + // input wire qsfp0_mgt_refclk_b1_n, + // input wire qsfp0_mgt_refclk_c0_p, + // input wire qsfp0_mgt_refclk_c0_n, + // input wire qsfp0_mgt_refclk_c1_p, + // input wire qsfp0_mgt_refclk_c1_n, + output wire qsfp0_resetl, + input wire qsfp0_modprsl, + input wire qsfp0_intl, + output wire qsfp0_lpmode, + inout wire qsfp0_i2c_scl, + inout wire qsfp0_i2c_sda, + + output wire qsfp1_tx1_p, + output wire qsfp1_tx1_n, + input wire qsfp1_rx1_p, + input wire qsfp1_rx1_n, + output wire qsfp1_tx2_p, + output wire qsfp1_tx2_n, + input wire qsfp1_rx2_p, + input wire qsfp1_rx2_n, + output wire qsfp1_tx3_p, + output wire qsfp1_tx3_n, + input wire qsfp1_rx3_p, + input wire qsfp1_rx3_n, + output wire qsfp1_tx4_p, + output wire qsfp1_tx4_n, + input wire qsfp1_rx4_p, + input wire qsfp1_rx4_n, + input wire qsfp1_mgt_refclk_b0_p, + input wire qsfp1_mgt_refclk_b0_n, + // input wire qsfp1_mgt_refclk_b1_p, + // input wire qsfp1_mgt_refclk_b1_n, + // input wire qsfp1_mgt_refclk_c2_p, + // input wire qsfp1_mgt_refclk_c2_n, + // input wire qsfp1_mgt_refclk_c3_p, + // input wire qsfp1_mgt_refclk_c3_n, + output wire qsfp1_resetl, + input wire qsfp1_modprsl, + input wire qsfp1_intl, + output wire qsfp1_lpmode, + inout wire qsfp1_i2c_scl, + inout wire qsfp1_i2c_sda, + + output wire qsfp2_tx1_p, + output wire qsfp2_tx1_n, + input wire qsfp2_rx1_p, + input wire qsfp2_rx1_n, + output wire qsfp2_tx2_p, + output wire qsfp2_tx2_n, + input wire qsfp2_rx2_p, + input wire qsfp2_rx2_n, + output wire qsfp2_tx3_p, + output wire qsfp2_tx3_n, + input wire qsfp2_rx3_p, + input wire qsfp2_rx3_n, + output wire qsfp2_tx4_p, + output wire qsfp2_tx4_n, + input wire qsfp2_rx4_p, + input wire qsfp2_rx4_n, + input wire qsfp2_mgt_refclk_b0_p, + input wire qsfp2_mgt_refclk_b0_n, + // input wire qsfp2_mgt_refclk_b2_p, + // input wire qsfp2_mgt_refclk_b2_n, + // input wire qsfp2_mgt_refclk_d0_p, + // input wire qsfp2_mgt_refclk_d0_n, + // input wire qsfp2_mgt_refclk_d1_p, + // input wire qsfp2_mgt_refclk_d1_n, + output wire qsfp2_resetl, + input wire qsfp2_modprsl, + input wire qsfp2_intl, + output wire qsfp2_lpmode, + inout wire qsfp2_i2c_scl, + inout wire qsfp2_i2c_sda, + + output wire qsfp3_tx1_p, + output wire qsfp3_tx1_n, + input wire qsfp3_rx1_p, + input wire qsfp3_rx1_n, + output wire qsfp3_tx2_p, + output wire qsfp3_tx2_n, + input wire qsfp3_rx2_p, + input wire qsfp3_rx2_n, + output wire qsfp3_tx3_p, + output wire qsfp3_tx3_n, + input wire qsfp3_rx3_p, + input wire qsfp3_rx3_n, + output wire qsfp3_tx4_p, + output wire qsfp3_tx4_n, + input wire qsfp3_rx4_p, + input wire qsfp3_rx4_n, + input wire qsfp3_mgt_refclk_b0_p, + input wire qsfp3_mgt_refclk_b0_n, + // input wire qsfp3_mgt_refclk_b3_p, + // input wire qsfp3_mgt_refclk_b3_n, + // input wire qsfp3_mgt_refclk_d2_p, + // input wire qsfp3_mgt_refclk_d2_n, + // input wire qsfp3_mgt_refclk_d3_p, + // input wire qsfp3_mgt_refclk_d3_n, + output wire qsfp3_resetl, + input wire qsfp3_modprsl, + input wire qsfp3_intl, + output wire qsfp3_lpmode, + inout wire qsfp3_i2c_scl, + inout wire qsfp3_i2c_sda, + + /* + * DDR4 + */ + output wire [16:0] ddr4_a_adr, + output wire [1:0] ddr4_a_ba, + output wire [1:0] ddr4_a_bg, + output wire [0:0] ddr4_a_ck_t, + output wire [0:0] ddr4_a_ck_c, + output wire [0:0] ddr4_a_cke, + output wire [0:0] ddr4_a_cs_n, + output wire ddr4_a_act_n, + output wire [0:0] ddr4_a_odt, + output wire ddr4_a_par, + output wire ddr4_a_reset_n, + inout wire [71:0] ddr4_a_dq, + inout wire [8:0] ddr4_a_dqs_t, + inout wire [8:0] ddr4_a_dqs_c, + inout wire [8:0] ddr4_a_dm_dbi_n, + + output wire [16:0] ddr4_b_adr, + output wire [1:0] ddr4_b_ba, + output wire [1:0] ddr4_b_bg, + output wire [0:0] ddr4_b_ck_t, + output wire [0:0] ddr4_b_ck_c, + output wire [0:0] ddr4_b_cke, + output wire [0:0] ddr4_b_cs_n, + output wire ddr4_b_act_n, + output wire [0:0] ddr4_b_odt, + output wire ddr4_b_par, + output wire ddr4_b_reset_n, + inout wire [71:0] ddr4_b_dq, + inout wire [8:0] ddr4_b_dqs_t, + inout wire [8:0] ddr4_b_dqs_c, + inout wire [8:0] ddr4_b_dm_dbi_n, + + output wire [16:0] ddr4_sodimm1_adr, + output wire [1:0] ddr4_sodimm1_ba, + output wire [1:0] ddr4_sodimm1_bg, + output wire [0:0] ddr4_sodimm1_ck_t, + output wire [0:0] ddr4_sodimm1_ck_c, + output wire [0:0] ddr4_sodimm1_cke, + output wire [0:0] ddr4_sodimm1_cs_n, + output wire ddr4_sodimm1_act_n, + output wire [0:0] ddr4_sodimm1_odt, + output wire ddr4_sodimm1_par, + output wire ddr4_sodimm1_reset_n, + input wire ddr4_sodimm1_alert_n, + inout wire [63:0] ddr4_sodimm1_dq, + inout wire [7:0] ddr4_sodimm1_dqs_t, + inout wire [7:0] ddr4_sodimm1_dqs_c, + inout wire [7:0] ddr4_sodimm1_dm_dbi_n, + + output wire [16:0] ddr4_sodimm2_adr, + output wire [1:0] ddr4_sodimm2_ba, + output wire [1:0] ddr4_sodimm2_bg, + output wire [0:0] ddr4_sodimm2_ck_t, + output wire [0:0] ddr4_sodimm2_ck_c, + output wire [0:0] ddr4_sodimm2_cke, + output wire [0:0] ddr4_sodimm2_cs_n, + output wire ddr4_sodimm2_act_n, + output wire [0:0] ddr4_sodimm2_odt, + output wire ddr4_sodimm2_par, + output wire ddr4_sodimm2_reset_n, + input wire ddr4_sodimm2_alert_n, + inout wire [63:0] ddr4_sodimm2_dq, + inout wire [7:0] ddr4_sodimm2_dqs_t, + inout wire [7:0] ddr4_sodimm2_dqs_c, + inout wire [7:0] ddr4_sodimm2_dm_dbi_n +); + +// PTP configuration +parameter PTP_CLK_PERIOD_NS_NUM = 512; +parameter PTP_CLK_PERIOD_NS_DENOM = 165; +parameter PTP_TS_WIDTH = 96; +parameter PTP_USE_SAMPLE_CLOCK = 1; +parameter IF_PTP_PERIOD_NS = 6'h6; +parameter IF_PTP_PERIOD_FNS = 16'h6666; + +// Interface configuration +parameter TX_TAG_WIDTH = 16; + +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + +// PCIe interface configuration +parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = 75; +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; +parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; +parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter RQ_SEQ_NUM_WIDTH = 4; +parameter PCIE_TAG_COUNT = 64; + +// Ethernet interface configuration +parameter XGMII_DATA_WIDTH = 64; +parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; +parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; +parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); +parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; +parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; + +// Clock and reset +wire pcie_user_clk; +wire pcie_user_reset; + +wire clk_125mhz_mmcm_out; + +// Internal 125 MHz clock +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = pcie_user_reset; +wire mmcm_locked; +wire mmcm_clkfb; + +// MMCM instance +// 48 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 600 MHz to 1440 MHz +// M = 62.5, D = 3 sets Fvco = 1000 MHz +// Divide by 8 to get output frequency of 125 MHz +MMCME3_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(62.5), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(3), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(20.833), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(clk_48mhz), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +assign qsfp_ctl_en = 1'b1; +assign fpga_i2c_master_l = 1'b0; + +wire eeprom_i2c_scl_i; +wire eeprom_i2c_scl_o; +wire eeprom_i2c_scl_t; +wire eeprom_i2c_sda_i; +wire eeprom_i2c_sda_o; +wire eeprom_i2c_sda_t; + +wire qsfp0_modprsl_int; +wire qsfp0_intl_int; +wire qsfp0_i2c_scl_i; +wire qsfp0_i2c_scl_o; +wire qsfp0_i2c_scl_t; +wire qsfp0_i2c_sda_i; +wire qsfp0_i2c_sda_o; +wire qsfp0_i2c_sda_t; + +wire qsfp1_modprsl_int; +wire qsfp1_intl_int; +wire qsfp1_i2c_scl_i; +wire qsfp1_i2c_scl_o; +wire qsfp1_i2c_scl_t; +wire qsfp1_i2c_sda_i; +wire qsfp1_i2c_sda_o; +wire qsfp1_i2c_sda_t; + +wire qsfp2_modprsl_int; +wire qsfp2_intl_int; +wire qsfp2_i2c_scl_i; +wire qsfp2_i2c_scl_o; +wire qsfp2_i2c_scl_t; +wire qsfp2_i2c_sda_i; +wire qsfp2_i2c_sda_o; +wire qsfp2_i2c_sda_t; + +wire qsfp3_modprsl_int; +wire qsfp3_intl_int; +wire qsfp3_i2c_scl_i; +wire qsfp3_i2c_scl_o; +wire qsfp3_i2c_scl_t; +wire qsfp3_i2c_sda_i; +wire qsfp3_i2c_sda_o; +wire qsfp3_i2c_sda_t; + +reg eeprom_i2c_scl_o_reg; +reg eeprom_i2c_scl_t_reg; +reg eeprom_i2c_sda_o_reg; +reg eeprom_i2c_sda_t_reg; + +reg qsfp0_i2c_scl_o_reg; +reg qsfp0_i2c_scl_t_reg; +reg qsfp0_i2c_sda_o_reg; +reg qsfp0_i2c_sda_t_reg; + +reg qsfp1_i2c_scl_o_reg; +reg qsfp1_i2c_scl_t_reg; +reg qsfp1_i2c_sda_o_reg; +reg qsfp1_i2c_sda_t_reg; + +reg qsfp2_i2c_scl_o_reg; +reg qsfp2_i2c_scl_t_reg; +reg qsfp2_i2c_sda_o_reg; +reg qsfp2_i2c_sda_t_reg; + +reg qsfp3_i2c_scl_o_reg; +reg qsfp3_i2c_scl_t_reg; +reg qsfp3_i2c_sda_o_reg; +reg qsfp3_i2c_sda_t_reg; + +always @(posedge pcie_user_clk) begin + eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o; + eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t; + eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o; + eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t; + + qsfp0_i2c_scl_o_reg <= qsfp0_i2c_scl_o; + qsfp0_i2c_scl_t_reg <= qsfp0_i2c_scl_t; + qsfp0_i2c_sda_o_reg <= qsfp0_i2c_sda_o; + qsfp0_i2c_sda_t_reg <= qsfp0_i2c_sda_t; + + qsfp1_i2c_scl_o_reg <= qsfp1_i2c_scl_o; + qsfp1_i2c_scl_t_reg <= qsfp1_i2c_scl_t; + qsfp1_i2c_sda_o_reg <= qsfp1_i2c_sda_o; + qsfp1_i2c_sda_t_reg <= qsfp1_i2c_sda_t; + + qsfp2_i2c_scl_o_reg <= qsfp2_i2c_scl_o; + qsfp2_i2c_scl_t_reg <= qsfp2_i2c_scl_t; + qsfp2_i2c_sda_o_reg <= qsfp2_i2c_sda_o; + qsfp2_i2c_sda_t_reg <= qsfp2_i2c_sda_t; + + qsfp3_i2c_scl_o_reg <= qsfp3_i2c_scl_o; + qsfp3_i2c_scl_t_reg <= qsfp3_i2c_scl_t; + qsfp3_i2c_sda_o_reg <= qsfp3_i2c_sda_o; + qsfp3_i2c_sda_t_reg <= qsfp3_i2c_sda_t; +end + +sync_signal #( + .WIDTH(18), + .N(2) +) +sync_signal_inst ( + .clk(pcie_user_clk), + .in({eeprom_i2c_scl, eeprom_i2c_sda, + qsfp0_modprsl, qsfp0_intl, qsfp0_i2c_scl, qsfp0_i2c_sda, + qsfp1_modprsl, qsfp1_intl, qsfp1_i2c_scl, qsfp1_i2c_sda, + qsfp2_modprsl, qsfp2_intl, qsfp2_i2c_scl, qsfp2_i2c_sda, + qsfp3_modprsl, qsfp3_intl, qsfp3_i2c_scl, qsfp3_i2c_sda}), + .out({eeprom_i2c_scl_i, eeprom_i2c_sda_i, + qsfp0_modprsl_int, qsfp0_intl_int, qsfp0_i2c_scl_i, qsfp0_i2c_sda_i, + qsfp1_modprsl_int, qsfp1_intl_int, qsfp1_i2c_scl_i, qsfp1_i2c_sda_i, + qsfp2_modprsl_int, qsfp2_intl_int, qsfp2_i2c_scl_i, qsfp2_i2c_sda_i, + qsfp3_modprsl_int, qsfp3_intl_int, qsfp3_i2c_scl_i, qsfp3_i2c_sda_i}) +); + +assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg; +assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg; + +assign qsfp0_i2c_scl = qsfp0_i2c_scl_t_reg ? 1'bz : qsfp0_i2c_scl_o_reg; +assign qsfp0_i2c_sda = qsfp0_i2c_sda_t_reg ? 1'bz : qsfp0_i2c_sda_o_reg; + +assign qsfp1_i2c_scl = qsfp1_i2c_scl_t_reg ? 1'bz : qsfp1_i2c_scl_o_reg; +assign qsfp1_i2c_sda = qsfp1_i2c_sda_t_reg ? 1'bz : qsfp1_i2c_sda_o_reg; + +assign qsfp2_i2c_scl = qsfp2_i2c_scl_t_reg ? 1'bz : qsfp2_i2c_scl_o_reg; +assign qsfp2_i2c_sda = qsfp2_i2c_sda_t_reg ? 1'bz : qsfp2_i2c_sda_o_reg; + +assign qsfp3_i2c_scl = qsfp3_i2c_scl_t_reg ? 1'bz : qsfp3_i2c_scl_o_reg; +assign qsfp3_i2c_sda = qsfp3_i2c_sda_t_reg ? 1'bz : qsfp3_i2c_sda_o_reg; + +// Flash +wire qspi_clk_int; +wire [3:0] qspi_dq_int; +wire [3:0] qspi_dq_i_int; +wire [3:0] qspi_dq_o_int; +wire [3:0] qspi_dq_oe_int; +wire qspi_cs_int; + +reg qspi_clk_reg; +reg [3:0] qspi_dq_o_reg; +reg [3:0] qspi_dq_oe_reg; +reg qspi_cs_reg; + +always @(posedge pcie_user_clk) begin + qspi_clk_reg <= qspi_clk_int; + qspi_dq_o_reg <= qspi_dq_o_int; + qspi_dq_oe_reg <= qspi_dq_oe_int; + qspi_cs_reg <= qspi_cs_int; +end + +sync_signal #( + .WIDTH(4), + .N(2) +) +flash_sync_signal_inst ( + .clk(pcie_user_clk), + .in({qspi_dq_int}), + .out({qspi_dq_i_int}) +); + +// startupe3 instance +STARTUPE3 +startupe3_inst ( + .CFGCLK(), + .CFGMCLK(), + .DI(qspi_dq_int), + .DO(qspi_dq_o_reg), + .DTS(~qspi_dq_oe_reg), + .EOS(), + .FCSBO(qspi_cs_reg), + .FCSBTS(1'b0), + .GSR(1'b0), + .GTS(1'b0), + .KEYCLEARB(1'b1), + .PACK(1'b0), + .PREQ(), + .USRCCLKO(qspi_clk_reg), + .USRCCLKTS(1'b0), + .USRDONEO(1'b0), + .USRDONETS(1'b1) +); + +// FPGA boot +wire fpga_boot; + +reg fpga_boot_sync_reg_0 = 1'b0; +reg fpga_boot_sync_reg_1 = 1'b0; +reg fpga_boot_sync_reg_2 = 1'b0; + +wire icap_avail; +reg [2:0] icap_state = 0; +reg icap_csib_reg = 1'b1; +reg icap_rdwrb_reg = 1'b0; +reg [31:0] icap_di_reg = 32'hffffffff; + +wire [31:0] icap_di_rev; + +assign icap_di_rev[ 7] = icap_di_reg[ 0]; +assign icap_di_rev[ 6] = icap_di_reg[ 1]; +assign icap_di_rev[ 5] = icap_di_reg[ 2]; +assign icap_di_rev[ 4] = icap_di_reg[ 3]; +assign icap_di_rev[ 3] = icap_di_reg[ 4]; +assign icap_di_rev[ 2] = icap_di_reg[ 5]; +assign icap_di_rev[ 1] = icap_di_reg[ 6]; +assign icap_di_rev[ 0] = icap_di_reg[ 7]; + +assign icap_di_rev[15] = icap_di_reg[ 8]; +assign icap_di_rev[14] = icap_di_reg[ 9]; +assign icap_di_rev[13] = icap_di_reg[10]; +assign icap_di_rev[12] = icap_di_reg[11]; +assign icap_di_rev[11] = icap_di_reg[12]; +assign icap_di_rev[10] = icap_di_reg[13]; +assign icap_di_rev[ 9] = icap_di_reg[14]; +assign icap_di_rev[ 8] = icap_di_reg[15]; + +assign icap_di_rev[23] = icap_di_reg[16]; +assign icap_di_rev[22] = icap_di_reg[17]; +assign icap_di_rev[21] = icap_di_reg[18]; +assign icap_di_rev[20] = icap_di_reg[19]; +assign icap_di_rev[19] = icap_di_reg[20]; +assign icap_di_rev[18] = icap_di_reg[21]; +assign icap_di_rev[17] = icap_di_reg[22]; +assign icap_di_rev[16] = icap_di_reg[23]; + +assign icap_di_rev[31] = icap_di_reg[24]; +assign icap_di_rev[30] = icap_di_reg[25]; +assign icap_di_rev[29] = icap_di_reg[26]; +assign icap_di_rev[28] = icap_di_reg[27]; +assign icap_di_rev[27] = icap_di_reg[28]; +assign icap_di_rev[26] = icap_di_reg[29]; +assign icap_di_rev[25] = icap_di_reg[30]; +assign icap_di_rev[24] = icap_di_reg[31]; + +always @(posedge clk_125mhz_int) begin + case (icap_state) + 0: begin + icap_state <= 0; + icap_csib_reg <= 1'b1; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + + if (fpga_boot_sync_reg_2 && icap_avail) begin + icap_state <= 1; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + end + end + 1: begin + icap_state <= 2; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hAA995566; // sync word + end + 2: begin + icap_state <= 3; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + 3: begin + icap_state <= 4; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h30008001; // write 1 word to CMD + end + 4: begin + icap_state <= 5; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h0000000F; // IPROG + end + 5: begin + icap_state <= 0; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + endcase + + fpga_boot_sync_reg_0 <= fpga_boot; + fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; + fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; +end + +ICAPE3 +icape3_inst ( + .AVAIL(icap_avail), + .CLK(clk_125mhz_int), + .CSIB(icap_csib_reg), + .I(icap_di_rev), + .O(), + .PRDONE(), + .PRERROR(), + .RDWRB(icap_rdwrb_reg) +); + +// PCIe +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE3 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte3_pcie_mgt_refclk_inst ( + .I (pcie_refclk_0_p), + .IB (pcie_refclk_0_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; +wire axis_rq_tlast; +wire axis_rq_tready; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; +wire axis_rq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; +wire axis_rc_tlast; +wire axis_rc_tready; +wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; +wire axis_rc_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; +wire axis_cq_tlast; +wire axis_cq_tready; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; +wire axis_cq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; +wire axis_cc_tlast; +wire axis_cc_tready; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; +wire axis_cc_tvalid; + +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num; +wire pcie_rq_seq_num_vld; + +wire [1:0] pcie_tfc_nph_av; +wire [1:0] pcie_tfc_npd_av; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; +wire [3:0] cfg_rcb_status; + +wire [18:0] cfg_mgmt_addr; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [7:0] cfg_fc_ph; +wire [11:0] cfg_fc_pd; +wire [7:0] cfg_fc_nph; +wire [11:0] cfg_fc_npd; +wire [7:0] cfg_fc_cplh; +wire [11:0] cfg_fc_cpld; +wire [2:0] cfg_fc_sel; + +wire [1:0] cfg_interrupt_msix_enable; +wire [1:0] cfg_interrupt_msix_mask; +wire [7:0] cfg_interrupt_msix_vf_enable; +wire [7:0] cfg_interrupt_msix_vf_mask; +wire [63:0] cfg_interrupt_msix_address; +wire [31:0] cfg_interrupt_msix_data; +wire cfg_interrupt_msix_int; +wire cfg_interrupt_msix_sent; +wire cfg_interrupt_msix_fail; +wire [3:0] cfg_interrupt_msi_function_number; + +wire status_error_cor; +wire status_error_uncor; + +// extra register for pcie_user_reset signal +wire pcie_user_reset_int; +(* shreg_extract = "no" *) +reg pcie_user_reset_reg_1 = 1'b1; +(* shreg_extract = "no" *) +reg pcie_user_reset_reg_2 = 1'b1; + +always @(posedge pcie_user_clk) begin + pcie_user_reset_reg_1 <= pcie_user_reset_int; + pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; +end + +BUFG +pcie_user_reset_bufg_inst ( + .I(pcie_user_reset_reg_2), + .O(pcie_user_reset) +); + +pcie3_ultrascale_0 +pcie3_ultrascale_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_reset_int), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_rq_tdata), + .s_axis_rq_tkeep(axis_rq_tkeep), + .s_axis_rq_tlast(axis_rq_tlast), + .s_axis_rq_tready(axis_rq_tready), + .s_axis_rq_tuser(axis_rq_tuser), + .s_axis_rq_tvalid(axis_rq_tvalid), + + .m_axis_rc_tdata(axis_rc_tdata), + .m_axis_rc_tkeep(axis_rc_tkeep), + .m_axis_rc_tlast(axis_rc_tlast), + .m_axis_rc_tready(axis_rc_tready), + .m_axis_rc_tuser(axis_rc_tuser), + .m_axis_rc_tvalid(axis_rc_tvalid), + + .m_axis_cq_tdata(axis_cq_tdata), + .m_axis_cq_tkeep(axis_cq_tkeep), + .m_axis_cq_tlast(axis_cq_tlast), + .m_axis_cq_tready(axis_cq_tready), + .m_axis_cq_tuser(axis_cq_tuser), + .m_axis_cq_tvalid(axis_cq_tvalid), + + .s_axis_cc_tdata(axis_cc_tdata), + .s_axis_cc_tkeep(axis_cc_tkeep), + .s_axis_cc_tlast(axis_cc_tlast), + .s_axis_cc_tready(axis_cc_tready), + .s_axis_cc_tuser(axis_cc_tuser), + .s_axis_cc_tvalid(axis_cc_tvalid), + + .pcie_rq_seq_num(pcie_rq_seq_num), + .pcie_rq_seq_num_vld(pcie_rq_seq_num_vld), + .pcie_rq_tag(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld(), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_type1_cfg_reg_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error(), + .cfg_ltr_enable(), + .cfg_ltssm_state(), + .cfg_rcb_status(cfg_rcb_status), + .cfg_dpa_substate_change(), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_per_func_status_control(3'd0), + .cfg_per_func_status_data(), + .cfg_per_function_number(4'd0), + .cfg_per_function_output_request(1'b0), + .cfg_per_function_update_done(), + + .cfg_dsn(64'd0), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(status_error_cor), + .cfg_err_uncor_in(status_error_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + .cfg_ds_function_number(3'd0), + + .cfg_subsys_vend_id(16'h1234), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_reset_n), + .pcie_perstn1_in(1'b0), + .pcie_perstn0_out(), + .pcie_perstn1_out(), + + .int_qpll1lock_out(), + .int_qpll1outrefclk_out(), + .int_qpll1outclk_out(), + .phy_rdy_out() +); + +// XGMII 10G PHY + +// QSFP0 +wire qsfp0_tx_clk_1_int; +wire qsfp0_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int; +wire qsfp0_tx_prbs31_enable_1_int; +wire qsfp0_rx_clk_1_int; +wire qsfp0_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int; +wire qsfp0_rx_prbs31_enable_1_int; +wire [6:0] qsfp0_rx_error_count_1_int; +wire qsfp0_tx_clk_2_int; +wire qsfp0_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int; +wire qsfp0_tx_prbs31_enable_2_int; +wire qsfp0_rx_clk_2_int; +wire qsfp0_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int; +wire qsfp0_rx_prbs31_enable_2_int; +wire [6:0] qsfp0_rx_error_count_2_int; +wire qsfp0_tx_clk_3_int; +wire qsfp0_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int; +wire qsfp0_tx_prbs31_enable_3_int; +wire qsfp0_rx_clk_3_int; +wire qsfp0_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int; +wire qsfp0_rx_prbs31_enable_3_int; +wire [6:0] qsfp0_rx_error_count_3_int; +wire qsfp0_tx_clk_4_int; +wire qsfp0_tx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int; +wire qsfp0_tx_prbs31_enable_4_int; +wire qsfp0_rx_clk_4_int; +wire qsfp0_rx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int; +wire qsfp0_rx_prbs31_enable_4_int; +wire [6:0] qsfp0_rx_error_count_4_int; + +wire qsfp0_drp_clk = clk_125mhz_int; +wire qsfp0_drp_rst = rst_125mhz_int; +wire [23:0] qsfp0_drp_addr; +wire [15:0] qsfp0_drp_di; +wire qsfp0_drp_en; +wire qsfp0_drp_we; +wire [15:0] qsfp0_drp_do; +wire qsfp0_drp_rdy; + +wire qsfp0_rx_block_lock_1; +wire qsfp0_rx_status_1; +wire qsfp0_rx_block_lock_2; +wire qsfp0_rx_status_2; +wire qsfp0_rx_block_lock_3; +wire qsfp0_rx_status_3; +wire qsfp0_rx_block_lock_4; +wire qsfp0_rx_status_4; + +wire qsfp0_gtpowergood; + +wire qsfp0_mgt_refclk_b0; +wire qsfp0_mgt_refclk_b0_int; +wire qsfp0_mgt_refclk_b0_bufg; + +IBUFDS_GTE3 ibufds_gte3_qsfp0_mgt_refclk_b0_inst ( + .I (qsfp0_mgt_refclk_b0_p), + .IB (qsfp0_mgt_refclk_b0_n), + .CEB (1'b0), + .O (qsfp0_mgt_refclk_b0), + .ODIV2 (qsfp0_mgt_refclk_b0_int) +); + +BUFG_GT bufg_gt_qsfp0_mgt_refclk_b0_inst ( + .CE (qsfp0_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp0_mgt_refclk_b0_int), + .O (qsfp0_mgt_refclk_b0_bufg) +); + +wire qsfp0_rst; + +sync_reset #( + .N(4) +) +qsfp0_sync_reset_inst ( + .clk(qsfp0_mgt_refclk_b0_bufg), + .rst(rst_125mhz_int), + .out(qsfp0_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp0_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp0_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp0_gtpowergood), + .xcvr_ref_clk(qsfp0_mgt_refclk_b0), + + /* + * DRP + */ + .drp_clk(qsfp0_drp_clk), + .drp_rst(qsfp0_drp_rst), + .drp_addr(qsfp0_drp_addr), + .drp_di(qsfp0_drp_di), + .drp_en(qsfp0_drp_en), + .drp_we(qsfp0_drp_we), + .drp_do(qsfp0_drp_do), + .drp_rdy(qsfp0_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}), + .xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}), + .xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}), + .xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp0_tx_clk_1_int), + .phy_1_tx_rst(qsfp0_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp0_txd_1_int), + .phy_1_xgmii_txc(qsfp0_txc_1_int), + .phy_1_rx_clk(qsfp0_rx_clk_1_int), + .phy_1_rx_rst(qsfp0_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp0_rxd_1_int), + .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp0_rx_error_count_1_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp0_rx_status_1), + .phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int), + .phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int), + + .phy_2_tx_clk(qsfp0_tx_clk_2_int), + .phy_2_tx_rst(qsfp0_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp0_txd_2_int), + .phy_2_xgmii_txc(qsfp0_txc_2_int), + .phy_2_rx_clk(qsfp0_rx_clk_2_int), + .phy_2_rx_rst(qsfp0_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp0_rxd_2_int), + .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp0_rx_error_count_2_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp0_rx_status_2), + .phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int), + .phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int), + + .phy_3_tx_clk(qsfp0_tx_clk_3_int), + .phy_3_tx_rst(qsfp0_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp0_txd_3_int), + .phy_3_xgmii_txc(qsfp0_txc_3_int), + .phy_3_rx_clk(qsfp0_rx_clk_3_int), + .phy_3_rx_rst(qsfp0_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp0_rxd_3_int), + .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp0_rx_error_count_3_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp0_rx_status_3), + .phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int), + .phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int), + + .phy_4_tx_clk(qsfp0_tx_clk_4_int), + .phy_4_tx_rst(qsfp0_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp0_txd_4_int), + .phy_4_xgmii_txc(qsfp0_txc_4_int), + .phy_4_rx_clk(qsfp0_rx_clk_4_int), + .phy_4_rx_rst(qsfp0_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp0_rxd_4_int), + .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp0_rx_error_count_4_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp0_rx_status_4), + .phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int), + .phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int) +); + +// QSFP1 +wire qsfp1_tx_clk_1_int; +wire qsfp1_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int; +wire qsfp1_tx_prbs31_enable_1_int; +wire qsfp1_rx_clk_1_int; +wire qsfp1_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int; +wire qsfp1_rx_prbs31_enable_1_int; +wire [6:0] qsfp1_rx_error_count_1_int; +wire qsfp1_tx_clk_2_int; +wire qsfp1_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int; +wire qsfp1_tx_prbs31_enable_2_int; +wire qsfp1_rx_clk_2_int; +wire qsfp1_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int; +wire qsfp1_rx_prbs31_enable_2_int; +wire [6:0] qsfp1_rx_error_count_2_int; +wire qsfp1_tx_clk_3_int; +wire qsfp1_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int; +wire qsfp1_tx_prbs31_enable_3_int; +wire qsfp1_rx_clk_3_int; +wire qsfp1_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int; +wire qsfp1_rx_prbs31_enable_3_int; +wire [6:0] qsfp1_rx_error_count_3_int; +wire qsfp1_tx_clk_4_int; +wire qsfp1_tx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int; +wire qsfp1_tx_prbs31_enable_4_int; +wire qsfp1_rx_clk_4_int; +wire qsfp1_rx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int; +wire qsfp1_rx_prbs31_enable_4_int; +wire [6:0] qsfp1_rx_error_count_4_int; + +wire qsfp1_drp_clk = clk_125mhz_int; +wire qsfp1_drp_rst = rst_125mhz_int; +wire [23:0] qsfp1_drp_addr; +wire [15:0] qsfp1_drp_di; +wire qsfp1_drp_en; +wire qsfp1_drp_we; +wire [15:0] qsfp1_drp_do; +wire qsfp1_drp_rdy; + +wire qsfp1_rx_block_lock_1; +wire qsfp1_rx_status_1; +wire qsfp1_rx_block_lock_2; +wire qsfp1_rx_status_2; +wire qsfp1_rx_block_lock_3; +wire qsfp1_rx_status_3; +wire qsfp1_rx_block_lock_4; +wire qsfp1_rx_status_4; + +wire qsfp1_gtpowergood; + +wire qsfp1_mgt_refclk_b0; +wire qsfp1_mgt_refclk_b0_int; +wire qsfp1_mgt_refclk_b0_bufg; + +IBUFDS_GTE3 ibufds_gte3_qsfp1_mgt_refclk_b0_inst ( + .I (qsfp1_mgt_refclk_b0_p), + .IB (qsfp1_mgt_refclk_b0_n), + .CEB (1'b0), + .O (qsfp1_mgt_refclk_b0), + .ODIV2 (qsfp1_mgt_refclk_b0_int) +); + +BUFG_GT bufg_gt_qsfp1_mgt_refclk_b0_inst ( + .CE (qsfp1_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp1_mgt_refclk_b0_int), + .O (qsfp1_mgt_refclk_b0_bufg) +); + +wire qsfp1_rst; + +sync_reset #( + .N(4) +) +qsfp1_sync_reset_inst ( + .clk(qsfp1_mgt_refclk_b0_bufg), + .rst(rst_125mhz_int), + .out(qsfp1_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp1_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp1_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp1_gtpowergood), + .xcvr_ref_clk(qsfp1_mgt_refclk_b0), + + /* + * DRP + */ + .drp_clk(qsfp1_drp_clk), + .drp_rst(qsfp1_drp_rst), + .drp_addr(qsfp1_drp_addr), + .drp_di(qsfp1_drp_di), + .drp_en(qsfp1_drp_en), + .drp_we(qsfp1_drp_we), + .drp_do(qsfp1_drp_do), + .drp_rdy(qsfp1_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}), + .xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}), + .xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}), + .xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp1_rx_error_count_1_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp1_rx_status_1), + .phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int), + .phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int), + + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp1_rx_error_count_2_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp1_rx_status_2), + .phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int), + .phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int), + + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp1_rx_error_count_3_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp1_rx_status_3), + .phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int), + .phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int), + + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp1_rx_error_count_4_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp1_rx_status_4), + .phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int), + .phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int) +); + +// QSFP2 +wire qsfp2_tx_clk_1_int; +wire qsfp2_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1_int; +wire qsfp2_tx_prbs31_enable_1_int; +wire qsfp2_rx_clk_1_int; +wire qsfp2_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1_int; +wire qsfp2_rx_prbs31_enable_1_int; +wire [6:0] qsfp2_rx_error_count_1_int; +wire qsfp2_tx_clk_2_int; +wire qsfp2_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2_int; +wire qsfp2_tx_prbs31_enable_2_int; +wire qsfp2_rx_clk_2_int; +wire qsfp2_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2_int; +wire qsfp2_rx_prbs31_enable_2_int; +wire [6:0] qsfp2_rx_error_count_2_int; +wire qsfp2_tx_clk_3_int; +wire qsfp2_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3_int; +wire qsfp2_tx_prbs31_enable_3_int; +wire qsfp2_rx_clk_3_int; +wire qsfp2_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3_int; +wire qsfp2_rx_prbs31_enable_3_int; +wire [6:0] qsfp2_rx_error_count_3_int; +wire qsfp2_tx_clk_4_int; +wire qsfp2_tx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4_int; +wire qsfp2_tx_prbs31_enable_4_int; +wire qsfp2_rx_clk_4_int; +wire qsfp2_rx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4_int; +wire qsfp2_rx_prbs31_enable_4_int; +wire [6:0] qsfp2_rx_error_count_4_int; + +wire qsfp2_drp_clk = clk_125mhz_int; +wire qsfp2_drp_rst = rst_125mhz_int; +wire [23:0] qsfp2_drp_addr; +wire [15:0] qsfp2_drp_di; +wire qsfp2_drp_en; +wire qsfp2_drp_we; +wire [15:0] qsfp2_drp_do; +wire qsfp2_drp_rdy; + +wire qsfp2_rx_block_lock_1; +wire qsfp2_rx_status_1; +wire qsfp2_rx_block_lock_2; +wire qsfp2_rx_status_2; +wire qsfp2_rx_block_lock_3; +wire qsfp2_rx_status_3; +wire qsfp2_rx_block_lock_4; +wire qsfp2_rx_status_4; + +wire qsfp2_gtpowergood; + +wire qsfp2_mgt_refclk_b0; +wire qsfp2_mgt_refclk_b0_int; +wire qsfp2_mgt_refclk_b0_bufg; + +IBUFDS_GTE3 ibufds_gte3_qsfp2_mgt_refclk_b0_inst ( + .I (qsfp2_mgt_refclk_b0_p), + .IB (qsfp2_mgt_refclk_b0_n), + .CEB (1'b0), + .O (qsfp2_mgt_refclk_b0), + .ODIV2 (qsfp2_mgt_refclk_b0_int) +); + +BUFG_GT bufg_gt_qsfp2_mgt_refclk_b0_inst ( + .CE (qsfp2_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp2_mgt_refclk_b0_int), + .O (qsfp2_mgt_refclk_b0_bufg) +); + +wire qsfp2_rst; + +sync_reset #( + .N(4) +) +qsfp2_sync_reset_inst ( + .clk(qsfp2_mgt_refclk_b0_bufg), + .rst(rst_125mhz_int), + .out(qsfp2_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp2_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp2_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp2_gtpowergood), + .xcvr_ref_clk(qsfp2_mgt_refclk_b0), + + /* + * DRP + */ + .drp_clk(qsfp2_drp_clk), + .drp_rst(qsfp2_drp_rst), + .drp_addr(qsfp2_drp_addr), + .drp_di(qsfp2_drp_di), + .drp_en(qsfp2_drp_en), + .drp_we(qsfp2_drp_we), + .drp_do(qsfp2_drp_do), + .drp_rdy(qsfp2_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p}), + .xcvr_txn({qsfp2_tx4_n, qsfp2_tx3_n, qsfp2_tx2_n, qsfp2_tx1_n}), + .xcvr_rxp({qsfp2_rx4_p, qsfp2_rx3_p, qsfp2_rx2_p, qsfp2_rx1_p}), + .xcvr_rxn({qsfp2_rx4_n, qsfp2_rx3_n, qsfp2_rx2_n, qsfp2_rx1_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp2_tx_clk_1_int), + .phy_1_tx_rst(qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp2_txd_1_int), + .phy_1_xgmii_txc(qsfp2_txc_1_int), + .phy_1_rx_clk(qsfp2_rx_clk_1_int), + .phy_1_rx_rst(qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp2_rx_error_count_1_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp2_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp2_rx_status_1), + .phy_1_tx_prbs31_enable(qsfp2_tx_prbs31_enable_1_int), + .phy_1_rx_prbs31_enable(qsfp2_rx_prbs31_enable_1_int), + + .phy_2_tx_clk(qsfp2_tx_clk_2_int), + .phy_2_tx_rst(qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp2_txd_2_int), + .phy_2_xgmii_txc(qsfp2_txc_2_int), + .phy_2_rx_clk(qsfp2_rx_clk_2_int), + .phy_2_rx_rst(qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp2_rx_error_count_2_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp2_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp2_rx_status_2), + .phy_2_tx_prbs31_enable(qsfp2_tx_prbs31_enable_2_int), + .phy_2_rx_prbs31_enable(qsfp2_rx_prbs31_enable_2_int), + + .phy_3_tx_clk(qsfp2_tx_clk_3_int), + .phy_3_tx_rst(qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp2_txd_3_int), + .phy_3_xgmii_txc(qsfp2_txc_3_int), + .phy_3_rx_clk(qsfp2_rx_clk_3_int), + .phy_3_rx_rst(qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp2_rx_error_count_3_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp2_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp2_rx_status_3), + .phy_3_tx_prbs31_enable(qsfp2_tx_prbs31_enable_3_int), + .phy_3_rx_prbs31_enable(qsfp2_rx_prbs31_enable_3_int), + + .phy_4_tx_clk(qsfp2_tx_clk_4_int), + .phy_4_tx_rst(qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp2_txd_4_int), + .phy_4_xgmii_txc(qsfp2_txc_4_int), + .phy_4_rx_clk(qsfp2_rx_clk_4_int), + .phy_4_rx_rst(qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp2_rx_error_count_4_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp2_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp2_rx_status_4), + .phy_4_tx_prbs31_enable(qsfp2_tx_prbs31_enable_4_int), + .phy_4_rx_prbs31_enable(qsfp2_rx_prbs31_enable_4_int) +); + +// QSFP3 +wire qsfp3_tx_clk_1_int; +wire qsfp3_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1_int; +wire qsfp3_tx_prbs31_enable_1_int; +wire qsfp3_rx_clk_1_int; +wire qsfp3_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1_int; +wire qsfp3_rx_prbs31_enable_1_int; +wire [6:0] qsfp3_rx_error_count_1_int; +wire qsfp3_tx_clk_2_int; +wire qsfp3_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2_int; +wire qsfp3_tx_prbs31_enable_2_int; +wire qsfp3_rx_clk_2_int; +wire qsfp3_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2_int; +wire qsfp3_rx_prbs31_enable_2_int; +wire [6:0] qsfp3_rx_error_count_2_int; +wire qsfp3_tx_clk_3_int; +wire qsfp3_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3_int; +wire qsfp3_tx_prbs31_enable_3_int; +wire qsfp3_rx_clk_3_int; +wire qsfp3_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3_int; +wire qsfp3_rx_prbs31_enable_3_int; +wire [6:0] qsfp3_rx_error_count_3_int; +wire qsfp3_tx_clk_4_int; +wire qsfp3_tx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4_int; +wire qsfp3_tx_prbs31_enable_4_int; +wire qsfp3_rx_clk_4_int; +wire qsfp3_rx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4_int; +wire qsfp3_rx_prbs31_enable_4_int; +wire [6:0] qsfp3_rx_error_count_4_int; + +wire qsfp3_drp_clk = clk_125mhz_int; +wire qsfp3_drp_rst = rst_125mhz_int; +wire [23:0] qsfp3_drp_addr; +wire [15:0] qsfp3_drp_di; +wire qsfp3_drp_en; +wire qsfp3_drp_we; +wire [15:0] qsfp3_drp_do; +wire qsfp3_drp_rdy; + +wire qsfp3_rx_block_lock_1; +wire qsfp3_rx_status_1; +wire qsfp3_rx_block_lock_2; +wire qsfp3_rx_status_2; +wire qsfp3_rx_block_lock_3; +wire qsfp3_rx_status_3; +wire qsfp3_rx_block_lock_4; +wire qsfp3_rx_status_4; + +wire qsfp3_gtpowergood; + +wire qsfp3_mgt_refclk_b0; +wire qsfp3_mgt_refclk_b0_int; +wire qsfp3_mgt_refclk_b0_bufg; + +IBUFDS_GTE3 ibufds_gte3_qsfp3_mgt_refclk_b0_inst ( + .I (qsfp3_mgt_refclk_b0_p), + .IB (qsfp3_mgt_refclk_b0_n), + .CEB (1'b0), + .O (qsfp3_mgt_refclk_b0), + .ODIV2 (qsfp3_mgt_refclk_b0_int) +); + +BUFG_GT bufg_gt_qsfp3_mgt_refclk_b0_inst ( + .CE (qsfp3_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp3_mgt_refclk_b0_int), + .O (qsfp3_mgt_refclk_b0_bufg) +); + +wire qsfp3_rst; + +sync_reset #( + .N(4) +) +qsfp3_sync_reset_inst ( + .clk(qsfp3_mgt_refclk_b0_bufg), + .rst(rst_125mhz_int), + .out(qsfp3_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp3_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp3_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp3_gtpowergood), + .xcvr_ref_clk(qsfp3_mgt_refclk_b0), + + /* + * DRP + */ + .drp_clk(qsfp3_drp_clk), + .drp_rst(qsfp3_drp_rst), + .drp_addr(qsfp3_drp_addr), + .drp_di(qsfp3_drp_di), + .drp_en(qsfp3_drp_en), + .drp_we(qsfp3_drp_we), + .drp_do(qsfp3_drp_do), + .drp_rdy(qsfp3_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({qsfp3_tx4_p, qsfp3_tx3_p, qsfp3_tx2_p, qsfp3_tx1_p}), + .xcvr_txn({qsfp3_tx4_n, qsfp3_tx3_n, qsfp3_tx2_n, qsfp3_tx1_n}), + .xcvr_rxp({qsfp3_rx4_p, qsfp3_rx3_p, qsfp3_rx2_p, qsfp3_rx1_p}), + .xcvr_rxn({qsfp3_rx4_n, qsfp3_rx3_n, qsfp3_rx2_n, qsfp3_rx1_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp3_tx_clk_1_int), + .phy_1_tx_rst(qsfp3_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp3_txd_1_int), + .phy_1_xgmii_txc(qsfp3_txc_1_int), + .phy_1_rx_clk(qsfp3_rx_clk_1_int), + .phy_1_rx_rst(qsfp3_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp3_rxd_1_int), + .phy_1_xgmii_rxc(qsfp3_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp3_rx_error_count_1_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp3_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp3_rx_status_1), + .phy_1_tx_prbs31_enable(qsfp3_tx_prbs31_enable_1_int), + .phy_1_rx_prbs31_enable(qsfp3_rx_prbs31_enable_1_int), + + .phy_2_tx_clk(qsfp3_tx_clk_2_int), + .phy_2_tx_rst(qsfp3_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp3_txd_2_int), + .phy_2_xgmii_txc(qsfp3_txc_2_int), + .phy_2_rx_clk(qsfp3_rx_clk_2_int), + .phy_2_rx_rst(qsfp3_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp3_rxd_2_int), + .phy_2_xgmii_rxc(qsfp3_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp3_rx_error_count_2_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp3_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp3_rx_status_2), + .phy_2_tx_prbs31_enable(qsfp3_tx_prbs31_enable_2_int), + .phy_2_rx_prbs31_enable(qsfp3_rx_prbs31_enable_2_int), + + .phy_3_tx_clk(qsfp3_tx_clk_3_int), + .phy_3_tx_rst(qsfp3_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp3_txd_3_int), + .phy_3_xgmii_txc(qsfp3_txc_3_int), + .phy_3_rx_clk(qsfp3_rx_clk_3_int), + .phy_3_rx_rst(qsfp3_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp3_rxd_3_int), + .phy_3_xgmii_rxc(qsfp3_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp3_rx_error_count_3_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp3_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp3_rx_status_3), + .phy_3_tx_prbs31_enable(qsfp3_tx_prbs31_enable_3_int), + .phy_3_rx_prbs31_enable(qsfp3_rx_prbs31_enable_3_int), + + .phy_4_tx_clk(qsfp3_tx_clk_4_int), + .phy_4_tx_rst(qsfp3_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp3_txd_4_int), + .phy_4_xgmii_txc(qsfp3_txc_4_int), + .phy_4_rx_clk(qsfp3_rx_clk_4_int), + .phy_4_rx_rst(qsfp3_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp3_rxd_4_int), + .phy_4_xgmii_rxc(qsfp3_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp3_rx_error_count_4_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp3_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp3_rx_status_4), + .phy_4_tx_prbs31_enable(qsfp3_tx_prbs31_enable_4_int), + .phy_4_rx_prbs31_enable(qsfp3_rx_prbs31_enable_4_int) +); + +wire ptp_clk; +wire ptp_rst; +wire ptp_sample_clk; + +assign ptp_clk = qsfp0_mgt_refclk_b0_bufg; +assign ptp_rst = qsfp0_rst; +assign ptp_sample_clk = clk_125mhz_int; + +assign led[0] = qsfp0_rx_block_lock_1; +assign led[1] = qsfp1_rx_block_lock_1; +assign led[2] = qsfp2_rx_block_lock_1; +assign led[3] = qsfp3_rx_block_lock_1; + +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +assign ddr4_a_par = 1'b0; + +if (DDR_ENABLE && DDR_CH > 0) begin + +reg ddr4_rst_reg = 1'b1; + +always @(posedge pcie_user_clk or posedge pcie_user_reset) begin + if (pcie_user_reset) begin + ddr4_rst_reg <= 1'b1; + end else begin + ddr4_rst_reg <= 1'b0; + end +end + +ddr4_0 ddr4_a_inst ( + .c0_sys_clk_p(clk_ddr_a_p), + .c0_sys_clk_n(clk_ddr_a_n), + .sys_rst(ddr4_rst_reg), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_a_adr), + .c0_ddr4_ba(ddr4_a_ba), + .c0_ddr4_cke(ddr4_a_cke), + .c0_ddr4_cs_n(ddr4_a_cs_n), + .c0_ddr4_dq(ddr4_a_dq), + .c0_ddr4_dqs_t(ddr4_a_dqs_t), + .c0_ddr4_dqs_c(ddr4_a_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_a_dm_dbi_n), + .c0_ddr4_odt(ddr4_a_odt), + .c0_ddr4_bg(ddr4_a_bg), + .c0_ddr4_reset_n(ddr4_a_reset_n), + .c0_ddr4_act_n(ddr4_a_act_n), + .c0_ddr4_ck_t(ddr4_a_ck_t), + .c0_ddr4_ck_c(ddr4_a_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_a_adr = {17{1'bz}}; +assign ddr4_a_ba = {2{1'bz}}; +assign ddr4_a_bg = {2{1'bz}}; +assign ddr4_a_cke = 1'bz; +assign ddr4_a_cs_n = 1'bz; +assign ddr4_a_act_n = 1'bz; +assign ddr4_a_odt = 1'bz; +assign ddr4_a_reset_n = 1'b0; +assign ddr4_a_dq = {72{1'bz}}; +assign ddr4_a_dqs_t = {9{1'bz}}; +assign ddr4_a_dqs_c = {9{1'bz}}; +assign ddr4_a_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_a_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_a_ck_t), + .OB(ddr4_a_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_b_par = 1'b0; + +if (DDR_ENABLE && DDR_CH > 1) begin + +reg ddr4_rst_reg = 1'b1; + +always @(posedge pcie_user_clk or posedge pcie_user_reset) begin + if (pcie_user_reset) begin + ddr4_rst_reg <= 1'b1; + end else begin + ddr4_rst_reg <= 1'b0; + end +end + +ddr4_0 ddr4_b_inst ( + .c0_sys_clk_p(clk_ddr_b_p), + .c0_sys_clk_n(clk_ddr_b_n), + .sys_rst(ddr4_rst_reg), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_b_adr), + .c0_ddr4_ba(ddr4_b_ba), + .c0_ddr4_cke(ddr4_b_cke), + .c0_ddr4_cs_n(ddr4_b_cs_n), + .c0_ddr4_dq(ddr4_b_dq), + .c0_ddr4_dqs_t(ddr4_b_dqs_t), + .c0_ddr4_dqs_c(ddr4_b_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_b_dm_dbi_n), + .c0_ddr4_odt(ddr4_b_odt), + .c0_ddr4_bg(ddr4_b_bg), + .c0_ddr4_reset_n(ddr4_b_reset_n), + .c0_ddr4_act_n(ddr4_b_act_n), + .c0_ddr4_ck_t(ddr4_b_ck_t), + .c0_ddr4_ck_c(ddr4_b_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_b_adr = {17{1'bz}}; +assign ddr4_b_ba = {2{1'bz}}; +assign ddr4_b_bg = {2{1'bz}}; +assign ddr4_b_cke = 1'bz; +assign ddr4_b_cs_n = 1'bz; +assign ddr4_b_act_n = 1'bz; +assign ddr4_b_odt = 1'bz; +assign ddr4_b_reset_n = 1'b0; +assign ddr4_b_dq = {72{1'bz}}; +assign ddr4_b_dqs_t = {9{1'bz}}; +assign ddr4_b_dqs_c = {9{1'bz}}; +assign ddr4_b_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_b_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_b_ck_t), + .OB(ddr4_b_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +reg ddr4_rst_reg = 1'b1; + +always @(posedge pcie_user_clk or posedge pcie_user_reset) begin + if (pcie_user_reset) begin + ddr4_rst_reg <= 1'b1; + end else begin + ddr4_rst_reg <= 1'b0; + end +end + +assign ddr4_sodimm1_par = 1'b0; + +ddr4_sodimm_0 ddr4_sodimm1_inst ( + .c0_sys_clk_p(clk_ddr_sodimm1_p), + .c0_sys_clk_n(clk_ddr_sodimm1_n), + .sys_rst(ddr4_rst_reg), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + // .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_sodimm1_adr), + .c0_ddr4_ba(ddr4_sodimm1_ba), + .c0_ddr4_cke(ddr4_sodimm1_cke), + .c0_ddr4_cs_n(ddr4_sodimm1_cs_n), + .c0_ddr4_dq(ddr4_sodimm1_dq), + .c0_ddr4_dqs_t(ddr4_sodimm1_dqs_t), + .c0_ddr4_dqs_c(ddr4_sodimm1_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_sodimm1_dm_dbi_n), + .c0_ddr4_odt(ddr4_sodimm1_odt), + // .c0_ddr4_parity(ddr4_sodimm1_par), + .c0_ddr4_bg(ddr4_sodimm1_bg), + .c0_ddr4_reset_n(ddr4_sodimm1_reset_n), + .c0_ddr4_act_n(ddr4_sodimm1_act_n), + .c0_ddr4_ck_t(ddr4_sodimm1_ck_t), + .c0_ddr4_ck_c(ddr4_sodimm1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + // .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + // .c0_ddr4_s_axi_ctrl_awready(), + // .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + // .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + // .c0_ddr4_s_axi_ctrl_wready(), + // .c0_ddr4_s_axi_ctrl_wdata(32'd0), + // .c0_ddr4_s_axi_ctrl_bvalid(), + // .c0_ddr4_s_axi_ctrl_bready(1'b1), + // .c0_ddr4_s_axi_ctrl_bresp(), + // .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + // .c0_ddr4_s_axi_ctrl_arready(), + // .c0_ddr4_s_axi_ctrl_araddr(31'd0), + // .c0_ddr4_s_axi_ctrl_rvalid(), + // .c0_ddr4_s_axi_ctrl_rready(1'b1), + // .c0_ddr4_s_axi_ctrl_rdata(), + // .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_sodimm1_adr = {17{1'bz}}; +assign ddr4_sodimm1_ba = {2{1'bz}}; +assign ddr4_sodimm1_bg = {2{1'bz}}; +assign ddr4_sodimm1_cke = 1'bz; +assign ddr4_sodimm1_cs_n = 1'bz; +assign ddr4_sodimm1_act_n = 1'bz; +assign ddr4_sodimm1_odt = 1'bz; +assign ddr4_sodimm1_par = 1'bz; +assign ddr4_sodimm1_reset_n = 1'b0; +assign ddr4_sodimm1_dq = {64{1'bz}}; +assign ddr4_sodimm1_dqs_t = {8{1'bz}}; +assign ddr4_sodimm1_dqs_c = {8{1'bz}}; +assign ddr4_sodimm1_dm_dbi_n = {8{1'bz}}; + +OBUFTDS ddr4_sodimm1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_sodimm1_ck_t), + .OB(ddr4_sodimm1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +reg ddr4_rst_reg = 1'b1; + +always @(posedge pcie_user_clk or posedge pcie_user_reset) begin + if (pcie_user_reset) begin + ddr4_rst_reg <= 1'b1; + end else begin + ddr4_rst_reg <= 1'b0; + end +end + +assign ddr4_sodimm2_par = 1'b0; + +ddr4_sodimm_0 ddr4_sodimm2_inst ( + .c0_sys_clk_p(clk_ddr_sodimm2_p), + .c0_sys_clk_n(clk_ddr_sodimm2_n), + .sys_rst(ddr4_rst_reg), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + // .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_sodimm2_adr), + .c0_ddr4_ba(ddr4_sodimm2_ba), + .c0_ddr4_cke(ddr4_sodimm2_cke), + .c0_ddr4_cs_n(ddr4_sodimm2_cs_n), + .c0_ddr4_dq(ddr4_sodimm2_dq), + .c0_ddr4_dqs_t(ddr4_sodimm2_dqs_t), + .c0_ddr4_dqs_c(ddr4_sodimm2_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_sodimm2_dm_dbi_n), + .c0_ddr4_odt(ddr4_sodimm2_odt), + // .c0_ddr4_parity(ddr4_sodimm2_par), + .c0_ddr4_bg(ddr4_sodimm2_bg), + .c0_ddr4_reset_n(ddr4_sodimm2_reset_n), + .c0_ddr4_act_n(ddr4_sodimm2_act_n), + .c0_ddr4_ck_t(ddr4_sodimm2_ck_t), + .c0_ddr4_ck_c(ddr4_sodimm2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + // .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + // .c0_ddr4_s_axi_ctrl_awready(), + // .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + // .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + // .c0_ddr4_s_axi_ctrl_wready(), + // .c0_ddr4_s_axi_ctrl_wdata(32'd0), + // .c0_ddr4_s_axi_ctrl_bvalid(), + // .c0_ddr4_s_axi_ctrl_bready(1'b1), + // .c0_ddr4_s_axi_ctrl_bresp(), + // .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + // .c0_ddr4_s_axi_ctrl_arready(), + // .c0_ddr4_s_axi_ctrl_araddr(31'd0), + // .c0_ddr4_s_axi_ctrl_rvalid(), + // .c0_ddr4_s_axi_ctrl_rready(1'b1), + // .c0_ddr4_s_axi_ctrl_rdata(), + // .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_sodimm2_adr = {17{1'bz}}; +assign ddr4_sodimm2_ba = {2{1'bz}}; +assign ddr4_sodimm2_bg = {2{1'bz}}; +assign ddr4_sodimm2_cke = 1'bz; +assign ddr4_sodimm2_cs_n = 1'bz; +assign ddr4_sodimm2_act_n = 1'bz; +assign ddr4_sodimm2_odt = 1'bz; +assign ddr4_sodimm2_par = 1'bz; +assign ddr4_sodimm2_reset_n = 1'b0; +assign ddr4_sodimm2_dq = {64{1'bz}}; +assign ddr4_sodimm2_dqs_t = {8{1'bz}}; +assign ddr4_sodimm2_dqs_c = {8{1'bz}}; +assign ddr4_sodimm2_dm_dbi_n = {8{1'bz}}; + +OBUFTDS ddr4_sodimm2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_sodimm2_ck_t), + .OB(ddr4_sodimm2_ck_c) +); + +end + +endgenerate + +fpga_core #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + .PORT_MASK(PORT_MASK), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RC_STRADDLE(RC_STRADDLE), + .RQ_STRADDLE(RQ_STRADDLE), + .CQ_STRADDLE(CQ_STRADDLE), + .CC_STRADDLE(CC_STRADDLE), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + /* + * Clock: 250 MHz + * Synchronous reset + */ + .clk_250mhz(pcie_user_clk), + .rst_250mhz(pcie_user_reset), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + + /* + * GPIO + */ + // .led(led), + .ext_pps_in(ext_pps_in), + .ext_clk_in(ext_clk_in), + + /* + * I2C + */ + .eeprom_i2c_scl_i(eeprom_i2c_scl_i), + .eeprom_i2c_scl_o(eeprom_i2c_scl_o), + .eeprom_i2c_scl_t(eeprom_i2c_scl_t), + .eeprom_i2c_sda_i(eeprom_i2c_sda_i), + .eeprom_i2c_sda_o(eeprom_i2c_sda_o), + .eeprom_i2c_sda_t(eeprom_i2c_sda_t), + + /* + * PCIe + */ + .m_axis_rq_tdata(axis_rq_tdata), + .m_axis_rq_tkeep(axis_rq_tkeep), + .m_axis_rq_tlast(axis_rq_tlast), + .m_axis_rq_tready(axis_rq_tready), + .m_axis_rq_tuser(axis_rq_tuser), + .m_axis_rq_tvalid(axis_rq_tvalid), + + .s_axis_rc_tdata(axis_rc_tdata), + .s_axis_rc_tkeep(axis_rc_tkeep), + .s_axis_rc_tlast(axis_rc_tlast), + .s_axis_rc_tready(axis_rc_tready), + .s_axis_rc_tuser(axis_rc_tuser), + .s_axis_rc_tvalid(axis_rc_tvalid), + + .s_axis_cq_tdata(axis_cq_tdata), + .s_axis_cq_tkeep(axis_cq_tkeep), + .s_axis_cq_tlast(axis_cq_tlast), + .s_axis_cq_tready(axis_cq_tready), + .s_axis_cq_tuser(axis_cq_tuser), + .s_axis_cq_tvalid(axis_cq_tvalid), + + .m_axis_cc_tdata(axis_cc_tdata), + .m_axis_cc_tkeep(axis_cc_tkeep), + .m_axis_cc_tlast(axis_cc_tlast), + .m_axis_cc_tready(axis_cc_tready), + .m_axis_cc_tuser(axis_cc_tuser), + .m_axis_cc_tvalid(axis_cc_tvalid), + + .s_axis_rq_seq_num(pcie_rq_seq_num), + .s_axis_rq_seq_num_valid(pcie_rq_seq_num_vld), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * Ethernet: QSFP28 + */ + .qsfp0_tx_clk_1(qsfp0_tx_clk_1_int), + .qsfp0_tx_rst_1(qsfp0_tx_rst_1_int), + .qsfp0_txd_1(qsfp0_txd_1_int), + .qsfp0_txc_1(qsfp0_txc_1_int), + .qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int), + .qsfp0_rx_clk_1(qsfp0_rx_clk_1_int), + .qsfp0_rx_rst_1(qsfp0_rx_rst_1_int), + .qsfp0_rxd_1(qsfp0_rxd_1_int), + .qsfp0_rxc_1(qsfp0_rxc_1_int), + .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int), + .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int), + .qsfp0_rx_status_1(qsfp0_rx_status_1), + .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int), + .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int), + .qsfp0_txd_2(qsfp0_txd_2_int), + .qsfp0_txc_2(qsfp0_txc_2_int), + .qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int), + .qsfp0_rx_clk_2(qsfp0_rx_clk_2_int), + .qsfp0_rx_rst_2(qsfp0_rx_rst_2_int), + .qsfp0_rxd_2(qsfp0_rxd_2_int), + .qsfp0_rxc_2(qsfp0_rxc_2_int), + .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int), + .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int), + .qsfp0_rx_status_2(qsfp0_rx_status_2), + .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int), + .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int), + .qsfp0_txd_3(qsfp0_txd_3_int), + .qsfp0_txc_3(qsfp0_txc_3_int), + .qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int), + .qsfp0_rx_clk_3(qsfp0_rx_clk_3_int), + .qsfp0_rx_rst_3(qsfp0_rx_rst_3_int), + .qsfp0_rxd_3(qsfp0_rxd_3_int), + .qsfp0_rxc_3(qsfp0_rxc_3_int), + .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int), + .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int), + .qsfp0_rx_status_3(qsfp0_rx_status_3), + .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int), + .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int), + .qsfp0_txd_4(qsfp0_txd_4_int), + .qsfp0_txc_4(qsfp0_txc_4_int), + .qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int), + .qsfp0_rx_clk_4(qsfp0_rx_clk_4_int), + .qsfp0_rx_rst_4(qsfp0_rx_rst_4_int), + .qsfp0_rxd_4(qsfp0_rxd_4_int), + .qsfp0_rxc_4(qsfp0_rxc_4_int), + .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int), + .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int), + .qsfp0_rx_status_4(qsfp0_rx_status_4), + + .qsfp0_drp_clk(qsfp0_drp_clk), + .qsfp0_drp_rst(qsfp0_drp_rst), + .qsfp0_drp_addr(qsfp0_drp_addr), + .qsfp0_drp_di(qsfp0_drp_di), + .qsfp0_drp_en(qsfp0_drp_en), + .qsfp0_drp_we(qsfp0_drp_we), + .qsfp0_drp_do(qsfp0_drp_do), + .qsfp0_drp_rdy(qsfp0_drp_rdy), + + .qsfp0_modprsl(qsfp0_modprsl_int), + .qsfp0_resetl(qsfp0_resetl), + .qsfp0_intl(qsfp0_intl_int), + .qsfp0_lpmode(qsfp0_lpmode), + + .qsfp0_i2c_scl_i(qsfp0_i2c_scl_i), + .qsfp0_i2c_scl_o(qsfp0_i2c_scl_o), + .qsfp0_i2c_scl_t(qsfp0_i2c_scl_t), + .qsfp0_i2c_sda_i(qsfp0_i2c_sda_i), + .qsfp0_i2c_sda_o(qsfp0_i2c_sda_o), + .qsfp0_i2c_sda_t(qsfp0_i2c_sda_t), + + .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), + .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), + .qsfp1_txd_1(qsfp1_txd_1_int), + .qsfp1_txc_1(qsfp1_txc_1_int), + .qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int), + .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), + .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), + .qsfp1_rxd_1(qsfp1_rxd_1_int), + .qsfp1_rxc_1(qsfp1_rxc_1_int), + .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int), + .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int), + .qsfp1_rx_status_1(qsfp1_rx_status_1), + .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), + .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), + .qsfp1_txd_2(qsfp1_txd_2_int), + .qsfp1_txc_2(qsfp1_txc_2_int), + .qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int), + .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), + .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), + .qsfp1_rxd_2(qsfp1_rxd_2_int), + .qsfp1_rxc_2(qsfp1_rxc_2_int), + .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int), + .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int), + .qsfp1_rx_status_2(qsfp1_rx_status_2), + .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), + .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), + .qsfp1_txd_3(qsfp1_txd_3_int), + .qsfp1_txc_3(qsfp1_txc_3_int), + .qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int), + .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), + .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), + .qsfp1_rxd_3(qsfp1_rxd_3_int), + .qsfp1_rxc_3(qsfp1_rxc_3_int), + .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int), + .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int), + .qsfp1_rx_status_3(qsfp1_rx_status_3), + .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), + .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), + .qsfp1_txd_4(qsfp1_txd_4_int), + .qsfp1_txc_4(qsfp1_txc_4_int), + .qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int), + .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), + .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), + .qsfp1_rxd_4(qsfp1_rxd_4_int), + .qsfp1_rxc_4(qsfp1_rxc_4_int), + .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int), + .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int), + .qsfp1_rx_status_4(qsfp1_rx_status_4), + + .qsfp1_drp_clk(qsfp1_drp_clk), + .qsfp1_drp_rst(qsfp1_drp_rst), + .qsfp1_drp_addr(qsfp1_drp_addr), + .qsfp1_drp_di(qsfp1_drp_di), + .qsfp1_drp_en(qsfp1_drp_en), + .qsfp1_drp_we(qsfp1_drp_we), + .qsfp1_drp_do(qsfp1_drp_do), + .qsfp1_drp_rdy(qsfp1_drp_rdy), + + .qsfp1_modprsl(qsfp1_modprsl_int), + .qsfp1_resetl(qsfp1_resetl), + .qsfp1_intl(qsfp1_intl_int), + .qsfp1_lpmode(qsfp1_lpmode), + + .qsfp1_i2c_scl_i(qsfp1_i2c_scl_i), + .qsfp1_i2c_scl_o(qsfp1_i2c_scl_o), + .qsfp1_i2c_scl_t(qsfp1_i2c_scl_t), + .qsfp1_i2c_sda_i(qsfp1_i2c_sda_i), + .qsfp1_i2c_sda_o(qsfp1_i2c_sda_o), + .qsfp1_i2c_sda_t(qsfp1_i2c_sda_t), + + .qsfp2_tx_clk_1(qsfp2_tx_clk_1_int), + .qsfp2_tx_rst_1(qsfp2_tx_rst_1_int), + .qsfp2_txd_1(qsfp2_txd_1_int), + .qsfp2_txc_1(qsfp2_txc_1_int), + .qsfp2_tx_prbs31_enable_1(qsfp2_tx_prbs31_enable_1_int), + .qsfp2_rx_clk_1(qsfp2_rx_clk_1_int), + .qsfp2_rx_rst_1(qsfp2_rx_rst_1_int), + .qsfp2_rxd_1(qsfp2_rxd_1_int), + .qsfp2_rxc_1(qsfp2_rxc_1_int), + .qsfp2_rx_prbs31_enable_1(qsfp2_rx_prbs31_enable_1_int), + .qsfp2_rx_error_count_1(qsfp2_rx_error_count_1_int), + .qsfp2_rx_status_1(qsfp2_rx_status_1), + .qsfp2_tx_clk_2(qsfp2_tx_clk_2_int), + .qsfp2_tx_rst_2(qsfp2_tx_rst_2_int), + .qsfp2_txd_2(qsfp2_txd_2_int), + .qsfp2_txc_2(qsfp2_txc_2_int), + .qsfp2_tx_prbs31_enable_2(qsfp2_tx_prbs31_enable_2_int), + .qsfp2_rx_clk_2(qsfp2_rx_clk_2_int), + .qsfp2_rx_rst_2(qsfp2_rx_rst_2_int), + .qsfp2_rxd_2(qsfp2_rxd_2_int), + .qsfp2_rxc_2(qsfp2_rxc_2_int), + .qsfp2_rx_prbs31_enable_2(qsfp2_rx_prbs31_enable_2_int), + .qsfp2_rx_error_count_2(qsfp2_rx_error_count_2_int), + .qsfp2_rx_status_2(qsfp2_rx_status_2), + .qsfp2_tx_clk_3(qsfp2_tx_clk_3_int), + .qsfp2_tx_rst_3(qsfp2_tx_rst_3_int), + .qsfp2_txd_3(qsfp2_txd_3_int), + .qsfp2_txc_3(qsfp2_txc_3_int), + .qsfp2_tx_prbs31_enable_3(qsfp2_tx_prbs31_enable_3_int), + .qsfp2_rx_clk_3(qsfp2_rx_clk_3_int), + .qsfp2_rx_rst_3(qsfp2_rx_rst_3_int), + .qsfp2_rxd_3(qsfp2_rxd_3_int), + .qsfp2_rxc_3(qsfp2_rxc_3_int), + .qsfp2_rx_prbs31_enable_3(qsfp2_rx_prbs31_enable_3_int), + .qsfp2_rx_error_count_3(qsfp2_rx_error_count_3_int), + .qsfp2_rx_status_3(qsfp2_rx_status_3), + .qsfp2_tx_clk_4(qsfp2_tx_clk_4_int), + .qsfp2_tx_rst_4(qsfp2_tx_rst_4_int), + .qsfp2_txd_4(qsfp2_txd_4_int), + .qsfp2_txc_4(qsfp2_txc_4_int), + .qsfp2_tx_prbs31_enable_4(qsfp2_tx_prbs31_enable_4_int), + .qsfp2_rx_clk_4(qsfp2_rx_clk_4_int), + .qsfp2_rx_rst_4(qsfp2_rx_rst_4_int), + .qsfp2_rxd_4(qsfp2_rxd_4_int), + .qsfp2_rxc_4(qsfp2_rxc_4_int), + .qsfp2_rx_prbs31_enable_4(qsfp2_rx_prbs31_enable_4_int), + .qsfp2_rx_error_count_4(qsfp2_rx_error_count_4_int), + .qsfp2_rx_status_4(qsfp2_rx_status_4), + + .qsfp2_drp_clk(qsfp2_drp_clk), + .qsfp2_drp_rst(qsfp2_drp_rst), + .qsfp2_drp_addr(qsfp2_drp_addr), + .qsfp2_drp_di(qsfp2_drp_di), + .qsfp2_drp_en(qsfp2_drp_en), + .qsfp2_drp_we(qsfp2_drp_we), + .qsfp2_drp_do(qsfp2_drp_do), + .qsfp2_drp_rdy(qsfp2_drp_rdy), + + .qsfp2_modprsl(qsfp2_modprsl_int), + .qsfp2_resetl(qsfp2_resetl), + .qsfp2_intl(qsfp2_intl_int), + .qsfp2_lpmode(qsfp2_lpmode), + + .qsfp2_i2c_scl_i(qsfp2_i2c_scl_i), + .qsfp2_i2c_scl_o(qsfp2_i2c_scl_o), + .qsfp2_i2c_scl_t(qsfp2_i2c_scl_t), + .qsfp2_i2c_sda_i(qsfp2_i2c_sda_i), + .qsfp2_i2c_sda_o(qsfp2_i2c_sda_o), + .qsfp2_i2c_sda_t(qsfp2_i2c_sda_t), + + .qsfp3_tx_clk_1(qsfp3_tx_clk_1_int), + .qsfp3_tx_rst_1(qsfp3_tx_rst_1_int), + .qsfp3_txd_1(qsfp3_txd_1_int), + .qsfp3_txc_1(qsfp3_txc_1_int), + .qsfp3_tx_prbs31_enable_1(qsfp3_tx_prbs31_enable_1_int), + .qsfp3_rx_clk_1(qsfp3_rx_clk_1_int), + .qsfp3_rx_rst_1(qsfp3_rx_rst_1_int), + .qsfp3_rxd_1(qsfp3_rxd_1_int), + .qsfp3_rxc_1(qsfp3_rxc_1_int), + .qsfp3_rx_prbs31_enable_1(qsfp3_rx_prbs31_enable_1_int), + .qsfp3_rx_error_count_1(qsfp3_rx_error_count_1_int), + .qsfp3_rx_status_1(qsfp3_rx_status_1), + .qsfp3_tx_clk_2(qsfp3_tx_clk_2_int), + .qsfp3_tx_rst_2(qsfp3_tx_rst_2_int), + .qsfp3_txd_2(qsfp3_txd_2_int), + .qsfp3_txc_2(qsfp3_txc_2_int), + .qsfp3_tx_prbs31_enable_2(qsfp3_tx_prbs31_enable_2_int), + .qsfp3_rx_clk_2(qsfp3_rx_clk_2_int), + .qsfp3_rx_rst_2(qsfp3_rx_rst_2_int), + .qsfp3_rxd_2(qsfp3_rxd_2_int), + .qsfp3_rxc_2(qsfp3_rxc_2_int), + .qsfp3_rx_prbs31_enable_2(qsfp3_rx_prbs31_enable_2_int), + .qsfp3_rx_error_count_2(qsfp3_rx_error_count_2_int), + .qsfp3_rx_status_2(qsfp3_rx_status_2), + .qsfp3_tx_clk_3(qsfp3_tx_clk_3_int), + .qsfp3_tx_rst_3(qsfp3_tx_rst_3_int), + .qsfp3_txd_3(qsfp3_txd_3_int), + .qsfp3_txc_3(qsfp3_txc_3_int), + .qsfp3_tx_prbs31_enable_3(qsfp3_tx_prbs31_enable_3_int), + .qsfp3_rx_clk_3(qsfp3_rx_clk_3_int), + .qsfp3_rx_rst_3(qsfp3_rx_rst_3_int), + .qsfp3_rxd_3(qsfp3_rxd_3_int), + .qsfp3_rxc_3(qsfp3_rxc_3_int), + .qsfp3_rx_prbs31_enable_3(qsfp3_rx_prbs31_enable_3_int), + .qsfp3_rx_error_count_3(qsfp3_rx_error_count_3_int), + .qsfp3_rx_status_3(qsfp3_rx_status_3), + .qsfp3_tx_clk_4(qsfp3_tx_clk_4_int), + .qsfp3_tx_rst_4(qsfp3_tx_rst_4_int), + .qsfp3_txd_4(qsfp3_txd_4_int), + .qsfp3_txc_4(qsfp3_txc_4_int), + .qsfp3_tx_prbs31_enable_4(qsfp3_tx_prbs31_enable_4_int), + .qsfp3_rx_clk_4(qsfp3_rx_clk_4_int), + .qsfp3_rx_rst_4(qsfp3_rx_rst_4_int), + .qsfp3_rxd_4(qsfp3_rxd_4_int), + .qsfp3_rxc_4(qsfp3_rxc_4_int), + .qsfp3_rx_prbs31_enable_4(qsfp3_rx_prbs31_enable_4_int), + .qsfp3_rx_error_count_4(qsfp3_rx_error_count_4_int), + .qsfp3_rx_status_4(qsfp3_rx_status_4), + + .qsfp3_drp_clk(qsfp3_drp_clk), + .qsfp3_drp_rst(qsfp3_drp_rst), + .qsfp3_drp_addr(qsfp3_drp_addr), + .qsfp3_drp_di(qsfp3_drp_di), + .qsfp3_drp_en(qsfp3_drp_en), + .qsfp3_drp_we(qsfp3_drp_we), + .qsfp3_drp_do(qsfp3_drp_do), + .qsfp3_drp_rdy(qsfp3_drp_rdy), + + .qsfp3_modprsl(qsfp3_modprsl_int), + .qsfp3_resetl(qsfp3_resetl), + .qsfp3_intl(qsfp3_intl_int), + .qsfp3_lpmode(qsfp3_lpmode), + + .qsfp3_i2c_scl_i(qsfp3_i2c_scl_i), + .qsfp3_i2c_scl_o(qsfp3_i2c_scl_o), + .qsfp3_i2c_scl_t(qsfp3_i2c_scl_t), + .qsfp3_i2c_sda_i(qsfp3_i2c_sda_i), + .qsfp3_i2c_sda_o(qsfp3_i2c_sda_o), + .qsfp3_i2c_sda_t(qsfp3_i2c_sda_t), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * BPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk_int), + .qspi_dq_i(qspi_dq_i_int), + .qspi_dq_o(qspi_dq_o_int), + .qspi_dq_oe(qspi_dq_oe_int), + .qspi_cs(qspi_cs_int) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v new file mode 100644 index 000000000..3dab516f6 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v @@ -0,0 +1,1952 @@ +// SPDX-License-Identifier: BSD-2-Clause-Views +/* + * Copyright (c) 2019-2023 The Regents of the University of California + */ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // FW and board IDs + parameter FPGA_ID = 32'h3842093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h12ba_8823, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 512, + parameter PTP_CLK_PERIOD_NS_DENOM = 165, + parameter PTP_TS_WIDTH = 96, + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_USE_SAMPLE_CLOCK = 1, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 1, + parameter PTP_PEROUT_COUNT = 1, + parameter IF_PTP_PERIOD_NS = 6'h6, + parameter IF_PTP_PERIOD_FNS = 16'h6666, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 11, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_TAG_WIDTH = 16, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 0, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_WIDTH = 256, + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + parameter AXIS_PCIE_RC_USER_WIDTH = 75, + parameter AXIS_PCIE_RQ_USER_WIDTH = 60, + parameter AXIS_PCIE_CQ_USER_WIDTH = 85, + parameter AXIS_PCIE_CC_USER_WIDTH = 33, + parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, + parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter RQ_SEQ_NUM_WIDTH = 4, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + parameter PCIE_TAG_COUNT = 64, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter XGMII_DATA_WIDTH = 64, + parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, + parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, + parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, + parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, + parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, + parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + parameter AXIS_ETH_TX_PIPELINE = 0, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, + parameter AXIS_ETH_TX_TS_PIPELINE = 0, + parameter AXIS_ETH_RX_PIPELINE = 0, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 250 MHz + * Synchronous reset + */ + input wire clk_250mhz, + input wire rst_250mhz, + + /* + * PTP clock + */ + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + + /* + * GPIO + */ + output wire [3:0] led, + input wire ext_pps_in, + input wire ext_clk_in, + + /* + * I2C + */ + input wire eeprom_i2c_scl_i, + output wire eeprom_i2c_scl_o, + output wire eeprom_i2c_scl_t, + input wire eeprom_i2c_sda_i, + output wire eeprom_i2c_sda_o, + output wire eeprom_i2c_sda_t, + + /* + * PCIe + */ + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tlast, + input wire m_axis_rq_tready, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, + output wire m_axis_rq_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tlast, + output wire s_axis_rc_tready, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, + input wire s_axis_rc_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tlast, + output wire s_axis_cq_tready, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, + input wire s_axis_cq_tvalid, + + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tlast, + input wire m_axis_cc_tready, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, + output wire m_axis_cc_tvalid, + + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num, + input wire s_axis_rq_seq_num_valid, + + input wire [1:0] pcie_tfc_nph_av, + input wire [1:0] pcie_tfc_npd_av, + + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, + input wire [3:0] cfg_rcb_status, + + output wire [18:0] cfg_mgmt_addr, + output wire cfg_mgmt_write, + output wire [31:0] cfg_mgmt_write_data, + output wire [3:0] cfg_mgmt_byte_enable, + output wire cfg_mgmt_read, + input wire [31:0] cfg_mgmt_read_data, + input wire cfg_mgmt_read_write_done, + + input wire [7:0] cfg_fc_ph, + input wire [11:0] cfg_fc_pd, + input wire [7:0] cfg_fc_nph, + input wire [11:0] cfg_fc_npd, + input wire [7:0] cfg_fc_cplh, + input wire [11:0] cfg_fc_cpld, + output wire [2:0] cfg_fc_sel, + + input wire [1:0] cfg_interrupt_msix_enable, + input wire [1:0] cfg_interrupt_msix_mask, + input wire [7:0] cfg_interrupt_msix_vf_enable, + input wire [7:0] cfg_interrupt_msix_vf_mask, + output wire [63:0] cfg_interrupt_msix_address, + output wire [31:0] cfg_interrupt_msix_data, + output wire cfg_interrupt_msix_int, + input wire cfg_interrupt_msix_sent, + input wire cfg_interrupt_msix_fail, + output wire [3:0] cfg_interrupt_msi_function_number, + + output wire status_error_cor, + output wire status_error_uncor, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp0_tx_clk_1, + input wire qsfp0_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1, + output wire qsfp0_tx_prbs31_enable_1, + input wire qsfp0_rx_clk_1, + input wire qsfp0_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1, + output wire qsfp0_rx_prbs31_enable_1, + input wire [6:0] qsfp0_rx_error_count_1, + input wire qsfp0_rx_status_1, + input wire qsfp0_tx_clk_2, + input wire qsfp0_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2, + output wire qsfp0_tx_prbs31_enable_2, + input wire qsfp0_rx_clk_2, + input wire qsfp0_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2, + output wire qsfp0_rx_prbs31_enable_2, + input wire [6:0] qsfp0_rx_error_count_2, + input wire qsfp0_rx_status_2, + input wire qsfp0_tx_clk_3, + input wire qsfp0_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3, + output wire qsfp0_tx_prbs31_enable_3, + input wire qsfp0_rx_clk_3, + input wire qsfp0_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3, + output wire qsfp0_rx_prbs31_enable_3, + input wire [6:0] qsfp0_rx_error_count_3, + input wire qsfp0_rx_status_3, + input wire qsfp0_tx_clk_4, + input wire qsfp0_tx_rst_4, + output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4, + output wire qsfp0_tx_prbs31_enable_4, + input wire qsfp0_rx_clk_4, + input wire qsfp0_rx_rst_4, + input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4, + output wire qsfp0_rx_prbs31_enable_4, + input wire [6:0] qsfp0_rx_error_count_4, + input wire qsfp0_rx_status_4, + + input wire qsfp0_drp_clk, + input wire qsfp0_drp_rst, + output wire [23:0] qsfp0_drp_addr, + output wire [15:0] qsfp0_drp_di, + output wire qsfp0_drp_en, + output wire qsfp0_drp_we, + input wire [15:0] qsfp0_drp_do, + input wire qsfp0_drp_rdy, + + output wire qsfp0_resetl, + input wire qsfp0_modprsl, + input wire qsfp0_intl, + output wire qsfp0_lpmode, + + input wire qsfp0_i2c_scl_i, + output wire qsfp0_i2c_scl_o, + output wire qsfp0_i2c_scl_t, + input wire qsfp0_i2c_sda_i, + output wire qsfp0_i2c_sda_o, + output wire qsfp0_i2c_sda_t, + + input wire qsfp1_tx_clk_1, + input wire qsfp1_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1, + output wire qsfp1_tx_prbs31_enable_1, + input wire qsfp1_rx_clk_1, + input wire qsfp1_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1, + output wire qsfp1_rx_prbs31_enable_1, + input wire [6:0] qsfp1_rx_error_count_1, + input wire qsfp1_rx_status_1, + input wire qsfp1_tx_clk_2, + input wire qsfp1_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2, + output wire qsfp1_tx_prbs31_enable_2, + input wire qsfp1_rx_clk_2, + input wire qsfp1_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2, + output wire qsfp1_rx_prbs31_enable_2, + input wire [6:0] qsfp1_rx_error_count_2, + input wire qsfp1_rx_status_2, + input wire qsfp1_tx_clk_3, + input wire qsfp1_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3, + output wire qsfp1_tx_prbs31_enable_3, + input wire qsfp1_rx_clk_3, + input wire qsfp1_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3, + output wire qsfp1_rx_prbs31_enable_3, + input wire [6:0] qsfp1_rx_error_count_3, + input wire qsfp1_rx_status_3, + input wire qsfp1_tx_clk_4, + input wire qsfp1_tx_rst_4, + output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4, + output wire qsfp1_tx_prbs31_enable_4, + input wire qsfp1_rx_clk_4, + input wire qsfp1_rx_rst_4, + input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4, + output wire qsfp1_rx_prbs31_enable_4, + input wire [6:0] qsfp1_rx_error_count_4, + input wire qsfp1_rx_status_4, + + input wire qsfp1_drp_clk, + input wire qsfp1_drp_rst, + output wire [23:0] qsfp1_drp_addr, + output wire [15:0] qsfp1_drp_di, + output wire qsfp1_drp_en, + output wire qsfp1_drp_we, + input wire [15:0] qsfp1_drp_do, + input wire qsfp1_drp_rdy, + + output wire qsfp1_resetl, + input wire qsfp1_modprsl, + input wire qsfp1_intl, + output wire qsfp1_lpmode, + + input wire qsfp1_i2c_scl_i, + output wire qsfp1_i2c_scl_o, + output wire qsfp1_i2c_scl_t, + input wire qsfp1_i2c_sda_i, + output wire qsfp1_i2c_sda_o, + output wire qsfp1_i2c_sda_t, + + input wire qsfp2_tx_clk_1, + input wire qsfp2_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1, + output wire qsfp2_tx_prbs31_enable_1, + input wire qsfp2_rx_clk_1, + input wire qsfp2_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1, + output wire qsfp2_rx_prbs31_enable_1, + input wire [6:0] qsfp2_rx_error_count_1, + input wire qsfp2_rx_status_1, + input wire qsfp2_tx_clk_2, + input wire qsfp2_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2, + output wire qsfp2_tx_prbs31_enable_2, + input wire qsfp2_rx_clk_2, + input wire qsfp2_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2, + output wire qsfp2_rx_prbs31_enable_2, + input wire [6:0] qsfp2_rx_error_count_2, + input wire qsfp2_rx_status_2, + input wire qsfp2_tx_clk_3, + input wire qsfp2_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3, + output wire qsfp2_tx_prbs31_enable_3, + input wire qsfp2_rx_clk_3, + input wire qsfp2_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3, + output wire qsfp2_rx_prbs31_enable_3, + input wire [6:0] qsfp2_rx_error_count_3, + input wire qsfp2_rx_status_3, + input wire qsfp2_tx_clk_4, + input wire qsfp2_tx_rst_4, + output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4, + output wire qsfp2_tx_prbs31_enable_4, + input wire qsfp2_rx_clk_4, + input wire qsfp2_rx_rst_4, + input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4, + output wire qsfp2_rx_prbs31_enable_4, + input wire [6:0] qsfp2_rx_error_count_4, + input wire qsfp2_rx_status_4, + + input wire qsfp2_drp_clk, + input wire qsfp2_drp_rst, + output wire [23:0] qsfp2_drp_addr, + output wire [15:0] qsfp2_drp_di, + output wire qsfp2_drp_en, + output wire qsfp2_drp_we, + input wire [15:0] qsfp2_drp_do, + input wire qsfp2_drp_rdy, + + output wire qsfp2_resetl, + input wire qsfp2_modprsl, + input wire qsfp2_intl, + output wire qsfp2_lpmode, + + input wire qsfp2_i2c_scl_i, + output wire qsfp2_i2c_scl_o, + output wire qsfp2_i2c_scl_t, + input wire qsfp2_i2c_sda_i, + output wire qsfp2_i2c_sda_o, + output wire qsfp2_i2c_sda_t, + + input wire qsfp3_tx_clk_1, + input wire qsfp3_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1, + output wire qsfp3_tx_prbs31_enable_1, + input wire qsfp3_rx_clk_1, + input wire qsfp3_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1, + output wire qsfp3_rx_prbs31_enable_1, + input wire [6:0] qsfp3_rx_error_count_1, + input wire qsfp3_rx_status_1, + input wire qsfp3_tx_clk_2, + input wire qsfp3_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2, + output wire qsfp3_tx_prbs31_enable_2, + input wire qsfp3_rx_clk_2, + input wire qsfp3_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2, + output wire qsfp3_rx_prbs31_enable_2, + input wire [6:0] qsfp3_rx_error_count_2, + input wire qsfp3_rx_status_2, + input wire qsfp3_tx_clk_3, + input wire qsfp3_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3, + output wire qsfp3_tx_prbs31_enable_3, + input wire qsfp3_rx_clk_3, + input wire qsfp3_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3, + output wire qsfp3_rx_prbs31_enable_3, + input wire [6:0] qsfp3_rx_error_count_3, + input wire qsfp3_rx_status_3, + input wire qsfp3_tx_clk_4, + input wire qsfp3_tx_rst_4, + output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4, + output wire qsfp3_tx_prbs31_enable_4, + input wire qsfp3_rx_clk_4, + input wire qsfp3_rx_rst_4, + input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4, + output wire qsfp3_rx_prbs31_enable_4, + input wire [6:0] qsfp3_rx_error_count_4, + input wire qsfp3_rx_status_4, + + input wire qsfp3_drp_clk, + input wire qsfp3_drp_rst, + output wire [23:0] qsfp3_drp_addr, + output wire [15:0] qsfp3_drp_di, + output wire qsfp3_drp_en, + output wire qsfp3_drp_we, + input wire [15:0] qsfp3_drp_do, + input wire qsfp3_drp_rdy, + + output wire qsfp3_resetl, + input wire qsfp3_modprsl, + input wire qsfp3_intl, + output wire qsfp3_lpmode, + + input wire qsfp3_i2c_scl_i, + output wire qsfp3_i2c_scl_o, + output wire qsfp3_i2c_scl_t, + input wire qsfp3_i2c_sda_i, + output wire qsfp3_i2c_sda_o, + output wire qsfp3_i2c_sda_t, + + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * BPI Flash + */ + output wire fpga_boot, + output wire qspi_clk, + input wire [3:0] qspi_dq_i, + output wire [3:0] qspi_dq_o, + output wire [3:0] qspi_dq_oe, + output wire qspi_cs +); + +parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; + +parameter F_COUNT = PF_COUNT+VF_COUNT; + +parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); +parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); +parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); + +localparam RB_BASE_ADDR = 16'h1000; +localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; + +localparam RB_DRP_QSFP0_BASE = RB_BASE_ADDR + 16'h80; +localparam RB_DRP_QSFP1_BASE = RB_DRP_QSFP0_BASE + 16'h20; +localparam RB_DRP_QSFP2_BASE = RB_DRP_QSFP1_BASE + 16'h20; +localparam RB_DRP_QSFP3_BASE = RB_DRP_QSFP2_BASE + 16'h20; + +initial begin + if (PORT_COUNT > 16) begin + $error("Error: Max port count exceeded (instance %m)"); + $finish; + end +end + +// AXI lite connections +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; +wire [2:0] axil_csr_awprot; +wire axil_csr_awvalid; +wire axil_csr_awready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; +wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; +wire axil_csr_wvalid; +wire axil_csr_wready; +wire [1:0] axil_csr_bresp; +wire axil_csr_bvalid; +wire axil_csr_bready; +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; +wire [2:0] axil_csr_arprot; +wire axil_csr_arvalid; +wire axil_csr_arready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; +wire [1:0] axil_csr_rresp; +wire axil_csr_rvalid; +wire axil_csr_rready; + +// PTP +wire [PTP_TS_WIDTH-1:0] ptp_ts_96; +wire ptp_ts_step; +wire ptp_pps; +wire ptp_pps_str; +wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; +wire ptp_sync_ts_step; +wire ptp_sync_pps; + +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; + +// control registers +wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; +wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; +wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; +wire ctrl_reg_wr_en; +wire ctrl_reg_wr_wait; +wire ctrl_reg_wr_ack; +wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; +wire ctrl_reg_rd_en; +wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; +wire ctrl_reg_rd_wait; +wire ctrl_reg_rd_ack; + +wire qsfp0_drp_reg_wr_wait; +wire qsfp0_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp0_drp_reg_rd_data; +wire qsfp0_drp_reg_rd_wait; +wire qsfp0_drp_reg_rd_ack; + +wire qsfp1_drp_reg_wr_wait; +wire qsfp1_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data; +wire qsfp1_drp_reg_rd_wait; +wire qsfp1_drp_reg_rd_ack; + +wire qsfp2_drp_reg_wr_wait; +wire qsfp2_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp2_drp_reg_rd_data; +wire qsfp2_drp_reg_rd_wait; +wire qsfp2_drp_reg_rd_ack; + +wire qsfp3_drp_reg_wr_wait; +wire qsfp3_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp3_drp_reg_rd_data; +wire qsfp3_drp_reg_rd_wait; +wire qsfp3_drp_reg_rd_ack; + +reg ctrl_reg_wr_ack_reg = 1'b0; +reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; +reg ctrl_reg_rd_ack_reg = 1'b0; + +reg qsfp0_reset_reg = 1'b0; +reg qsfp1_reset_reg = 1'b0; +reg qsfp2_reset_reg = 1'b0; +reg qsfp3_reset_reg = 1'b0; + +reg qsfp0_lpmode_reg = 1'b0; +reg qsfp1_lpmode_reg = 1'b0; +reg qsfp2_lpmode_reg = 1'b0; +reg qsfp3_lpmode_reg = 1'b0; + +reg eeprom_i2c_scl_o_reg = 1'b1; +reg eeprom_i2c_sda_o_reg = 1'b1; + +reg qsfp0_i2c_scl_o_reg = 1'b1; +reg qsfp0_i2c_sda_o_reg = 1'b1; + +reg qsfp1_i2c_scl_o_reg = 1'b1; +reg qsfp1_i2c_sda_o_reg = 1'b1; + +reg qsfp2_i2c_scl_o_reg = 1'b1; +reg qsfp2_i2c_sda_o_reg = 1'b1; + +reg qsfp3_i2c_scl_o_reg = 1'b1; +reg qsfp3_i2c_sda_o_reg = 1'b1; + +reg fpga_boot_reg = 1'b0; + +reg qspi_clk_reg = 1'b0; +reg qspi_cs_reg = 1'b1; +reg [3:0] qspi_dq_o_reg = 4'd0; +reg [3:0] qspi_dq_oe_reg = 4'd0; + +assign ctrl_reg_wr_wait = qsfp0_drp_reg_wr_wait | qsfp1_drp_reg_wr_wait | qsfp2_drp_reg_wr_wait | qsfp3_drp_reg_wr_wait; +assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp0_drp_reg_wr_ack | qsfp1_drp_reg_wr_ack | qsfp2_drp_reg_wr_ack | qsfp3_drp_reg_wr_ack; +assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp0_drp_reg_rd_data | qsfp1_drp_reg_rd_data | qsfp2_drp_reg_rd_data | qsfp3_drp_reg_rd_data; +assign ctrl_reg_rd_wait = qsfp0_drp_reg_rd_wait | qsfp1_drp_reg_rd_wait | qsfp2_drp_reg_rd_wait | qsfp3_drp_reg_rd_wait; +assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp0_drp_reg_rd_ack | qsfp1_drp_reg_rd_ack | qsfp2_drp_reg_rd_ack | qsfp3_drp_reg_rd_ack; + +assign qsfp0_resetl = !qsfp0_reset_reg; +assign qsfp1_resetl = !qsfp1_reset_reg; +assign qsfp2_resetl = !qsfp2_reset_reg; +assign qsfp3_resetl = !qsfp3_reset_reg; + +assign qsfp0_lpmode = qsfp0_lpmode_reg; +assign qsfp1_lpmode = qsfp1_lpmode_reg; +assign qsfp2_lpmode = qsfp2_lpmode_reg; +assign qsfp3_lpmode = qsfp3_lpmode_reg; + +assign eeprom_i2c_scl_o = eeprom_i2c_scl_o_reg; +assign eeprom_i2c_scl_t = eeprom_i2c_scl_o_reg; +assign eeprom_i2c_sda_o = eeprom_i2c_sda_o_reg; +assign eeprom_i2c_sda_t = eeprom_i2c_sda_o_reg; + +assign qsfp0_i2c_scl_o = qsfp0_i2c_scl_o_reg; +assign qsfp0_i2c_scl_t = qsfp0_i2c_scl_o_reg; +assign qsfp0_i2c_sda_o = qsfp0_i2c_sda_o_reg; +assign qsfp0_i2c_sda_t = qsfp0_i2c_sda_o_reg; + +assign qsfp1_i2c_scl_o = qsfp1_i2c_scl_o_reg; +assign qsfp1_i2c_scl_t = qsfp1_i2c_scl_o_reg; +assign qsfp1_i2c_sda_o = qsfp1_i2c_sda_o_reg; +assign qsfp1_i2c_sda_t = qsfp1_i2c_sda_o_reg; + +assign qsfp2_i2c_scl_o = qsfp2_i2c_scl_o_reg; +assign qsfp2_i2c_scl_t = qsfp2_i2c_scl_o_reg; +assign qsfp2_i2c_sda_o = qsfp2_i2c_sda_o_reg; +assign qsfp2_i2c_sda_t = qsfp2_i2c_sda_o_reg; + +assign qsfp3_i2c_scl_o = qsfp3_i2c_scl_o_reg; +assign qsfp3_i2c_scl_t = qsfp3_i2c_scl_o_reg; +assign qsfp3_i2c_sda_o = qsfp3_i2c_sda_o_reg; +assign qsfp3_i2c_sda_t = qsfp3_i2c_sda_o_reg; + +assign fpga_boot = fpga_boot_reg; + +assign qspi_clk = qspi_clk_reg; +assign qspi_cs = qspi_cs_reg; +assign qspi_dq_o = qspi_dq_o_reg; +assign qspi_dq_oe = qspi_dq_oe_reg; + +always @(posedge clk_250mhz) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; + ctrl_reg_rd_ack_reg <= 1'b0; + + if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin + // write operation + ctrl_reg_wr_ack_reg <= 1'b0; + case ({ctrl_reg_wr_addr >> 2, 2'b00}) + // FW ID + 8'h0C: begin + // FW ID: FPGA JTAG ID + fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; + end + // I2C 0 + RBB+8'h0C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + qsfp0_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp0_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // I2C 1 + RBB+8'h1C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + qsfp1_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp1_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // I2C 2 + RBB+8'h2C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + qsfp2_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp2_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // I2C 3 + RBB+8'h3C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + qsfp3_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp3_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // I2C 4 + RBB+8'h4C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + eeprom_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + eeprom_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // XCVR GPIO + RBB+8'h5C: begin + // XCVR GPIO: control 0123 + if (ctrl_reg_wr_strb[0]) begin + qsfp0_reset_reg <= ctrl_reg_wr_data[4]; + qsfp0_lpmode_reg <= ctrl_reg_wr_data[5]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp1_reset_reg <= ctrl_reg_wr_data[12]; + qsfp1_lpmode_reg <= ctrl_reg_wr_data[13]; + end + if (ctrl_reg_wr_strb[2]) begin + qsfp2_reset_reg <= ctrl_reg_wr_data[20]; + qsfp2_lpmode_reg <= ctrl_reg_wr_data[21]; + end + if (ctrl_reg_wr_strb[3]) begin + qsfp3_reset_reg <= ctrl_reg_wr_data[28]; + qsfp3_lpmode_reg <= ctrl_reg_wr_data[29]; + end + end + // QSPI flash + RBB+8'h6C: begin + // SPI flash ctrl: format + fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; + end + RBB+8'h70: begin + // SPI flash ctrl: control 0 + if (ctrl_reg_wr_strb[0]) begin + qspi_dq_o_reg <= ctrl_reg_wr_data[3:0]; + end + if (ctrl_reg_wr_strb[1]) begin + qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8]; + end + if (ctrl_reg_wr_strb[2]) begin + qspi_clk_reg <= ctrl_reg_wr_data[16]; + qspi_cs_reg <= ctrl_reg_wr_data[17]; + end + end + default: ctrl_reg_wr_ack_reg <= 1'b0; + endcase + end + + if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin + // read operation + ctrl_reg_rd_ack_reg <= 1'b1; + case ({ctrl_reg_rd_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header + RBB+8'h0C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= qsfp0_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= qsfp0_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= qsfp0_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= qsfp0_i2c_sda_o_reg; + end + // I2C 1 + RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // I2C ctrl: Next header + RBB+8'h1C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= qsfp1_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= qsfp1_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= qsfp1_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= qsfp1_i2c_sda_o_reg; + end + // I2C 2 + RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h30; // I2C ctrl: Next header + RBB+8'h2C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= qsfp2_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= qsfp2_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= qsfp2_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= qsfp2_i2c_sda_o_reg; + end + // I2C 3 + RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h38: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // I2C ctrl: Next header + RBB+8'h3C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= qsfp3_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= qsfp3_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= qsfp3_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= qsfp3_i2c_sda_o_reg; + end + // I2C 4 + RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h48: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h50; // I2C ctrl: Next header + RBB+8'h4C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= eeprom_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= eeprom_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= eeprom_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= eeprom_i2c_sda_o_reg; + end + // XCVR GPIO + RBB+8'h50: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type + RBB+8'h54: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version + RBB+8'h58: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h60; // XCVR GPIO: Next header + RBB+8'h5C: begin + // XCVR GPIO: control 0123 + ctrl_reg_rd_data_reg[0] <= !qsfp0_modprsl; + ctrl_reg_rd_data_reg[1] <= !qsfp0_intl; + ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg; + ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg; + ctrl_reg_rd_data_reg[8] <= !qsfp1_modprsl; + ctrl_reg_rd_data_reg[9] <= !qsfp1_intl; + ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg; + ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg; + ctrl_reg_rd_data_reg[16] <= !qsfp2_modprsl; + ctrl_reg_rd_data_reg[17] <= !qsfp2_intl; + ctrl_reg_rd_data_reg[20] <= qsfp2_reset_reg; + ctrl_reg_rd_data_reg[21] <= qsfp2_lpmode_reg; + ctrl_reg_rd_data_reg[24] <= !qsfp3_modprsl; + ctrl_reg_rd_data_reg[25] <= !qsfp3_intl; + ctrl_reg_rd_data_reg[28] <= qsfp3_reset_reg; + ctrl_reg_rd_data_reg[29] <= qsfp3_lpmode_reg; + end + // QSPI flash + RBB+8'h60: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type + RBB+8'h64: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version + RBB+8'h68: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // SPI flash ctrl: Next header + RBB+8'h6C: begin + // SPI flash ctrl: format + ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) + ctrl_reg_rd_data_reg[7:4] <= 0; // default segment + ctrl_reg_rd_data_reg[11:8] <= 1; // fallback segment + ctrl_reg_rd_data_reg[31:12] <= 32'h03000000 >> 12; // first segment size (48 M) + end + RBB+8'h70: begin + // SPI flash ctrl: control 0 + ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i; + ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe; + ctrl_reg_rd_data_reg[16] <= qspi_clk; + ctrl_reg_rd_data_reg[17] <= qspi_cs; + end + default: ctrl_reg_rd_ack_reg <= 1'b0; + endcase + end + + if (rst_250mhz) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_ack_reg <= 1'b0; + + qsfp0_reset_reg <= 1'b0; + qsfp1_reset_reg <= 1'b0; + qsfp2_reset_reg <= 1'b0; + qsfp3_reset_reg <= 1'b0; + + qsfp0_lpmode_reg <= 1'b0; + qsfp1_lpmode_reg <= 1'b0; + qsfp2_lpmode_reg <= 1'b0; + qsfp3_lpmode_reg <= 1'b0; + + eeprom_i2c_scl_o_reg <= 1'b1; + eeprom_i2c_sda_o_reg <= 1'b1; + + qsfp0_i2c_scl_o_reg <= 1'b1; + qsfp0_i2c_sda_o_reg <= 1'b1; + + qsfp1_i2c_scl_o_reg <= 1'b1; + qsfp1_i2c_sda_o_reg <= 1'b1; + + qsfp2_i2c_scl_o_reg <= 1'b1; + qsfp2_i2c_sda_o_reg <= 1'b1; + + qsfp3_i2c_scl_o_reg <= 1'b1; + qsfp3_i2c_sda_o_reg <= 1'b1; + + fpga_boot_reg <= 1'b0; + + qspi_clk_reg <= 1'b0; + qspi_cs_reg <= 1'b1; + qspi_dq_o_reg <= 4'd0; + qspi_dq_oe_reg <= 4'd0; + end +end + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP0_BASE), + .RB_NEXT_PTR(RB_DRP_QSFP1_BASE) +) +qsfp0_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp0_drp_reg_wr_wait), + .reg_wr_ack(qsfp0_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp0_drp_reg_rd_data), + .reg_rd_wait(qsfp0_drp_reg_rd_wait), + .reg_rd_ack(qsfp0_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp0_drp_clk), + .drp_rst(qsfp0_drp_rst), + .drp_addr(qsfp0_drp_addr), + .drp_di(qsfp0_drp_di), + .drp_en(qsfp0_drp_en), + .drp_we(qsfp0_drp_we), + .drp_do(qsfp0_drp_do), + .drp_rdy(qsfp0_drp_rdy) +); + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP1_BASE), + .RB_NEXT_PTR(RB_DRP_QSFP2_BASE) +) +qsfp1_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp1_drp_reg_wr_wait), + .reg_wr_ack(qsfp1_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp1_drp_reg_rd_data), + .reg_rd_wait(qsfp1_drp_reg_rd_wait), + .reg_rd_ack(qsfp1_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp1_drp_clk), + .drp_rst(qsfp1_drp_rst), + .drp_addr(qsfp1_drp_addr), + .drp_di(qsfp1_drp_di), + .drp_en(qsfp1_drp_en), + .drp_we(qsfp1_drp_we), + .drp_do(qsfp1_drp_do), + .drp_rdy(qsfp1_drp_rdy) +); + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP2_BASE), + .RB_NEXT_PTR(RB_DRP_QSFP3_BASE) +) +qsfp2_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp2_drp_reg_wr_wait), + .reg_wr_ack(qsfp2_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp2_drp_reg_rd_data), + .reg_rd_wait(qsfp2_drp_reg_rd_wait), + .reg_rd_ack(qsfp2_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp2_drp_clk), + .drp_rst(qsfp2_drp_rst), + .drp_addr(qsfp2_drp_addr), + .drp_di(qsfp2_drp_di), + .drp_en(qsfp2_drp_en), + .drp_we(qsfp2_drp_we), + .drp_do(qsfp2_drp_do), + .drp_rdy(qsfp2_drp_rdy) +); + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h08, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP3_BASE), + .RB_NEXT_PTR(0) +) +qsfp3_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp3_drp_reg_wr_wait), + .reg_wr_ack(qsfp3_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp3_drp_reg_rd_data), + .reg_rd_wait(qsfp3_drp_reg_rd_wait), + .reg_rd_ack(qsfp3_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp3_drp_clk), + .drp_rst(qsfp3_drp_rst), + .drp_addr(qsfp3_drp_addr), + .drp_di(qsfp3_drp_di), + .drp_en(qsfp3_drp_en), + .drp_we(qsfp3_drp_we), + .drp_do(qsfp3_drp_do), + .drp_rdy(qsfp3_drp_rdy) +); + +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(16), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(16)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_rx_error_count({qsfp3_rx_error_count_4, qsfp3_rx_error_count_3, qsfp3_rx_error_count_2, qsfp3_rx_error_count_1, qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp3_tx_prbs31_enable_4, qsfp3_tx_prbs31_enable_3, qsfp3_tx_prbs31_enable_2, qsfp3_tx_prbs31_enable_1, qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp3_rx_prbs31_enable_4, qsfp3_rx_prbs31_enable_3, qsfp3_rx_prbs31_enable_2, qsfp3_rx_prbs31_enable_1, qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp0_tx_prbs31_enable_1 = 1'b0; + assign qsfp0_rx_prbs31_enable_1 = 1'b0; + assign qsfp0_tx_prbs31_enable_2 = 1'b0; + assign qsfp0_rx_prbs31_enable_2 = 1'b0; + assign qsfp0_tx_prbs31_enable_3 = 1'b0; + assign qsfp0_rx_prbs31_enable_3 = 1'b0; + assign qsfp0_tx_prbs31_enable_4 = 1'b0; + assign qsfp0_rx_prbs31_enable_4 = 1'b0; + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + assign qsfp2_tx_prbs31_enable_1 = 1'b0; + assign qsfp2_rx_prbs31_enable_1 = 1'b0; + assign qsfp2_tx_prbs31_enable_2 = 1'b0; + assign qsfp2_rx_prbs31_enable_2 = 1'b0; + assign qsfp2_tx_prbs31_enable_3 = 1'b0; + assign qsfp2_rx_prbs31_enable_3 = 1'b0; + assign qsfp2_tx_prbs31_enable_4 = 1'b0; + assign qsfp2_rx_prbs31_enable_4 = 1'b0; + assign qsfp3_tx_prbs31_enable_1 = 1'b0; + assign qsfp3_rx_prbs31_enable_1 = 1'b0; + assign qsfp3_tx_prbs31_enable_2 = 1'b0; + assign qsfp3_rx_prbs31_enable_2 = 1'b0; + assign qsfp3_tx_prbs31_enable_3 = 1'b0; + assign qsfp3_rx_prbs31_enable_3 = 1'b0; + assign qsfp3_tx_prbs31_enable_4 = 1'b0; + assign qsfp3_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate + +assign led[2:0] = 3'b111; +assign led[3] = !ptp_pps_str; + +wire [PORT_COUNT-1:0] eth_tx_clk; +wire [PORT_COUNT-1:0] eth_tx_rst; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; + +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; +wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; +wire [PORT_COUNT-1:0] axis_eth_tx_tready; +wire [PORT_COUNT-1:0] axis_eth_tx_tlast; +wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; +wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; + +wire [PORT_COUNT-1:0] eth_tx_status; + +wire [PORT_COUNT-1:0] eth_rx_clk; +wire [PORT_COUNT-1:0] eth_rx_rst; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; + +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; +wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; +wire [PORT_COUNT-1:0] axis_eth_rx_tready; +wire [PORT_COUNT-1:0] axis_eth_rx_tlast; +wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; + +wire [PORT_COUNT-1:0] eth_rx_status; + +wire [PORT_COUNT-1:0] port_xgmii_tx_clk; +wire [PORT_COUNT-1:0] port_xgmii_tx_rst; +wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; +wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; + +wire [PORT_COUNT-1:0] port_xgmii_rx_clk; +wire [PORT_COUNT-1:0] port_xgmii_rx_rst; +wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; +wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; + +mqnic_port_map_phy_xgmii #( + .PHY_COUNT(16), + .PORT_MASK(PORT_MASK), + .PORT_GROUP_SIZE(4), + + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) +) +mqnic_port_map_phy_xgmii_inst ( + // towards PHY + .phy_xgmii_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_xgmii_tx_rst({qsfp3_tx_rst_4, qsfp3_tx_rst_3, qsfp3_tx_rst_2, qsfp3_tx_rst_1, qsfp2_tx_rst_4, qsfp2_tx_rst_3, qsfp2_tx_rst_2, qsfp2_tx_rst_1, qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}), + .phy_xgmii_txd({qsfp3_txd_4, qsfp3_txd_3, qsfp3_txd_2, qsfp3_txd_1, qsfp2_txd_4, qsfp2_txd_3, qsfp2_txd_2, qsfp2_txd_1, qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}), + .phy_xgmii_txc({qsfp3_txc_4, qsfp3_txc_3, qsfp3_txc_2, qsfp3_txc_1, qsfp2_txc_4, qsfp2_txc_3, qsfp2_txc_2, qsfp2_txc_1, qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}), + .phy_tx_status(16'hffff), + + .phy_xgmii_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_xgmii_rx_rst({qsfp3_rx_rst_4, qsfp3_rx_rst_3, qsfp3_rx_rst_2, qsfp3_rx_rst_1, qsfp2_rx_rst_4, qsfp2_rx_rst_3, qsfp2_rx_rst_2, qsfp2_rx_rst_1, qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}), + .phy_xgmii_rxd({qsfp3_rxd_4, qsfp3_rxd_3, qsfp3_rxd_2, qsfp3_rxd_1, qsfp2_rxd_4, qsfp2_rxd_3, qsfp2_rxd_2, qsfp2_rxd_1, qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}), + .phy_xgmii_rxc({qsfp3_rxc_4, qsfp3_rxc_3, qsfp3_rxc_2, qsfp3_rxc_1, qsfp2_rxc_4, qsfp2_rxc_3, qsfp2_rxc_2, qsfp2_rxc_1, qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}), + .phy_rx_status({qsfp3_rx_status_4, qsfp3_rx_status_3, qsfp3_rx_status_2, qsfp3_rx_status_1, qsfp2_rx_status_4, qsfp2_rx_status_3, qsfp2_rx_status_2, qsfp2_rx_status_1, qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}), + + // towards MAC + .port_xgmii_tx_clk(port_xgmii_tx_clk), + .port_xgmii_tx_rst(port_xgmii_tx_rst), + .port_xgmii_txd(port_xgmii_txd), + .port_xgmii_txc(port_xgmii_txc), + .port_tx_status(eth_tx_status), + + .port_xgmii_rx_clk(port_xgmii_rx_clk), + .port_xgmii_rx_rst(port_xgmii_rx_rst), + .port_xgmii_rxd(port_xgmii_rxd), + .port_xgmii_rxc(port_xgmii_rxc), + .port_rx_status(eth_rx_status) +); + +generate + genvar n; + + for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac + + assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; + assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; + assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; + assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; + + eth_mac_10g #( + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), + .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), + .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), + .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) + ) + eth_mac_inst ( + .tx_clk(port_xgmii_tx_clk[n]), + .tx_rst(port_xgmii_tx_rst[n]), + .rx_clk(port_xgmii_rx_clk[n]), + .rx_rst(port_xgmii_rx_rst[n]), + + .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), + .tx_axis_tready(axis_eth_tx_tready[n +: 1]), + .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), + .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), + + .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), + .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), + .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), + + .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + + .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), + .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), + + .tx_error_underflow(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + + .ifg_delay(8'd12) + ); + + end + +endgenerate + +mqnic_core_pcie_us #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_SEPARATE_TX_CLOCK(0), + .PTP_SEPARATE_RX_CLOCK(0), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + .APP_GPIO_IN_WIDTH(32), + .APP_GPIO_OUT_WIDTH(32), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RC_STRADDLE(RC_STRADDLE), + .RQ_STRADDLE(RQ_STRADDLE), + .CQ_STRADDLE(CQ_STRADDLE), + .CC_STRADDLE(CC_STRADDLE), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .F_COUNT(F_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), + .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), + .RB_NEXT_PTR(RB_BASE_ADDR), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_RX_USE_READY(0), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input (RC) + */ + .s_axis_rc_tdata(s_axis_rc_tdata), + .s_axis_rc_tkeep(s_axis_rc_tkeep), + .s_axis_rc_tvalid(s_axis_rc_tvalid), + .s_axis_rc_tready(s_axis_rc_tready), + .s_axis_rc_tlast(s_axis_rc_tlast), + .s_axis_rc_tuser(s_axis_rc_tuser), + + /* + * AXI output (RQ) + */ + .m_axis_rq_tdata(m_axis_rq_tdata), + .m_axis_rq_tkeep(m_axis_rq_tkeep), + .m_axis_rq_tvalid(m_axis_rq_tvalid), + .m_axis_rq_tready(m_axis_rq_tready), + .m_axis_rq_tlast(m_axis_rq_tlast), + .m_axis_rq_tuser(m_axis_rq_tuser), + + /* + * AXI input (CQ) + */ + .s_axis_cq_tdata(s_axis_cq_tdata), + .s_axis_cq_tkeep(s_axis_cq_tkeep), + .s_axis_cq_tvalid(s_axis_cq_tvalid), + .s_axis_cq_tready(s_axis_cq_tready), + .s_axis_cq_tlast(s_axis_cq_tlast), + .s_axis_cq_tuser(s_axis_cq_tuser), + + /* + * AXI output (CC) + */ + .m_axis_cc_tdata(m_axis_cc_tdata), + .m_axis_cc_tkeep(m_axis_cc_tkeep), + .m_axis_cc_tvalid(m_axis_cc_tvalid), + .m_axis_cc_tready(m_axis_cc_tready), + .m_axis_cc_tlast(m_axis_cc_tlast), + .m_axis_cc_tuser(m_axis_cc_tuser), + + /* + * Transmit sequence number input + */ + .s_axis_rq_seq_num_0(s_axis_rq_seq_num), + .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid), + .s_axis_rq_seq_num_1(4'd0), + .s_axis_rq_seq_num_valid_1(1'b0), + + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + /* + * Configuration inputs + */ + .cfg_max_read_req(cfg_max_read_req), + .cfg_max_payload(cfg_max_payload), + .cfg_rcb_status(cfg_rcb_status), + + /* + * Configuration interface + */ + .cfg_mgmt_addr(cfg_mgmt_addr[9:0]), + .cfg_mgmt_function_number(cfg_mgmt_addr[17:10]), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + /* + * Interrupt interface + */ + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(), + .cfg_interrupt_msix_vec_pending_status(1'b0), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * PCIe error outputs + */ + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * AXI-Lite master interface (passthrough for NIC control and status) + */ + .m_axil_csr_awaddr(axil_csr_awaddr), + .m_axil_csr_awprot(axil_csr_awprot), + .m_axil_csr_awvalid(axil_csr_awvalid), + .m_axil_csr_awready(axil_csr_awready), + .m_axil_csr_wdata(axil_csr_wdata), + .m_axil_csr_wstrb(axil_csr_wstrb), + .m_axil_csr_wvalid(axil_csr_wvalid), + .m_axil_csr_wready(axil_csr_wready), + .m_axil_csr_bresp(axil_csr_bresp), + .m_axil_csr_bvalid(axil_csr_bvalid), + .m_axil_csr_bready(axil_csr_bready), + .m_axil_csr_araddr(axil_csr_araddr), + .m_axil_csr_arprot(axil_csr_arprot), + .m_axil_csr_arvalid(axil_csr_arvalid), + .m_axil_csr_arready(axil_csr_arready), + .m_axil_csr_rdata(axil_csr_rdata), + .m_axil_csr_rresp(axil_csr_rresp), + .m_axil_csr_rvalid(axil_csr_rvalid), + .m_axil_csr_rready(axil_csr_rready), + + /* + * Control register interface + */ + .ctrl_reg_wr_addr(ctrl_reg_wr_addr), + .ctrl_reg_wr_data(ctrl_reg_wr_data), + .ctrl_reg_wr_strb(ctrl_reg_wr_strb), + .ctrl_reg_wr_en(ctrl_reg_wr_en), + .ctrl_reg_wr_wait(ctrl_reg_wr_wait), + .ctrl_reg_wr_ack(ctrl_reg_wr_ack), + .ctrl_reg_rd_addr(ctrl_reg_rd_addr), + .ctrl_reg_rd_en(ctrl_reg_rd_en), + .ctrl_reg_rd_data(ctrl_reg_rd_data), + .ctrl_reg_rd_wait(ctrl_reg_rd_wait), + .ctrl_reg_rd_ack(ctrl_reg_rd_ack), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_pps(ptp_pps), + .ptp_pps_str(ptp_pps_str), + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + .ptp_sync_pps(ptp_sync_pps), + .ptp_sync_ts_96(ptp_sync_ts_96), + .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_perout_locked(ptp_perout_locked), + .ptp_perout_error(ptp_perout_error), + .ptp_perout_pulse(ptp_perout_pulse), + + /* + * Ethernet + */ + .eth_tx_clk(eth_tx_clk), + .eth_tx_rst(eth_tx_rst), + + .eth_tx_ptp_clk(0), + .eth_tx_ptp_rst(0), + .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), + .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + + .m_axis_eth_tx_tdata(axis_eth_tx_tdata), + .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), + .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), + .m_axis_eth_tx_tready(axis_eth_tx_tready), + .m_axis_eth_tx_tlast(axis_eth_tx_tlast), + .m_axis_eth_tx_tuser(axis_eth_tx_tuser), + + .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), + .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), + .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), + .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), + + .eth_tx_status(eth_tx_status), + + .eth_rx_clk(eth_rx_clk), + .eth_rx_rst(eth_rx_rst), + + .eth_rx_ptp_clk(0), + .eth_rx_ptp_rst(0), + .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), + .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + + .s_axis_eth_rx_tdata(axis_eth_rx_tdata), + .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), + .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), + .s_axis_eth_rx_tready(axis_eth_rx_tready), + .s_axis_eth_rx_tlast(axis_eth_rx_tlast), + .s_axis_eth_rx_tuser(axis_eth_rx_tuser), + + .eth_rx_status(eth_rx_status), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + + /* + * Statistics input + */ + .s_axis_stat_tdata(0), + .s_axis_stat_tid(0), + .s_axis_stat_tvalid(1'b0), + .s_axis_stat_tready(), + + /* + * GPIO + */ + .app_gpio_in(0), + .app_gpio_out(), + + /* + * JTAG + */ + .app_jtag_tdi(1'b0), + .app_jtag_tdo(), + .app_jtag_tms(1'b0), + .app_jtag_tck(1'b0) +); + +assign cfg_mgmt_addr[18] = 1'b0; + +endmodule + +`resetall diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/sync_signal.v new file mode 100644 index 000000000..74b855fa1 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/rtl/sync_signal.v @@ -0,0 +1,62 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule + +`resetall diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile new file mode 100644 index 000000000..eb46883b9 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile @@ -0,0 +1,256 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2020-2023 The Regents of the University of California + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v +VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v +VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v +VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v +VERILOG_SOURCES += ../../rtl/common/cpl_write.v +VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v +VERILOG_SOURCES += ../../rtl/common/desc_fetch.v +VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/common/queue_manager.v +VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v +VERILOG_SOURCES += ../../rtl/common/tx_engine.v +VERILOG_SOURCES += ../../rtl/common/rx_engine.v +VERILOG_SOURCES += ../../rtl/common/tx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rx_hash.v +VERILOG_SOURCES += ../../rtl/common/rx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rb_drp.v +VERILOG_SOURCES += ../../rtl/common/stats_counter.v +VERILOG_SOURCES += ../../rtl/common/stats_collect.v +VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v +VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v +VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v +VERILOG_SOURCES += ../../rtl/common/tdma_ber.v +VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v +VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v + +# module parameters + +# Structural configuration +export PARAM_IF_COUNT := 2 +export PARAM_PORTS_PER_IF := 1 +export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) +export PARAM_PORT_MASK := 0 + +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM := 4 +export PARAM_CLK_PERIOD_NS_DENOM := 1 + +# PTP configuration +export PARAM_PTP_CLK_PERIOD_NS_NUM := 512 +export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 +export PARAM_PTP_CLOCK_PIPELINE := 0 +export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 +export PARAM_PTP_USE_SAMPLE_CLOCK := 1 +export PARAM_PTP_PORT_CDC_PIPELINE := 0 +export PARAM_PTP_PEROUT_ENABLE := 1 +export PARAM_PTP_PEROUT_COUNT := 1 + +# Queue manager configuration +export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 5 +export PARAM_TX_QUEUE_INDEX_WIDTH := 11 +export PARAM_RX_QUEUE_INDEX_WIDTH := 8 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 +export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") + +# TX and RX engine configuration +export PARAM_TX_DESC_TABLE_SIZE := 32 +export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") + +# Scheduler configuration +export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) +export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_TDMA_INDEX_WIDTH := 6 + +# Interface configuration +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_TX_CPL_FIFO_DEPTH := 32 +export PARAM_TX_CHECKSUM_ENABLE := 1 +export PARAM_RX_HASH_ENABLE := 1 +export PARAM_RX_CHECKSUM_ENABLE := 1 +export PARAM_TX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_MAX_TX_SIZE := 9214 +export PARAM_MAX_RX_SIZE := 9214 +export PARAM_TX_RAM_SIZE := 32768 +export PARAM_RX_RAM_SIZE := 32768 + +# Application block configuration +export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) +export PARAM_APP_ENABLE := 0 +export PARAM_APP_CTRL_ENABLE := 1 +export PARAM_APP_DMA_ENABLE := 1 +export PARAM_APP_AXIS_DIRECT_ENABLE := 1 +export PARAM_APP_AXIS_SYNC_ENABLE := 1 +export PARAM_APP_AXIS_IF_ENABLE := 1 +export PARAM_APP_STAT_ENABLE := 1 + +# DMA interface configuration +export PARAM_DMA_IMM_ENABLE := 0 +export PARAM_DMA_IMM_WIDTH := 32 +export PARAM_DMA_LEN_WIDTH := 16 +export PARAM_DMA_TAG_WIDTH := 16 +export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") +export PARAM_RAM_PIPELINE := 2 + +# PCIe interface configuration +export PARAM_AXIS_PCIE_DATA_WIDTH := 256 +export PARAM_PF_COUNT := 1 +export PARAM_VF_COUNT := 0 + +# Interrupt configuration +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_WIDTH := 32 +export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 + +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 + +# Ethernet interface configuration +export PARAM_AXIS_ETH_TX_PIPELINE := 0 +export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2 +export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0 +export PARAM_AXIS_ETH_RX_PIPELINE := 0 +export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2 + +# Statistics counter subsystem +export PARAM_STAT_ENABLE := 1 +export PARAM_STAT_DMA_ENABLE := 1 +export PARAM_STAT_PCIE_ENABLE := 1 +export PARAM_STAT_INC_WIDTH := 24 +export PARAM_STAT_ID_WIDTH := 12 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/mqnic.py new file mode 120000 index 000000000..dfa8522e7 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/mqnic.py @@ -0,0 +1 @@ +../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..08a200315 --- /dev/null +++ b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,752 @@ +# SPDX-License-Identifier: BSD-2-Clause-Views +# Copyright (c) 2020-2023 The Regents of the University of California + +import logging +import os +import sys + +import scapy.utils +from scapy.layers.l2 import Ether +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer + +from cocotbext.axi import AxiStreamBus +from cocotbext.eth import XgmiiSource, XgmiiSink +from cocotbext.pcie.core import RootComplex +from cocotbext.pcie.xilinx.us import UltraScalePcieDevice + +try: + import mqnic +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + import mqnic + finally: + del sys.path[0] + + +class TB(object): + def __init__(self, dut, msix_count=32): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # PCIe + self.rc = RootComplex() + + self.rc.max_payload_size = 0x1 # 256 bytes + self.rc.max_read_request_size = 0x2 # 512 bytes + + self.dev = UltraScalePcieDevice( + # configuration options + pcie_generation=3, + pcie_link_width=8, + user_clk_frequency=250e6, + alignment="dword", + rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, + pf_count=1, + max_payload_size=1024, + enable_client_tag=True, + enable_extended_tag=True, + enable_parity=False, + enable_rx_msg_interface=False, + enable_sriov=False, + enable_extended_configuration=False, + + pf0_msi_enable=False, + pf0_msi_count=32, + pf1_msi_enable=False, + pf1_msi_count=1, + pf0_msix_enable=True, + pf0_msix_table_size=msix_count-1, + pf0_msix_table_bir=0, + pf0_msix_table_offset=0x00010000, + pf0_msix_pba_bir=0, + pf0_msix_pba_offset=0x00018000, + pf1_msix_enable=False, + pf1_msix_table_size=0, + pf1_msix_table_bir=0, + pf1_msix_table_offset=0x00000000, + pf1_msix_pba_bir=0, + pf1_msix_pba_offset=0x00000000, + + # signals + # Clock and Reset Interface + user_clk=dut.clk_250mhz, + user_reset=dut.rst_250mhz, + # user_lnk_up + # sys_clk + # sys_clk_gt + # sys_reset + # phy_rdy_out + + # Requester reQuest Interface + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), + pcie_rq_seq_num=dut.s_axis_rq_seq_num, + pcie_rq_seq_num_vld=dut.s_axis_rq_seq_num_valid, + # pcie_rq_tag + # pcie_rq_tag_av + # pcie_rq_tag_vld + + # Requester Completion Interface + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), + + # Completer reQuest Interface + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), + # pcie_cq_np_req + # pcie_cq_np_req_count + + # Completer Completion Interface + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), + + # Transmit Flow Control Interface + # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, + # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, + + # Configuration Management Interface + cfg_mgmt_addr=dut.cfg_mgmt_addr, + cfg_mgmt_write=dut.cfg_mgmt_write, + cfg_mgmt_write_data=dut.cfg_mgmt_write_data, + cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, + cfg_mgmt_read=dut.cfg_mgmt_read, + cfg_mgmt_read_data=dut.cfg_mgmt_read_data, + cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, + # cfg_mgmt_debug_access + + # Configuration Status Interface + # cfg_phy_link_down + # cfg_phy_link_status + # cfg_negotiated_width + # cfg_current_speed + cfg_max_payload=dut.cfg_max_payload, + cfg_max_read_req=dut.cfg_max_read_req, + # cfg_function_status + # cfg_vf_status + # cfg_function_power_state + # cfg_vf_power_state + # cfg_link_power_state + # cfg_err_cor_out + # cfg_err_nonfatal_out + # cfg_err_fatal_out + # cfg_local_error_out + # cfg_local_error_valid + # cfg_rx_pm_state + # cfg_tx_pm_state + # cfg_ltssm_state + cfg_rcb_status=dut.cfg_rcb_status, + # cfg_obff_enable + # cfg_pl_status_change + # cfg_tph_requester_enable + # cfg_tph_st_mode + # cfg_vf_tph_requester_enable + # cfg_vf_tph_st_mode + + # Configuration Received Message Interface + # cfg_msg_received + # cfg_msg_received_data + # cfg_msg_received_type + + # Configuration Transmit Message Interface + # cfg_msg_transmit + # cfg_msg_transmit_type + # cfg_msg_transmit_data + # cfg_msg_transmit_done + + # Configuration Flow Control Interface + cfg_fc_ph=dut.cfg_fc_ph, + cfg_fc_pd=dut.cfg_fc_pd, + cfg_fc_nph=dut.cfg_fc_nph, + cfg_fc_npd=dut.cfg_fc_npd, + cfg_fc_cplh=dut.cfg_fc_cplh, + cfg_fc_cpld=dut.cfg_fc_cpld, + cfg_fc_sel=dut.cfg_fc_sel, + + # Configuration Control Interface + # cfg_hot_reset_in + # cfg_hot_reset_out + # cfg_config_space_enable + # cfg_dsn + # cfg_bus_number + # cfg_ds_port_number + # cfg_ds_bus_number + # cfg_ds_device_number + # cfg_ds_function_number + # cfg_power_state_change_ack + # cfg_power_state_change_interrupt + cfg_err_cor_in=dut.status_error_cor, + cfg_err_uncor_in=dut.status_error_uncor, + # cfg_flr_in_process + # cfg_flr_done + # cfg_vf_flr_in_process + # cfg_vf_flr_func_num + # cfg_vf_flr_done + # cfg_pm_aspm_l1_entry_reject + # cfg_pm_aspm_tx_l0s_entry_disable + # cfg_req_pm_transition_l23_ready + # cfg_link_training_enable + + # Configuration Interrupt Controller Interface + # cfg_interrupt_int + # cfg_interrupt_sent + # cfg_interrupt_pending + # cfg_interrupt_msi_enable + # cfg_interrupt_msi_vf_enable + # cfg_interrupt_msi_mmenable + # cfg_interrupt_msi_mask_update + # cfg_interrupt_msi_data + # cfg_interrupt_msi_select + # cfg_interrupt_msi_int + # cfg_interrupt_msi_pending_status + # cfg_interrupt_msi_pending_status_data_enable + # cfg_interrupt_msi_pending_status_function_num + # cfg_interrupt_msi_sent + # cfg_interrupt_msi_fail + cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, + cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, + cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, + cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, + cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, + cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, + cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, + cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, + cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, + # cfg_interrupt_msi_attr + # cfg_interrupt_msi_tph_present + # cfg_interrupt_msi_tph_type + # cfg_interrupt_msi_tph_st_tag + cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, + + # Configuration Extend Interface + # cfg_ext_read_received + # cfg_ext_write_received + # cfg_ext_register_number + # cfg_ext_function_number + # cfg_ext_write_data + # cfg_ext_write_byte_enable + # cfg_ext_read_data + # cfg_ext_read_data_valid + ) + + # self.dev.log.setLevel(logging.DEBUG) + + self.rc.make_port().connect(self.dev) + + self.driver = mqnic.Driver() + + self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + + cocotb.start_soon(Clock(dut.ptp_clk, 3.102, units="ns").start()) + dut.ptp_rst.setimmediatevalue(0) + cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) + + # Ethernet + self.qsfp_source = [] + self.qsfp_sink = [] + + for x in range(4): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + getattr(dut, f"qsfp{x}_rx_status_{y}").setimmediatevalue(1) + getattr(dut, f"qsfp{x}_rx_error_count_{y}").setimmediatevalue(0) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) + + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_drp_clk"), 8, units="ns").start()) + getattr(dut, f"qsfp{x}_drp_rst").setimmediatevalue(0) + getattr(dut, f"qsfp{x}_drp_do").setimmediatevalue(0) + getattr(dut, f"qsfp{x}_drp_rdy").setimmediatevalue(0) + + getattr(dut, f"qsfp{x}_modprsl").setimmediatevalue(0) + getattr(dut, f"qsfp{x}_intl").setimmediatevalue(1) + getattr(dut, f"qsfp{x}_i2c_scl_i").setimmediatevalue(1) + getattr(dut, f"qsfp{x}_i2c_sda_i").setimmediatevalue(1) + + dut.eeprom_i2c_scl_i.setimmediatevalue(1) + dut.eeprom_i2c_sda_i.setimmediatevalue(1) + + dut.ext_pps_in.setimmediatevalue(0) + dut.ext_clk_in.setimmediatevalue(0) + + dut.qspi_dq_i.setimmediatevalue(0) + + self.loopback_enable = False + cocotb.start_soon(self._run_loopback()) + + async def init(self): + + self.dut.ptp_rst.setimmediatevalue(0) + for x in range(4): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) + + await RisingEdge(self.dut.clk_250mhz) + await RisingEdge(self.dut.clk_250mhz) + + self.dut.ptp_rst.setimmediatevalue(1) + for x in range(4): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(1) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(1) + + await FallingEdge(self.dut.rst_250mhz) + await Timer(100, 'ns') + + await RisingEdge(self.dut.clk_250mhz) + await RisingEdge(self.dut.clk_250mhz) + + self.dut.ptp_rst.setimmediatevalue(0) + for x in range(4): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) + + await self.rc.enumerate() + + async def _run_loopback(self): + while True: + await RisingEdge(self.dut.clk_250mhz) + + if self.loopback_enable: + for x in range(len(self.qsfp_sink)): + for y in range(len(self.qsfp_sink[x])): + if not self.qsfp_sink[x][y].empty(): + await self.qsfp_source[x][y].send(await self.qsfp_sink[x][y].recv()) + + +@cocotb.test() +async def run_test_nic(dut): + + tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) + + await tb.init() + + tb.log.info("Init driver") + await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) + await tb.driver.interfaces[0].open() + # await tb.driver.interfaces[1].open() + + # enable queues + tb.log.info("Enable queues") + await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) + for k in range(len(tb.driver.interfaces[0].txq)): + await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) + + # wait for all writes to complete + await tb.driver.hw_regs.read_dword(0) + tb.log.info("Init complete") + + tb.log.info("Send and receive single packet") + + data = bytearray([x % 256 for x in range(1024)]) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.qsfp_sink[0][0].recv() + tb.log.info("Packet: %s", pkt) + + await tb.qsfp_source[0][0].send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + # await tb.driver.interfaces[1].start_xmit(data, 0) + + # pkt = await tb.qsfp_sink[1][0].recv() + # tb.log.info("Packet: %s", pkt) + + # await tb.qsfp_source[1][0].send(pkt) + + # pkt = await tb.driver.interfaces[1].recv() + + # tb.log.info("Packet: %s", pkt) + # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.log.info("RX and TX checksum tests") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=2) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + pkt = await tb.qsfp_sink[0][0].recv() + tb.log.info("Packet: %s", pkt) + + await tb.qsfp_source[0][0].send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert Ether(pkt.data).build() == test_pkt.build() + + tb.log.info("Queue mapping offset test") + + data = bytearray([x % 256 for x in range(1024)]) + + tb.loopback_enable = True + + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert pkt.queue == k + + tb.loopback_enable = False + + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) + + tb.log.info("Queue mapping RSS mask test") + + await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + + tb.loopback_enable = True + + queues = set() + + for k in range(64): + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=k+0) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + for k in range(64): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + queues.add(pkt.queue) + + assert len(queues) == 4 + + tb.loopback_enable = False + + await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + tb.log.info("Multiple large packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + await RisingEdge(dut.clk_250mhz) + await RisingEdge(dut.clk_250mhz) + + +# cocotb-test + +tests_dir = os.path.dirname(__file__) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) +axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) +pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), + os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), + os.path.join(rtl_dir, "common", "mqnic_interface.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), + os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), + os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), + os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), + os.path.join(rtl_dir, "common", "cpl_write.v"), + os.path.join(rtl_dir, "common", "cpl_op_mux.v"), + os.path.join(rtl_dir, "common", "desc_fetch.v"), + os.path.join(rtl_dir, "common", "desc_op_mux.v"), + os.path.join(rtl_dir, "common", "queue_manager.v"), + os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), + os.path.join(rtl_dir, "common", "tx_engine.v"), + os.path.join(rtl_dir, "common", "rx_engine.v"), + os.path.join(rtl_dir, "common", "tx_checksum.v"), + os.path.join(rtl_dir, "common", "rx_hash.v"), + os.path.join(rtl_dir, "common", "rx_checksum.v"), + os.path.join(rtl_dir, "common", "rb_drp.v"), + os.path.join(rtl_dir, "common", "stats_counter.v"), + os.path.join(rtl_dir, "common", "stats_collect.v"), + os.path.join(rtl_dir, "common", "stats_pcie_if.v"), + os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), + os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), + os.path.join(rtl_dir, "common", "stats_dma_latency.v"), + os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), + os.path.join(rtl_dir, "common", "tdma_scheduler.v"), + os.path.join(rtl_dir, "common", "tdma_ber.v"), + os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "ptp_clock.v"), + os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_perout.v"), + os.path.join(axi_rtl_dir, "axil_interconnect.v"), + os.path.join(axi_rtl_dir, "axil_crossbar.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), + os.path.join(axi_rtl_dir, "axil_reg_if.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), + os.path.join(axi_rtl_dir, "axil_register_rd.v"), + os.path.join(axi_rtl_dir, "axil_register_wr.v"), + os.path.join(axi_rtl_dir, "arbiter.v"), + os.path.join(axi_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_adapter.v"), + os.path.join(axis_rtl_dir, "axis_arb_mux.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), + os.path.join(axis_rtl_dir, "axis_register.v"), + os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), + os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_psdpram.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), + os.path.join(pcie_rtl_dir, "pulse_merge.v"), + ] + + parameters = {} + + # Structural configuration + parameters['IF_COUNT'] = 2 + parameters['PORTS_PER_IF'] = 1 + parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] + parameters['PORT_MASK'] = 0 + + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + + # PTP configuration + parameters['PTP_CLK_PERIOD_NS_NUM'] = 512 + parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 + parameters['PTP_CLOCK_PIPELINE'] = 0 + parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 + parameters['PTP_USE_SAMPLE_CLOCK'] = 1 + parameters['PTP_PORT_CDC_PIPELINE'] = 0 + parameters['PTP_PEROUT_ENABLE'] = 0 + parameters['PTP_PEROUT_COUNT'] = 1 + + # Queue manager configuration + parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 + parameters['TX_QUEUE_INDEX_WIDTH'] = 9 + parameters['RX_QUEUE_INDEX_WIDTH'] = 8 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 + parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) + + # TX and RX engine configuration + parameters['TX_DESC_TABLE_SIZE'] = 32 + parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) + + # Scheduler configuration + parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] + parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['TDMA_INDEX_WIDTH'] = 6 + + # Interface configuration + parameters['PTP_TS_ENABLE'] = 1 + parameters['TX_CPL_FIFO_DEPTH'] = 32 + parameters['TX_CHECKSUM_ENABLE'] = 1 + parameters['RX_HASH_ENABLE'] = 1 + parameters['RX_CHECKSUM_ENABLE'] = 1 + parameters['TX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 32768 + parameters['MAX_TX_SIZE'] = 9214 + parameters['MAX_RX_SIZE'] = 9214 + parameters['TX_RAM_SIZE'] = 32768 + parameters['RX_RAM_SIZE'] = 32768 + + # Application block configuration + parameters['APP_ID'] = 0x00000000 + parameters['APP_ENABLE'] = 0 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + + # DMA interface configuration + parameters['DMA_IMM_ENABLE'] = 0 + parameters['DMA_IMM_WIDTH'] = 32 + parameters['DMA_LEN_WIDTH'] = 16 + parameters['DMA_TAG_WIDTH'] = 16 + parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() + parameters['RAM_PIPELINE'] = 2 + + # PCIe interface configuration + parameters['AXIS_PCIE_DATA_WIDTH'] = 256 + parameters['PF_COUNT'] = 1 + parameters['VF_COUNT'] = 0 + + # Interrupt configuration + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_WIDTH'] = 32 + parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 + + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + + # Ethernet interface configuration + parameters['AXIS_ETH_TX_PIPELINE'] = 0 + parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 + parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0 + parameters['AXIS_ETH_RX_PIPELINE'] = 0 + parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2 + + # Statistics counter subsystem + parameters['STAT_ENABLE'] = 1 + parameters['STAT_DMA_ENABLE'] = 1 + parameters['STAT_PCIE_ENABLE'] = 1 + parameters['STAT_INC_WIDTH'] = 24 + parameters['STAT_ID_WIDTH'] = 12 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/modules/mqnic/mqnic_board.c b/modules/mqnic/mqnic_board.c index 1ae95fe6e..5d2dc9504 100644 --- a/modules/mqnic/mqnic_board.c +++ b/modules/mqnic/mqnic_board.c @@ -606,6 +606,7 @@ static int mqnic_generic_board_init(struct mqnic_dev *mqnic) init_mac_list_from_eeprom(mqnic, mqnic->eeprom_i2c_client, 0x4B, 16); break; + case MQNIC_BOARD_ID_XUSP3S: case MQNIC_BOARD_ID_XUPP3R: request_module("at24"); diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h index c5d147d93..ea8a0477d 100644 --- a/modules/mqnic/mqnic_hw.h +++ b/modules/mqnic/mqnic_hw.h @@ -41,6 +41,7 @@ #define MQNIC_BOARD_ID_DK_DEV_1SDX_P_A 0x1172a00d #define MQNIC_BOARD_ID_DK_DEV_AGF014EA 0x1172b00e #define MQNIC_BOARD_ID_DE10_AGILEX 0x1172b00a +#define MQNIC_BOARD_ID_XUSP3S 0x12ba8823 #define MQNIC_BOARD_ID_XUPP3R 0x12ba9823 #define MQNIC_BOARD_ID_520NMX 0x198a0521 #define MQNIC_BOARD_ID_250SOC 0x198a250e