Add enable signal

rtl/eth_arb_mux.py

@@ -141,6 +141,7 @@ module {{name}} #
 wire [{{n-1}}:0] request;
 wire [{{n-1}}:0] acknowledge;
 wire [{{n-1}}:0] grant;
+wire grant_valid;
 wire [{{w-1}}:0] grant_encoded;
 {% for p in ports %}
 assign acknowledge[{{p}}] = input_{{p}}_eth_payload_tvalid & input_{{p}}_eth_payload_tready & input_{{p}}_eth_payload_tlast;
@@ -174,6 +175,7 @@ mux_inst (
     .output_eth_payload_tready(output_eth_payload_tready),
     .output_eth_payload_tlast(output_eth_payload_tlast),
     .output_eth_payload_tuser(output_eth_payload_tuser),
+    .enable(grant_valid),
     .select(grant_encoded)
 );
 
@@ -189,6 +191,7 @@ arb_inst (
     .request(request),
     .acknowledge(acknowledge),
     .grant(grant),
+    .grant_valid(grant_valid),
     .grant_encoded(grant_encoded)
 );
 

rtl/eth_arb_mux_4.v

@@ -103,6 +103,7 @@ module eth_arb_mux_4 #
 wire [3:0] request;
 wire [3:0] acknowledge;
 wire [3:0] grant;
+wire grant_valid;
 wire [1:0] grant_encoded;
 
 assign acknowledge[0] = input_0_eth_payload_tvalid & input_0_eth_payload_tready & input_0_eth_payload_tlast;
@@ -169,6 +170,7 @@ mux_inst (
     .output_eth_payload_tready(output_eth_payload_tready),
     .output_eth_payload_tlast(output_eth_payload_tlast),
     .output_eth_payload_tuser(output_eth_payload_tuser),
+    .enable(grant_valid),
     .select(grant_encoded)
 );
 
@@ -184,6 +186,7 @@ arb_inst (
     .request(request),
     .acknowledge(acknowledge),
     .grant(grant),
+    .grant_valid(grant_valid),
     .grant_encoded(grant_encoded)
 );
 

rtl/eth_arb_mux_64.py

@@ -143,6 +143,7 @@ module {{name}} #
 wire [{{n-1}}:0] request;
 wire [{{n-1}}:0] acknowledge;
 wire [{{n-1}}:0] grant;
+wire grant_valid;
 wire [{{w-1}}:0] grant_encoded;
 {% for p in ports %}
 assign acknowledge[{{p}}] = input_{{p}}_eth_payload_tvalid & input_{{p}}_eth_payload_tready & input_{{p}}_eth_payload_tlast;
@@ -178,6 +179,7 @@ mux_inst (
     .output_eth_payload_tready(output_eth_payload_tready),
     .output_eth_payload_tlast(output_eth_payload_tlast),
     .output_eth_payload_tuser(output_eth_payload_tuser),
+    .enable(grant_valid),
     .select(grant_encoded)
 );
 
@@ -193,6 +195,7 @@ arb_inst (
     .request(request),
     .acknowledge(acknowledge),
     .grant(grant),
+    .grant_valid(grant_valid),
     .grant_encoded(grant_encoded)
 );
 

rtl/eth_arb_mux_64_4.v

@@ -108,6 +108,7 @@ module eth_arb_mux_64_4 #
 wire [3:0] request;
 wire [3:0] acknowledge;
 wire [3:0] grant;
+wire grant_valid;
 wire [1:0] grant_encoded;
 
 assign acknowledge[0] = input_0_eth_payload_tvalid & input_0_eth_payload_tready & input_0_eth_payload_tlast;
@@ -179,6 +180,7 @@ mux_inst (
     .output_eth_payload_tready(output_eth_payload_tready),
     .output_eth_payload_tlast(output_eth_payload_tlast),
     .output_eth_payload_tuser(output_eth_payload_tuser),
+    .enable(grant_valid),
     .select(grant_encoded)
 );
 
@@ -194,6 +196,7 @@ arb_inst (
     .request(request),
     .acknowledge(acknowledge),
     .grant(grant),
+    .grant_valid(grant_valid),
     .grant_encoded(grant_encoded)
 );
 

rtl/eth_mux.py

@@ -136,6 +136,7 @@ module {{name}}
     /*
      * Control
      */
+    input  wire        enable,
     input  wire [{{w-1}}:0]  select
 );
 
@@ -230,7 +231,7 @@ always @* begin
             // end of frame detection
             frame_next = ~current_input_tlast;
         end
-    end else if (selected_input_eth_hdr_valid) begin
+    end else if (enable & selected_input_eth_hdr_valid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;

rtl/eth_mux_4.v

@@ -98,6 +98,7 @@ module eth_mux_4
     /*
      * Control
      */
+    input  wire        enable,
     input  wire [1:0]  select
 );
 
@@ -239,7 +240,7 @@ always @* begin
             // end of frame detection
             frame_next = ~current_input_tlast;
         end
-    end else if (selected_input_eth_hdr_valid) begin
+    end else if (enable & selected_input_eth_hdr_valid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;

rtl/eth_mux_64.py

@@ -138,6 +138,7 @@ module {{name}}
     /*
      * Control
      */
+    input  wire        enable,
     input  wire [{{w-1}}:0]  select
 );
 
@@ -235,7 +236,7 @@ always @* begin
             // end of frame detection
             frame_next = ~current_input_tlast;
         end
-    end else if (selected_input_eth_hdr_valid) begin
+    end else if (enable & selected_input_eth_hdr_valid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;

rtl/eth_mux_64_4.v

@@ -103,6 +103,7 @@ module eth_mux_64_4
     /*
      * Control
      */
+    input  wire        enable,
     input  wire [1:0]  select
 );
 
@@ -250,7 +251,7 @@ always @* begin
             // end of frame detection
             frame_next = ~current_input_tlast;
         end
-    end else if (selected_input_eth_hdr_valid) begin
+    end else if (enable & selected_input_eth_hdr_valid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;

tb/test_eth_mux_4.py

@@ -96,6 +96,7 @@ def dut_eth_mux_4(clk,
                  output_eth_payload_tlast,
                  output_eth_payload_tuser,
 
+                 enable,
                  select):
 
     if os.system(build_cmd):
@@ -157,6 +158,7 @@ def dut_eth_mux_4(clk,
                 output_eth_payload_tlast=output_eth_payload_tlast,
                 output_eth_payload_tuser=output_eth_payload_tuser,
 
+                enable=enable,
                 select=select)
 
 def bench():
@@ -202,6 +204,7 @@ def bench():
     output_eth_payload_tready = Signal(bool(0))
     output_eth_hdr_ready = Signal(bool(0))
 
+    enable = Signal(bool(0))
     select = Signal(intbv(0)[2:])
 
     # Outputs
@@ -372,6 +375,7 @@ def bench():
                        output_eth_payload_tlast,
                        output_eth_payload_tuser,
 
+                       enable,
                        select)
 
     @always(delay(4))
@@ -390,6 +394,7 @@ def bench():
         yield clk.posedge
 
         yield clk.posedge
+        enable.next = True
 
         yield clk.posedge
         print("test 1: select port 0")

tb/test_eth_mux_4.v

@@ -69,6 +69,7 @@ reg input_3_eth_payload_tuser = 0;
 reg output_eth_hdr_ready = 0;
 reg output_eth_payload_tready = 0;
 
+reg enable = 0;
 reg [1:0] select = 0;
 
 // Outputs
@@ -129,6 +130,7 @@ initial begin
                 input_3_eth_payload_tuser,
                 output_eth_hdr_ready,
                 output_eth_payload_tready,
+                enable,
                 select);
     $to_myhdl(input_0_eth_hdr_ready,
               input_0_eth_payload_tready,
@@ -209,6 +211,7 @@ UUT (
     .output_eth_payload_tlast(output_eth_payload_tlast),
     .output_eth_payload_tuser(output_eth_payload_tuser),
     // Control
+    .enable(enable),
     .select(select)
 );
 

tb/test_eth_mux_64_4.py

@@ -101,6 +101,7 @@ def dut_eth_mux_64_4(clk,
                  output_eth_payload_tlast,
                  output_eth_payload_tuser,
 
+                 enable,
                  select):
 
     if os.system(build_cmd):
@@ -167,6 +168,7 @@ def dut_eth_mux_64_4(clk,
                 output_eth_payload_tlast=output_eth_payload_tlast,
                 output_eth_payload_tuser=output_eth_payload_tuser,
 
+                enable=enable,
                 select=select)
 
 def bench():
@@ -216,6 +218,7 @@ def bench():
     output_eth_payload_tready = Signal(bool(0))
     output_eth_hdr_ready = Signal(bool(0))
 
+    enable = Signal(bool(0))
     select = Signal(intbv(0)[2:])
 
     # Outputs
@@ -397,6 +400,7 @@ def bench():
                        output_eth_payload_tlast,
                        output_eth_payload_tuser,
 
+                       enable,
                        select)
 
     @always(delay(4))
@@ -415,6 +419,7 @@ def bench():
         yield clk.posedge
 
         yield clk.posedge
+        enable.next = True
 
         yield clk.posedge
         print("test 1: select port 0")

tb/test_eth_mux_64_4.v

@@ -73,6 +73,7 @@ reg input_3_eth_payload_tuser = 0;
 reg output_eth_hdr_ready = 0;
 reg output_eth_payload_tready = 0;
 
+reg enable = 0;
 reg [1:0] select = 0;
 
 // Outputs
@@ -138,6 +139,7 @@ initial begin
                 input_3_eth_payload_tuser,
                 output_eth_hdr_ready,
                 output_eth_payload_tready,
+                enable,
                 select);
     $to_myhdl(input_0_eth_hdr_ready,
               input_0_eth_payload_tready,
@@ -224,6 +226,7 @@ UUT (
     .output_eth_payload_tlast(output_eth_payload_tlast),
     .output_eth_payload_tuser(output_eth_payload_tuser),
     // Control
+    .enable(enable),
     .select(select)
 );