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https://github.com/corundum/corundum.git
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Add mqnic-dump utility
This commit is contained in:
Alex Forencich
parent
317aa34db5
commit
f35d576301
@ -5,13 +5,16 @@ BINDIR=$(DESTDIR)$(PREFIX)/bin
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CC=gcc
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CFLAGS=-O3 -Wall -I../modules/mqnic
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BIN=mqnic-config mqnic-fw perout
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BIN=mqnic-config mqnic-dump mqnic-fw perout
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all: $(BIN)
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mqnic-config: mqnic-config.c mqnic.c timespec.c
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$(CC) $(CFLAGS) $^ -o $@
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mqnic-dump: mqnic-dump.c mqnic.c
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$(CC) $(CFLAGS) $^ -o $@
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mqnic-fw: mqnic-fw.c mqnic.c
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$(CC) $(CFLAGS) $^ -o $@
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241
utils/mqnic-dump.c
Normal file
241
utils/mqnic-dump.c
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@ -0,0 +1,241 @@
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/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "mqnic.h"
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static void usage(char *name)
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{
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fprintf(stderr,
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"usage: %s [options]\n"
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" -d name device to open (/dev/mqnic0)\n"
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" -i number interface\n"
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" -P number port\n",
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name);
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}
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int main(int argc, char *argv[])
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{
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char *name;
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int opt;
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int ret = 0;
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char *device = NULL;
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struct mqnic *dev;
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int interface = 0;
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int port = 0;
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name = strrchr(argv[0], '/');
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name = name ? 1+name : argv[0];
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while ((opt = getopt(argc, argv, "d:i:P:h?")) != EOF)
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{
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switch (opt)
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{
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case 'd':
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device = optarg;
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break;
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case 'i':
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interface = atoi(optarg);
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break;
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case 'P':
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port = atoi(optarg);
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break;
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case 'h':
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case '?':
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usage(name);
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return 0;
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default:
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usage(name);
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return -1;
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}
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}
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if (!device)
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{
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fprintf(stderr, "Device not specified\n");
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usage(name);
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return -1;
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}
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dev = mqnic_open(device);
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if (!dev)
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{
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fprintf(stderr, "Failed to open device\n");
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return -1;
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}
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printf("FW ID: 0x%08x\n", dev->fw_id);
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printf("FW version: %d.%d\n", dev->fw_ver >> 16, dev->fw_ver & 0xffff);
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printf("Board ID: 0x%08x\n", dev->board_id);
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printf("Board version: %d.%d\n", dev->board_ver >> 16, dev->board_ver & 0xffff);
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printf("PHC count: %d\n", dev->phc_count);
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printf("PHC offset: 0x%08x\n", dev->phc_offset);
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printf("IF count: %d\n", dev->if_count);
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printf("IF stride: 0x%08x\n", dev->if_stride);
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printf("IF CSR offset: 0x%08x\n", dev->if_csr_offset);
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if (interface < 0 || interface >= dev->if_count)
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{
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fprintf(stderr, "Interface out of range\n");
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ret = -1;
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goto err;
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}
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struct mqnic_if *dev_interface = &dev->interfaces[interface];
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printf("IF ID: 0x%08x\n", dev_interface->if_id);
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printf("Event queue count: %d\n", dev_interface->event_queue_count);
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printf("Event queue offset: 0x%08x\n", dev_interface->event_queue_offset);
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printf("TX queue count: %d\n", dev_interface->tx_queue_count);
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printf("TX queue offset: 0x%08x\n", dev_interface->tx_queue_offset);
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printf("TX completion queue count: %d\n", dev_interface->tx_cpl_queue_count);
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printf("TX completion queue offset: 0x%08x\n", dev_interface->tx_cpl_queue_offset);
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printf("RX queue count: %d\n", dev_interface->rx_queue_count);
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printf("RX queue offset: 0x%08x\n", dev_interface->rx_queue_offset);
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printf("RX completion queue count: %d\n", dev_interface->rx_cpl_queue_count);
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printf("RX completion queue offset: 0x%08x\n", dev_interface->rx_cpl_queue_offset);
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printf("Port count: %d\n", dev_interface->port_count);
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printf("Port offset: 0x%08x\n", dev_interface->port_offset);
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printf("Port stride: 0x%08x\n", dev_interface->port_stride);
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if (port < 0 || port >= dev_interface->port_count)
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{
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fprintf(stderr, "Port out of range\n");
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ret = -1;
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goto err;
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}
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struct mqnic_port *dev_port = &dev_interface->ports[port];
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printf("Port ID: 0x%08x\n", dev_port->port_id);
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printf("Sched count: %d\n", dev_port->sched_count);
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printf("Sched offset: 0x%08x\n", dev_port->sched_offset);
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printf("Sched stride: 0x%08x\n", dev_port->sched_stride);
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printf("Sched type: 0x%08x\n", dev_port->sched_type);
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printf("Timeslot count: %d\n", dev_port->tdma_timeslot_count);
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printf("TX queue info\n");
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printf(" Queue Base Address E LS CPL Head Tail Len\n");
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for (int k = 0; k < dev_interface->tx_queue_count; k++)
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{
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volatile uint8_t *base = dev_interface->regs+dev_interface->tx_queue_offset+k*MQNIC_QUEUE_STRIDE;
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uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG+4) << 32);
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uint8_t active = (mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_QUEUE_ACTIVE_MASK) != 0;
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uint8_t log_size = mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
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uint32_t cpl_queue_index = mqnic_reg_read32(base, MQNIC_QUEUE_CPL_QUEUE_INDEX_REG);
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uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_QUEUE_HEAD_PTR_REG);
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uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_QUEUE_TAIL_PTR_REG);
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uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
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printf("TXQ %4d 0x%016lx %d %2d %4d %6d %6d %6d\n", k, base_addr, active, log_size, cpl_queue_index, head_ptr, tail_ptr, occupancy);
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}
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printf("TX completion queue info\n");
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printf(" Queue Base Address E LS A C Int Head Tail Len\n");
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for (int k = 0; k < dev_interface->tx_queue_count; k++)
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{
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volatile uint8_t *base = dev_interface->regs+dev_interface->tx_cpl_queue_offset+k*MQNIC_CPL_QUEUE_STRIDE;
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uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG+4) << 32);
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uint8_t active = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_CPL_QUEUE_ACTIVE_MASK) != 0;
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uint8_t log_size = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
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uint8_t armed = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_ARM_MASK) != 0;
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uint8_t continuous = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_CONT_MASK) != 0;
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uint32_t interrupt_index = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & 0xffff;
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uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_HEAD_PTR_REG);
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uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_TAIL_PTR_REG);
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uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
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printf("TXCQ %4d 0x%016lx %d %2d %d %d %4d %6d %6d %6d\n", k, base_addr, active, log_size, armed, continuous, interrupt_index, head_ptr, tail_ptr, occupancy);
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}
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printf("RX queue info\n");
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printf(" Queue Base Address E LS CPL Head Tail Len\n");
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for (int k = 0; k < dev_interface->tx_queue_count; k++)
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{
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volatile uint8_t *base = dev_interface->regs+dev_interface->rx_queue_offset+k*MQNIC_QUEUE_STRIDE;
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uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_QUEUE_BASE_ADDR_REG+4) << 32);
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uint8_t active = (mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_QUEUE_ACTIVE_MASK) != 0;
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uint8_t log_size = mqnic_reg_read32(base, MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
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uint32_t cpl_queue_index = mqnic_reg_read32(base, MQNIC_QUEUE_CPL_QUEUE_INDEX_REG);
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uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_QUEUE_HEAD_PTR_REG);
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uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_QUEUE_TAIL_PTR_REG);
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uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
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printf("RXQ %4d 0x%016lx %d %2d %4d %6d %6d %6d\n", k, base_addr, active, log_size, cpl_queue_index, head_ptr, tail_ptr, occupancy);
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}
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printf("RX completion queue info\n");
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printf(" Queue Base Address E LS A C Int Head Tail Len\n");
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for (int k = 0; k < dev_interface->tx_queue_count; k++)
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{
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volatile uint8_t *base = dev_interface->regs+dev_interface->rx_cpl_queue_offset+k*MQNIC_CPL_QUEUE_STRIDE;
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uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CPL_QUEUE_BASE_ADDR_REG+4) << 32);
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uint8_t active = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & MQNIC_CPL_QUEUE_ACTIVE_MASK) != 0;
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uint8_t log_size = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG) & 0xff;
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uint8_t armed = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_ARM_MASK) != 0;
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uint8_t continuous = (mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & MQNIC_CPL_QUEUE_CONT_MASK) != 0;
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uint32_t interrupt_index = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG) & 0xffff;
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uint32_t head_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_HEAD_PTR_REG);
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uint32_t tail_ptr = mqnic_reg_read32(base, MQNIC_CPL_QUEUE_TAIL_PTR_REG);
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uint32_t occupancy = (head_ptr - tail_ptr) & 0xffff;
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printf("RXCQ %4d 0x%016lx %d %2d %d %d %4d %6d %6d %6d\n", k, base_addr, active, log_size, armed, continuous, interrupt_index, head_ptr, tail_ptr, occupancy);
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}
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for (int k = 0; k < dev_port->sched_count; k++)
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{
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printf("Port %d scheduler %d\n", port, k);
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for (int l = 0; l < dev_interface->tx_queue_count; l++)
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{
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printf("Sched %2d queue %4d state: 0x%08x\n", k, l, mqnic_reg_read32(dev_port->sched[k].regs, l*4));
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}
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}
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err:
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mqnic_close(dev);
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return ret;
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}
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