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Add ExaNIC X25 mqnic design
This commit is contained in:
Alex Forencich
parent
533f19dfb7
commit
f43cd09dac
@ -28,6 +28,7 @@ devices. Desgins are included for the following FPGA boards:
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* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex Ultrascale Plus XCVU3P)
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* Exablaze ExaNIC X10 (Xilinx Kintex Ultrascale XCKU035)
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* Exablaze ExaNIC X25 (Xilinx Kintex Ultrascale Plus XCKU3P)
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* Xilinx VCU108 (Xilinx Virtex Ultrascale XCVU095)
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* Xilinx VCU118 (Xilinx Virtex Ultrascale Plus XCVU9P)
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25
fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile
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25
fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile
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@ -0,0 +1,25 @@
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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
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24
fpga/mqnic/ExaNIC_X25/fpga_10g/README.md
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24
fpga/mqnic/ExaNIC_X25/fpga_10g/README.md
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@ -0,0 +1,24 @@
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# Corundum mqnic for ExaNIC X25
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## Introduction
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This design targets the Exablaze ExaNIC X25 FPGA board.
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FPGA: xcku3p-ffvb676-2-e
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PHY: 10G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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Run make to build the driver. Ensure the headers for the running kernel are
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installed, otherwise the driver cannot be compiled.
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## How to test
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Run make program to program the ExaNIC X25 board with Vivado. Then load the
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driver with insmod mqnic.ko. Check dmesg for output from driver
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initialization.
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118
fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk
Normal file
118
fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk
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@ -0,0 +1,118 @@
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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tmpclean:
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-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean: tmpclean
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-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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distclean: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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%.xpr: Makefile $(XCI_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
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echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
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for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
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for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
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echo "exit" >> create_project.tcl
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vivado -nojournal -nolog -mode batch -source create_project.tcl
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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echo "exit" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "exit" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.bit" >> generate_bit.tcl
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echo "exit" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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158
fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc
Normal file
158
fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc
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@ -0,0 +1,158 @@
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# XDC constraints for the ExaNIC X25
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# part: xcku3p-ffvb676-2-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 31.9 [current_design]
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set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 8 [current_design]
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set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 4 [current_design]
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set_property BITSTREAM.CONFIG.REVISIONSELECT_TRISTATE Enable [current_design]
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set_property CONFIG_MODE BPI16 [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# 10 MHz TXCO
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#set_property -dict {LOC D14 IOSTANDARD LVCMOS33} [get_ports clk_10mhz]
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#create_clock -period 100 -name clk_100mhz [get_ports clk_10mhz]
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# LEDs
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set_property -dict {LOC J12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[0]}]
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set_property -dict {LOC H12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[1]}]
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set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[0]}]
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set_property -dict {LOC H13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[1]}]
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set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
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set_property -dict {LOC G12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
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# GPIO
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#set_property -dict {LOC F9 IOSTANDARD LVCMOS18} [get_ports gpio[0]]
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#set_property -dict {LOC F10 IOSTANDARD LVCMOS18} [get_ports gpio[1]]
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#set_property -dict {LOC G9 IOSTANDARD LVCMOS18} [get_ports gpio[2]]
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#set_property -dict {LOC G10 IOSTANDARD LVCMOS18} [get_ports gpio[3]]
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# SMA
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set_property -dict {LOC A14 IOSTANDARD LVCMOS33} [get_ports sma_in]
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set_property -dict {LOC A12 IOSTANDARD LVCMOS33} [get_ports sma_out]
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set_property -dict {LOC A13 IOSTANDARD LVCMOS33} [get_ports sma_out_en]
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set_property -dict {LOC B12 IOSTANDARD LVCMOS33} [get_ports sma_term_en]
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# Config
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#set_property -dict {LOC C14 IOSTANDARD LVCMOS33} [get_ports ddr_npres]
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# SFP28 Interfaces
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set_property -dict {LOC D2 } [get_ports sfp_1_rx_p] ;# MGTYRXP0_227 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC D1 } [get_ports sfp_1_rx_n] ;# MGTYRXN0_227 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC A4 } [get_ports sfp_2_rx_p] ;# MGTYRXP3_227 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC A3 } [get_ports sfp_2_rx_n] ;# MGTYRXN3_227 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC F7 } [get_ports sfp_1_tx_p] ;# MGTYTXP0_227 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC F6 } [get_ports sfp_1_tx_n] ;# MGTYTXN0_227 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC B7 } [get_ports sfp_2_tx_p] ;# MGTYTXP3_227 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC B6 } [get_ports sfp_2_tx_n] ;# MGTYTXN3_227 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC K7 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_227 from X2
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#set_property -dict {LOC K6 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_227 from X2
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set_property -dict {LOC AC17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable]
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set_property -dict {LOC AA17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable]
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set_property -dict {LOC F12 IOSTANDARD LVCMOS33 PULLUP true} [get_ports sfp_1_npres]
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set_property -dict {LOC F14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports sfp_2_npres]
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set_property -dict {LOC AC16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_los]
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set_property -dict {LOC Y17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los]
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set_property -dict {LOC G14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_1_rs]
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set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_2_rs]
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set_property -dict {LOC A10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl]
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set_property -dict {LOC C11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda]
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set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda]
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# 161.1328125 MHz MGT reference clock
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create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
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# I2C interface
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set_property -dict {LOC B9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
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set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
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# PCIe Interface
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set_property -dict {LOC P2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC P1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC R5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC R4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC T2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC T1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC U5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC U4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC V2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC V1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC W5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC W4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC AA5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC AA4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
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#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
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set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
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#set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
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set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
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#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
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set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
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#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
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set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
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#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
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set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
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#set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
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set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
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#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
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set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC V7 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC V6 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_225
|
||||
set_property -dict {LOC T19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
|
||||
|
||||
# Flash
|
||||
set_property -dict {LOC AF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[0]}]
|
||||
set_property -dict {LOC AE18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[1]}]
|
||||
set_property -dict {LOC AF19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[2]}]
|
||||
set_property -dict {LOC AF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[3]}]
|
||||
set_property -dict {LOC AB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
|
||||
set_property -dict {LOC AD19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
|
||||
set_property -dict {LOC AB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
|
||||
set_property -dict {LOC AE17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
|
||||
set_property -dict {LOC AD16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
|
||||
set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
|
||||
set_property -dict {LOC AD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
|
||||
set_property -dict {LOC AC21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
|
||||
set_property -dict {LOC AE22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
|
||||
set_property -dict {LOC AF22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
|
||||
set_property -dict {LOC AF25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
|
||||
set_property -dict {LOC AF24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
|
||||
set_property -dict {LOC AE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
|
||||
set_property -dict {LOC AE26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
|
||||
set_property -dict {LOC AD24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
|
||||
set_property -dict {LOC AC23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
|
||||
set_property -dict {LOC AE23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
|
||||
set_property -dict {LOC AD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
|
||||
set_property -dict {LOC AC24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
|
||||
set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
|
||||
set_property -dict {LOC AD23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
|
||||
set_property -dict {LOC AD21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
|
||||
set_property -dict {LOC AB22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
|
||||
set_property -dict {LOC AA22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
|
||||
set_property -dict {LOC AE25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
|
||||
set_property -dict {LOC AD26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
|
||||
set_property -dict {LOC AB25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
|
||||
set_property -dict {LOC AB26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
|
||||
set_property -dict {LOC AD25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
|
||||
set_property -dict {LOC AC26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
|
||||
set_property -dict {LOC AB21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
|
||||
set_property -dict {LOC AB24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
|
||||
set_property -dict {LOC Y18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
|
||||
set_property -dict {LOC AA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
|
||||
set_property -dict {LOC AC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
|
||||
set_property -dict {LOC Y20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
|
||||
set_property -dict {LOC AF18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_ce_n}]
|
||||
set_property -dict {LOC Y21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
|
||||
set_property -dict {LOC AB20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
|
||||
set_property -dict {LOC AF23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
|
||||
|
||||
132
fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
Normal file
132
fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
Normal file
@ -0,0 +1,132 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku3p-ffvb676-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_reset.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/interface.v
|
||||
SYN_FILES += rtl/common/port.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl
|
||||
XDC_FILES += ../../../common/syn/tdma_ber_ch.tcl
|
||||
|
||||
# IP
|
||||
XCI_FILES = ip/pcie4_uscale_plus_0.xci
|
||||
XCI_FILES += ip/gtwizard_ultrascale_0.xci
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s29gl256p-bpi-x16}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.BPI_RS_PINS {none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
1406
fpga/mqnic/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.xci
Normal file
1406
fpga/mqnic/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.xci
Normal file
File diff suppressed because it is too large
Load Diff
1278
fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.xci
Normal file
1278
fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.xci
Normal file
File diff suppressed because it is too large
Load Diff
1
fpga/mqnic/ExaNIC_X25/fpga_10g/lib
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/lib
Symbolic link
@ -0,0 +1 @@
|
||||
../../../lib/
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/rtl/
|
||||
89
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/debounce_switch.v
Normal file
89
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/debounce_switch.v
Normal file
@ -0,0 +1,89 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes switch and button inputs with a slow sampled shift register
|
||||
*/
|
||||
module debounce_switch #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=3, // length of shift register
|
||||
parameter RATE=125000 // clock division factor
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [23:0] cnt_reg = 24'd0;
|
||||
|
||||
reg [N-1:0] debounce_reg[WIDTH-1:0];
|
||||
|
||||
reg [WIDTH-1:0] state;
|
||||
|
||||
/*
|
||||
* The synchronized output is the state register
|
||||
*/
|
||||
assign out = state;
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
cnt_reg <= 0;
|
||||
state <= 0;
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= 0;
|
||||
end
|
||||
end else begin
|
||||
if (cnt_reg < RATE) begin
|
||||
cnt_reg <= cnt_reg + 24'd1;
|
||||
end else begin
|
||||
cnt_reg <= 24'd0;
|
||||
end
|
||||
|
||||
if (cnt_reg == 24'd0) begin
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
|
||||
end
|
||||
end
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
if (|debounce_reg[k] == 0) begin
|
||||
state[k] <= 0;
|
||||
end else if (&debounce_reg[k] == 1) begin
|
||||
state[k] <= 1;
|
||||
end else begin
|
||||
state[k] <= state[k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
981
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v
Normal file
981
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v
Normal file
@ -0,0 +1,981 @@
|
||||
/*
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga (
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire [1:0] sfp_1_led,
|
||||
output wire [1:0] sfp_2_led,
|
||||
output wire [1:0] sma_led,
|
||||
|
||||
input wire sma_in,
|
||||
output wire sma_out,
|
||||
output wire sma_out_en,
|
||||
output wire sma_term_en,
|
||||
|
||||
/*
|
||||
* PCI express
|
||||
*/
|
||||
input wire [7:0] pcie_rx_p,
|
||||
input wire [7:0] pcie_rx_n,
|
||||
output wire [7:0] pcie_tx_p,
|
||||
output wire [7:0] pcie_tx_n,
|
||||
input wire pcie_refclk_p,
|
||||
input wire pcie_refclk_n,
|
||||
input wire pcie_reset_n,
|
||||
|
||||
/*
|
||||
* Ethernet: SFP28
|
||||
*/
|
||||
input wire sfp_1_rx_p,
|
||||
input wire sfp_1_rx_n,
|
||||
output wire sfp_1_tx_p,
|
||||
output wire sfp_1_tx_n,
|
||||
input wire sfp_2_rx_p,
|
||||
input wire sfp_2_rx_n,
|
||||
output wire sfp_2_tx_p,
|
||||
output wire sfp_2_tx_n,
|
||||
input wire sfp_mgt_refclk_p,
|
||||
input wire sfp_mgt_refclk_n,
|
||||
output wire sfp_1_tx_disable,
|
||||
output wire sfp_2_tx_disable,
|
||||
input wire sfp_1_npres,
|
||||
input wire sfp_2_npres,
|
||||
input wire sfp_1_los,
|
||||
input wire sfp_2_los,
|
||||
output wire sfp_1_rs,
|
||||
output wire sfp_2_rs,
|
||||
|
||||
inout wire sfp_i2c_scl,
|
||||
inout wire sfp_1_i2c_sda,
|
||||
inout wire sfp_2_i2c_sda,
|
||||
|
||||
inout wire eeprom_i2c_scl,
|
||||
inout wire eeprom_i2c_sda,
|
||||
|
||||
/*
|
||||
* BPI Flash
|
||||
*/
|
||||
inout wire [15:0] flash_dq,
|
||||
output wire [22:0] flash_addr,
|
||||
output wire flash_region,
|
||||
output wire flash_ce_n,
|
||||
output wire flash_oe_n,
|
||||
output wire flash_we_n,
|
||||
output wire flash_adv_n
|
||||
);
|
||||
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 256;
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = 75;
|
||||
parameter AXIS_PCIE_RQ_USER_WIDTH = 62;
|
||||
parameter AXIS_PCIE_CQ_USER_WIDTH = 88;
|
||||
parameter AXIS_PCIE_CC_USER_WIDTH = 33;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
wire pcie_user_reset;
|
||||
|
||||
wire clk_161mhz_int;
|
||||
|
||||
wire clk_125mhz_mmcm_out;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
// Internal 156.25 MHz clock
|
||||
wire clk_156mhz_int;
|
||||
wire rst_156mhz_int;
|
||||
|
||||
wire mmcm_rst = pcie_user_reset;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
// 161.13 MHz in, 125 MHz out
|
||||
// PFD range: 10 MHz to 500 MHz
|
||||
// VCO range: 800 MHz to 1600 MHz
|
||||
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
|
||||
// Divide by 7.5 to get output frequency of 125 MHz
|
||||
MMCME4_BASE #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
.DIVCLK_DIVIDE(11),
|
||||
.REF_JITTER1(0.010),
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.STARTUP_WAIT("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
.CLKIN1(clk_161mhz_int),
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.RST(mmcm_rst),
|
||||
.PWRDWN(1'b0),
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
.CLKOUT4(),
|
||||
.CLKOUT5(),
|
||||
.CLKOUT6(),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.sync_reset_out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire sfp_i2c_scl_i;
|
||||
wire sfp_i2c_scl_o;
|
||||
wire sfp_i2c_scl_t;
|
||||
wire sfp_1_i2c_sda_i;
|
||||
wire sfp_1_i2c_sda_o;
|
||||
wire sfp_1_i2c_sda_t;
|
||||
wire sfp_2_i2c_sda_i;
|
||||
wire sfp_2_i2c_sda_o;
|
||||
wire sfp_2_i2c_sda_t;
|
||||
wire eeprom_i2c_scl_i;
|
||||
wire eeprom_i2c_scl_o;
|
||||
wire eeprom_i2c_scl_t;
|
||||
wire eeprom_i2c_sda_i;
|
||||
wire eeprom_i2c_sda_o;
|
||||
wire eeprom_i2c_sda_t;
|
||||
|
||||
sync_signal #(
|
||||
.WIDTH(5),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(pcie_user_clk),
|
||||
.in({sfp_i2c_scl, sfp_1_i2c_sda, sfp_2_i2c_sda,
|
||||
eeprom_i2c_scl, eeprom_i2c_sda}),
|
||||
.out({sfp_i2c_scl_i, sfp_1_i2c_sda_i, sfp_2_i2c_sda_i,
|
||||
eeprom_i2c_scl_i, eeprom_i2c_sda_i})
|
||||
);
|
||||
|
||||
assign sfp_i2c_scl = sfp_i2c_scl_t ? 1'bz : sfp_i2c_scl_o;
|
||||
assign sfp_1_i2c_sda = sfp_1_i2c_sda_t ? 1'bz : sfp_1_i2c_sda_o;
|
||||
assign sfp_2_i2c_sda = sfp_2_i2c_sda_t ? 1'bz : sfp_2_i2c_sda_o;
|
||||
assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
|
||||
assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
|
||||
|
||||
// Flash
|
||||
wire [15:0] flash_dq_i_int;
|
||||
wire [15:0] flash_dq_o_int;
|
||||
wire flash_dq_oe_int;
|
||||
wire [22:0] flash_addr_int;
|
||||
wire flash_region_int;
|
||||
wire flash_region_oe_int;
|
||||
wire flash_ce_n_int;
|
||||
wire flash_oe_n_int;
|
||||
wire flash_we_n_int;
|
||||
wire flash_adv_n_int;
|
||||
|
||||
assign flash_dq = flash_dq_oe_int ? flash_dq_o_int : 16'hzzzz;
|
||||
assign flash_addr = flash_addr_int;
|
||||
assign flash_region = flash_region_oe_int ? flash_region_int : 1'bz;
|
||||
assign flash_ce_n = flash_ce_n_int;
|
||||
assign flash_oe_n = flash_oe_n_int;
|
||||
assign flash_we_n = flash_we_n_int;
|
||||
assign flash_adv_n = flash_adv_n_int;
|
||||
|
||||
sync_signal #(
|
||||
.WIDTH(16),
|
||||
.N(2)
|
||||
)
|
||||
flash_sync_signal_inst (
|
||||
.clk(pcie_user_clk),
|
||||
.in(flash_dq),
|
||||
.out(flash_dq_i_int)
|
||||
);
|
||||
|
||||
// PCIe
|
||||
wire pcie_sys_clk;
|
||||
wire pcie_sys_clk_gt;
|
||||
|
||||
IBUFDS_GTE4 #(
|
||||
.REFCLK_HROW_CK_SEL(2'b00)
|
||||
)
|
||||
ibufds_gte4_pcie_mgt_refclk_inst (
|
||||
.I (pcie_refclk_p),
|
||||
.IB (pcie_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (pcie_sys_clk_gt),
|
||||
.ODIV2 (pcie_sys_clk)
|
||||
);
|
||||
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep;
|
||||
wire axis_rq_tlast;
|
||||
wire axis_rq_tready;
|
||||
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
|
||||
wire axis_rq_tvalid;
|
||||
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep;
|
||||
wire axis_rc_tlast;
|
||||
wire axis_rc_tready;
|
||||
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
|
||||
wire axis_rc_tvalid;
|
||||
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep;
|
||||
wire axis_cq_tlast;
|
||||
wire axis_cq_tready;
|
||||
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
|
||||
wire axis_cq_tvalid;
|
||||
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep;
|
||||
wire axis_cc_tlast;
|
||||
wire axis_cc_tready;
|
||||
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
|
||||
wire axis_cc_tvalid;
|
||||
|
||||
wire [3:0] pcie_tfc_nph_av;
|
||||
wire [3:0] pcie_tfc_npd_av;
|
||||
|
||||
wire [2:0] cfg_max_payload;
|
||||
wire [2:0] cfg_max_read_req;
|
||||
|
||||
wire [9:0] cfg_mgmt_addr;
|
||||
wire [7:0] cfg_mgmt_function_number;
|
||||
wire cfg_mgmt_write;
|
||||
wire [31:0] cfg_mgmt_write_data;
|
||||
wire [3:0] cfg_mgmt_byte_enable;
|
||||
wire cfg_mgmt_read;
|
||||
wire [31:0] cfg_mgmt_read_data;
|
||||
wire cfg_mgmt_read_write_done;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
|
||||
// ila_0 ila_rq (
|
||||
// .clk(pcie_user_clk),
|
||||
// .trig_out(),
|
||||
// .trig_out_ack(1'b0),
|
||||
// .trig_in(1'b0),
|
||||
// .trig_in_ack(),
|
||||
// .probe0(axis_rq_tdata),
|
||||
// .probe1(axis_rq_tkeep),
|
||||
// .probe2(axis_rq_tvalid),
|
||||
// .probe3(axis_rq_tready),
|
||||
// .probe4({pcie_tfc_npd_av, pcie_tfc_nph_av, axis_rq_tuser}),
|
||||
// .probe5(axis_rq_tlast)
|
||||
// );
|
||||
|
||||
// ila_0 ila_rc (
|
||||
// .clk(pcie_user_clk),
|
||||
// .trig_out(),
|
||||
// .trig_out_ack(1'b0),
|
||||
// .trig_in(1'b0),
|
||||
// .trig_in_ack(),
|
||||
// .probe0(axis_rc_tdata),
|
||||
// .probe1(axis_rc_tkeep),
|
||||
// .probe2(axis_rc_tvalid),
|
||||
// .probe3(axis_rc_tready),
|
||||
// .probe4(axis_rc_tuser),
|
||||
// .probe5(axis_rc_tlast)
|
||||
// );
|
||||
|
||||
pcie4_uscale_plus_0
|
||||
pcie4_uscale_plus_inst (
|
||||
.pci_exp_txn(pcie_tx_n),
|
||||
.pci_exp_txp(pcie_tx_p),
|
||||
.pci_exp_rxn(pcie_rx_n),
|
||||
.pci_exp_rxp(pcie_rx_p),
|
||||
.user_clk(pcie_user_clk),
|
||||
.user_reset(pcie_user_reset),
|
||||
.user_lnk_up(),
|
||||
|
||||
.s_axis_rq_tdata(axis_rq_tdata),
|
||||
.s_axis_rq_tkeep(axis_rq_tkeep),
|
||||
.s_axis_rq_tlast(axis_rq_tlast),
|
||||
.s_axis_rq_tready(axis_rq_tready),
|
||||
.s_axis_rq_tuser(axis_rq_tuser),
|
||||
.s_axis_rq_tvalid(axis_rq_tvalid),
|
||||
|
||||
.m_axis_rc_tdata(axis_rc_tdata),
|
||||
.m_axis_rc_tkeep(axis_rc_tkeep),
|
||||
.m_axis_rc_tlast(axis_rc_tlast),
|
||||
.m_axis_rc_tready(axis_rc_tready),
|
||||
.m_axis_rc_tuser(axis_rc_tuser),
|
||||
.m_axis_rc_tvalid(axis_rc_tvalid),
|
||||
|
||||
.m_axis_cq_tdata(axis_cq_tdata),
|
||||
.m_axis_cq_tkeep(axis_cq_tkeep),
|
||||
.m_axis_cq_tlast(axis_cq_tlast),
|
||||
.m_axis_cq_tready(axis_cq_tready),
|
||||
.m_axis_cq_tuser(axis_cq_tuser),
|
||||
.m_axis_cq_tvalid(axis_cq_tvalid),
|
||||
|
||||
.s_axis_cc_tdata(axis_cc_tdata),
|
||||
.s_axis_cc_tkeep(axis_cc_tkeep),
|
||||
.s_axis_cc_tlast(axis_cc_tlast),
|
||||
.s_axis_cc_tready(axis_cc_tready),
|
||||
.s_axis_cc_tuser(axis_cc_tuser),
|
||||
.s_axis_cc_tvalid(axis_cc_tvalid),
|
||||
|
||||
.pcie_rq_seq_num0(),
|
||||
.pcie_rq_seq_num_vld0(),
|
||||
.pcie_rq_seq_num1(),
|
||||
.pcie_rq_seq_num_vld1(),
|
||||
.pcie_rq_tag0(),
|
||||
.pcie_rq_tag1(),
|
||||
.pcie_rq_tag_av(),
|
||||
.pcie_rq_tag_vld0(),
|
||||
.pcie_rq_tag_vld1(),
|
||||
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
|
||||
.pcie_cq_np_req(1'b1),
|
||||
.pcie_cq_np_req_count(),
|
||||
|
||||
.cfg_phy_link_down(),
|
||||
.cfg_phy_link_status(),
|
||||
.cfg_negotiated_width(),
|
||||
.cfg_current_speed(),
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_function_status(),
|
||||
.cfg_function_power_state(),
|
||||
.cfg_vf_status(),
|
||||
.cfg_vf_power_state(),
|
||||
.cfg_link_power_state(),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
.cfg_mgmt_debug_access(1'b0),
|
||||
|
||||
.cfg_err_cor_out(),
|
||||
.cfg_err_nonfatal_out(),
|
||||
.cfg_err_fatal_out(),
|
||||
.cfg_local_error_valid(),
|
||||
.cfg_local_error_out(),
|
||||
.cfg_ltssm_state(),
|
||||
.cfg_rx_pm_state(),
|
||||
.cfg_tx_pm_state(),
|
||||
.cfg_rcb_status(),
|
||||
.cfg_obff_enable(),
|
||||
.cfg_pl_status_change(),
|
||||
.cfg_tph_requester_enable(),
|
||||
.cfg_tph_st_mode(),
|
||||
.cfg_vf_tph_requester_enable(),
|
||||
.cfg_vf_tph_st_mode(),
|
||||
|
||||
.cfg_msg_received(),
|
||||
.cfg_msg_received_data(),
|
||||
.cfg_msg_received_type(),
|
||||
.cfg_msg_transmit(1'b0),
|
||||
.cfg_msg_transmit_type(3'd0),
|
||||
.cfg_msg_transmit_data(32'd0),
|
||||
.cfg_msg_transmit_done(),
|
||||
|
||||
.cfg_fc_ph(),
|
||||
.cfg_fc_pd(),
|
||||
.cfg_fc_nph(),
|
||||
.cfg_fc_npd(),
|
||||
.cfg_fc_cplh(),
|
||||
.cfg_fc_cpld(),
|
||||
.cfg_fc_sel(3'd0),
|
||||
|
||||
.cfg_dsn(64'd0),
|
||||
|
||||
.cfg_power_state_change_ack(1'b1),
|
||||
.cfg_power_state_change_interrupt(),
|
||||
|
||||
.cfg_err_cor_in(status_error_cor),
|
||||
.cfg_err_uncor_in(status_error_uncor),
|
||||
.cfg_flr_in_process(),
|
||||
.cfg_flr_done(4'd0),
|
||||
.cfg_vf_flr_in_process(),
|
||||
.cfg_vf_flr_func_num(8'd0),
|
||||
.cfg_vf_flr_done(8'd0),
|
||||
|
||||
.cfg_link_training_enable(1'b1),
|
||||
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
.cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
|
||||
|
||||
.cfg_hot_reset_out(),
|
||||
|
||||
.cfg_config_space_enable(1'b1),
|
||||
.cfg_req_pm_transition_l23_ready(1'b0),
|
||||
.cfg_hot_reset_in(1'b0),
|
||||
|
||||
.cfg_ds_port_number(8'd0),
|
||||
.cfg_ds_bus_number(8'd0),
|
||||
.cfg_ds_device_number(5'd0),
|
||||
//.cfg_ds_function_number(3'd0),
|
||||
|
||||
//.cfg_subsys_vend_id(16'h1234),
|
||||
|
||||
.sys_clk(pcie_sys_clk),
|
||||
.sys_clk_gt(pcie_sys_clk_gt),
|
||||
.sys_reset(pcie_reset_n),
|
||||
|
||||
// .int_qpll0lock_out(),
|
||||
// .int_qpll0outrefclk_out(),
|
||||
// .int_qpll0outclk_out(),
|
||||
// .int_qpll1lock_out(),
|
||||
// .int_qpll1outrefclk_out(),
|
||||
// .int_qpll1outclk_out(),
|
||||
.phy_rdy_out()
|
||||
);
|
||||
|
||||
// XGMII 10G PHY
|
||||
|
||||
assign sfp_1_tx_disable = 1'b1;
|
||||
assign sfp_2_tx_disable = 1'b1;
|
||||
assign sfp_1_rs = 1'b0;
|
||||
assign sfp_2_rs = 1'b0;
|
||||
|
||||
wire sfp_1_tx_clk_int;
|
||||
wire sfp_1_tx_rst_int;
|
||||
wire [63:0] sfp_1_txd_int;
|
||||
wire [7:0] sfp_1_txc_int;
|
||||
wire sfp_1_rx_clk_int;
|
||||
wire sfp_1_rx_rst_int;
|
||||
wire [63:0] sfp_1_rxd_int;
|
||||
wire [7:0] sfp_1_rxc_int;
|
||||
wire sfp_2_tx_clk_int;
|
||||
wire sfp_2_tx_rst_int;
|
||||
wire [63:0] sfp_2_txd_int;
|
||||
wire [7:0] sfp_2_txc_int;
|
||||
wire sfp_2_rx_clk_int;
|
||||
wire sfp_2_rx_rst_int;
|
||||
wire [63:0] sfp_2_rxd_int;
|
||||
wire [7:0] sfp_2_rxc_int;
|
||||
|
||||
wire sfp_1_rx_block_lock;
|
||||
wire sfp_2_rx_block_lock;
|
||||
|
||||
wire sfp_gtpowergood;
|
||||
|
||||
wire sfp_mgt_refclk;
|
||||
wire sfp_mgt_refclk_int;
|
||||
wire sfp_mgt_refclk_bufg;
|
||||
|
||||
assign clk_161mhz_int = sfp_mgt_refclk_bufg;
|
||||
|
||||
wire [1:0] gt_txclkout;
|
||||
wire gt_txusrclk;
|
||||
|
||||
wire [1:0] gt_rxclkout;
|
||||
wire [1:0] gt_rxusrclk;
|
||||
|
||||
wire gt_reset_tx_done;
|
||||
wire gt_reset_rx_done;
|
||||
|
||||
wire [1:0] gt_txprgdivresetdone;
|
||||
wire [1:0] gt_txpmaresetdone;
|
||||
wire [1:0] gt_rxprgdivresetdone;
|
||||
wire [1:0] gt_rxpmaresetdone;
|
||||
|
||||
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
|
||||
wire gt_rx_reset = ~>_rxpmaresetdone;
|
||||
|
||||
reg gt_userclk_tx_active = 1'b0;
|
||||
reg [1:0] gt_userclk_rx_active = 1'b0;
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_inst (
|
||||
.I (sfp_mgt_refclk_p),
|
||||
.IB (sfp_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (sfp_mgt_refclk),
|
||||
.ODIV2 (sfp_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_refclk_inst (
|
||||
.CE (sfp_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'b000),
|
||||
.I (sfp_mgt_refclk_int),
|
||||
.O (sfp_mgt_refclk_bufg)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_tx_usrclk_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_tx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd0),
|
||||
.I (gt_txclkout[0]),
|
||||
.O (gt_txusrclk)
|
||||
);
|
||||
|
||||
assign clk_156mhz_int = gt_txusrclk;
|
||||
|
||||
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
|
||||
if (gt_tx_reset) begin
|
||||
gt_userclk_tx_active <= 1'b0;
|
||||
end else begin
|
||||
gt_userclk_tx_active <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
|
||||
genvar n;
|
||||
|
||||
for (n = 0 ; n < 2; n = n + 1) begin
|
||||
|
||||
BUFG_GT bufg_gt_rx_usrclk_0_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_rx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd0),
|
||||
.I (gt_rxclkout[n]),
|
||||
.O (gt_rxusrclk[n])
|
||||
);
|
||||
|
||||
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
|
||||
if (gt_rx_reset) begin
|
||||
gt_userclk_rx_active[n] <= 1'b0;
|
||||
end else begin
|
||||
gt_userclk_rx_active[n] <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_156mhz_inst (
|
||||
.clk(clk_156mhz_int),
|
||||
.rst(~gt_reset_tx_done),
|
||||
.sync_reset_out(rst_156mhz_int)
|
||||
);
|
||||
|
||||
wire [5:0] sfp_1_gt_txheader;
|
||||
wire [63:0] sfp_1_gt_txdata;
|
||||
wire sfp_1_gt_rxgearboxslip;
|
||||
wire [5:0] sfp_1_gt_rxheader;
|
||||
wire [1:0] sfp_1_gt_rxheadervalid;
|
||||
wire [63:0] sfp_1_gt_rxdata;
|
||||
wire [1:0] sfp_1_gt_rxdatavalid;
|
||||
|
||||
wire [5:0] sfp_2_gt_txheader;
|
||||
wire [63:0] sfp_2_gt_txdata;
|
||||
wire sfp_2_gt_rxgearboxslip;
|
||||
wire [5:0] sfp_2_gt_rxheader;
|
||||
wire [1:0] sfp_2_gt_rxheadervalid;
|
||||
wire [63:0] sfp_2_gt_rxdata;
|
||||
wire [1:0] sfp_2_gt_rxdatavalid;
|
||||
|
||||
gtwizard_ultrascale_0
|
||||
sfp_gty_inst (
|
||||
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
|
||||
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
|
||||
|
||||
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
|
||||
.gtwiz_reset_all_in(rst_125mhz_int),
|
||||
|
||||
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_tx_datapath_in(1'b0),
|
||||
|
||||
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_rx_datapath_in(1'b0),
|
||||
|
||||
.gtwiz_reset_rx_cdr_stable_out(),
|
||||
|
||||
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
||||
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
||||
|
||||
.gtrefclk00_in(sfp_mgt_refclk),
|
||||
|
||||
.qpll0outclk_out(),
|
||||
.qpll0outrefclk_out(),
|
||||
|
||||
// .rxpmareset_in(2'd0),
|
||||
|
||||
.gtyrxn_in({sfp_2_rx_n, sfp_1_rx_n}),
|
||||
.gtyrxp_in({sfp_2_rx_p, sfp_1_rx_p}),
|
||||
|
||||
.rxusrclk_in(gt_rxusrclk),
|
||||
.rxusrclk2_in(gt_rxusrclk),
|
||||
|
||||
.gtwiz_userdata_tx_in({sfp_2_gt_txdata, sfp_1_gt_txdata}),
|
||||
.txheader_in({sfp_2_gt_txheader, sfp_1_gt_txheader}),
|
||||
.txsequence_in({2{7'b0}}),
|
||||
|
||||
.txusrclk_in({2{gt_txusrclk}}),
|
||||
.txusrclk2_in({2{gt_txusrclk}}),
|
||||
|
||||
.gtpowergood_out(sfp_gtpowergood),
|
||||
|
||||
.gtytxn_out({sfp_2_tx_n, sfp_1_tx_n}),
|
||||
.gtytxp_out({sfp_2_tx_p, sfp_1_tx_p}),
|
||||
|
||||
.txpolarity_in(2'b11),
|
||||
.rxpolarity_in(2'b00),
|
||||
|
||||
.rxgearboxslip_in({sfp_2_gt_rxgearboxslip, sfp_1_gt_rxgearboxslip}),
|
||||
.gtwiz_userdata_rx_out({sfp_2_gt_rxdata, sfp_1_gt_rxdata}),
|
||||
.rxdatavalid_out({sfp_2_gt_rxdatavalid, sfp_1_gt_rxdatavalid}),
|
||||
.rxheader_out({sfp_2_gt_rxheader, sfp_1_gt_rxheader}),
|
||||
.rxheadervalid_out({sfp_2_gt_rxheadervalid, sfp_1_gt_rxheadervalid}),
|
||||
.rxoutclk_out(gt_rxclkout),
|
||||
.rxpmaresetdone_out(gt_rxpmaresetdone),
|
||||
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
|
||||
.rxstartofseq_out(),
|
||||
|
||||
.txoutclk_out(gt_txclkout),
|
||||
.txpmaresetdone_out(gt_txpmaresetdone),
|
||||
.txprgdivresetdone_out(gt_txprgdivresetdone)
|
||||
);
|
||||
|
||||
assign sfp_1_tx_clk_int = clk_156mhz_int;
|
||||
assign sfp_1_tx_rst_int = rst_156mhz_int;
|
||||
|
||||
assign sfp_1_rx_clk_int = gt_rxusrclk[0];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sfp_1_rx_rst_reset_sync_inst (
|
||||
.clk(sfp_1_rx_clk_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(sfp_1_rx_rst_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
sfp_1_phy_inst (
|
||||
.tx_clk(sfp_1_tx_clk_int),
|
||||
.tx_rst(sfp_1_tx_rst_int),
|
||||
.rx_clk(sfp_1_rx_clk_int),
|
||||
.rx_rst(sfp_1_rx_rst_int),
|
||||
.xgmii_txd(sfp_1_txd_int),
|
||||
.xgmii_txc(sfp_1_txc_int),
|
||||
.xgmii_rxd(sfp_1_rxd_int),
|
||||
.xgmii_rxc(sfp_1_rxc_int),
|
||||
.serdes_tx_data(sfp_1_gt_txdata),
|
||||
.serdes_tx_hdr(sfp_1_gt_txheader),
|
||||
.serdes_rx_data(sfp_1_gt_rxdata),
|
||||
.serdes_rx_hdr(sfp_1_gt_rxheader),
|
||||
.serdes_rx_bitslip(sfp_1_gt_rxgearboxslip),
|
||||
.rx_block_lock(sfp_1_rx_block_lock),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign sfp_2_tx_clk_int = clk_156mhz_int;
|
||||
assign sfp_2_tx_rst_int = rst_156mhz_int;
|
||||
|
||||
assign sfp_2_rx_clk_int = gt_rxusrclk[1];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sfp_2_rx_rst_reset_sync_inst (
|
||||
.clk(sfp_2_rx_clk_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(sfp_2_rx_rst_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
sfp_2_phy_inst (
|
||||
.tx_clk(sfp_2_tx_clk_int),
|
||||
.tx_rst(sfp_2_tx_rst_int),
|
||||
.rx_clk(sfp_2_rx_clk_int),
|
||||
.rx_rst(sfp_2_rx_rst_int),
|
||||
.xgmii_txd(sfp_2_txd_int),
|
||||
.xgmii_txc(sfp_2_txc_int),
|
||||
.xgmii_rxd(sfp_2_rxd_int),
|
||||
.xgmii_rxc(sfp_2_rxc_int),
|
||||
.serdes_tx_data(sfp_2_gt_txdata),
|
||||
.serdes_tx_hdr(sfp_2_gt_txheader),
|
||||
.serdes_rx_data(sfp_2_gt_rxdata),
|
||||
.serdes_rx_hdr(sfp_2_gt_rxheader),
|
||||
.serdes_rx_bitslip(sfp_2_gt_rxgearboxslip),
|
||||
.rx_block_lock(sfp_2_rx_block_lock),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign sfp_1_led[0] = sfp_1_rx_block_lock;
|
||||
assign sfp_1_led[1] = 1'b0;
|
||||
assign sfp_2_led[0] = sfp_2_rx_block_lock;
|
||||
assign sfp_2_led[1] = 1'b0;
|
||||
|
||||
fpga_core #(
|
||||
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
|
||||
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
|
||||
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
|
||||
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
|
||||
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
|
||||
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 156.25 MHz, 250 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_156mhz(clk_156mhz_int),
|
||||
.rst_156mhz(rst_156mhz_int),
|
||||
.clk_250mhz(pcie_user_clk),
|
||||
.rst_250mhz(pcie_user_reset),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
//.sfp_1_led(sfp_1_led),
|
||||
//.sfp_2_led(sfp_2_led),
|
||||
.sma_led(sma_led),
|
||||
|
||||
.sma_in(sma_in),
|
||||
.sma_out(sma_out),
|
||||
.sma_out_en(sma_out_en),
|
||||
.sma_term_en(sma_term_en),
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
.m_axis_rq_tdata(axis_rq_tdata),
|
||||
.m_axis_rq_tkeep(axis_rq_tkeep),
|
||||
.m_axis_rq_tlast(axis_rq_tlast),
|
||||
.m_axis_rq_tready(axis_rq_tready),
|
||||
.m_axis_rq_tuser(axis_rq_tuser),
|
||||
.m_axis_rq_tvalid(axis_rq_tvalid),
|
||||
|
||||
.s_axis_rc_tdata(axis_rc_tdata),
|
||||
.s_axis_rc_tkeep(axis_rc_tkeep),
|
||||
.s_axis_rc_tlast(axis_rc_tlast),
|
||||
.s_axis_rc_tready(axis_rc_tready),
|
||||
.s_axis_rc_tuser(axis_rc_tuser),
|
||||
.s_axis_rc_tvalid(axis_rc_tvalid),
|
||||
|
||||
.s_axis_cq_tdata(axis_cq_tdata),
|
||||
.s_axis_cq_tkeep(axis_cq_tkeep),
|
||||
.s_axis_cq_tlast(axis_cq_tlast),
|
||||
.s_axis_cq_tready(axis_cq_tready),
|
||||
.s_axis_cq_tuser(axis_cq_tuser),
|
||||
.s_axis_cq_tvalid(axis_cq_tvalid),
|
||||
|
||||
.m_axis_cc_tdata(axis_cc_tdata),
|
||||
.m_axis_cc_tkeep(axis_cc_tkeep),
|
||||
.m_axis_cc_tlast(axis_cc_tlast),
|
||||
.m_axis_cc_tready(axis_cc_tready),
|
||||
.m_axis_cc_tuser(axis_cc_tuser),
|
||||
.m_axis_cc_tvalid(axis_cc_tvalid),
|
||||
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
.status_error_uncor(status_error_uncor),
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
.sfp_1_tx_clk(sfp_1_tx_clk_int),
|
||||
.sfp_1_tx_rst(sfp_1_tx_rst_int),
|
||||
.sfp_1_txd(sfp_1_txd_int),
|
||||
.sfp_1_txc(sfp_1_txc_int),
|
||||
.sfp_1_rx_clk(sfp_1_rx_clk_int),
|
||||
.sfp_1_rx_rst(sfp_1_rx_rst_int),
|
||||
.sfp_1_rxd(sfp_1_rxd_int),
|
||||
.sfp_1_rxc(sfp_1_rxc_int),
|
||||
.sfp_2_tx_clk(sfp_2_tx_clk_int),
|
||||
.sfp_2_tx_rst(sfp_2_tx_rst_int),
|
||||
.sfp_2_txd(sfp_2_txd_int),
|
||||
.sfp_2_txc(sfp_2_txc_int),
|
||||
.sfp_2_rx_clk(sfp_2_rx_clk_int),
|
||||
.sfp_2_rx_rst(sfp_2_rx_rst_int),
|
||||
.sfp_2_rxd(sfp_2_rxd_int),
|
||||
.sfp_2_rxc(sfp_2_rxc_int),
|
||||
|
||||
.sfp_i2c_scl_i(sfp_i2c_scl_i),
|
||||
.sfp_i2c_scl_o(sfp_i2c_scl_o),
|
||||
.sfp_i2c_scl_t(sfp_i2c_scl_t),
|
||||
.sfp_1_i2c_sda_i(sfp_1_i2c_sda_i),
|
||||
.sfp_1_i2c_sda_o(sfp_1_i2c_sda_o),
|
||||
.sfp_1_i2c_sda_t(sfp_1_i2c_sda_t),
|
||||
.sfp_2_i2c_sda_i(sfp_2_i2c_sda_i),
|
||||
.sfp_2_i2c_sda_o(sfp_2_i2c_sda_o),
|
||||
.sfp_2_i2c_sda_t(sfp_2_i2c_sda_t),
|
||||
|
||||
.eeprom_i2c_scl_i(eeprom_i2c_scl_i),
|
||||
.eeprom_i2c_scl_o(eeprom_i2c_scl_o),
|
||||
.eeprom_i2c_scl_t(eeprom_i2c_scl_t),
|
||||
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
|
||||
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
|
||||
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
|
||||
|
||||
/*
|
||||
* BPI flash
|
||||
*/
|
||||
.flash_dq_i(flash_dq_i_int),
|
||||
.flash_dq_o(flash_dq_o_int),
|
||||
.flash_dq_oe(flash_dq_oe_int),
|
||||
.flash_addr(flash_addr_int),
|
||||
.flash_region(flash_region_int),
|
||||
.flash_region_oe(flash_region_oe_int),
|
||||
.flash_ce_n(flash_ce_n_int),
|
||||
.flash_oe_n(flash_oe_n_int),
|
||||
.flash_we_n(flash_we_n_int),
|
||||
.flash_adv_n(flash_adv_n_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
1798
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v
Normal file
1798
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
52
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_reset.v
Normal file
52
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_reset.v
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an active-high asynchronous reset signal to a given clock by
|
||||
* using a pipeline of N registers.
|
||||
*/
|
||||
module sync_reset #(
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
output wire sync_reset_out
|
||||
);
|
||||
|
||||
reg [N-1:0] sync_reg = {N{1'b1}};
|
||||
|
||||
assign sync_reset_out = sync_reg[N-1];
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst)
|
||||
sync_reg <= {N{1'b1}};
|
||||
else
|
||||
sync_reg <= {sync_reg[N-2:0], 1'b0};
|
||||
end
|
||||
|
||||
endmodule
|
||||
58
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v
Normal file
58
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/axis_ep.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/axis_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/axis_ep.py
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/eth_ep.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/eth_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/eth_ep.py
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/ip_ep.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/ip_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/ip_ep.py
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/mqnic.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/tb/mqnic.py
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie.py
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_us.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_us.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie_us.py
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_usp.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_usp.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie_usp.py
|
||||
810
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py
Executable file
810
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py
Executable file
@ -0,0 +1,810 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
|
||||
import pcie
|
||||
import pcie_us
|
||||
import xgmii_ep
|
||||
import axis_ep
|
||||
import eth_ep
|
||||
import udp_ep
|
||||
|
||||
import struct
|
||||
|
||||
import mqnic
|
||||
|
||||
module = 'fpga_core'
|
||||
testbench = 'test_%s' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../rtl/common/interface.v")
|
||||
srcs.append("../rtl/common/port.v")
|
||||
srcs.append("../rtl/common/cpl_write.v")
|
||||
srcs.append("../rtl/common/cpl_op_mux.v")
|
||||
srcs.append("../rtl/common/desc_fetch.v")
|
||||
srcs.append("../rtl/common/desc_op_mux.v")
|
||||
srcs.append("../rtl/common/queue_manager.v")
|
||||
srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tdma_scheduler.v")
|
||||
srcs.append("../rtl/common/event_mux.v")
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/lfsr.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_clock.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_perout.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
|
||||
srcs.append("../lib/axi/rtl/axil_interconnect.v")
|
||||
srcs.append("../lib/axi/rtl/arbiter.v")
|
||||
srcs.append("../lib/axi/rtl/priority_encoder.v")
|
||||
srcs.append("../lib/axis/rtl/axis_adapter.v")
|
||||
srcs.append("../lib/axis/rtl/axis_arb_mux.v")
|
||||
srcs.append("../lib/axis/rtl/axis_async_fifo.v")
|
||||
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
|
||||
srcs.append("../lib/axis/rtl/axis_fifo.v")
|
||||
srcs.append("../lib/axis/rtl/axis_register.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")
|
||||
srcs.append("../lib/pcie/rtl/pulse_merge.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def frame_checksum(frame):
|
||||
data = frame[14:]
|
||||
|
||||
csum = 0
|
||||
odd = False
|
||||
|
||||
for b in data:
|
||||
if odd:
|
||||
csum += b
|
||||
else:
|
||||
csum += b << 8
|
||||
odd = not odd
|
||||
|
||||
csum = (csum & 0xffff) + (csum >> 16)
|
||||
csum = (csum & 0xffff) + (csum >> 16)
|
||||
|
||||
return csum
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
AXIS_PCIE_DATA_WIDTH = 256
|
||||
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32)
|
||||
AXIS_PCIE_RC_USER_WIDTH = 75
|
||||
AXIS_PCIE_RQ_USER_WIDTH = 60
|
||||
AXIS_PCIE_CQ_USER_WIDTH = 85
|
||||
AXIS_PCIE_CC_USER_WIDTH = 33
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
clk_156mhz = Signal(bool(0))
|
||||
rst_156mhz = Signal(bool(0))
|
||||
clk_250mhz = Signal(bool(0))
|
||||
rst_250mhz = Signal(bool(0))
|
||||
m_axis_rq_tready = Signal(bool(0))
|
||||
s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
|
||||
s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
|
||||
s_axis_rc_tlast = Signal(bool(0))
|
||||
s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
|
||||
s_axis_rc_tvalid = Signal(bool(0))
|
||||
s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
|
||||
s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
|
||||
s_axis_cq_tlast = Signal(bool(0))
|
||||
s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
|
||||
s_axis_cq_tvalid = Signal(bool(0))
|
||||
m_axis_cc_tready = Signal(bool(0))
|
||||
pcie_tfc_nph_av = Signal(intbv(0)[2:])
|
||||
pcie_tfc_npd_av = Signal(intbv(0)[2:])
|
||||
cfg_max_payload = Signal(intbv(0)[3:])
|
||||
cfg_max_read_req = Signal(intbv(0)[3:])
|
||||
cfg_mgmt_read_data = Signal(intbv(0)[32:])
|
||||
cfg_mgmt_read_write_done = Signal(bool(0))
|
||||
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
|
||||
cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:])
|
||||
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
|
||||
cfg_interrupt_msi_mask_update = Signal(bool(0))
|
||||
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_sent = Signal(bool(0))
|
||||
cfg_interrupt_msi_fail = Signal(bool(0))
|
||||
sfp_1_tx_clk = Signal(bool(0))
|
||||
sfp_1_tx_rst = Signal(bool(0))
|
||||
sfp_1_rx_clk = Signal(bool(0))
|
||||
sfp_1_rx_rst = Signal(bool(0))
|
||||
sfp_1_rxd = Signal(intbv(0)[64:])
|
||||
sfp_1_rxc = Signal(intbv(0)[8:])
|
||||
sfp_2_tx_clk = Signal(bool(0))
|
||||
sfp_2_tx_rst = Signal(bool(0))
|
||||
sfp_2_rx_clk = Signal(bool(0))
|
||||
sfp_2_rx_rst = Signal(bool(0))
|
||||
sfp_2_rxd = Signal(intbv(0)[64:])
|
||||
sfp_2_rxc = Signal(intbv(0)[8:])
|
||||
sfp_i2c_scl_i = Signal(bool(1))
|
||||
sfp_1_i2c_sda_i = Signal(bool(1))
|
||||
sfp_2_i2c_sda_i = Signal(bool(1))
|
||||
eeprom_i2c_scl_i = Signal(bool(1))
|
||||
eeprom_i2c_sda_i = Signal(bool(1))
|
||||
flash_dq_i = Signal(intbv(0)[16:])
|
||||
|
||||
# Outputs
|
||||
sfp_1_led = Signal(intbv(0)[2:])
|
||||
sfp_2_led = Signal(intbv(0)[2:])
|
||||
sma_led = Signal(intbv(0)[2:])
|
||||
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
|
||||
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
|
||||
m_axis_rq_tlast = Signal(bool(0))
|
||||
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
|
||||
m_axis_rq_tvalid = Signal(bool(0))
|
||||
s_axis_rc_tready = Signal(bool(0))
|
||||
s_axis_cq_tready = Signal(bool(0))
|
||||
m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
|
||||
m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
|
||||
m_axis_cc_tlast = Signal(bool(0))
|
||||
m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:])
|
||||
m_axis_cc_tvalid = Signal(bool(0))
|
||||
status_error_cor = Signal(bool(0))
|
||||
status_error_uncor = Signal(bool(0))
|
||||
cfg_mgmt_addr = Signal(intbv(0)[19:])
|
||||
cfg_mgmt_write = Signal(bool(0))
|
||||
cfg_mgmt_write_data = Signal(intbv(0)[32:])
|
||||
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
|
||||
cfg_mgmt_read = Signal(bool(0))
|
||||
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_select = Signal(intbv(0)[4:])
|
||||
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:])
|
||||
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
|
||||
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
|
||||
cfg_interrupt_msi_tph_present = Signal(bool(0))
|
||||
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
|
||||
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:])
|
||||
cfg_interrupt_msi_function_number = Signal(intbv(0)[4:])
|
||||
sfp_1_txd = Signal(intbv(0)[64:])
|
||||
sfp_1_txc = Signal(intbv(0)[8:])
|
||||
sfp_2_txd = Signal(intbv(0)[64:])
|
||||
sfp_2_txc = Signal(intbv(0)[8:])
|
||||
sfp_i2c_scl_o = Signal(bool(1))
|
||||
sfp_i2c_scl_t = Signal(bool(1))
|
||||
sfp_1_i2c_sda_o = Signal(bool(1))
|
||||
sfp_1_i2c_sda_t = Signal(bool(1))
|
||||
sfp_2_i2c_sda_o = Signal(bool(1))
|
||||
sfp_2_i2c_sda_t = Signal(bool(1))
|
||||
eeprom_i2c_scl_o = Signal(bool(1))
|
||||
eeprom_i2c_scl_t = Signal(bool(1))
|
||||
eeprom_i2c_sda_o = Signal(bool(1))
|
||||
eeprom_i2c_sda_t = Signal(bool(1))
|
||||
flash_dq_o = Signal(intbv(0)[16:])
|
||||
flash_dq_oe = Signal(bool(0))
|
||||
flash_addr = Signal(intbv(0)[23:])
|
||||
flash_region = Signal(bool(0))
|
||||
flash_region_oe = Signal(bool(0))
|
||||
flash_ce_n = Signal(bool(1))
|
||||
flash_oe_n = Signal(bool(1))
|
||||
flash_we_n = Signal(bool(1))
|
||||
flash_adv_n = Signal(bool(1))
|
||||
|
||||
# sources and sinks
|
||||
sfp_1_source = xgmii_ep.XGMIISource()
|
||||
sfp_1_source_logic = sfp_1_source.create_logic(sfp_1_rx_clk, sfp_1_rx_rst, txd=sfp_1_rxd, txc=sfp_1_rxc, name='sfp_1_source')
|
||||
|
||||
sfp_1_sink = xgmii_ep.XGMIISink()
|
||||
sfp_1_sink_logic = sfp_1_sink.create_logic(sfp_1_tx_clk, sfp_1_tx_rst, rxd=sfp_1_txd, rxc=sfp_1_txc, name='sfp_1_sink')
|
||||
|
||||
sfp_2_source = xgmii_ep.XGMIISource()
|
||||
sfp_2_source_logic = sfp_2_source.create_logic(sfp_2_rx_clk, sfp_2_rx_rst, txd=sfp_2_rxd, txc=sfp_2_rxc, name='sfp_2_source')
|
||||
|
||||
sfp_2_sink = xgmii_ep.XGMIISink()
|
||||
sfp_2_sink_logic = sfp_2_sink.create_logic(sfp_2_tx_clk, sfp_2_tx_rst, rxd=sfp_2_txd, rxc=sfp_2_txc, name='sfp_2_sink')
|
||||
|
||||
# Clock and Reset Interface
|
||||
user_clk=Signal(bool(0))
|
||||
user_reset=Signal(bool(0))
|
||||
sys_clk=Signal(bool(0))
|
||||
sys_reset=Signal(bool(0))
|
||||
|
||||
# PCIe devices
|
||||
rc = pcie.RootComplex()
|
||||
|
||||
rc.max_payload_size = 0x1 # 256 bytes
|
||||
rc.max_read_request_size = 0x5 # 4096 bytes
|
||||
|
||||
driver = mqnic.Driver(rc)
|
||||
|
||||
dev = pcie_us.UltrascalePCIe()
|
||||
|
||||
dev.pcie_generation = 3
|
||||
dev.pcie_link_width = 8
|
||||
dev.user_clock_frequency = 256e6
|
||||
|
||||
dev.functions[0].msi_multiple_message_capable = 5
|
||||
|
||||
dev.functions[0].configure_bar(0, 16*1024*1024)
|
||||
dev.functions[0].configure_bar(1, 16*1024*1024)
|
||||
|
||||
rc.make_port().connect(dev)
|
||||
|
||||
pcie_logic = dev.create_logic(
|
||||
# Completer reQuest Interface
|
||||
m_axis_cq_tdata=s_axis_cq_tdata,
|
||||
m_axis_cq_tuser=s_axis_cq_tuser,
|
||||
m_axis_cq_tlast=s_axis_cq_tlast,
|
||||
m_axis_cq_tkeep=s_axis_cq_tkeep,
|
||||
m_axis_cq_tvalid=s_axis_cq_tvalid,
|
||||
m_axis_cq_tready=s_axis_cq_tready,
|
||||
#pcie_cq_np_req=pcie_cq_np_req,
|
||||
pcie_cq_np_req=Signal(bool(1)),
|
||||
#pcie_cq_np_req_count=pcie_cq_np_req_count,
|
||||
|
||||
# Completer Completion Interface
|
||||
s_axis_cc_tdata=m_axis_cc_tdata,
|
||||
s_axis_cc_tuser=m_axis_cc_tuser,
|
||||
s_axis_cc_tlast=m_axis_cc_tlast,
|
||||
s_axis_cc_tkeep=m_axis_cc_tkeep,
|
||||
s_axis_cc_tvalid=m_axis_cc_tvalid,
|
||||
s_axis_cc_tready=m_axis_cc_tready,
|
||||
|
||||
# Requester reQuest Interface
|
||||
s_axis_rq_tdata=m_axis_rq_tdata,
|
||||
s_axis_rq_tuser=m_axis_rq_tuser,
|
||||
s_axis_rq_tlast=m_axis_rq_tlast,
|
||||
s_axis_rq_tkeep=m_axis_rq_tkeep,
|
||||
s_axis_rq_tvalid=m_axis_rq_tvalid,
|
||||
s_axis_rq_tready=m_axis_rq_tready,
|
||||
#pcie_rq_seq_num=pcie_rq_seq_num,
|
||||
#pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
|
||||
#pcie_rq_tag=pcie_rq_tag,
|
||||
#pcie_rq_tag_vld=pcie_rq_tag_vld,
|
||||
|
||||
# Requester Completion Interface
|
||||
m_axis_rc_tdata=s_axis_rc_tdata,
|
||||
m_axis_rc_tuser=s_axis_rc_tuser,
|
||||
m_axis_rc_tlast=s_axis_rc_tlast,
|
||||
m_axis_rc_tkeep=s_axis_rc_tkeep,
|
||||
m_axis_rc_tvalid=s_axis_rc_tvalid,
|
||||
m_axis_rc_tready=s_axis_rc_tready,
|
||||
|
||||
# Transmit Flow Control Interface
|
||||
pcie_tfc_nph_av=pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av=pcie_tfc_npd_av,
|
||||
|
||||
# Configuration Management Interface
|
||||
cfg_mgmt_addr=cfg_mgmt_addr,
|
||||
cfg_mgmt_write=cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
|
||||
#cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access,
|
||||
|
||||
# Configuration Status Interface
|
||||
#cfg_phy_link_down=cfg_phy_link_down,
|
||||
#cfg_phy_link_status=cfg_phy_link_status,
|
||||
#cfg_negotiated_width=cfg_negotiated_width,
|
||||
#cfg_current_speed=cfg_current_speed,
|
||||
cfg_max_payload=cfg_max_payload,
|
||||
cfg_max_read_req=cfg_max_read_req,
|
||||
#cfg_function_status=cfg_function_status,
|
||||
#cfg_vf_status=cfg_vf_status,
|
||||
#cfg_function_power_state=cfg_function_power_state,
|
||||
#cfg_vf_power_state=cfg_vf_power_state,
|
||||
#cfg_link_power_state=cfg_link_power_state,
|
||||
#cfg_err_cor_out=cfg_err_cor_out,
|
||||
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
|
||||
#cfg_err_fatal_out=cfg_err_fatal_out,
|
||||
#cfg_ltr_enable=cfg_ltr_enable,
|
||||
#cfg_ltssm_state=cfg_ltssm_state,
|
||||
#cfg_rcb_status=cfg_rcb_status,
|
||||
#cfg_dpa_substate_change=cfg_dpa_substate_change,
|
||||
#cfg_obff_enable=cfg_obff_enable,
|
||||
#cfg_pl_status_change=cfg_pl_status_change,
|
||||
#cfg_tph_requester_enable=cfg_tph_requester_enable,
|
||||
#cfg_tph_st_mode=cfg_tph_st_mode,
|
||||
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
|
||||
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
|
||||
|
||||
# Configuration Received Message Interface
|
||||
#cfg_msg_received=cfg_msg_received,
|
||||
#cfg_msg_received_data=cfg_msg_received_data,
|
||||
#cfg_msg_received_type=cfg_msg_received_type,
|
||||
|
||||
# Configuration Transmit Message Interface
|
||||
#cfg_msg_transmit=cfg_msg_transmit,
|
||||
#cfg_msg_transmit_type=cfg_msg_transmit_type,
|
||||
#cfg_msg_transmit_data=cfg_msg_transmit_data,
|
||||
#cfg_msg_transmit_done=cfg_msg_transmit_done,
|
||||
|
||||
# Configuration Flow Control Interface
|
||||
#cfg_fc_ph=cfg_fc_ph,
|
||||
#cfg_fc_pd=cfg_fc_pd,
|
||||
#cfg_fc_nph=cfg_fc_nph,
|
||||
#cfg_fc_npd=cfg_fc_npd,
|
||||
#cfg_fc_cplh=cfg_fc_cplh,
|
||||
#cfg_fc_cpld=cfg_fc_cpld,
|
||||
#cfg_fc_sel=cfg_fc_sel,
|
||||
|
||||
# Per-Function Status Interface
|
||||
#cfg_per_func_status_control=cfg_per_func_status_control,
|
||||
#cfg_per_func_status_data=cfg_per_func_status_data,
|
||||
|
||||
# Configuration Control Interface
|
||||
#cfg_hot_reset_in=cfg_hot_reset_in,
|
||||
#cfg_hot_reset_out=cfg_hot_reset_out,
|
||||
#cfg_config_space_enable=cfg_config_space_enable,
|
||||
#cfg_per_function_update_done=cfg_per_function_update_done,
|
||||
#cfg_per_function_number=cfg_per_function_number,
|
||||
#cfg_per_function_output_request=cfg_per_function_output_request,
|
||||
#cfg_dsn=cfg_dsn,
|
||||
#cfg_ds_bus_number=cfg_ds_bus_number,
|
||||
#cfg_ds_device_number=cfg_ds_device_number,
|
||||
#cfg_ds_function_number=cfg_ds_function_number,
|
||||
#cfg_power_state_change_ack=cfg_power_state_change_ack,
|
||||
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
|
||||
cfg_err_cor_in=status_error_cor,
|
||||
cfg_err_uncor_in=status_error_uncor,
|
||||
#cfg_flr_done=cfg_flr_done,
|
||||
#cfg_vf_flr_done=cfg_vf_flr_done,
|
||||
#cfg_flr_in_process=cfg_flr_in_process,
|
||||
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
|
||||
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
|
||||
#cfg_link_training_enable=cfg_link_training_enable,
|
||||
|
||||
# Configuration Interrupt Controller Interface
|
||||
#cfg_interrupt_int=cfg_interrupt_int,
|
||||
#cfg_interrupt_sent=cfg_interrupt_sent,
|
||||
#cfg_interrupt_pending=cfg_interrupt_pending,
|
||||
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
|
||||
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
|
||||
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
|
||||
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
|
||||
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
|
||||
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
|
||||
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
|
||||
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
|
||||
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
|
||||
#cfg_interrupt_msix_sent=cfg_interrupt_msix_sent,
|
||||
#cfg_interrupt_msix_fail=cfg_interrupt_msix_fail,
|
||||
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
#cfg_ext_read_received=cfg_ext_read_received,
|
||||
#cfg_ext_write_received=cfg_ext_write_received,
|
||||
#cfg_ext_register_number=cfg_ext_register_number,
|
||||
#cfg_ext_function_number=cfg_ext_function_number,
|
||||
#cfg_ext_write_data=cfg_ext_write_data,
|
||||
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
|
||||
#cfg_ext_read_data=cfg_ext_read_data,
|
||||
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
|
||||
|
||||
# Clock and Reset Interface
|
||||
user_clk=user_clk,
|
||||
user_reset=user_reset,
|
||||
sys_clk=sys_clk,
|
||||
sys_clk_gt=sys_clk,
|
||||
sys_reset=sys_reset,
|
||||
#pcie_perstn0_out=pcie_perstn0_out,
|
||||
#pcie_perstn1_in=pcie_perstn1_in,
|
||||
#pcie_perstn1_out=pcie_perstn1_out
|
||||
)
|
||||
|
||||
# DUT
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
|
||||
dut = Cosimulation(
|
||||
"vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
clk_156mhz=clk_156mhz,
|
||||
rst_156mhz=rst_156mhz,
|
||||
clk_250mhz=user_clk,
|
||||
rst_250mhz=user_reset,
|
||||
sfp_1_led=sfp_1_led,
|
||||
sfp_2_led=sfp_2_led,
|
||||
sma_led=sma_led,
|
||||
m_axis_rq_tdata=m_axis_rq_tdata,
|
||||
m_axis_rq_tkeep=m_axis_rq_tkeep,
|
||||
m_axis_rq_tlast=m_axis_rq_tlast,
|
||||
m_axis_rq_tready=m_axis_rq_tready,
|
||||
m_axis_rq_tuser=m_axis_rq_tuser,
|
||||
m_axis_rq_tvalid=m_axis_rq_tvalid,
|
||||
s_axis_rc_tdata=s_axis_rc_tdata,
|
||||
s_axis_rc_tkeep=s_axis_rc_tkeep,
|
||||
s_axis_rc_tlast=s_axis_rc_tlast,
|
||||
s_axis_rc_tready=s_axis_rc_tready,
|
||||
s_axis_rc_tuser=s_axis_rc_tuser,
|
||||
s_axis_rc_tvalid=s_axis_rc_tvalid,
|
||||
s_axis_cq_tdata=s_axis_cq_tdata,
|
||||
s_axis_cq_tkeep=s_axis_cq_tkeep,
|
||||
s_axis_cq_tlast=s_axis_cq_tlast,
|
||||
s_axis_cq_tready=s_axis_cq_tready,
|
||||
s_axis_cq_tuser=s_axis_cq_tuser,
|
||||
s_axis_cq_tvalid=s_axis_cq_tvalid,
|
||||
m_axis_cc_tdata=m_axis_cc_tdata,
|
||||
m_axis_cc_tkeep=m_axis_cc_tkeep,
|
||||
m_axis_cc_tlast=m_axis_cc_tlast,
|
||||
m_axis_cc_tready=m_axis_cc_tready,
|
||||
m_axis_cc_tuser=m_axis_cc_tuser,
|
||||
m_axis_cc_tvalid=m_axis_cc_tvalid,
|
||||
pcie_tfc_nph_av=pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av=pcie_tfc_npd_av,
|
||||
cfg_max_payload=cfg_max_payload,
|
||||
cfg_max_read_req=cfg_max_read_req,
|
||||
cfg_mgmt_addr=cfg_mgmt_addr,
|
||||
cfg_mgmt_write=cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
|
||||
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
|
||||
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
|
||||
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
|
||||
status_error_cor=status_error_cor,
|
||||
status_error_uncor=status_error_uncor,
|
||||
sfp_1_tx_clk=sfp_1_tx_clk,
|
||||
sfp_1_tx_rst=sfp_1_tx_rst,
|
||||
sfp_1_txd=sfp_1_txd,
|
||||
sfp_1_txc=sfp_1_txc,
|
||||
sfp_1_rx_clk=sfp_1_rx_clk,
|
||||
sfp_1_rx_rst=sfp_1_rx_rst,
|
||||
sfp_1_rxd=sfp_1_rxd,
|
||||
sfp_1_rxc=sfp_1_rxc,
|
||||
sfp_2_tx_clk=sfp_2_tx_clk,
|
||||
sfp_2_tx_rst=sfp_2_tx_rst,
|
||||
sfp_2_txd=sfp_2_txd,
|
||||
sfp_2_txc=sfp_2_txc,
|
||||
sfp_2_rx_clk=sfp_2_rx_clk,
|
||||
sfp_2_rx_rst=sfp_2_rx_rst,
|
||||
sfp_2_rxd=sfp_2_rxd,
|
||||
sfp_2_rxc=sfp_2_rxc,
|
||||
sfp_i2c_scl_i=sfp_i2c_scl_i,
|
||||
sfp_i2c_scl_o=sfp_i2c_scl_o,
|
||||
sfp_i2c_scl_t=sfp_i2c_scl_t,
|
||||
sfp_1_i2c_sda_i=sfp_1_i2c_sda_i,
|
||||
sfp_1_i2c_sda_o=sfp_1_i2c_sda_o,
|
||||
sfp_1_i2c_sda_t=sfp_1_i2c_sda_t,
|
||||
sfp_2_i2c_sda_i=sfp_2_i2c_sda_i,
|
||||
sfp_2_i2c_sda_o=sfp_2_i2c_sda_o,
|
||||
sfp_2_i2c_sda_t=sfp_2_i2c_sda_t,
|
||||
eeprom_i2c_scl_i=eeprom_i2c_scl_i,
|
||||
eeprom_i2c_scl_o=eeprom_i2c_scl_o,
|
||||
eeprom_i2c_scl_t=eeprom_i2c_scl_t,
|
||||
eeprom_i2c_sda_i=eeprom_i2c_sda_i,
|
||||
eeprom_i2c_sda_o=eeprom_i2c_sda_o,
|
||||
eeprom_i2c_sda_t=eeprom_i2c_sda_t,
|
||||
flash_dq_i=flash_dq_i,
|
||||
flash_dq_o=flash_dq_o,
|
||||
flash_dq_oe=flash_dq_oe,
|
||||
flash_addr=flash_addr,
|
||||
flash_region=flash_region,
|
||||
flash_region_oe=flash_region_oe,
|
||||
flash_ce_n=flash_ce_n,
|
||||
flash_oe_n=flash_oe_n,
|
||||
flash_we_n=flash_we_n,
|
||||
flash_adv_n=flash_adv_n
|
||||
)
|
||||
|
||||
@always(delay(5))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
@always_comb
|
||||
def clk_logic():
|
||||
sys_clk.next = clk
|
||||
sys_reset.next = not rst
|
||||
|
||||
sfp_1_tx_clk.next = clk
|
||||
sfp_1_tx_rst.next = rst
|
||||
sfp_1_rx_clk.next = clk
|
||||
sfp_1_rx_rst.next = rst
|
||||
sfp_2_tx_clk.next = clk
|
||||
sfp_2_tx_rst.next = rst
|
||||
sfp_2_rx_clk.next = clk
|
||||
sfp_2_rx_rst.next = rst
|
||||
|
||||
loopback_enable = Signal(bool(0))
|
||||
|
||||
@instance
|
||||
def loopback():
|
||||
while True:
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
if loopback_enable:
|
||||
if not sfp_1_sink.empty():
|
||||
pkt = sfp_1_sink.recv()
|
||||
sfp_1_source.send(pkt)
|
||||
if not sfp_2_sink.empty():
|
||||
pkt = sfp_2_sink.recv()
|
||||
sfp_2_source.send(pkt)
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
# testbench stimulus
|
||||
|
||||
current_tag = 1
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: enumeration")
|
||||
current_test.next = 1
|
||||
|
||||
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
|
||||
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
|
||||
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
|
||||
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x270, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x274, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x278, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x27C, 0);
|
||||
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x290, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x294, 1000);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x298, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x29C, 0);
|
||||
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x280, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x284, 2000);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x288, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x28C, 0);
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: init NIC")
|
||||
current_test.next = 2
|
||||
|
||||
yield from driver.init_dev(dev.functions[0].get_id())
|
||||
yield from driver.interfaces[0].open()
|
||||
|
||||
# enable queues
|
||||
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0040, 0x00000001)
|
||||
for k in range(32):
|
||||
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+4*k, 0x00000001)
|
||||
|
||||
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: send and receive a packet")
|
||||
current_test.next = 3
|
||||
|
||||
data = bytearray([x%256 for x in range(1024)])
|
||||
|
||||
yield from driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
yield sfp_1_sink.wait()
|
||||
|
||||
pkt = sfp_1_sink.recv()
|
||||
print(pkt)
|
||||
|
||||
sfp_1_source.send(pkt)
|
||||
|
||||
yield driver.interfaces[0].wait()
|
||||
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: checksum tests")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame = udp_ep.UDPFrame()
|
||||
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
|
||||
test_frame.eth_src_mac = 0x5A5152535455
|
||||
test_frame.eth_type = 0x0800
|
||||
test_frame.ip_version = 4
|
||||
test_frame.ip_ihl = 5
|
||||
test_frame.ip_length = None
|
||||
test_frame.ip_identification = 0
|
||||
test_frame.ip_flags = 2
|
||||
test_frame.ip_fragment_offset = 0
|
||||
test_frame.ip_ttl = 64
|
||||
test_frame.ip_protocol = 0x11
|
||||
test_frame.ip_header_checksum = None
|
||||
test_frame.ip_source_ip = 0xc0a80164
|
||||
test_frame.ip_dest_ip = 0xc0a80165
|
||||
test_frame.udp_source_port = 1
|
||||
test_frame.udp_dest_port = 2
|
||||
test_frame.udp_length = None
|
||||
test_frame.udp_checksum = None
|
||||
test_frame.payload = bytearray((x%256 for x in range(256)))
|
||||
|
||||
test_frame.set_udp_pseudo_header_checksum()
|
||||
|
||||
axis_frame = test_frame.build_axis()
|
||||
|
||||
yield from driver.interfaces[0].start_xmit(axis_frame.data, 0, 34, 6)
|
||||
|
||||
yield sfp_1_sink.wait()
|
||||
|
||||
pkt = sfp_1_sink.recv()
|
||||
print(pkt)
|
||||
|
||||
sfp_1_source.send(pkt)
|
||||
|
||||
yield driver.interfaces[0].wait()
|
||||
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
|
||||
assert pkt.rx_checksum == frame_checksum(pkt.data)
|
||||
|
||||
check_frame = udp_ep.UDPFrame()
|
||||
check_frame.parse_axis(pkt.data)
|
||||
|
||||
assert check_frame.verify_checksums()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 5: multiple small packets")
|
||||
current_test.next = 5
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k)%256 for x in range(64)]) for k in range(count)]
|
||||
|
||||
loopback_enable.next = True
|
||||
|
||||
for p in pkts:
|
||||
yield from driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
if not pkt:
|
||||
yield driver.interfaces[0].wait()
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert frame_checksum(pkt.data) == pkt.rx_checksum
|
||||
|
||||
loopback_enable.next = False
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 6: multiple large packets")
|
||||
current_test.next = 6
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k)%256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
loopback_enable.next = True
|
||||
|
||||
for p in pkts:
|
||||
yield from driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
if not pkt:
|
||||
yield driver.interfaces[0].wait()
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert frame_checksum(pkt.data) == pkt.rx_checksum
|
||||
|
||||
loopback_enable.next = False
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return instances()
|
||||
|
||||
def test_bench():
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
389
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v
Normal file
389
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v
Normal file
@ -0,0 +1,389 @@
|
||||
/*
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for fpga_core
|
||||
*/
|
||||
module test_fpga_core;
|
||||
|
||||
// Parameters
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 256;
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = 75;
|
||||
parameter AXIS_PCIE_RQ_USER_WIDTH = 60;
|
||||
parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
|
||||
parameter AXIS_PCIE_CC_USER_WIDTH = 33;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg clk_156mhz = 0;
|
||||
reg rst_156mhz = 0;
|
||||
reg clk_250mhz = 0;
|
||||
reg rst_250mhz = 0;
|
||||
reg m_axis_rq_tready = 0;
|
||||
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata = 0;
|
||||
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep = 0;
|
||||
reg s_axis_rc_tlast = 0;
|
||||
reg [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser = 0;
|
||||
reg s_axis_rc_tvalid = 0;
|
||||
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0;
|
||||
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0;
|
||||
reg s_axis_cq_tlast = 0;
|
||||
reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
|
||||
reg s_axis_cq_tvalid = 0;
|
||||
reg m_axis_cc_tready = 0;
|
||||
reg [1:0] pcie_tfc_nph_av = 0;
|
||||
reg [1:0] pcie_tfc_npd_av = 0;
|
||||
reg [2:0] cfg_max_payload = 0;
|
||||
reg [2:0] cfg_max_read_req = 0;
|
||||
reg [31:0] cfg_mgmt_read_data = 0;
|
||||
reg cfg_mgmt_read_write_done = 0;
|
||||
reg [3:0] cfg_interrupt_msi_enable = 0;
|
||||
reg [7:0] cfg_interrupt_msi_vf_enable = 0;
|
||||
reg [11:0] cfg_interrupt_msi_mmenable = 0;
|
||||
reg cfg_interrupt_msi_mask_update = 0;
|
||||
reg [31:0] cfg_interrupt_msi_data = 0;
|
||||
reg cfg_interrupt_msi_sent = 0;
|
||||
reg cfg_interrupt_msi_fail = 0;
|
||||
reg sfp_1_tx_clk = 0;
|
||||
reg sfp_1_tx_rst = 0;
|
||||
reg sfp_1_rx_clk = 0;
|
||||
reg sfp_1_rx_rst = 0;
|
||||
reg [63:0] sfp_1_rxd = 0;
|
||||
reg [7:0] sfp_1_rxc = 0;
|
||||
reg sfp_2_tx_clk = 0;
|
||||
reg sfp_2_tx_rst = 0;
|
||||
reg sfp_2_rx_clk = 0;
|
||||
reg sfp_2_rx_rst = 0;
|
||||
reg [63:0] sfp_2_rxd = 0;
|
||||
reg [7:0] sfp_2_rxc = 0;
|
||||
reg sfp_i2c_scl_i = 1;
|
||||
reg sfp_1_i2c_sda_i = 1;
|
||||
reg sfp_2_i2c_sda_i = 1;
|
||||
reg eeprom_i2c_scl_i = 1;
|
||||
reg eeprom_i2c_sda_i = 1;
|
||||
reg [15:0] flash_dq_i = 0;
|
||||
|
||||
// Outputs
|
||||
wire [1:0] sfp_1_led;
|
||||
wire [1:0] sfp_2_led;
|
||||
wire [1:0] sma_led;
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep;
|
||||
wire m_axis_rq_tlast;
|
||||
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser;
|
||||
wire m_axis_rq_tvalid;
|
||||
wire s_axis_rc_tready;
|
||||
wire s_axis_cq_tready;
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep;
|
||||
wire m_axis_cc_tlast;
|
||||
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser;
|
||||
wire m_axis_cc_tvalid;
|
||||
wire [18:0] cfg_mgmt_addr;
|
||||
wire cfg_mgmt_write;
|
||||
wire [31:0] cfg_mgmt_write_data;
|
||||
wire [3:0] cfg_mgmt_byte_enable;
|
||||
wire cfg_mgmt_read;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
wire [63:0] sfp_1_txd;
|
||||
wire [7:0] sfp_1_txc;
|
||||
wire [63:0] sfp_2_txd;
|
||||
wire [7:0] sfp_2_txc;
|
||||
wire sfp_i2c_scl_o;
|
||||
wire sfp_i2c_scl_t;
|
||||
wire sfp_1_i2c_sda_o;
|
||||
wire sfp_1_i2c_sda_t;
|
||||
wire sfp_2_i2c_sda_o;
|
||||
wire sfp_2_i2c_sda_t;
|
||||
wire eeprom_i2c_scl_o;
|
||||
wire eeprom_i2c_scl_t;
|
||||
wire eeprom_i2c_sda_o;
|
||||
wire eeprom_i2c_sda_t;
|
||||
wire [15:0] flash_dq_o;
|
||||
wire flash_dq_oe;
|
||||
wire [22:0] flash_addr;
|
||||
wire flash_region;
|
||||
wire flash_region_oe;
|
||||
wire flash_ce_n;
|
||||
wire flash_oe_n;
|
||||
wire flash_we_n;
|
||||
wire flash_adv_n;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(
|
||||
clk_156mhz,
|
||||
rst_156mhz,
|
||||
clk_250mhz,
|
||||
rst_250mhz,
|
||||
current_test,
|
||||
m_axis_rq_tready,
|
||||
s_axis_rc_tdata,
|
||||
s_axis_rc_tkeep,
|
||||
s_axis_rc_tlast,
|
||||
s_axis_rc_tuser,
|
||||
s_axis_rc_tvalid,
|
||||
s_axis_cq_tdata,
|
||||
s_axis_cq_tkeep,
|
||||
s_axis_cq_tlast,
|
||||
s_axis_cq_tuser,
|
||||
s_axis_cq_tvalid,
|
||||
m_axis_cc_tready,
|
||||
pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av,
|
||||
cfg_max_payload,
|
||||
cfg_max_read_req,
|
||||
cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done,
|
||||
cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_vf_enable,
|
||||
cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail,
|
||||
sfp_1_tx_clk,
|
||||
sfp_1_tx_rst,
|
||||
sfp_1_rx_clk,
|
||||
sfp_1_rx_rst,
|
||||
sfp_1_rxd,
|
||||
sfp_1_rxc,
|
||||
sfp_2_tx_clk,
|
||||
sfp_2_tx_rst,
|
||||
sfp_2_rx_clk,
|
||||
sfp_2_rx_rst,
|
||||
sfp_2_rxd,
|
||||
sfp_2_rxc,
|
||||
sfp_i2c_scl_i,
|
||||
sfp_1_i2c_sda_i,
|
||||
sfp_2_i2c_sda_i,
|
||||
eeprom_i2c_scl_i,
|
||||
eeprom_i2c_sda_i,
|
||||
flash_dq_i
|
||||
);
|
||||
$to_myhdl(
|
||||
sfp_1_led,
|
||||
sfp_2_led,
|
||||
sma_led,
|
||||
m_axis_rq_tdata,
|
||||
m_axis_rq_tkeep,
|
||||
m_axis_rq_tlast,
|
||||
m_axis_rq_tuser,
|
||||
m_axis_rq_tvalid,
|
||||
s_axis_rc_tready,
|
||||
s_axis_cq_tready,
|
||||
m_axis_cc_tdata,
|
||||
m_axis_cc_tkeep,
|
||||
m_axis_cc_tlast,
|
||||
m_axis_cc_tuser,
|
||||
m_axis_cc_tvalid,
|
||||
cfg_mgmt_addr,
|
||||
cfg_mgmt_write,
|
||||
cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read,
|
||||
cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number,
|
||||
status_error_cor,
|
||||
status_error_uncor,
|
||||
sfp_1_txd,
|
||||
sfp_1_txc,
|
||||
sfp_2_txd,
|
||||
sfp_2_txc,
|
||||
sfp_i2c_scl_o,
|
||||
sfp_i2c_scl_t,
|
||||
sfp_1_i2c_sda_o,
|
||||
sfp_1_i2c_sda_t,
|
||||
sfp_2_i2c_sda_o,
|
||||
sfp_2_i2c_sda_t,
|
||||
eeprom_i2c_scl_o,
|
||||
eeprom_i2c_scl_t,
|
||||
eeprom_i2c_sda_o,
|
||||
eeprom_i2c_sda_t,
|
||||
flash_dq_o,
|
||||
flash_dq_oe,
|
||||
flash_addr,
|
||||
flash_region,
|
||||
flash_region_oe,
|
||||
flash_ce_n,
|
||||
flash_oe_n,
|
||||
flash_we_n,
|
||||
flash_adv_n
|
||||
);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_fpga_core.lxt");
|
||||
$dumpvars(0, test_fpga_core);
|
||||
end
|
||||
|
||||
fpga_core #(
|
||||
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
|
||||
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
|
||||
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
|
||||
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
|
||||
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
|
||||
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk_156mhz(clk_156mhz),
|
||||
.rst_156mhz(rst_156mhz),
|
||||
.clk_250mhz(clk_250mhz),
|
||||
.rst_250mhz(rst_250mhz),
|
||||
.sfp_1_led(sfp_1_led),
|
||||
.sfp_2_led(sfp_2_led),
|
||||
.sma_led(sma_led),
|
||||
.m_axis_rq_tdata(m_axis_rq_tdata),
|
||||
.m_axis_rq_tkeep(m_axis_rq_tkeep),
|
||||
.m_axis_rq_tlast(m_axis_rq_tlast),
|
||||
.m_axis_rq_tready(m_axis_rq_tready),
|
||||
.m_axis_rq_tuser(m_axis_rq_tuser),
|
||||
.m_axis_rq_tvalid(m_axis_rq_tvalid),
|
||||
.s_axis_rc_tdata(s_axis_rc_tdata),
|
||||
.s_axis_rc_tkeep(s_axis_rc_tkeep),
|
||||
.s_axis_rc_tlast(s_axis_rc_tlast),
|
||||
.s_axis_rc_tready(s_axis_rc_tready),
|
||||
.s_axis_rc_tuser(s_axis_rc_tuser),
|
||||
.s_axis_rc_tvalid(s_axis_rc_tvalid),
|
||||
.s_axis_cq_tdata(s_axis_cq_tdata),
|
||||
.s_axis_cq_tkeep(s_axis_cq_tkeep),
|
||||
.s_axis_cq_tlast(s_axis_cq_tlast),
|
||||
.s_axis_cq_tready(s_axis_cq_tready),
|
||||
.s_axis_cq_tuser(s_axis_cq_tuser),
|
||||
.s_axis_cq_tvalid(s_axis_cq_tvalid),
|
||||
.m_axis_cc_tdata(m_axis_cc_tdata),
|
||||
.m_axis_cc_tkeep(m_axis_cc_tkeep),
|
||||
.m_axis_cc_tlast(m_axis_cc_tlast),
|
||||
.m_axis_cc_tready(m_axis_cc_tready),
|
||||
.m_axis_cc_tuser(m_axis_cc_tuser),
|
||||
.m_axis_cc_tvalid(m_axis_cc_tvalid),
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
.status_error_cor(status_error_cor),
|
||||
.status_error_uncor(status_error_uncor),
|
||||
.sfp_1_tx_clk(sfp_1_tx_clk),
|
||||
.sfp_1_tx_rst(sfp_1_tx_rst),
|
||||
.sfp_1_txd(sfp_1_txd),
|
||||
.sfp_1_txc(sfp_1_txc),
|
||||
.sfp_1_rx_clk(sfp_1_rx_clk),
|
||||
.sfp_1_rx_rst(sfp_1_rx_rst),
|
||||
.sfp_1_rxd(sfp_1_rxd),
|
||||
.sfp_1_rxc(sfp_1_rxc),
|
||||
.sfp_2_tx_clk(sfp_2_tx_clk),
|
||||
.sfp_2_tx_rst(sfp_2_tx_rst),
|
||||
.sfp_2_txd(sfp_2_txd),
|
||||
.sfp_2_txc(sfp_2_txc),
|
||||
.sfp_2_rx_clk(sfp_2_rx_clk),
|
||||
.sfp_2_rx_rst(sfp_2_rx_rst),
|
||||
.sfp_2_rxd(sfp_2_rxd),
|
||||
.sfp_2_rxc(sfp_2_rxc),
|
||||
.sfp_i2c_scl_i(sfp_i2c_scl_i),
|
||||
.sfp_i2c_scl_o(sfp_i2c_scl_o),
|
||||
.sfp_i2c_scl_t(sfp_i2c_scl_t),
|
||||
.sfp_1_i2c_sda_i(sfp_1_i2c_sda_i),
|
||||
.sfp_1_i2c_sda_o(sfp_1_i2c_sda_o),
|
||||
.sfp_1_i2c_sda_t(sfp_1_i2c_sda_t),
|
||||
.sfp_2_i2c_sda_i(sfp_2_i2c_sda_i),
|
||||
.sfp_2_i2c_sda_o(sfp_2_i2c_sda_o),
|
||||
.sfp_2_i2c_sda_t(sfp_2_i2c_sda_t),
|
||||
.eeprom_i2c_scl_i(eeprom_i2c_scl_i),
|
||||
.eeprom_i2c_scl_o(eeprom_i2c_scl_o),
|
||||
.eeprom_i2c_scl_t(eeprom_i2c_scl_t),
|
||||
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
|
||||
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
|
||||
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
|
||||
.flash_dq_i(flash_dq_i),
|
||||
.flash_dq_o(flash_dq_o),
|
||||
.flash_dq_oe(flash_dq_oe),
|
||||
.flash_addr(flash_addr),
|
||||
.flash_region(flash_region),
|
||||
.flash_region_oe(flash_region_oe),
|
||||
.flash_ce_n(flash_ce_n),
|
||||
.flash_oe_n(flash_oe_n),
|
||||
.flash_we_n(flash_we_n),
|
||||
.flash_adv_n(flash_adv_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/udp_ep.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/udp_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/udp_ep.py
|
||||
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/xgmii_ep.py
Symbolic link
1
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/xgmii_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/xgmii_ep.py
|
||||
@ -48,6 +48,7 @@ either expressed or implied, of The Regents of the University of California.
|
||||
#define MQNIC_BOARD_ID_VCU108 0x10ee806c
|
||||
#define MQNIC_BOARD_ID_VCU118 0x10ee9076
|
||||
#define MQNIC_BOARD_ID_EXANIC_X10 0x1ce40003
|
||||
#define MQNIC_BOARD_ID_EXANIC_X25 0x1ce40009
|
||||
#define MQNIC_BOARD_ID_ADM_PCIE_9V3 0x41449003
|
||||
|
||||
// NIC CSRs
|
||||
|
||||
@ -97,6 +97,7 @@ int mqnic_init_i2c(struct mqnic_dev *mqnic)
|
||||
// eeprom i2c interface
|
||||
switch (mqnic->board_id) {
|
||||
case MQNIC_BOARD_ID_EXANIC_X10:
|
||||
case MQNIC_BOARD_ID_EXANIC_X25:
|
||||
case MQNIC_BOARD_ID_ADM_PCIE_9V3:
|
||||
mqnic->eeprom_i2c_adap.owner = THIS_MODULE;
|
||||
mqnic->eeprom_i2c_priv.mqnic = mqnic;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user