diff --git a/README.md b/README.md
index fb7d13bfe..91c3662c2 100644
--- a/README.md
+++ b/README.md
@@ -28,6 +28,7 @@ devices. Desgins are included for the following FPGA boards:
* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex Ultrascale Plus XCVU3P)
* Exablaze ExaNIC X10 (Xilinx Kintex Ultrascale XCKU035)
+* Exablaze ExaNIC X25 (Xilinx Kintex Ultrascale Plus XCKU3P)
* Xilinx VCU108 (Xilinx Virtex Ultrascale XCVU095)
* Xilinx VCU118 (Xilinx Virtex Ultrascale Plus XCVU9P)
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile
new file mode 100644
index 000000000..f504bd06f
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/Makefile
@@ -0,0 +1,25 @@
+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+ cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+ cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+ -rm -rf $(TARGETS)
+
+program:
+ #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/README.md b/fpga/mqnic/ExaNIC_X25/fpga_10g/README.md
new file mode 100644
index 000000000..4aee74956
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/README.md
@@ -0,0 +1,24 @@
+# Corundum mqnic for ExaNIC X25
+
+## Introduction
+
+This design targets the Exablaze ExaNIC X25 FPGA board.
+
+FPGA: xcku3p-ffvb676-2-e
+PHY: 10G BASE-R PHY IP core and internal GTY transceiver
+
+## How to build
+
+Run make to build. Ensure that the Xilinx Vivado toolchain components are
+in PATH.
+
+Run make to build the driver. Ensure the headers for the running kernel are
+installed, otherwise the driver cannot be compiled.
+
+## How to test
+
+Run make program to program the ExaNIC X25 board with Vivado. Then load the
+driver with insmod mqnic.ko. Check dmesg for output from driver
+initialization.
+
+
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk b/fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk
new file mode 100644
index 000000000..964ed04eb
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/common/vivado.mk
@@ -0,0 +1,118 @@
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: clean fpga
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
+
+ifdef XDC_FILES
+ XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
+else
+ XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+tmpclean:
+ -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+ -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean: tmpclean
+ -rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean: clean
+ -rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+%.xpr: Makefile $(XCI_FILES_REL)
+ rm -rf defines.v
+ touch defines.v
+ for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+ echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
+ echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
+ for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
+ for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
+ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
+ echo "exit" >> create_project.tcl
+ vivado -nojournal -nolog -mode batch -source create_project.tcl
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+ echo "open_project $*.xpr" > run_synth.tcl
+ echo "reset_run synth_1" >> run_synth.tcl
+ echo "launch_runs synth_1" >> run_synth.tcl
+ echo "wait_on_run synth_1" >> run_synth.tcl
+ echo "exit" >> run_synth.tcl
+ vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+ echo "open_project $*.xpr" > run_impl.tcl
+ echo "reset_run impl_1" >> run_impl.tcl
+ echo "launch_runs impl_1" >> run_impl.tcl
+ echo "wait_on_run impl_1" >> run_impl.tcl
+ echo "exit" >> run_impl.tcl
+ vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+ echo "open_project $*.xpr" > generate_bit.tcl
+ echo "open_run impl_1" >> generate_bit.tcl
+ echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+ echo "exit" >> generate_bit.tcl
+ vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+ mkdir -p rev
+ EXT=bit; COUNT=100; \
+ while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+ do COUNT=$$((COUNT+1)); done; \
+ cp $@ rev/$*_rev$$COUNT.$$EXT; \
+ echo "Output: rev/$*_rev$$COUNT.$$EXT";
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc
new file mode 100644
index 000000000..f5b8b9b22
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga.xdc
@@ -0,0 +1,158 @@
+# XDC constraints for the ExaNIC X25
+# part: xcku3p-ffvb676-2-e
+
+# General configuration
+set_property CFGBVS GND [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 31.9 [current_design]
+set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 8 [current_design]
+set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 4 [current_design]
+set_property BITSTREAM.CONFIG.REVISIONSELECT_TRISTATE Enable [current_design]
+set_property CONFIG_MODE BPI16 [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
+
+# 10 MHz TXCO
+#set_property -dict {LOC D14 IOSTANDARD LVCMOS33} [get_ports clk_10mhz]
+#create_clock -period 100 -name clk_100mhz [get_ports clk_10mhz]
+
+# LEDs
+set_property -dict {LOC J12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[0]}]
+set_property -dict {LOC H12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[1]}]
+set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[0]}]
+set_property -dict {LOC H13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[1]}]
+set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
+set_property -dict {LOC G12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
+
+# GPIO
+#set_property -dict {LOC F9 IOSTANDARD LVCMOS18} [get_ports gpio[0]]
+#set_property -dict {LOC F10 IOSTANDARD LVCMOS18} [get_ports gpio[1]]
+#set_property -dict {LOC G9 IOSTANDARD LVCMOS18} [get_ports gpio[2]]
+#set_property -dict {LOC G10 IOSTANDARD LVCMOS18} [get_ports gpio[3]]
+
+# SMA
+set_property -dict {LOC A14 IOSTANDARD LVCMOS33} [get_ports sma_in]
+set_property -dict {LOC A12 IOSTANDARD LVCMOS33} [get_ports sma_out]
+set_property -dict {LOC A13 IOSTANDARD LVCMOS33} [get_ports sma_out_en]
+set_property -dict {LOC B12 IOSTANDARD LVCMOS33} [get_ports sma_term_en]
+
+# Config
+#set_property -dict {LOC C14 IOSTANDARD LVCMOS33} [get_ports ddr_npres]
+
+# SFP28 Interfaces
+set_property -dict {LOC D2 } [get_ports sfp_1_rx_p] ;# MGTYRXP0_227 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
+#set_property -dict {LOC D1 } [get_ports sfp_1_rx_n] ;# MGTYRXN0_227 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
+set_property -dict {LOC A4 } [get_ports sfp_2_rx_p] ;# MGTYRXP3_227 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
+#set_property -dict {LOC A3 } [get_ports sfp_2_rx_n] ;# MGTYRXN3_227 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
+set_property -dict {LOC F7 } [get_ports sfp_1_tx_p] ;# MGTYTXP0_227 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
+#set_property -dict {LOC F6 } [get_ports sfp_1_tx_n] ;# MGTYTXN0_227 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
+set_property -dict {LOC B7 } [get_ports sfp_2_tx_p] ;# MGTYTXP3_227 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
+#set_property -dict {LOC B6 } [get_ports sfp_2_tx_n] ;# MGTYTXN3_227 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
+set_property -dict {LOC K7 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_227 from X2
+#set_property -dict {LOC K6 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_227 from X2
+set_property -dict {LOC AC17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable]
+set_property -dict {LOC AA17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable]
+set_property -dict {LOC F12 IOSTANDARD LVCMOS33 PULLUP true} [get_ports sfp_1_npres]
+set_property -dict {LOC F14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports sfp_2_npres]
+set_property -dict {LOC AC16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_los]
+set_property -dict {LOC Y17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los]
+set_property -dict {LOC G14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_1_rs]
+set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_2_rs]
+set_property -dict {LOC A10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl]
+set_property -dict {LOC C11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda]
+set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda]
+
+# 161.1328125 MHz MGT reference clock
+create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
+
+# I2C interface
+set_property -dict {LOC B9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
+set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
+
+# PCIe Interface
+set_property -dict {LOC P2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
+#set_property -dict {LOC P1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
+set_property -dict {LOC R5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
+#set_property -dict {LOC R4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
+set_property -dict {LOC T2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
+#set_property -dict {LOC T1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
+set_property -dict {LOC U5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
+#set_property -dict {LOC U4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
+set_property -dict {LOC V2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
+#set_property -dict {LOC V1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
+set_property -dict {LOC W5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
+#set_property -dict {LOC W4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
+set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
+#set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
+set_property -dict {LOC AA5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
+#set_property -dict {LOC AA4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
+set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
+#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
+set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
+#set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
+set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
+#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
+set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
+#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
+set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
+#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
+set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
+#set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
+set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
+#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
+set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
+#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
+set_property -dict {LOC V7 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225
+#set_property -dict {LOC V6 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_225
+set_property -dict {LOC T19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
+
+# 100 MHz MGT reference clock
+create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
+
+# Flash
+set_property -dict {LOC AF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[0]}]
+set_property -dict {LOC AE18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[1]}]
+set_property -dict {LOC AF19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[2]}]
+set_property -dict {LOC AF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[3]}]
+set_property -dict {LOC AB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
+set_property -dict {LOC AD19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
+set_property -dict {LOC AB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
+set_property -dict {LOC AE17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
+set_property -dict {LOC AD16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
+set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
+set_property -dict {LOC AD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
+set_property -dict {LOC AC21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
+set_property -dict {LOC AE22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
+set_property -dict {LOC AF22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
+set_property -dict {LOC AF25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
+set_property -dict {LOC AF24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
+set_property -dict {LOC AE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
+set_property -dict {LOC AE26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
+set_property -dict {LOC AD24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
+set_property -dict {LOC AC23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
+set_property -dict {LOC AE23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
+set_property -dict {LOC AD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
+set_property -dict {LOC AC24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
+set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
+set_property -dict {LOC AD23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
+set_property -dict {LOC AD21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
+set_property -dict {LOC AB22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
+set_property -dict {LOC AA22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
+set_property -dict {LOC AE25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
+set_property -dict {LOC AD26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
+set_property -dict {LOC AB25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
+set_property -dict {LOC AB26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
+set_property -dict {LOC AD25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
+set_property -dict {LOC AC26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
+set_property -dict {LOC AB21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
+set_property -dict {LOC AB24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
+set_property -dict {LOC Y18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
+set_property -dict {LOC AA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
+set_property -dict {LOC AC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
+set_property -dict {LOC Y20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
+set_property -dict {LOC AF18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_ce_n}]
+set_property -dict {LOC Y21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
+set_property -dict {LOC AB20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
+set_property -dict {LOC AF23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
+
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
new file mode 100644
index 000000000..c024d6915
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
@@ -0,0 +1,132 @@
+
+# FPGA settings
+FPGA_PART = xcku3p-ffvb676-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = kintexuplus
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_reset.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += rtl/common/interface.v
+SYN_FILES += rtl/common/port.v
+SYN_FILES += rtl/common/cpl_write.v
+SYN_FILES += rtl/common/cpl_op_mux.v
+SYN_FILES += rtl/common/desc_fetch.v
+SYN_FILES += rtl/common/desc_op_mux.v
+SYN_FILES += rtl/common/queue_manager.v
+SYN_FILES += rtl/common/cpl_queue_manager.v
+SYN_FILES += rtl/common/event_mux.v
+SYN_FILES += rtl/common/tx_scheduler_rr.v
+SYN_FILES += rtl/common/tdma_scheduler.v
+SYN_FILES += rtl/common/tdma_ber.v
+SYN_FILES += rtl/common/tdma_ber_ch.v
+SYN_FILES += rtl/common/tx_engine.v
+SYN_FILES += rtl/common/rx_engine.v
+SYN_FILES += rtl/common/tx_checksum.v
+SYN_FILES += rtl/common/rx_checksum.v
+SYN_FILES += lib/eth/rtl/eth_mac_10g.v
+SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/ptp_clock.v
+SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
+SYN_FILES += lib/eth/rtl/ptp_perout.v
+SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
+SYN_FILES += lib/axi/rtl/axil_interconnect.v
+SYN_FILES += lib/axi/rtl/arbiter.v
+SYN_FILES += lib/axi/rtl/priority_encoder.v
+SYN_FILES += lib/axis/rtl/axis_adapter.v
+SYN_FILES += lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/axis/rtl/axis_arb_mux.v
+SYN_FILES += lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/axis/rtl/axis_register.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
+SYN_FILES += lib/pcie/rtl/dma_psdpram.v
+SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
+SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
+SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
+SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
+SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
+XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/tdma_ber_ch.tcl
+
+# IP
+XCI_FILES = ip/pcie4_uscale_plus_0.xci
+XCI_FILES += ip/gtwizard_ultrascale_0.xci
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+ echo "open_hw" > program.tcl
+ echo "connect_hw_server" >> program.tcl
+ echo "open_hw_target" >> program.tcl
+ echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+ echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+ echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+ echo "program_hw_devices [current_hw_device]" >> program.tcl
+ echo "exit" >> program.tcl
+ vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+ echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+ echo "exit" >> generate_mcs.tcl
+ vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+ mkdir -p rev
+ COUNT=100; \
+ while [ -e rev/$*_rev$$COUNT.bit ]; \
+ do COUNT=$$((COUNT+1)); done; \
+ COUNT=$$((COUNT-1)); \
+ for x in .mcs .prm; \
+ do cp $*$$x rev/$*_rev$$COUNT$$x; \
+ echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+ echo "open_hw" > flash.tcl
+ echo "connect_hw_server" >> flash.tcl
+ echo "open_hw_target" >> flash.tcl
+ echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+ echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+ echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s29gl256p-bpi-x16}] 0]" >> flash.tcl
+ echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+ echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+ echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+ echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+ echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+ echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+ echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+ echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+ echo "set_property PROGRAM.BPI_RS_PINS {none} [current_hw_cfgmem]" >> flash.tcl
+ echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+ echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+ echo "program_hw_devices [current_hw_device]" >> flash.tcl
+ echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+ echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+ echo "boot_hw_device [current_hw_device]" >> flash.tcl
+ echo "exit" >> flash.tcl
+ vivado -nojournal -nolog -mode batch -source flash.tcl
+
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.xci b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.xci
new file mode 100644
index 000000000..cf560103c
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.xci
@@ -0,0 +1,1406 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ gtwizard_ultrascale_0
+
+
+ "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000"
+ 1
+ 2578.125
+ 0
+ 0
+ 125
+ 67
+ 3
+ 2
+ 0
+ 2
+ 0
+ 0
+ 1
+ 0
+ 1
+ 0
+ 250
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ "00000000"
+ "00000000"
+ 1
+ 1
+ 0
+ "00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+ "00000000"
+ 0
+ "00000000"
+ 1
+ 0
+ 5000
+ "00000000000000000000000000000000000000000000000000000000000000000000000000000000"
+ 0
+ "1010000011"
+ 0
+ "0101111100"
+ 4
+ 1
+ 64
+ 10.3125
+ 12
+ 1
+ 156.2500000
+ 4
+ 0
+ 0x000000000000000000000000000000000000000000000000
+ 161.1328125
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 64
+ 156.2500000
+ 156.2500000
+ 0
+ 257.8125
+ 1
+ 2
+ 1
+ 0
+ 0
+ 0
+ 156.25
+ 0
+ 0
+ 1
+ 4
+ 1
+ 64
+ 10.3125
+ 12
+ 1
+ 156.2500000
+ 4
+ 0
+ 161.1328125
+ 0
+ 0
+ 1
+ 1
+ 0
+ 64
+ 156.2500000
+ 156.2500000
+ 1
+ X0Y13 X0Y12
+ gtwizard_ultrascale_0
+ 0
+ 0
+ rxpolarity_in txpolarity_in
+ 125
+ BOTH
+ 0
+ GTY
+ 2
+ 20
+ 96
+ 1
+ gtye4
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ -1
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ 1
+ 1
+ -1
+ -1
+ -1
+ -1
+ 1
+ 1
+ -1
+ 1
+ 1
+ 1
+ -1
+ 1
+ 1
+ 1
+ -1
+ -1
+ -1
+ -1
+ -1
+ 1
+ -1
+ -1
+ -1
+ -1
+ -1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ -1
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ -1
+ -1
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ -1
+ -1
+ -1
+ 0
+ 0
+ 0
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ -1
+ -1
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ -1
+ 0
+ 0
+ 0
+ -1
+ 0
+ 1
+ -1
+ -1
+ -1
+ -1
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 14
+ 0
+ 10GBASE-R
+ 5
+ 156.2500000
+ 2
+ 1
+ 156.2500000
+ false
+ CORE
+ NONE
+ CORE
+ CORE
+ EXAMPLE_DESIGN
+ CORE
+ EXAMPLE_DESIGN
+ CORE
+ false
+ NAME
+ false
+ 250
+ false
+ false
+ 250
+ GTY-10GBASE-R
+ 0
+ MULTI
+ 1
+ ENABLE
+ DISABLE
+ ENABLE
+ 00000000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 00000000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 1
+ 00000000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 1
+ 1
+ 0
+ 00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 00000000
+ DISABLE
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 1
+ 00000000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 0
+ 5000
+ ENABLE
+ 0
+ 00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 1
+ false
+ 0000000000
+ false
+ 1010000011
+ NONE
+ false
+ 0101111100
+ true
+ 0
+ AC
+ 64B66B_ASYNC
+ true
+ AUTO
+ 64
+ 6.1862627
+ -20
+ 10.3125
+ X0Y12
+ RXPROGDIVCLK
+ QPLL0
+ 200
+ 0
+
+ 161.1328125
+
+ OFF
+ 0
+ PROGRAMMABLE
+ 800
+ 64
+ 15
+ false
+ 0
+ 10.3125
+ 257.8125
+ 1
+ false
+ QPLL0
+ 156.25
+ 1
+ ENABLE
+ 64B66B_ASYNC
+ CUSTOM
+ true
+ 64
+ 10.3125
+ X0Y12
+ TXPROGDIVCLK
+ QPLL0
+ 0
+ 161.1328125
+
+ 64
+ false
+ 1
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ true
+ true
+ true
+ false
+ true
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ true
+ true
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ kintexuplus
+
+
+ xcku3p
+ ffvb676
+ VERILOG
+
+ MIXED
+ -2
+
+ E
+ TRUE
+ TRUE
+ IP_Flow
+ 6
+ TRUE
+ .
+
+ .
+ 2019.1
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.xci b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.xci
new file mode 100644
index 000000000..e5e88c4e8
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/ip/pcie4_uscale_plus_0.xci
@@ -0,0 +1,1278 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ pcie4_uscale_plus_0
+
+
+
+
+
+ 0
+ 0.000
+
+
+
+ 0
+ 0.000
+
+
+
+ 100000000
+ 0
+ 0.000
+
+
+
+ 100000000
+ 0
+ 0.000
+
+ 0
+ 0.000
+
+ 100000000
+ 1
+ 1
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 32
+ 0
+ 0
+ 88
+
+ 100000000
+ 1
+ 1
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 32
+ 0
+ 0
+ 75
+ 0
+ ACTIVE_LOW
+ 0
+
+ 100000000
+ 1
+ 1
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 32
+ 0
+ 0
+ 33
+
+ 100000000
+ 1
+ 1
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 32
+ 0
+ 0
+ 62
+ 0x000
+ FALSE
+ FALSE
+ 0
+ 33
+ 88
+ 256
+ 75
+ 62
+ 0x0
+ 0x0
+ TRUE
+ FALSE
+ 0x00000
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 0x0
+ FALSE
+ 0x0
+ FALSE
+ FALSE
+ FALSE
+ TRUE
+ TRUE
+ TRUE
+ TRUE
+ TRUE
+ TRUE
+ TRUE
+ FALSE
+ TRUE
+ 2
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ 0
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 1
+ TRUE
+ 2
+ 1
+ 0
+ ADD-IN_CARD
+ 0
+ FALSE
+ FALSE
+ FALSE
+ 0x000
+ NONE
+ 0x00000000
+ FALSE
+ TRUE
+ 32
+ None
+ TRUE
+ FALSE
+ FALSE
+ NONE
+ FALSE
+ TRUE
+ FALSE
+ 0x1C0
+ 0x1C0
+ 0x00
+ 0x011
+ 0x4
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x40
+ 0x020000
+ 0x1001
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ TRUE
+ FALSE
+ 0x3
+ 0x1C0
+ 0x000
+ FALSE
+ 0x0
+ 0
+ TRUE
+ 0x70
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 5
+ 0x70
+ TRUE
+ 0x48
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 0x0
+ 0x7
+ 0x7
+ 0x7
+ 0x7
+ 0x7
+ 0xffffffffffff
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x1
+ 0x00
+ 0x000
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x0000
+ 0x000
+ 0x0000
+ 0x1
+ 0x0000
+ 0x0000
+ 0x00000553
+ 0x0000
+ 0x1001
+ 0x1234
+ TRUE
+ FALSE
+ FALSE
+ 0x000
+ 0x0
+ 0x0
+ 0x000
+ 0x1
+ FALSE
+ 0x000
+ 0x1234
+ 0x000
+ 0x000
+ 0x00
+ 0x011
+ 0x4
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x40
+ 0x058000
+ 0x9011
+ 0x3
+ 0x000
+ 0x000
+ FALSE
+ 0x0
+ 0x70
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0x70
+ TRUE
+ 0x70
+ 0x0
+ 0x7
+ 0x7
+ 0x7
+ 0x7
+ 0x7
+ 0xffffffffffff
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x1
+ 0x00
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x0000
+ 0x000
+ 0x0000
+ 0x1
+ 0x0000
+ 0x0001
+ 0x00000553
+ 0x0000
+ 0x0007
+ 0x000
+ 0x0
+ 0x000
+ 0x000
+ 0x00
+ 0x011
+ 0x4
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x40
+ 0x058000
+ 0x9438
+ 0x3
+ 0x000
+ 0x000
+ FALSE
+ 0x0
+ 0x70
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0x70
+ TRUE
+ 0x70
+ 0x0
+ 0x7
+ 0x7
+ 0x7
+ 0x7
+ 0x7
+ 0xffffffffffff
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x1
+ 0x00
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x0000
+ 0x000
+ 0x0000
+ 0x1
+ 0x0000
+ 0x0002
+ 0x00000553
+ 0x0000
+ 0x0007
+ 0x000
+ 0x0
+ 0x000
+ 0x000
+ 0x00
+ 0x011
+ 0x4
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x000
+ 0x0
+ 0x40
+ 0x058000
+ 0x9638
+ 0x3
+ 0x000
+ 0x000
+ FALSE
+ 0x0
+ 0x70
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0x70
+ TRUE
+ 0x70
+ 0x0
+ 0x7
+ 0x7
+ 0x7
+ 0x7
+ 0x7
+ 0xffffffffffff
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x1
+ 0x00
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x00
+ 0x0
+ 0x0000
+ 0x000
+ 0x0000
+ 0x1
+ 0x0000
+ 0x0003
+ 0x00000553
+ 0x0000
+ 0x0007
+ 0x000
+ 0x0
+ 4
+ 0
+ FALSE
+ 2
+ TRUE
+ FALSE
+ 4
+ 8
+ TRUE
+ FALSE
+ 0x000
+ FALSE
+ TRUE
+ GTY_Quad_225
+ 1
+ 0x00000000
+ 0x0
+ FALSE
+ 0
+ FALSE
+ FALSE
+ 0x2
+ 0x000
+ 0x00
+ 0x004
+ 0x20
+ 0x3E0
+ 0x20
+ FALSE
+ 0
+ FALSE
+ X8G3
+ FALSE
+ TRUE
+ FALSE
+ 0x70
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ 0
+ 0x00000000
+ 0
+ 0x00000000
+ 0x000
+ FALSE
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ Beta
+ 0
+ false
+ true
+ true
+ true
+ true
+ true
+ DWORD_Aligned
+ false
+ false
+ false
+ true
+ false
+ false
+ DWORD_Aligned
+ pcie4_uscale_plus_0
+ 15
+ None
+ Custom
+ false
+ 020000
+ 1001
+ false
+ false
+ false
+ false
+ false
+ NONE
+ true
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 32_vectors
+ false
+ false
+ false
+ false
+ 00
+ 0
+ 0
+ 0000
+ 00000553
+ 0000
+ 1001
+ 1234
+ true
+ 058000
+ 9011
+ NONE
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ 00
+ 0
+ 1
+ 0
+ 0001
+ 00000553
+ 0000
+ 0007
+ 1234
+ false
+ 058000
+ 9438
+ NONE
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ 00
+ 0
+ 1
+ 0
+ 0002
+ 00000553
+ 0000
+ 0007
+ 1234
+ false
+ 058000
+ 9638
+ NONE
+ BAR_0
+ 00000000
+ BAR_0
+ 00000000
+ 000
+ 1_vector
+ 00
+ 0
+ 1
+ 0
+ 0003
+ 00000553
+ 0000
+ 0007
+ 1234
+ false
+ 4
+ true
+ 8.0_GT/s
+ X8
+ 100_MHz
+ 0
+ 0
+ false
+ false
+ 1
+ Custom
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ false
+ DWORD_Aligned
+ No_ASPM
+ 0
+ 250
+ true
+ 00000
+ false
+ false
+ 256_bit
+ false
+ true
+ true
+ true
+ true
+ true
+ true
+ true
+ false
+ true
+ true
+ 500
+ true
+ false
+ false
+ PCI_Express_Endpoint_device
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ False
+ false
+ 0000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ 100_MHz
+ true
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ Internal
+ 2
+ 1
+ Add-in_Card
+ false
+ false
+ false
+ None
+ 00000000
+ Advanced
+ HARD
+ true
+ X0Y0
+ false
+ true
+ Extreme
+ true
+ false
+ false
+ true
+ 0
+ false
+ Megabytes
+ 16
+ Memory
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ Network_controller
+ 02
+ 00
+ 00
+ 1024_bytes
+ false
+ false
+ Kilobytes
+ 2
+ true
+ false
+ 0xffffffffffff
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 1
+ false
+ true
+ false
+ Kilobytes
+ 2
+ Memory
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ 1
+ Ethernet_controller
+ false
+ false
+ false
+ true
+ 0
+ false
+ Megabytes
+ 16
+ Memory
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ Memory_controller
+ 05
+ 00
+ 80
+ false
+ Kilobytes
+ 2
+ false
+ false
+ 0xffffffffffff
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 1
+ false
+ true
+ false
+ Kilobytes
+ 2
+ Memory
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ Other_memory_controller
+ 1234
+ false
+ true
+ 0
+ false
+ Megabytes
+ 16
+ Memory
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ Memory_controller
+ 05
+ 00
+ 80
+ false
+ Kilobytes
+ 2
+ false
+ false
+ 0xffffffffffff
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 1
+ false
+ true
+ false
+ Kilobytes
+ 2
+ Memory
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ Other_memory_controller
+ 1234
+ false
+ true
+ 0
+ false
+ Megabytes
+ 16
+ Memory
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ false
+ 7
+ false
+ Kilobytes
+ 128
+ N/A
+ Memory_controller
+ 05
+ 00
+ 80
+ false
+ Kilobytes
+ 2
+ false
+ false
+ 0xffffffffffff
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 0x000000000000
+ 1
+ false
+ true
+ false
+ Kilobytes
+ 2
+ Memory
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ Other_memory_controller
+ 1234
+ false
+ QPLL1
+ false
+ true
+ GTY_Quad_225
+ false
+ false
+ ACTIVE_LOW
+ false
+ 15
+ 15
+ X8G3
+ false
+ true
+ Enabled
+ 64bit_Enabled
+ true
+ false
+ 1234
+ false
+ None
+ kintexuplus
+
+
+ xcku3p
+ ffvb676
+ VERILOG
+
+ MIXED
+ -2
+
+ E
+ TRUE
+ TRUE
+ IP_Flow
+ 5
+ TRUE
+ .
+
+ .
+ 2019.1
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/lib b/fpga/mqnic/ExaNIC_X25/fpga_10g/lib
new file mode 120000
index 000000000..9512b3d5e
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/lib
@@ -0,0 +1 @@
+../../../lib/
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common
new file mode 120000
index 000000000..449c9409c
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/common
@@ -0,0 +1 @@
+../../../../common/rtl/
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/debounce_switch.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/debounce_switch.v
new file mode 100644
index 000000000..bb631cc35
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/debounce_switch.v
@@ -0,0 +1,89 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Synchronizes switch and button inputs with a slow sampled shift register
+ */
+module debounce_switch #(
+ parameter WIDTH=1, // width of the input and output signals
+ parameter N=3, // length of shift register
+ parameter RATE=125000 // clock division factor
+)(
+ input wire clk,
+ input wire rst,
+ input wire [WIDTH-1:0] in,
+ output wire [WIDTH-1:0] out
+);
+
+reg [23:0] cnt_reg = 24'd0;
+
+reg [N-1:0] debounce_reg[WIDTH-1:0];
+
+reg [WIDTH-1:0] state;
+
+/*
+ * The synchronized output is the state register
+ */
+assign out = state;
+
+integer k;
+
+always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ cnt_reg <= 0;
+ state <= 0;
+
+ for (k = 0; k < WIDTH; k = k + 1) begin
+ debounce_reg[k] <= 0;
+ end
+ end else begin
+ if (cnt_reg < RATE) begin
+ cnt_reg <= cnt_reg + 24'd1;
+ end else begin
+ cnt_reg <= 24'd0;
+ end
+
+ if (cnt_reg == 24'd0) begin
+ for (k = 0; k < WIDTH; k = k + 1) begin
+ debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
+ end
+ end
+
+ for (k = 0; k < WIDTH; k = k + 1) begin
+ if (|debounce_reg[k] == 0) begin
+ state[k] <= 0;
+ end else if (&debounce_reg[k] == 1) begin
+ state[k] <= 1;
+ end else begin
+ state[k] <= state[k];
+ end
+ end
+ end
+end
+
+endmodule
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v
new file mode 100644
index 000000000..6cfe727a1
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v
@@ -0,0 +1,981 @@
+/*
+
+Copyright 2019, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * FPGA top-level module
+ */
+module fpga (
+ /*
+ * GPIO
+ */
+ output wire [1:0] sfp_1_led,
+ output wire [1:0] sfp_2_led,
+ output wire [1:0] sma_led,
+
+ input wire sma_in,
+ output wire sma_out,
+ output wire sma_out_en,
+ output wire sma_term_en,
+
+ /*
+ * PCI express
+ */
+ input wire [7:0] pcie_rx_p,
+ input wire [7:0] pcie_rx_n,
+ output wire [7:0] pcie_tx_p,
+ output wire [7:0] pcie_tx_n,
+ input wire pcie_refclk_p,
+ input wire pcie_refclk_n,
+ input wire pcie_reset_n,
+
+ /*
+ * Ethernet: SFP28
+ */
+ input wire sfp_1_rx_p,
+ input wire sfp_1_rx_n,
+ output wire sfp_1_tx_p,
+ output wire sfp_1_tx_n,
+ input wire sfp_2_rx_p,
+ input wire sfp_2_rx_n,
+ output wire sfp_2_tx_p,
+ output wire sfp_2_tx_n,
+ input wire sfp_mgt_refclk_p,
+ input wire sfp_mgt_refclk_n,
+ output wire sfp_1_tx_disable,
+ output wire sfp_2_tx_disable,
+ input wire sfp_1_npres,
+ input wire sfp_2_npres,
+ input wire sfp_1_los,
+ input wire sfp_2_los,
+ output wire sfp_1_rs,
+ output wire sfp_2_rs,
+
+ inout wire sfp_i2c_scl,
+ inout wire sfp_1_i2c_sda,
+ inout wire sfp_2_i2c_sda,
+
+ inout wire eeprom_i2c_scl,
+ inout wire eeprom_i2c_sda,
+
+ /*
+ * BPI Flash
+ */
+ inout wire [15:0] flash_dq,
+ output wire [22:0] flash_addr,
+ output wire flash_region,
+ output wire flash_ce_n,
+ output wire flash_oe_n,
+ output wire flash_we_n,
+ output wire flash_adv_n
+);
+
+parameter AXIS_PCIE_DATA_WIDTH = 256;
+parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
+parameter AXIS_PCIE_RC_USER_WIDTH = 75;
+parameter AXIS_PCIE_RQ_USER_WIDTH = 62;
+parameter AXIS_PCIE_CQ_USER_WIDTH = 88;
+parameter AXIS_PCIE_CC_USER_WIDTH = 33;
+
+// Clock and reset
+wire pcie_user_clk;
+wire pcie_user_reset;
+
+wire clk_161mhz_int;
+
+wire clk_125mhz_mmcm_out;
+
+// Internal 125 MHz clock
+wire clk_125mhz_int;
+wire rst_125mhz_int;
+
+// Internal 156.25 MHz clock
+wire clk_156mhz_int;
+wire rst_156mhz_int;
+
+wire mmcm_rst = pcie_user_reset;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+// MMCM instance
+// 161.13 MHz in, 125 MHz out
+// PFD range: 10 MHz to 500 MHz
+// VCO range: 800 MHz to 1600 MHz
+// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
+// Divide by 7.5 to get output frequency of 125 MHz
+MMCME4_BASE #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKOUT0_DIVIDE_F(7.5),
+ .CLKOUT0_DUTY_CYCLE(0.5),
+ .CLKOUT0_PHASE(0),
+ .CLKOUT1_DIVIDE(1),
+ .CLKOUT1_DUTY_CYCLE(0.5),
+ .CLKOUT1_PHASE(0),
+ .CLKOUT2_DIVIDE(1),
+ .CLKOUT2_DUTY_CYCLE(0.5),
+ .CLKOUT2_PHASE(0),
+ .CLKOUT3_DIVIDE(1),
+ .CLKOUT3_DUTY_CYCLE(0.5),
+ .CLKOUT3_PHASE(0),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.5),
+ .CLKOUT4_PHASE(0),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.5),
+ .CLKOUT5_PHASE(0),
+ .CLKOUT6_DIVIDE(1),
+ .CLKOUT6_DUTY_CYCLE(0.5),
+ .CLKOUT6_PHASE(0),
+ .CLKFBOUT_MULT_F(64),
+ .CLKFBOUT_PHASE(0),
+ .DIVCLK_DIVIDE(11),
+ .REF_JITTER1(0.010),
+ .CLKIN1_PERIOD(6.206),
+ .STARTUP_WAIT("FALSE"),
+ .CLKOUT4_CASCADE("FALSE")
+)
+clk_mmcm_inst (
+ .CLKIN1(clk_161mhz_int),
+ .CLKFBIN(mmcm_clkfb),
+ .RST(mmcm_rst),
+ .PWRDWN(1'b0),
+ .CLKOUT0(clk_125mhz_mmcm_out),
+ .CLKOUT0B(),
+ .CLKOUT1(),
+ .CLKOUT1B(),
+ .CLKOUT2(),
+ .CLKOUT2B(),
+ .CLKOUT3(),
+ .CLKOUT3B(),
+ .CLKOUT4(),
+ .CLKOUT5(),
+ .CLKOUT6(),
+ .CLKFBOUT(mmcm_clkfb),
+ .CLKFBOUTB(),
+ .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_125mhz_bufg_inst (
+ .I(clk_125mhz_mmcm_out),
+ .O(clk_125mhz_int)
+);
+
+sync_reset #(
+ .N(4)
+)
+sync_reset_125mhz_inst (
+ .clk(clk_125mhz_int),
+ .rst(~mmcm_locked),
+ .sync_reset_out(rst_125mhz_int)
+);
+
+// GPIO
+wire sfp_i2c_scl_i;
+wire sfp_i2c_scl_o;
+wire sfp_i2c_scl_t;
+wire sfp_1_i2c_sda_i;
+wire sfp_1_i2c_sda_o;
+wire sfp_1_i2c_sda_t;
+wire sfp_2_i2c_sda_i;
+wire sfp_2_i2c_sda_o;
+wire sfp_2_i2c_sda_t;
+wire eeprom_i2c_scl_i;
+wire eeprom_i2c_scl_o;
+wire eeprom_i2c_scl_t;
+wire eeprom_i2c_sda_i;
+wire eeprom_i2c_sda_o;
+wire eeprom_i2c_sda_t;
+
+sync_signal #(
+ .WIDTH(5),
+ .N(2)
+)
+sync_signal_inst (
+ .clk(pcie_user_clk),
+ .in({sfp_i2c_scl, sfp_1_i2c_sda, sfp_2_i2c_sda,
+ eeprom_i2c_scl, eeprom_i2c_sda}),
+ .out({sfp_i2c_scl_i, sfp_1_i2c_sda_i, sfp_2_i2c_sda_i,
+ eeprom_i2c_scl_i, eeprom_i2c_sda_i})
+);
+
+assign sfp_i2c_scl = sfp_i2c_scl_t ? 1'bz : sfp_i2c_scl_o;
+assign sfp_1_i2c_sda = sfp_1_i2c_sda_t ? 1'bz : sfp_1_i2c_sda_o;
+assign sfp_2_i2c_sda = sfp_2_i2c_sda_t ? 1'bz : sfp_2_i2c_sda_o;
+assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
+assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
+
+// Flash
+wire [15:0] flash_dq_i_int;
+wire [15:0] flash_dq_o_int;
+wire flash_dq_oe_int;
+wire [22:0] flash_addr_int;
+wire flash_region_int;
+wire flash_region_oe_int;
+wire flash_ce_n_int;
+wire flash_oe_n_int;
+wire flash_we_n_int;
+wire flash_adv_n_int;
+
+assign flash_dq = flash_dq_oe_int ? flash_dq_o_int : 16'hzzzz;
+assign flash_addr = flash_addr_int;
+assign flash_region = flash_region_oe_int ? flash_region_int : 1'bz;
+assign flash_ce_n = flash_ce_n_int;
+assign flash_oe_n = flash_oe_n_int;
+assign flash_we_n = flash_we_n_int;
+assign flash_adv_n = flash_adv_n_int;
+
+sync_signal #(
+ .WIDTH(16),
+ .N(2)
+)
+flash_sync_signal_inst (
+ .clk(pcie_user_clk),
+ .in(flash_dq),
+ .out(flash_dq_i_int)
+);
+
+// PCIe
+wire pcie_sys_clk;
+wire pcie_sys_clk_gt;
+
+IBUFDS_GTE4 #(
+ .REFCLK_HROW_CK_SEL(2'b00)
+)
+ibufds_gte4_pcie_mgt_refclk_inst (
+ .I (pcie_refclk_p),
+ .IB (pcie_refclk_n),
+ .CEB (1'b0),
+ .O (pcie_sys_clk_gt),
+ .ODIV2 (pcie_sys_clk)
+);
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep;
+wire axis_rq_tlast;
+wire axis_rq_tready;
+wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
+wire axis_rq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep;
+wire axis_rc_tlast;
+wire axis_rc_tready;
+wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
+wire axis_rc_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep;
+wire axis_cq_tlast;
+wire axis_cq_tready;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
+wire axis_cq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep;
+wire axis_cc_tlast;
+wire axis_cc_tready;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
+wire axis_cc_tvalid;
+
+wire [3:0] pcie_tfc_nph_av;
+wire [3:0] pcie_tfc_npd_av;
+
+wire [2:0] cfg_max_payload;
+wire [2:0] cfg_max_read_req;
+
+wire [9:0] cfg_mgmt_addr;
+wire [7:0] cfg_mgmt_function_number;
+wire cfg_mgmt_write;
+wire [31:0] cfg_mgmt_write_data;
+wire [3:0] cfg_mgmt_byte_enable;
+wire cfg_mgmt_read;
+wire [31:0] cfg_mgmt_read_data;
+wire cfg_mgmt_read_write_done;
+
+wire [3:0] cfg_interrupt_msi_enable;
+wire [11:0] cfg_interrupt_msi_mmenable;
+wire cfg_interrupt_msi_mask_update;
+wire [31:0] cfg_interrupt_msi_data;
+wire [3:0] cfg_interrupt_msi_select;
+wire [31:0] cfg_interrupt_msi_int;
+wire [31:0] cfg_interrupt_msi_pending_status;
+wire cfg_interrupt_msi_pending_status_data_enable;
+wire [3:0] cfg_interrupt_msi_pending_status_function_num;
+wire cfg_interrupt_msi_sent;
+wire cfg_interrupt_msi_fail;
+wire [2:0] cfg_interrupt_msi_attr;
+wire cfg_interrupt_msi_tph_present;
+wire [1:0] cfg_interrupt_msi_tph_type;
+wire [8:0] cfg_interrupt_msi_tph_st_tag;
+wire [3:0] cfg_interrupt_msi_function_number;
+
+wire status_error_cor;
+wire status_error_uncor;
+
+// ila_0 ila_rq (
+// .clk(pcie_user_clk),
+// .trig_out(),
+// .trig_out_ack(1'b0),
+// .trig_in(1'b0),
+// .trig_in_ack(),
+// .probe0(axis_rq_tdata),
+// .probe1(axis_rq_tkeep),
+// .probe2(axis_rq_tvalid),
+// .probe3(axis_rq_tready),
+// .probe4({pcie_tfc_npd_av, pcie_tfc_nph_av, axis_rq_tuser}),
+// .probe5(axis_rq_tlast)
+// );
+
+// ila_0 ila_rc (
+// .clk(pcie_user_clk),
+// .trig_out(),
+// .trig_out_ack(1'b0),
+// .trig_in(1'b0),
+// .trig_in_ack(),
+// .probe0(axis_rc_tdata),
+// .probe1(axis_rc_tkeep),
+// .probe2(axis_rc_tvalid),
+// .probe3(axis_rc_tready),
+// .probe4(axis_rc_tuser),
+// .probe5(axis_rc_tlast)
+// );
+
+pcie4_uscale_plus_0
+pcie4_uscale_plus_inst (
+ .pci_exp_txn(pcie_tx_n),
+ .pci_exp_txp(pcie_tx_p),
+ .pci_exp_rxn(pcie_rx_n),
+ .pci_exp_rxp(pcie_rx_p),
+ .user_clk(pcie_user_clk),
+ .user_reset(pcie_user_reset),
+ .user_lnk_up(),
+
+ .s_axis_rq_tdata(axis_rq_tdata),
+ .s_axis_rq_tkeep(axis_rq_tkeep),
+ .s_axis_rq_tlast(axis_rq_tlast),
+ .s_axis_rq_tready(axis_rq_tready),
+ .s_axis_rq_tuser(axis_rq_tuser),
+ .s_axis_rq_tvalid(axis_rq_tvalid),
+
+ .m_axis_rc_tdata(axis_rc_tdata),
+ .m_axis_rc_tkeep(axis_rc_tkeep),
+ .m_axis_rc_tlast(axis_rc_tlast),
+ .m_axis_rc_tready(axis_rc_tready),
+ .m_axis_rc_tuser(axis_rc_tuser),
+ .m_axis_rc_tvalid(axis_rc_tvalid),
+
+ .m_axis_cq_tdata(axis_cq_tdata),
+ .m_axis_cq_tkeep(axis_cq_tkeep),
+ .m_axis_cq_tlast(axis_cq_tlast),
+ .m_axis_cq_tready(axis_cq_tready),
+ .m_axis_cq_tuser(axis_cq_tuser),
+ .m_axis_cq_tvalid(axis_cq_tvalid),
+
+ .s_axis_cc_tdata(axis_cc_tdata),
+ .s_axis_cc_tkeep(axis_cc_tkeep),
+ .s_axis_cc_tlast(axis_cc_tlast),
+ .s_axis_cc_tready(axis_cc_tready),
+ .s_axis_cc_tuser(axis_cc_tuser),
+ .s_axis_cc_tvalid(axis_cc_tvalid),
+
+ .pcie_rq_seq_num0(),
+ .pcie_rq_seq_num_vld0(),
+ .pcie_rq_seq_num1(),
+ .pcie_rq_seq_num_vld1(),
+ .pcie_rq_tag0(),
+ .pcie_rq_tag1(),
+ .pcie_rq_tag_av(),
+ .pcie_rq_tag_vld0(),
+ .pcie_rq_tag_vld1(),
+
+ .pcie_tfc_nph_av(pcie_tfc_nph_av),
+ .pcie_tfc_npd_av(pcie_tfc_npd_av),
+
+ .pcie_cq_np_req(1'b1),
+ .pcie_cq_np_req_count(),
+
+ .cfg_phy_link_down(),
+ .cfg_phy_link_status(),
+ .cfg_negotiated_width(),
+ .cfg_current_speed(),
+ .cfg_max_payload(cfg_max_payload),
+ .cfg_max_read_req(cfg_max_read_req),
+ .cfg_function_status(),
+ .cfg_function_power_state(),
+ .cfg_vf_status(),
+ .cfg_vf_power_state(),
+ .cfg_link_power_state(),
+
+ .cfg_mgmt_addr(cfg_mgmt_addr),
+ .cfg_mgmt_function_number(cfg_mgmt_function_number),
+ .cfg_mgmt_write(cfg_mgmt_write),
+ .cfg_mgmt_write_data(cfg_mgmt_write_data),
+ .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+ .cfg_mgmt_read(cfg_mgmt_read),
+ .cfg_mgmt_read_data(cfg_mgmt_read_data),
+ .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+ .cfg_mgmt_debug_access(1'b0),
+
+ .cfg_err_cor_out(),
+ .cfg_err_nonfatal_out(),
+ .cfg_err_fatal_out(),
+ .cfg_local_error_valid(),
+ .cfg_local_error_out(),
+ .cfg_ltssm_state(),
+ .cfg_rx_pm_state(),
+ .cfg_tx_pm_state(),
+ .cfg_rcb_status(),
+ .cfg_obff_enable(),
+ .cfg_pl_status_change(),
+ .cfg_tph_requester_enable(),
+ .cfg_tph_st_mode(),
+ .cfg_vf_tph_requester_enable(),
+ .cfg_vf_tph_st_mode(),
+
+ .cfg_msg_received(),
+ .cfg_msg_received_data(),
+ .cfg_msg_received_type(),
+ .cfg_msg_transmit(1'b0),
+ .cfg_msg_transmit_type(3'd0),
+ .cfg_msg_transmit_data(32'd0),
+ .cfg_msg_transmit_done(),
+
+ .cfg_fc_ph(),
+ .cfg_fc_pd(),
+ .cfg_fc_nph(),
+ .cfg_fc_npd(),
+ .cfg_fc_cplh(),
+ .cfg_fc_cpld(),
+ .cfg_fc_sel(3'd0),
+
+ .cfg_dsn(64'd0),
+
+ .cfg_power_state_change_ack(1'b1),
+ .cfg_power_state_change_interrupt(),
+
+ .cfg_err_cor_in(status_error_cor),
+ .cfg_err_uncor_in(status_error_uncor),
+ .cfg_flr_in_process(),
+ .cfg_flr_done(4'd0),
+ .cfg_vf_flr_in_process(),
+ .cfg_vf_flr_func_num(8'd0),
+ .cfg_vf_flr_done(8'd0),
+
+ .cfg_link_training_enable(1'b1),
+
+ .cfg_interrupt_int(4'd0),
+ .cfg_interrupt_pending(4'd0),
+ .cfg_interrupt_sent(),
+ .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+ .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+ .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+ .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+ .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+ .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+ .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+ .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+ .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+ .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+ .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+ .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+ .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+ .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+ .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+ .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+ .cfg_pm_aspm_l1_entry_reject(1'b0),
+ .cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
+
+ .cfg_hot_reset_out(),
+
+ .cfg_config_space_enable(1'b1),
+ .cfg_req_pm_transition_l23_ready(1'b0),
+ .cfg_hot_reset_in(1'b0),
+
+ .cfg_ds_port_number(8'd0),
+ .cfg_ds_bus_number(8'd0),
+ .cfg_ds_device_number(5'd0),
+ //.cfg_ds_function_number(3'd0),
+
+ //.cfg_subsys_vend_id(16'h1234),
+
+ .sys_clk(pcie_sys_clk),
+ .sys_clk_gt(pcie_sys_clk_gt),
+ .sys_reset(pcie_reset_n),
+
+ // .int_qpll0lock_out(),
+ // .int_qpll0outrefclk_out(),
+ // .int_qpll0outclk_out(),
+ // .int_qpll1lock_out(),
+ // .int_qpll1outrefclk_out(),
+ // .int_qpll1outclk_out(),
+ .phy_rdy_out()
+);
+
+// XGMII 10G PHY
+
+assign sfp_1_tx_disable = 1'b1;
+assign sfp_2_tx_disable = 1'b1;
+assign sfp_1_rs = 1'b0;
+assign sfp_2_rs = 1'b0;
+
+wire sfp_1_tx_clk_int;
+wire sfp_1_tx_rst_int;
+wire [63:0] sfp_1_txd_int;
+wire [7:0] sfp_1_txc_int;
+wire sfp_1_rx_clk_int;
+wire sfp_1_rx_rst_int;
+wire [63:0] sfp_1_rxd_int;
+wire [7:0] sfp_1_rxc_int;
+wire sfp_2_tx_clk_int;
+wire sfp_2_tx_rst_int;
+wire [63:0] sfp_2_txd_int;
+wire [7:0] sfp_2_txc_int;
+wire sfp_2_rx_clk_int;
+wire sfp_2_rx_rst_int;
+wire [63:0] sfp_2_rxd_int;
+wire [7:0] sfp_2_rxc_int;
+
+wire sfp_1_rx_block_lock;
+wire sfp_2_rx_block_lock;
+
+wire sfp_gtpowergood;
+
+wire sfp_mgt_refclk;
+wire sfp_mgt_refclk_int;
+wire sfp_mgt_refclk_bufg;
+
+assign clk_161mhz_int = sfp_mgt_refclk_bufg;
+
+wire [1:0] gt_txclkout;
+wire gt_txusrclk;
+
+wire [1:0] gt_rxclkout;
+wire [1:0] gt_rxusrclk;
+
+wire gt_reset_tx_done;
+wire gt_reset_rx_done;
+
+wire [1:0] gt_txprgdivresetdone;
+wire [1:0] gt_txpmaresetdone;
+wire [1:0] gt_rxprgdivresetdone;
+wire [1:0] gt_rxpmaresetdone;
+
+wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
+wire gt_rx_reset = ~>_rxpmaresetdone;
+
+reg gt_userclk_tx_active = 1'b0;
+reg [1:0] gt_userclk_rx_active = 1'b0;
+
+IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_inst (
+ .I (sfp_mgt_refclk_p),
+ .IB (sfp_mgt_refclk_n),
+ .CEB (1'b0),
+ .O (sfp_mgt_refclk),
+ .ODIV2 (sfp_mgt_refclk_int)
+);
+
+BUFG_GT bufg_gt_refclk_inst (
+ .CE (sfp_gtpowergood),
+ .CEMASK (1'b1),
+ .CLR (1'b0),
+ .CLRMASK (1'b1),
+ .DIV (3'b000),
+ .I (sfp_mgt_refclk_int),
+ .O (sfp_mgt_refclk_bufg)
+);
+
+BUFG_GT bufg_gt_tx_usrclk_inst (
+ .CE (1'b1),
+ .CEMASK (1'b0),
+ .CLR (gt_tx_reset),
+ .CLRMASK (1'b0),
+ .DIV (3'd0),
+ .I (gt_txclkout[0]),
+ .O (gt_txusrclk)
+);
+
+assign clk_156mhz_int = gt_txusrclk;
+
+always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
+ if (gt_tx_reset) begin
+ gt_userclk_tx_active <= 1'b0;
+ end else begin
+ gt_userclk_tx_active <= 1'b1;
+ end
+end
+
+generate
+
+genvar n;
+
+for (n = 0 ; n < 2; n = n + 1) begin
+
+ BUFG_GT bufg_gt_rx_usrclk_0_inst (
+ .CE (1'b1),
+ .CEMASK (1'b0),
+ .CLR (gt_rx_reset),
+ .CLRMASK (1'b0),
+ .DIV (3'd0),
+ .I (gt_rxclkout[n]),
+ .O (gt_rxusrclk[n])
+ );
+
+ always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
+ if (gt_rx_reset) begin
+ gt_userclk_rx_active[n] <= 1'b0;
+ end else begin
+ gt_userclk_rx_active[n] <= 1'b1;
+ end
+ end
+
+end
+
+endgenerate
+
+sync_reset #(
+ .N(4)
+)
+sync_reset_156mhz_inst (
+ .clk(clk_156mhz_int),
+ .rst(~gt_reset_tx_done),
+ .sync_reset_out(rst_156mhz_int)
+);
+
+wire [5:0] sfp_1_gt_txheader;
+wire [63:0] sfp_1_gt_txdata;
+wire sfp_1_gt_rxgearboxslip;
+wire [5:0] sfp_1_gt_rxheader;
+wire [1:0] sfp_1_gt_rxheadervalid;
+wire [63:0] sfp_1_gt_rxdata;
+wire [1:0] sfp_1_gt_rxdatavalid;
+
+wire [5:0] sfp_2_gt_txheader;
+wire [63:0] sfp_2_gt_txdata;
+wire sfp_2_gt_rxgearboxslip;
+wire [5:0] sfp_2_gt_rxheader;
+wire [1:0] sfp_2_gt_rxheadervalid;
+wire [63:0] sfp_2_gt_rxdata;
+wire [1:0] sfp_2_gt_rxdatavalid;
+
+gtwizard_ultrascale_0
+sfp_gty_inst (
+ .gtwiz_userclk_tx_active_in(>_userclk_tx_active),
+ .gtwiz_userclk_rx_active_in(>_userclk_rx_active),
+
+ .gtwiz_reset_clk_freerun_in(clk_125mhz_int),
+ .gtwiz_reset_all_in(rst_125mhz_int),
+
+ .gtwiz_reset_tx_pll_and_datapath_in(1'b0),
+ .gtwiz_reset_tx_datapath_in(1'b0),
+
+ .gtwiz_reset_rx_pll_and_datapath_in(1'b0),
+ .gtwiz_reset_rx_datapath_in(1'b0),
+
+ .gtwiz_reset_rx_cdr_stable_out(),
+
+ .gtwiz_reset_tx_done_out(gt_reset_tx_done),
+ .gtwiz_reset_rx_done_out(gt_reset_rx_done),
+
+ .gtrefclk00_in(sfp_mgt_refclk),
+
+ .qpll0outclk_out(),
+ .qpll0outrefclk_out(),
+
+ // .rxpmareset_in(2'd0),
+
+ .gtyrxn_in({sfp_2_rx_n, sfp_1_rx_n}),
+ .gtyrxp_in({sfp_2_rx_p, sfp_1_rx_p}),
+
+ .rxusrclk_in(gt_rxusrclk),
+ .rxusrclk2_in(gt_rxusrclk),
+
+ .gtwiz_userdata_tx_in({sfp_2_gt_txdata, sfp_1_gt_txdata}),
+ .txheader_in({sfp_2_gt_txheader, sfp_1_gt_txheader}),
+ .txsequence_in({2{7'b0}}),
+
+ .txusrclk_in({2{gt_txusrclk}}),
+ .txusrclk2_in({2{gt_txusrclk}}),
+
+ .gtpowergood_out(sfp_gtpowergood),
+
+ .gtytxn_out({sfp_2_tx_n, sfp_1_tx_n}),
+ .gtytxp_out({sfp_2_tx_p, sfp_1_tx_p}),
+
+ .txpolarity_in(2'b11),
+ .rxpolarity_in(2'b00),
+
+ .rxgearboxslip_in({sfp_2_gt_rxgearboxslip, sfp_1_gt_rxgearboxslip}),
+ .gtwiz_userdata_rx_out({sfp_2_gt_rxdata, sfp_1_gt_rxdata}),
+ .rxdatavalid_out({sfp_2_gt_rxdatavalid, sfp_1_gt_rxdatavalid}),
+ .rxheader_out({sfp_2_gt_rxheader, sfp_1_gt_rxheader}),
+ .rxheadervalid_out({sfp_2_gt_rxheadervalid, sfp_1_gt_rxheadervalid}),
+ .rxoutclk_out(gt_rxclkout),
+ .rxpmaresetdone_out(gt_rxpmaresetdone),
+ .rxprgdivresetdone_out(gt_rxprgdivresetdone),
+ .rxstartofseq_out(),
+
+ .txoutclk_out(gt_txclkout),
+ .txpmaresetdone_out(gt_txpmaresetdone),
+ .txprgdivresetdone_out(gt_txprgdivresetdone)
+);
+
+assign sfp_1_tx_clk_int = clk_156mhz_int;
+assign sfp_1_tx_rst_int = rst_156mhz_int;
+
+assign sfp_1_rx_clk_int = gt_rxusrclk[0];
+
+sync_reset #(
+ .N(4)
+)
+sfp_1_rx_rst_reset_sync_inst (
+ .clk(sfp_1_rx_clk_int),
+ .rst(~gt_reset_rx_done),
+ .sync_reset_out(sfp_1_rx_rst_int)
+);
+
+eth_phy_10g #(
+ .BIT_REVERSE(1)
+)
+sfp_1_phy_inst (
+ .tx_clk(sfp_1_tx_clk_int),
+ .tx_rst(sfp_1_tx_rst_int),
+ .rx_clk(sfp_1_rx_clk_int),
+ .rx_rst(sfp_1_rx_rst_int),
+ .xgmii_txd(sfp_1_txd_int),
+ .xgmii_txc(sfp_1_txc_int),
+ .xgmii_rxd(sfp_1_rxd_int),
+ .xgmii_rxc(sfp_1_rxc_int),
+ .serdes_tx_data(sfp_1_gt_txdata),
+ .serdes_tx_hdr(sfp_1_gt_txheader),
+ .serdes_rx_data(sfp_1_gt_rxdata),
+ .serdes_rx_hdr(sfp_1_gt_rxheader),
+ .serdes_rx_bitslip(sfp_1_gt_rxgearboxslip),
+ .rx_block_lock(sfp_1_rx_block_lock),
+ .rx_high_ber()
+);
+
+assign sfp_2_tx_clk_int = clk_156mhz_int;
+assign sfp_2_tx_rst_int = rst_156mhz_int;
+
+assign sfp_2_rx_clk_int = gt_rxusrclk[1];
+
+sync_reset #(
+ .N(4)
+)
+sfp_2_rx_rst_reset_sync_inst (
+ .clk(sfp_2_rx_clk_int),
+ .rst(~gt_reset_rx_done),
+ .sync_reset_out(sfp_2_rx_rst_int)
+);
+
+eth_phy_10g #(
+ .BIT_REVERSE(1)
+)
+sfp_2_phy_inst (
+ .tx_clk(sfp_2_tx_clk_int),
+ .tx_rst(sfp_2_tx_rst_int),
+ .rx_clk(sfp_2_rx_clk_int),
+ .rx_rst(sfp_2_rx_rst_int),
+ .xgmii_txd(sfp_2_txd_int),
+ .xgmii_txc(sfp_2_txc_int),
+ .xgmii_rxd(sfp_2_rxd_int),
+ .xgmii_rxc(sfp_2_rxc_int),
+ .serdes_tx_data(sfp_2_gt_txdata),
+ .serdes_tx_hdr(sfp_2_gt_txheader),
+ .serdes_rx_data(sfp_2_gt_rxdata),
+ .serdes_rx_hdr(sfp_2_gt_rxheader),
+ .serdes_rx_bitslip(sfp_2_gt_rxgearboxslip),
+ .rx_block_lock(sfp_2_rx_block_lock),
+ .rx_high_ber()
+);
+
+assign sfp_1_led[0] = sfp_1_rx_block_lock;
+assign sfp_1_led[1] = 1'b0;
+assign sfp_2_led[0] = sfp_2_rx_block_lock;
+assign sfp_2_led[1] = 1'b0;
+
+fpga_core #(
+ .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+ .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+ .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+ .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+ .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+ .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
+)
+core_inst (
+ /*
+ * Clock: 156.25 MHz, 250 MHz
+ * Synchronous reset
+ */
+ .clk_156mhz(clk_156mhz_int),
+ .rst_156mhz(rst_156mhz_int),
+ .clk_250mhz(pcie_user_clk),
+ .rst_250mhz(pcie_user_reset),
+
+ /*
+ * GPIO
+ */
+ //.sfp_1_led(sfp_1_led),
+ //.sfp_2_led(sfp_2_led),
+ .sma_led(sma_led),
+
+ .sma_in(sma_in),
+ .sma_out(sma_out),
+ .sma_out_en(sma_out_en),
+ .sma_term_en(sma_term_en),
+
+ /*
+ * PCIe
+ */
+ .m_axis_rq_tdata(axis_rq_tdata),
+ .m_axis_rq_tkeep(axis_rq_tkeep),
+ .m_axis_rq_tlast(axis_rq_tlast),
+ .m_axis_rq_tready(axis_rq_tready),
+ .m_axis_rq_tuser(axis_rq_tuser),
+ .m_axis_rq_tvalid(axis_rq_tvalid),
+
+ .s_axis_rc_tdata(axis_rc_tdata),
+ .s_axis_rc_tkeep(axis_rc_tkeep),
+ .s_axis_rc_tlast(axis_rc_tlast),
+ .s_axis_rc_tready(axis_rc_tready),
+ .s_axis_rc_tuser(axis_rc_tuser),
+ .s_axis_rc_tvalid(axis_rc_tvalid),
+
+ .s_axis_cq_tdata(axis_cq_tdata),
+ .s_axis_cq_tkeep(axis_cq_tkeep),
+ .s_axis_cq_tlast(axis_cq_tlast),
+ .s_axis_cq_tready(axis_cq_tready),
+ .s_axis_cq_tuser(axis_cq_tuser),
+ .s_axis_cq_tvalid(axis_cq_tvalid),
+
+ .m_axis_cc_tdata(axis_cc_tdata),
+ .m_axis_cc_tkeep(axis_cc_tkeep),
+ .m_axis_cc_tlast(axis_cc_tlast),
+ .m_axis_cc_tready(axis_cc_tready),
+ .m_axis_cc_tuser(axis_cc_tuser),
+ .m_axis_cc_tvalid(axis_cc_tvalid),
+
+ .pcie_tfc_nph_av(pcie_tfc_nph_av),
+ .pcie_tfc_npd_av(pcie_tfc_npd_av),
+
+ .cfg_max_payload(cfg_max_payload),
+ .cfg_max_read_req(cfg_max_read_req),
+
+ .cfg_mgmt_addr(cfg_mgmt_addr),
+ .cfg_mgmt_function_number(cfg_mgmt_function_number),
+ .cfg_mgmt_write(cfg_mgmt_write),
+ .cfg_mgmt_write_data(cfg_mgmt_write_data),
+ .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+ .cfg_mgmt_read(cfg_mgmt_read),
+ .cfg_mgmt_read_data(cfg_mgmt_read_data),
+ .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+ .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+ .cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
+ .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+ .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+ .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+ .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+ .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+ .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+ .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+ .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+ .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+ .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+ .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+ .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+ .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+ .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+ .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+ .status_error_cor(status_error_cor),
+ .status_error_uncor(status_error_uncor),
+
+ /*
+ * Ethernet: SFP+
+ */
+ .sfp_1_tx_clk(sfp_1_tx_clk_int),
+ .sfp_1_tx_rst(sfp_1_tx_rst_int),
+ .sfp_1_txd(sfp_1_txd_int),
+ .sfp_1_txc(sfp_1_txc_int),
+ .sfp_1_rx_clk(sfp_1_rx_clk_int),
+ .sfp_1_rx_rst(sfp_1_rx_rst_int),
+ .sfp_1_rxd(sfp_1_rxd_int),
+ .sfp_1_rxc(sfp_1_rxc_int),
+ .sfp_2_tx_clk(sfp_2_tx_clk_int),
+ .sfp_2_tx_rst(sfp_2_tx_rst_int),
+ .sfp_2_txd(sfp_2_txd_int),
+ .sfp_2_txc(sfp_2_txc_int),
+ .sfp_2_rx_clk(sfp_2_rx_clk_int),
+ .sfp_2_rx_rst(sfp_2_rx_rst_int),
+ .sfp_2_rxd(sfp_2_rxd_int),
+ .sfp_2_rxc(sfp_2_rxc_int),
+
+ .sfp_i2c_scl_i(sfp_i2c_scl_i),
+ .sfp_i2c_scl_o(sfp_i2c_scl_o),
+ .sfp_i2c_scl_t(sfp_i2c_scl_t),
+ .sfp_1_i2c_sda_i(sfp_1_i2c_sda_i),
+ .sfp_1_i2c_sda_o(sfp_1_i2c_sda_o),
+ .sfp_1_i2c_sda_t(sfp_1_i2c_sda_t),
+ .sfp_2_i2c_sda_i(sfp_2_i2c_sda_i),
+ .sfp_2_i2c_sda_o(sfp_2_i2c_sda_o),
+ .sfp_2_i2c_sda_t(sfp_2_i2c_sda_t),
+
+ .eeprom_i2c_scl_i(eeprom_i2c_scl_i),
+ .eeprom_i2c_scl_o(eeprom_i2c_scl_o),
+ .eeprom_i2c_scl_t(eeprom_i2c_scl_t),
+ .eeprom_i2c_sda_i(eeprom_i2c_sda_i),
+ .eeprom_i2c_sda_o(eeprom_i2c_sda_o),
+ .eeprom_i2c_sda_t(eeprom_i2c_sda_t),
+
+ /*
+ * BPI flash
+ */
+ .flash_dq_i(flash_dq_i_int),
+ .flash_dq_o(flash_dq_o_int),
+ .flash_dq_oe(flash_dq_oe_int),
+ .flash_addr(flash_addr_int),
+ .flash_region(flash_region_int),
+ .flash_region_oe(flash_region_oe_int),
+ .flash_ce_n(flash_ce_n_int),
+ .flash_oe_n(flash_oe_n_int),
+ .flash_we_n(flash_we_n_int),
+ .flash_adv_n(flash_adv_n_int)
+);
+
+endmodule
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v
new file mode 100644
index 000000000..d6ae01887
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v
@@ -0,0 +1,1798 @@
+/*
+
+Copyright 2019, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+ parameter TARGET = "XILINX",
+ parameter AXIS_PCIE_DATA_WIDTH = 256,
+ parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
+ parameter AXIS_PCIE_RC_USER_WIDTH = 75,
+ parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
+ parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
+ parameter AXIS_PCIE_CC_USER_WIDTH = 33
+)
+(
+ /*
+ * Clock: 156.25 MHz, 250 MHz
+ * Synchronous reset
+ */
+ input wire clk_156mhz,
+ input wire rst_156mhz,
+ input wire clk_250mhz,
+ input wire rst_250mhz,
+
+ /*
+ * GPIO
+ */
+ output wire [1:0] sfp_1_led,
+ output wire [1:0] sfp_2_led,
+ output wire [1:0] sma_led,
+
+ input wire sma_in,
+ output wire sma_out,
+ output wire sma_out_en,
+ output wire sma_term_en,
+
+ /*
+ * PCIe
+ */
+ output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
+ output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
+ output wire m_axis_rq_tlast,
+ input wire m_axis_rq_tready,
+ output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
+ output wire m_axis_rq_tvalid,
+
+ input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
+ input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
+ input wire s_axis_rc_tlast,
+ output wire s_axis_rc_tready,
+ input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
+ input wire s_axis_rc_tvalid,
+
+ input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
+ input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
+ input wire s_axis_cq_tlast,
+ output wire s_axis_cq_tready,
+ input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
+ input wire s_axis_cq_tvalid,
+
+ output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
+ output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
+ output wire m_axis_cc_tlast,
+ input wire m_axis_cc_tready,
+ output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
+ output wire m_axis_cc_tvalid,
+
+ input wire [1:0] pcie_tfc_nph_av,
+ input wire [1:0] pcie_tfc_npd_av,
+
+ input wire [2:0] cfg_max_payload,
+ input wire [2:0] cfg_max_read_req,
+
+ output wire [9:0] cfg_mgmt_addr,
+ output wire [7:0] cfg_mgmt_function_number,
+ output wire cfg_mgmt_write,
+ output wire [31:0] cfg_mgmt_write_data,
+ output wire [3:0] cfg_mgmt_byte_enable,
+ output wire cfg_mgmt_read,
+ input wire [31:0] cfg_mgmt_read_data,
+ input wire cfg_mgmt_read_write_done,
+
+ input wire [3:0] cfg_interrupt_msi_enable,
+ input wire [7:0] cfg_interrupt_msi_vf_enable,
+ input wire [11:0] cfg_interrupt_msi_mmenable,
+ input wire cfg_interrupt_msi_mask_update,
+ input wire [31:0] cfg_interrupt_msi_data,
+ output wire [3:0] cfg_interrupt_msi_select,
+ output wire [31:0] cfg_interrupt_msi_int,
+ output wire [31:0] cfg_interrupt_msi_pending_status,
+ output wire cfg_interrupt_msi_pending_status_data_enable,
+ output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
+ input wire cfg_interrupt_msi_sent,
+ input wire cfg_interrupt_msi_fail,
+ output wire [2:0] cfg_interrupt_msi_attr,
+ output wire cfg_interrupt_msi_tph_present,
+ output wire [1:0] cfg_interrupt_msi_tph_type,
+ output wire [8:0] cfg_interrupt_msi_tph_st_tag,
+ output wire [3:0] cfg_interrupt_msi_function_number,
+
+ output wire status_error_cor,
+ output wire status_error_uncor,
+
+ /*
+ * Ethernet: SFP+
+ */
+ input wire sfp_1_tx_clk,
+ input wire sfp_1_tx_rst,
+ output wire [63:0] sfp_1_txd,
+ output wire [7:0] sfp_1_txc,
+ input wire sfp_1_rx_clk,
+ input wire sfp_1_rx_rst,
+ input wire [63:0] sfp_1_rxd,
+ input wire [7:0] sfp_1_rxc,
+ input wire sfp_2_tx_clk,
+ input wire sfp_2_tx_rst,
+ output wire [63:0] sfp_2_txd,
+ output wire [7:0] sfp_2_txc,
+ input wire sfp_2_rx_clk,
+ input wire sfp_2_rx_rst,
+ input wire [63:0] sfp_2_rxd,
+ input wire [7:0] sfp_2_rxc,
+
+ input wire sfp_i2c_scl_i,
+ output wire sfp_i2c_scl_o,
+ output wire sfp_i2c_scl_t,
+ input wire sfp_1_i2c_sda_i,
+ output wire sfp_1_i2c_sda_o,
+ output wire sfp_1_i2c_sda_t,
+ input wire sfp_2_i2c_sda_i,
+ output wire sfp_2_i2c_sda_o,
+ output wire sfp_2_i2c_sda_t,
+
+ input wire eeprom_i2c_scl_i,
+ output wire eeprom_i2c_scl_o,
+ output wire eeprom_i2c_scl_t,
+ input wire eeprom_i2c_sda_i,
+ output wire eeprom_i2c_sda_o,
+ output wire eeprom_i2c_sda_t,
+
+ /*
+ * BPI Flash
+ */
+ input wire [15:0] flash_dq_i,
+ output wire [15:0] flash_dq_o,
+ output wire flash_dq_oe,
+ output wire [22:0] flash_addr,
+ output wire flash_region,
+ output wire flash_region_oe,
+ output wire flash_ce_n,
+ output wire flash_oe_n,
+ output wire flash_we_n,
+ output wire flash_adv_n
+);
+
+parameter PCIE_ADDR_WIDTH = 64;
+
+// AXI lite interface parameters
+parameter AXIL_DATA_WIDTH = 32;
+parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
+parameter AXIL_ADDR_WIDTH = 24;
+
+// AXI stream interface parameters
+parameter AXIS_DATA_WIDTH = 256;
+parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8;
+
+// PCIe DMA parameters
+parameter PCIE_DMA_LEN_WIDTH = 16;
+parameter PCIE_DMA_TAG_WIDTH = 16;
+
+// PHC parameters
+parameter PTP_PERIOD_NS_WIDTH = 4;
+parameter PTP_OFFSET_NS_WIDTH = 32;
+parameter PTP_FNS_WIDTH = 32;
+parameter PTP_PERIOD_NS = 4'd4;
+parameter PTP_PERIOD_FNS = 32'd0;
+
+// FW and board IDs
+parameter FW_ID = 32'd0;
+parameter FW_VER = {16'd0, 16'd1};
+parameter BOARD_ID = {16'h1ce4, 16'h0009};
+parameter BOARD_VER = {16'd0, 16'd1};
+
+// Structural parameters
+parameter IF_COUNT = 2;
+parameter PORTS_PER_IF = 1;
+
+parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
+
+// Queue manager parameters (interface)
+parameter EVENT_QUEUE_OP_TABLE_SIZE = 32;
+parameter TX_QUEUE_OP_TABLE_SIZE = 32;
+parameter RX_QUEUE_OP_TABLE_SIZE = 32;
+parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 32;
+parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 32;
+parameter TX_QUEUE_INDEX_WIDTH = 8;
+parameter RX_QUEUE_INDEX_WIDTH = 8;
+parameter TX_CPL_QUEUE_INDEX_WIDTH = 8;
+parameter RX_CPL_QUEUE_INDEX_WIDTH = 8;
+
+// TX and RX engine parameters (port)
+parameter TX_DESC_TABLE_SIZE = 32;
+parameter TX_PKT_TABLE_SIZE = 8;
+parameter RX_DESC_TABLE_SIZE = 32;
+parameter RX_PKT_TABLE_SIZE = 8;
+
+// Scheduler parameters (port)
+parameter TX_SCHEDULER = "RR";
+parameter TX_SCHEDULER_OP_TABLE_SIZE = 32;
+parameter TDMA_INDEX_WIDTH = 6;
+
+// Timstamping parameters (port)
+parameter LOGIC_PTP_PERIOD_NS = 6'h4;
+parameter LOGIC_PTP_PERIOD_FNS = 16'h0000;
+parameter IF_PTP_PERIOD_NS = 6'h6;
+parameter IF_PTP_PERIOD_FNS = 16'h6666;
+parameter PTP_TS_ENABLE = 1;
+parameter PTP_TS_WIDTH = 96;
+parameter TX_PTP_TS_FIFO_DEPTH = 32;
+parameter RX_PTP_TS_FIFO_DEPTH = 32;
+
+// Interface parameters (port)
+parameter TX_CHECKSUM_ENABLE = 1;
+parameter RX_CHECKSUM_ENABLE = 1;
+parameter ENABLE_PADDING = 1;
+parameter ENABLE_DIC = 1;
+parameter MIN_FRAME_LENGTH = 64;
+parameter TX_FIFO_DEPTH = 16384;
+parameter RX_FIFO_DEPTH = 16384;
+parameter MAX_TX_SIZE = 2048;
+parameter MAX_RX_SIZE = 2048;
+
+// PCIe DMA parameters
+parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
+parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
+parameter SEG_ADDR_WIDTH = 12;
+parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
+parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+$clog2(PORTS_PER_IF+1);
+parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
+parameter RAM_PIPELINE = 4;
+
+parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE;
+parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE;
+
+// AXI lite connections
+wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr;
+wire [2:0] axil_pcie_awprot;
+wire axil_pcie_awvalid;
+wire axil_pcie_awready;
+wire [AXIL_DATA_WIDTH-1:0] axil_pcie_wdata;
+wire [AXIL_STRB_WIDTH-1:0] axil_pcie_wstrb;
+wire axil_pcie_wvalid;
+wire axil_pcie_wready;
+wire [1:0] axil_pcie_bresp;
+wire axil_pcie_bvalid;
+wire axil_pcie_bready;
+wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_araddr;
+wire [2:0] axil_pcie_arprot;
+wire axil_pcie_arvalid;
+wire axil_pcie_arready;
+wire [AXIL_DATA_WIDTH-1:0] axil_pcie_rdata;
+wire [1:0] axil_pcie_rresp;
+wire axil_pcie_rvalid;
+wire axil_pcie_rready;
+
+wire [AXIL_ADDR_WIDTH-1:0] axil_csr_awaddr;
+wire [2:0] axil_csr_awprot;
+wire axil_csr_awvalid;
+wire axil_csr_awready;
+wire [AXIL_DATA_WIDTH-1:0] axil_csr_wdata;
+wire [AXIL_STRB_WIDTH-1:0] axil_csr_wstrb;
+wire axil_csr_wvalid;
+wire axil_csr_wready;
+wire [1:0] axil_csr_bresp;
+wire axil_csr_bvalid;
+wire axil_csr_bready;
+wire [AXIL_ADDR_WIDTH-1:0] axil_csr_araddr;
+wire [2:0] axil_csr_arprot;
+wire axil_csr_arvalid;
+wire axil_csr_arready;
+wire [AXIL_DATA_WIDTH-1:0] axil_csr_rdata;
+wire [1:0] axil_csr_rresp;
+wire axil_csr_rvalid;
+wire axil_csr_rready;
+
+// DMA connections
+wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
+wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
+wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
+wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
+wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
+wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
+wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
+wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
+wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
+wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
+wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
+wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid;
+wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready;
+
+// Error handling
+wire [1:0] status_error_uncor_int;
+wire [1:0] status_error_cor_int;
+
+wire [31:0] msi_irq;
+
+wire ext_tag_enable;
+
+// PCIe DMA control
+wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
+wire [RAM_SEL_WIDTH-1:0] pcie_dma_read_desc_ram_sel;
+wire [RAM_ADDR_WIDTH-1:0] pcie_dma_read_desc_ram_addr;
+wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_read_desc_len;
+wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag;
+wire pcie_dma_read_desc_valid;
+wire pcie_dma_read_desc_ready;
+
+wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag;
+wire pcie_dma_read_desc_status_valid;
+
+wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
+wire [RAM_SEL_WIDTH-1:0] pcie_dma_write_desc_ram_sel;
+wire [RAM_ADDR_WIDTH-1:0] pcie_dma_write_desc_ram_addr;
+wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_dma_write_desc_len;
+wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag;
+wire pcie_dma_write_desc_valid;
+wire pcie_dma_write_desc_ready;
+
+wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag;
+wire pcie_dma_write_desc_status_valid;
+
+wire pcie_dma_enable = 1;
+
+wire [95:0] ptp_ts_96;
+wire ptp_ts_step;
+wire ptp_pps;
+
+reg ptp_perout_enable_reg = 1'b0;
+wire ptp_perout_locked;
+wire ptp_perout_error;
+wire ptp_perout_pulse;
+
+// control registers
+reg axil_csr_awready_reg = 1'b0;
+reg axil_csr_wready_reg = 1'b0;
+reg axil_csr_bvalid_reg = 1'b0;
+reg axil_csr_arready_reg = 1'b0;
+reg [AXIL_DATA_WIDTH-1:0] axil_csr_rdata_reg = {AXIL_DATA_WIDTH{1'b0}};
+reg axil_csr_rvalid_reg = 1'b0;
+
+// reg sfp_0_sel_l_reg = 1'b1;
+// reg sfp_1_sel_l_reg = 1'b1;
+
+// reg sfp_reset_l_reg = 1'b1;
+
+reg sfp_i2c_scl_o_reg = 1'b1;
+reg sfp_1_i2c_sda_o_reg = 1'b1;
+reg sfp_2_i2c_sda_o_reg = 1'b1;
+
+reg eeprom_i2c_scl_o_reg = 1'b1;
+reg eeprom_i2c_sda_o_reg = 1'b1;
+
+reg [15:0] flash_dq_o_reg = 16'd0;
+reg flash_dq_oe_reg = 1'b0;
+reg [22:0] flash_addr_reg = 23'd0;
+reg flash_region_reg = 1'b0;
+reg flash_region_oe_reg = 1'b0;
+reg flash_ce_n_reg = 1'b1;
+reg flash_oe_n_reg = 1'b1;
+reg flash_we_n_reg = 1'b1;
+reg flash_adv_n_reg = 1'b1;
+
+reg pcie_dma_enable_reg = 0;
+
+reg [95:0] get_ptp_ts_96_reg = 0;
+reg [95:0] set_ptp_ts_96_reg = 0;
+reg set_ptp_ts_96_valid_reg = 0;
+reg [PTP_PERIOD_NS_WIDTH-1:0] set_ptp_period_ns_reg = 0;
+reg [PTP_FNS_WIDTH-1:0] set_ptp_period_fns_reg = 0;
+reg set_ptp_period_valid_reg = 0;
+reg [PTP_OFFSET_NS_WIDTH-1:0] set_ptp_offset_ns_reg = 0;
+reg [PTP_FNS_WIDTH-1:0] set_ptp_offset_fns_reg = 0;
+reg [15:0] set_ptp_offset_count_reg = 0;
+reg set_ptp_offset_valid_reg = 0;
+wire set_ptp_offset_active;
+
+reg [95:0] set_ptp_perout_start_ts_96_reg = 0;
+reg set_ptp_perout_start_ts_96_valid_reg = 0;
+reg [95:0] set_ptp_perout_period_ts_96_reg = 0;
+reg set_ptp_perout_period_ts_96_valid_reg = 0;
+reg [95:0] set_ptp_perout_width_ts_96_reg = 0;
+reg set_ptp_perout_width_ts_96_valid_reg = 0;
+
+assign axil_csr_awready = axil_csr_awready_reg;
+assign axil_csr_wready = axil_csr_wready_reg;
+assign axil_csr_bresp = 2'b00;
+assign axil_csr_bvalid = axil_csr_bvalid_reg;
+assign axil_csr_arready = axil_csr_arready_reg;
+assign axil_csr_rdata = axil_csr_rdata_reg;
+assign axil_csr_rresp = 2'b00;
+assign axil_csr_rvalid = axil_csr_rvalid_reg;
+
+// assign sfp_0_sel_l = sfp_0_sel_l_reg;
+// assign sfp_1_sel_l = sfp_1_sel_l_reg;
+
+// assign sfp_reset_l = sfp_reset_l_reg;
+
+assign sfp_i2c_scl_o = sfp_i2c_scl_o_reg;
+assign sfp_i2c_scl_t = sfp_i2c_scl_o_reg;
+assign sfp_1_i2c_sda_o = sfp_1_i2c_sda_o_reg;
+assign sfp_1_i2c_sda_t = sfp_1_i2c_sda_o_reg;
+assign sfp_2_i2c_sda_o = sfp_2_i2c_sda_o_reg;
+assign sfp_2_i2c_sda_t = sfp_2_i2c_sda_o_reg;
+
+assign eeprom_i2c_scl_o = eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_scl_t = eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_sda_o = eeprom_i2c_sda_o_reg;
+assign eeprom_i2c_sda_t = eeprom_i2c_sda_o_reg;
+
+assign flash_dq_o = flash_dq_o_reg;
+assign flash_dq_oe = flash_dq_oe_reg;
+assign flash_addr = flash_addr_reg;
+assign flash_region = flash_region_reg;
+assign flash_region_oe = flash_region_oe_reg;
+assign flash_ce_n = flash_ce_n_reg;
+assign flash_oe_n = flash_oe_n_reg;
+assign flash_we_n = flash_we_n_reg;
+assign flash_adv_n = flash_adv_n_reg;
+
+//assign pcie_dma_enable = pcie_dma_enable_reg;
+
+always @(posedge clk_250mhz) begin
+ axil_csr_awready_reg <= 1'b0;
+ axil_csr_wready_reg <= 1'b0;
+ axil_csr_bvalid_reg <= axil_csr_bvalid_reg && !axil_csr_bready;
+ axil_csr_arready_reg <= 1'b0;
+ axil_csr_rvalid_reg <= axil_csr_rvalid_reg && !axil_csr_rready;
+
+ pcie_dma_enable_reg <= pcie_dma_enable_reg;
+
+ set_ptp_ts_96_valid_reg <= 1'b0;
+ set_ptp_period_valid_reg <= 1'b0;
+ set_ptp_offset_valid_reg <= 1'b0;
+
+ set_ptp_perout_start_ts_96_valid_reg <= 1'b0;
+ set_ptp_perout_period_ts_96_valid_reg <= 1'b0;
+ set_ptp_perout_width_ts_96_valid_reg <= 1'b0;
+
+ if (axil_csr_awvalid && axil_csr_wvalid && !axil_csr_bvalid) begin
+ // write operation
+ axil_csr_awready_reg <= 1'b1;
+ axil_csr_wready_reg <= 1'b1;
+ axil_csr_bvalid_reg <= 1'b1;
+
+ case ({axil_csr_awaddr[15:2], 2'b00})
+ // GPIO
+ 16'h0100: begin
+ // GPIO out
+ // if (axil_csr_wstrb[1]) begin
+ // sfp_0_sel_l_reg <= axil_csr_wdata[9];
+ // sfp_1_sel_l_reg <= axil_csr_wdata[11];
+ // end
+ // if (axil_csr_wstrb[0]) begin
+ // sfp_reset_l_reg <= axil_csr_wdata[0];
+ // end
+ if (axil_csr_wstrb[2]) begin
+ sfp_i2c_scl_o_reg <= axil_csr_wdata[16];
+ sfp_1_i2c_sda_o_reg <= axil_csr_wdata[17];
+ sfp_2_i2c_sda_o_reg <= axil_csr_wdata[18];
+ end
+ if (axil_csr_wstrb[3]) begin
+ eeprom_i2c_scl_o_reg <= axil_csr_wdata[24];
+ eeprom_i2c_sda_o_reg <= axil_csr_wdata[25];
+ end
+ end
+ // Flash
+ 16'h0144: begin
+ // Flash address
+ flash_addr_reg <= axil_csr_wdata[22:0];
+ flash_region_reg <= axil_csr_wdata[23];
+ end
+ 16'h0148: flash_dq_o_reg <= axil_csr_wdata; // Flash data
+ 16'h014C: begin
+ // Flash control
+ if (axil_csr_wstrb[0]) begin
+ flash_ce_n_reg <= axil_csr_wdata[0];
+ flash_oe_n_reg <= axil_csr_wdata[1];
+ flash_we_n_reg <= axil_csr_wdata[2];
+ flash_adv_n_reg <= axil_csr_wdata[3];
+ end
+ if (axil_csr_wstrb[1]) begin
+ flash_dq_oe_reg <= axil_csr_wdata[8];
+ end
+ if (axil_csr_wstrb[2]) begin
+ flash_region_oe_reg <= axil_csr_wdata[16];
+ end
+ end
+ // PHC
+ 16'h0230: set_ptp_ts_96_reg[15:0] <= axil_csr_wdata; // PTP set fns
+ 16'h0234: set_ptp_ts_96_reg[45:16] <= axil_csr_wdata;// PTP set ns
+ 16'h0238: set_ptp_ts_96_reg[79:48] <= axil_csr_wdata;// PTP set sec l
+ 16'h023C: begin
+ // PTP set sec h
+ set_ptp_ts_96_reg[95:80] <= axil_csr_wdata;
+ set_ptp_ts_96_valid_reg <= 1'b1;
+ end
+ 16'h0240: set_ptp_period_fns_reg <= axil_csr_wdata;// PTP period fns
+ 16'h0244: begin
+ // PTP period ns
+ set_ptp_period_ns_reg <= axil_csr_wdata;
+ set_ptp_period_valid_reg <= 1'b1;
+ end
+ 16'h0250: set_ptp_offset_fns_reg <= axil_csr_wdata;// PTP offset fns
+ 16'h0254: set_ptp_offset_ns_reg <= axil_csr_wdata; // PTP offset ns
+ 16'h0258: begin
+ // PTP offset count
+ set_ptp_offset_count_reg <= axil_csr_wdata;
+ set_ptp_offset_valid_reg <= 1'b1;
+ end
+ 16'h0260: begin
+ // PTP perout control
+ ptp_perout_enable_reg <= axil_csr_wdata[0];
+ end
+ 16'h0270: set_ptp_perout_start_ts_96_reg[15:0] <= axil_csr_wdata; // PTP perout start fns
+ 16'h0274: set_ptp_perout_start_ts_96_reg[45:16] <= axil_csr_wdata; // PTP perout start ns
+ 16'h0278: set_ptp_perout_start_ts_96_reg[79:48] <= axil_csr_wdata; // PTP perout start sec l
+ 16'h027C: begin
+ // PTP perout start sec h
+ set_ptp_perout_start_ts_96_reg[95:80] <= axil_csr_wdata;
+ set_ptp_perout_start_ts_96_valid_reg <= 1'b1;
+ end
+ 16'h0280: set_ptp_perout_period_ts_96_reg[15:0] <= axil_csr_wdata; // PTP perout period fns
+ 16'h0284: set_ptp_perout_period_ts_96_reg[45:16] <= axil_csr_wdata; // PTP perout period ns
+ 16'h0288: set_ptp_perout_period_ts_96_reg[79:48] <= axil_csr_wdata; // PTP perout period sec l
+ 16'h028C: begin
+ // PTP perout period sec h
+ set_ptp_perout_period_ts_96_reg[95:80] <= axil_csr_wdata;
+ set_ptp_perout_period_ts_96_valid_reg <= 1'b1;
+ end
+ 16'h0290: set_ptp_perout_width_ts_96_reg[15:0] <= axil_csr_wdata; // PTP perout width fns
+ 16'h0294: set_ptp_perout_width_ts_96_reg[45:16] <= axil_csr_wdata; // PTP perout width ns
+ 16'h0298: set_ptp_perout_width_ts_96_reg[79:48] <= axil_csr_wdata; // PTP perout width sec l
+ 16'h029C: begin
+ // PTP perout width sec h
+ set_ptp_perout_width_ts_96_reg[95:80] <= axil_csr_wdata;
+ set_ptp_perout_width_ts_96_valid_reg <= 1'b1;
+ end
+ endcase
+ end
+
+ if (axil_csr_arvalid && !axil_csr_rvalid) begin
+ // read operation
+ axil_csr_arready_reg <= 1'b1;
+ axil_csr_rvalid_reg <= 1'b1;
+ axil_csr_rdata_reg <= {AXIL_DATA_WIDTH{1'b0}};
+
+ case ({axil_csr_araddr[15:2], 2'b00})
+ 16'h0000: axil_csr_rdata_reg <= FW_ID; // fw_id
+ 16'h0004: axil_csr_rdata_reg <= FW_VER; // fw_ver
+ 16'h0008: axil_csr_rdata_reg <= BOARD_ID; // board_id
+ 16'h000C: axil_csr_rdata_reg <= BOARD_VER; // board_ver
+ 16'h0010: axil_csr_rdata_reg <= 1; // phc_count
+ 16'h0014: axil_csr_rdata_reg <= 16'h0200; // phc_offset
+ 16'h0018: axil_csr_rdata_reg <= 16'h0080; // phc_stride
+ 16'h0020: axil_csr_rdata_reg <= IF_COUNT; // if_count
+ 16'h0024: axil_csr_rdata_reg <= 24'h800000; // if_stride
+ 16'h002C: axil_csr_rdata_reg <= 24'h040000; // if_csr_offset
+ // GPIO
+ 16'h0100: begin
+ // GPIO out
+ // axil_csr_rdata_reg[9] <= sfp_0_sel_l_reg;
+ // axil_csr_rdata_reg[11] <= sfp_1_sel_l_reg;
+ // axil_csr_rdata_reg[0] <= sfp_reset_l_reg;
+ axil_csr_rdata_reg[16] <= sfp_i2c_scl_o_reg;
+ axil_csr_rdata_reg[17] <= sfp_1_i2c_sda_o_reg;
+ axil_csr_rdata_reg[18] <= sfp_2_i2c_sda_o_reg;
+ axil_csr_rdata_reg[24] <= eeprom_i2c_scl_o_reg;
+ axil_csr_rdata_reg[25] <= eeprom_i2c_sda_o_reg;
+ end
+ 16'h0104: begin
+ // GPIO in
+ // axil_csr_rdata_reg[8] <= sfp_0_modprs_l;
+ // axil_csr_rdata_reg[9] <= sfp_0_sel_l;
+ // axil_csr_rdata_reg[10] <= sfp_1_modprs_l;
+ // axil_csr_rdata_reg[11] <= sfp_1_sel_l;
+ // axil_csr_rdata_reg[0] <= sfp_reset_l;
+ // axil_csr_rdata_reg[1] <= sfp_int_l;
+ axil_csr_rdata_reg[16] <= sfp_i2c_scl_i;
+ axil_csr_rdata_reg[17] <= sfp_1_i2c_sda_i;
+ axil_csr_rdata_reg[18] <= sfp_2_i2c_sda_i;
+ axil_csr_rdata_reg[24] <= eeprom_i2c_scl_i;
+ axil_csr_rdata_reg[25] <= eeprom_i2c_sda_i;
+ end
+ // Flash
+ 16'h0140: axil_csr_rdata_reg <= 32'd0; // Flash ID
+ 16'h0144: begin
+ // Flash address
+ axil_csr_rdata_reg[22:0] <= flash_addr_reg;
+ axil_csr_rdata_reg[23] <= flash_region_reg;
+ end
+ 16'h0148: axil_csr_rdata_reg <= flash_dq_i; // Flash data
+ 16'h014C: begin
+ // Flash control
+ axil_csr_rdata_reg[0] <= flash_ce_n_reg; // chip enable (inverted)
+ axil_csr_rdata_reg[1] <= flash_oe_n_reg; // output enable (inverted)
+ axil_csr_rdata_reg[2] <= flash_we_n_reg; // write enable (inverted)
+ axil_csr_rdata_reg[3] <= flash_adv_n_reg; // address valid (inverted)
+ axil_csr_rdata_reg[8] <= flash_dq_oe_reg; // data output enable
+ axil_csr_rdata_reg[16] <= flash_region_oe_reg; // region output enable (addr bit 23)
+ end
+ // PHC
+ 16'h0200: axil_csr_rdata_reg <= {8'd0, 8'd0, 8'd0, 8'd1}; // PHC features
+ 16'h0210: axil_csr_rdata_reg <= ptp_ts_96[15:0]; // PTP cur fns
+ 16'h0214: axil_csr_rdata_reg <= ptp_ts_96[45:16]; // PTP cur ns
+ 16'h0218: axil_csr_rdata_reg <= ptp_ts_96[79:48]; // PTP cur sec l
+ 16'h021C: axil_csr_rdata_reg <= ptp_ts_96[95:80]; // PTP cur sec h
+ 16'h0220: begin
+ // PTP get fns
+ get_ptp_ts_96_reg <= ptp_ts_96;
+ axil_csr_rdata_reg <= ptp_ts_96[15:0];
+ end
+ 16'h0224: axil_csr_rdata_reg <= get_ptp_ts_96_reg[45:16]; // PTP get ns
+ 16'h0228: axil_csr_rdata_reg <= get_ptp_ts_96_reg[79:48]; // PTP get sec l
+ 16'h022C: axil_csr_rdata_reg <= get_ptp_ts_96_reg[95:80]; // PTP get sec h
+ 16'h0230: axil_csr_rdata_reg <= set_ptp_ts_96_reg[15:0]; // PTP set fns
+ 16'h0234: axil_csr_rdata_reg <= set_ptp_ts_96_reg[45:16]; // PTP set ns
+ 16'h0238: axil_csr_rdata_reg <= set_ptp_ts_96_reg[79:48]; // PTP set sec l
+ 16'h023C: axil_csr_rdata_reg <= set_ptp_ts_96_reg[95:80]; // PTP set sec h
+ 16'h0240: axil_csr_rdata_reg <= set_ptp_period_fns_reg; // PTP period fns
+ 16'h0244: axil_csr_rdata_reg <= set_ptp_period_ns_reg; // PTP period ns
+ 16'h0248: axil_csr_rdata_reg <= PTP_PERIOD_FNS; // PTP nom period fns
+ 16'h024C: axil_csr_rdata_reg <= PTP_PERIOD_NS; // PTP nom period ns
+ 16'h0250: axil_csr_rdata_reg <= set_ptp_offset_fns_reg; // PTP offset fns
+ 16'h0254: axil_csr_rdata_reg <= set_ptp_offset_ns_reg; // PTP offset ns
+ 16'h0258: axil_csr_rdata_reg <= set_ptp_offset_count_reg; // PTP offset count
+ 16'h025C: axil_csr_rdata_reg <= set_ptp_offset_active; // PTP offset status
+ 16'h0260: begin
+ // PTP perout control
+ axil_csr_rdata_reg[0] <= ptp_perout_enable_reg;
+ end
+ 16'h0264: begin
+ // PTP perout status
+ axil_csr_rdata_reg[0] <= ptp_perout_locked;
+ axil_csr_rdata_reg[1] <= ptp_perout_error;
+ end
+ 16'h0270: axil_csr_rdata_reg <= set_ptp_perout_start_ts_96_reg[15:0]; // PTP perout start fns
+ 16'h0274: axil_csr_rdata_reg <= set_ptp_perout_start_ts_96_reg[45:16]; // PTP perout start ns
+ 16'h0278: axil_csr_rdata_reg <= set_ptp_perout_start_ts_96_reg[79:48]; // PTP perout start sec l
+ 16'h027C: axil_csr_rdata_reg <= set_ptp_perout_start_ts_96_reg[95:80]; // PTP perout start sec h
+ 16'h0280: axil_csr_rdata_reg <= set_ptp_perout_period_ts_96_reg[15:0]; // PTP perout period fns
+ 16'h0284: axil_csr_rdata_reg <= set_ptp_perout_period_ts_96_reg[45:16]; // PTP perout period ns
+ 16'h0288: axil_csr_rdata_reg <= set_ptp_perout_period_ts_96_reg[79:48]; // PTP perout period sec l
+ 16'h028C: axil_csr_rdata_reg <= set_ptp_perout_period_ts_96_reg[95:80]; // PTP perout period sec h
+ 16'h0290: axil_csr_rdata_reg <= set_ptp_perout_width_ts_96_reg[15:0]; // PTP perout width fns
+ 16'h0294: axil_csr_rdata_reg <= set_ptp_perout_width_ts_96_reg[45:16]; // PTP perout width ns
+ 16'h0298: axil_csr_rdata_reg <= set_ptp_perout_width_ts_96_reg[79:48]; // PTP perout width sec l
+ 16'h029C: axil_csr_rdata_reg <= set_ptp_perout_width_ts_96_reg[95:80]; // PTP perout width sec h
+ endcase
+ end
+
+ if (rst_250mhz) begin
+ axil_csr_awready_reg <= 1'b0;
+ axil_csr_wready_reg <= 1'b0;
+ axil_csr_bvalid_reg <= 1'b0;
+ axil_csr_arready_reg <= 1'b0;
+ axil_csr_rvalid_reg <= 1'b0;
+
+ // sfp_0_sel_l_reg <= 1'b1;
+ // sfp_1_sel_l_reg <= 1'b1;
+
+ // sfp_reset_l_reg <= 1'b1;
+
+ sfp_i2c_scl_o_reg <= 1'b1;
+ sfp_1_i2c_sda_o_reg <= 1'b1;
+ sfp_2_i2c_sda_o_reg <= 1'b1;
+
+ eeprom_i2c_scl_o_reg <= 1'b1;
+ eeprom_i2c_sda_o_reg <= 1'b1;
+
+ flash_dq_o_reg <= 16'd0;
+ flash_dq_oe_reg <= 1'b0;
+ flash_addr_reg <= 23'd0;
+ flash_region_reg <= 1'b0;
+ flash_region_oe_reg <= 1'b0;
+ flash_ce_n_reg <= 1'b1;
+ flash_oe_n_reg <= 1'b1;
+ flash_we_n_reg <= 1'b1;
+ flash_adv_n_reg <= 1'b1;
+
+ pcie_dma_enable_reg <= 1'b0;
+
+ ptp_perout_enable_reg <= 1'b0;
+ end
+end
+
+pcie_us_cfg #(
+ .PF_COUNT(1),
+ .VF_COUNT(0),
+ .VF_OFFSET(4),
+ .PCIE_CAP_OFFSET(12'h070)
+)
+pcie_us_cfg_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ /*
+ * Configuration outputs
+ */
+ .ext_tag_enable(ext_tag_enable),
+ .max_read_request_size(),
+ .max_payload_size(),
+
+ /*
+ * Interface to Ultrascale PCIe IP core
+ */
+ .cfg_mgmt_addr(cfg_mgmt_addr),
+ .cfg_mgmt_function_number(cfg_mgmt_function_number),
+ .cfg_mgmt_write(cfg_mgmt_write),
+ .cfg_mgmt_write_data(cfg_mgmt_write_data),
+ .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+ .cfg_mgmt_read(cfg_mgmt_read),
+ .cfg_mgmt_read_data(cfg_mgmt_read_data),
+ .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
+);
+
+pcie_us_axil_master #(
+ .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+ .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+ .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+ .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+ .AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
+ .AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
+ .ENABLE_PARITY(0)
+)
+pcie_us_axil_master_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ /*
+ * AXI input (CQ)
+ */
+ .s_axis_cq_tdata(s_axis_cq_tdata),
+ .s_axis_cq_tkeep(s_axis_cq_tkeep),
+ .s_axis_cq_tvalid(s_axis_cq_tvalid),
+ .s_axis_cq_tready(s_axis_cq_tready),
+ .s_axis_cq_tlast(s_axis_cq_tlast),
+ .s_axis_cq_tuser(s_axis_cq_tuser),
+
+ /*
+ * AXI input (CC)
+ */
+ .m_axis_cc_tdata(m_axis_cc_tdata),
+ .m_axis_cc_tkeep(m_axis_cc_tkeep),
+ .m_axis_cc_tvalid(m_axis_cc_tvalid),
+ .m_axis_cc_tready(m_axis_cc_tready),
+ .m_axis_cc_tlast(m_axis_cc_tlast),
+ .m_axis_cc_tuser(m_axis_cc_tuser),
+
+ /*
+ * AXI Lite Master output
+ */
+ .m_axil_awaddr(axil_pcie_awaddr),
+ .m_axil_awprot(axil_pcie_awprot),
+ .m_axil_awvalid(axil_pcie_awvalid),
+ .m_axil_awready(axil_pcie_awready),
+ .m_axil_wdata(axil_pcie_wdata),
+ .m_axil_wstrb(axil_pcie_wstrb),
+ .m_axil_wvalid(axil_pcie_wvalid),
+ .m_axil_wready(axil_pcie_wready),
+ .m_axil_bresp(axil_pcie_bresp),
+ .m_axil_bvalid(axil_pcie_bvalid),
+ .m_axil_bready(axil_pcie_bready),
+ .m_axil_araddr(axil_pcie_araddr),
+ .m_axil_arprot(axil_pcie_arprot),
+ .m_axil_arvalid(axil_pcie_arvalid),
+ .m_axil_arready(axil_pcie_arready),
+ .m_axil_rdata(axil_pcie_rdata),
+ .m_axil_rresp(axil_pcie_rresp),
+ .m_axil_rvalid(axil_pcie_rvalid),
+ .m_axil_rready(axil_pcie_rready),
+
+ /*
+ * Configuration
+ */
+ .completer_id({8'd0, 5'd0, 3'd0}),
+ .completer_id_enable(1'b0),
+
+ /*
+ * Status
+ */
+ .status_error_cor(status_error_cor_int[0]),
+ .status_error_uncor(status_error_uncor_int[0])
+);
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
+wire axis_rc_tlast_r;
+wire axis_rc_tready_r;
+wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
+wire axis_rc_tvalid_r;
+
+axis_register #(
+ .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+ .KEEP_ENABLE(1),
+ .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+ .LAST_ENABLE(1),
+ .ID_ENABLE(0),
+ .DEST_ENABLE(0),
+ .USER_ENABLE(1),
+ .USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
+)
+rc_reg (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ /*
+ * AXI input
+ */
+ .s_axis_tdata(s_axis_rc_tdata),
+ .s_axis_tkeep(s_axis_rc_tkeep),
+ .s_axis_tvalid(s_axis_rc_tvalid),
+ .s_axis_tready(s_axis_rc_tready),
+ .s_axis_tlast(s_axis_rc_tlast),
+ .s_axis_tid(0),
+ .s_axis_tdest(0),
+ .s_axis_tuser(s_axis_rc_tuser),
+
+ /*
+ * AXI output
+ */
+ .m_axis_tdata(axis_rc_tdata_r),
+ .m_axis_tkeep(axis_rc_tkeep_r),
+ .m_axis_tvalid(axis_rc_tvalid_r),
+ .m_axis_tready(axis_rc_tready_r),
+ .m_axis_tlast(axis_rc_tlast_r),
+ .m_axis_tid(),
+ .m_axis_tdest(),
+ .m_axis_tuser(axis_rc_tuser_r)
+);
+
+dma_if_pcie_us #
+(
+ .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+ .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+ .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+ .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+ .SEG_COUNT(SEG_COUNT),
+ .SEG_DATA_WIDTH(SEG_DATA_WIDTH),
+ .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
+ .SEG_BE_WIDTH(SEG_BE_WIDTH),
+ .RAM_SEL_WIDTH(RAM_SEL_WIDTH),
+ .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
+ .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
+ .PCIE_TAG_COUNT(64),
+ .PCIE_EXT_TAG_ENABLE(1),
+ .LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
+ .TAG_WIDTH(PCIE_DMA_TAG_WIDTH)
+)
+dma_if_pcie_us_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ /*
+ * AXI input (RC)
+ */
+ .s_axis_rc_tdata(axis_rc_tdata_r),
+ .s_axis_rc_tkeep(axis_rc_tkeep_r),
+ .s_axis_rc_tvalid(axis_rc_tvalid_r),
+ .s_axis_rc_tready(axis_rc_tready_r),
+ .s_axis_rc_tlast(axis_rc_tlast_r),
+ .s_axis_rc_tuser(axis_rc_tuser_r),
+
+ /*
+ * AXI output (RQ)
+ */
+ .m_axis_rq_tdata(m_axis_rq_tdata),
+ .m_axis_rq_tkeep(m_axis_rq_tkeep),
+ .m_axis_rq_tvalid(m_axis_rq_tvalid),
+ .m_axis_rq_tready(m_axis_rq_tready),
+ .m_axis_rq_tlast(m_axis_rq_tlast),
+ .m_axis_rq_tuser(m_axis_rq_tuser),
+
+ /*
+ * AXI read descriptor input
+ */
+ .s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
+ .s_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
+ .s_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
+ .s_axis_read_desc_len(pcie_dma_read_desc_len),
+ .s_axis_read_desc_tag(pcie_dma_read_desc_tag),
+ .s_axis_read_desc_valid(pcie_dma_read_desc_valid),
+ .s_axis_read_desc_ready(pcie_dma_read_desc_ready),
+
+ /*
+ * AXI read descriptor status output
+ */
+ .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
+ .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
+
+ /*
+ * AXI write descriptor input
+ */
+ .s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
+ .s_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
+ .s_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
+ .s_axis_write_desc_len(pcie_dma_write_desc_len),
+ .s_axis_write_desc_tag(pcie_dma_write_desc_tag),
+ .s_axis_write_desc_valid(pcie_dma_write_desc_valid),
+ .s_axis_write_desc_ready(pcie_dma_write_desc_ready),
+
+ /*
+ * AXI write descriptor status output
+ */
+ .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
+ .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
+
+ /*
+ * RAM interface
+ */
+ .ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
+ .ram_wr_cmd_be(dma_ram_wr_cmd_be),
+ .ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
+ .ram_wr_cmd_data(dma_ram_wr_cmd_data),
+ .ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
+ .ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
+ .ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
+ .ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
+ .ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
+ .ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
+ .ram_rd_resp_data(dma_ram_rd_resp_data),
+ .ram_rd_resp_valid(dma_ram_rd_resp_valid),
+ .ram_rd_resp_ready(dma_ram_rd_resp_ready),
+
+ /*
+ * Configuration
+ */
+ .read_enable(pcie_dma_enable),
+ .write_enable(pcie_dma_enable),
+ .ext_tag_enable(ext_tag_enable),
+ .requester_id({8'd0, 5'd0, 3'd0}),
+ .requester_id_enable(1'b0),
+ .max_read_request_size(cfg_max_read_req),
+ .max_payload_size(cfg_max_payload),
+
+ /*
+ * Status
+ */
+ .status_error_cor(status_error_cor_int[1]),
+ .status_error_uncor(status_error_uncor_int[1])
+);
+
+pulse_merge #(
+ .INPUT_WIDTH(2),
+ .COUNT_WIDTH(4)
+)
+status_error_cor_pm_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ .pulse_in(status_error_cor_int),
+ .count_out(),
+ .pulse_out(status_error_cor)
+);
+
+pulse_merge #(
+ .INPUT_WIDTH(2),
+ .COUNT_WIDTH(4)
+)
+status_error_uncor_pm_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ .pulse_in(status_error_uncor_int),
+ .count_out(),
+ .pulse_out(status_error_uncor)
+);
+
+pcie_us_msi #(
+ .MSI_COUNT(32)
+)
+pcie_us_msi_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ .msi_irq(msi_irq),
+
+ .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+ .cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
+ .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+ .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+ .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+ .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+ .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+ .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+ .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+ .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+ .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+ .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+ .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+ .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+ .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+ .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+ .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
+);
+
+parameter IF_AXIL_ADDR_WIDTH = 32'd23;
+parameter IF_AXIL_BASE_ADDR_WIDTH = IF_COUNT*AXIL_ADDR_WIDTH;
+parameter IF_AXIL_BASE_ADDR = calcIFAxiLiteBaseAddrs(IF_AXIL_ADDR_WIDTH);
+
+function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_addr_width);
+ integer i;
+ begin
+ calcIFAxiLiteBaseAddrs = {IF_AXIL_BASE_ADDR_WIDTH{1'b0}};
+ for (i = 0; i < IF_COUNT; i = i + 1) begin
+ calcIFAxiLiteBaseAddrs[i * AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH] = i * (2**if_addr_width);
+ end
+ end
+endfunction
+
+wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
+wire [IF_COUNT*3-1:0] axil_if_awprot;
+wire [IF_COUNT-1:0] axil_if_awvalid;
+wire [IF_COUNT-1:0] axil_if_awready;
+wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_wdata;
+wire [IF_COUNT*AXIL_STRB_WIDTH-1:0] axil_if_wstrb;
+wire [IF_COUNT-1:0] axil_if_wvalid;
+wire [IF_COUNT-1:0] axil_if_wready;
+wire [IF_COUNT*2-1:0] axil_if_bresp;
+wire [IF_COUNT-1:0] axil_if_bvalid;
+wire [IF_COUNT-1:0] axil_if_bready;
+wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_araddr;
+wire [IF_COUNT*3-1:0] axil_if_arprot;
+wire [IF_COUNT-1:0] axil_if_arvalid;
+wire [IF_COUNT-1:0] axil_if_arready;
+wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_rdata;
+wire [IF_COUNT*2-1:0] axil_if_rresp;
+wire [IF_COUNT-1:0] axil_if_rvalid;
+wire [IF_COUNT-1:0] axil_if_rready;
+
+wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_csr_awaddr;
+wire [IF_COUNT*3-1:0] axil_if_csr_awprot;
+wire [IF_COUNT-1:0] axil_if_csr_awvalid;
+wire [IF_COUNT-1:0] axil_if_csr_awready;
+wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_csr_wdata;
+wire [IF_COUNT*AXIL_STRB_WIDTH-1:0] axil_if_csr_wstrb;
+wire [IF_COUNT-1:0] axil_if_csr_wvalid;
+wire [IF_COUNT-1:0] axil_if_csr_wready;
+wire [IF_COUNT*2-1:0] axil_if_csr_bresp;
+wire [IF_COUNT-1:0] axil_if_csr_bvalid;
+wire [IF_COUNT-1:0] axil_if_csr_bready;
+wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_csr_araddr;
+wire [IF_COUNT*3-1:0] axil_if_csr_arprot;
+wire [IF_COUNT-1:0] axil_if_csr_arvalid;
+wire [IF_COUNT-1:0] axil_if_csr_arready;
+wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_csr_rdata;
+wire [IF_COUNT*2-1:0] axil_if_csr_rresp;
+wire [IF_COUNT-1:0] axil_if_csr_rvalid;
+wire [IF_COUNT-1:0] axil_if_csr_rready;
+
+axil_interconnect #(
+ .DATA_WIDTH(AXIL_DATA_WIDTH),
+ .ADDR_WIDTH(AXIL_ADDR_WIDTH),
+ .S_COUNT(1),
+ .M_COUNT(IF_COUNT),
+ .M_BASE_ADDR(IF_AXIL_BASE_ADDR),
+ .M_ADDR_WIDTH({IF_COUNT{IF_AXIL_ADDR_WIDTH}}),
+ .M_CONNECT_READ({IF_COUNT{1'b1}}),
+ .M_CONNECT_WRITE({IF_COUNT{1'b1}})
+)
+axil_interconnect_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+ .s_axil_awaddr(axil_pcie_awaddr),
+ .s_axil_awprot(axil_pcie_awprot),
+ .s_axil_awvalid(axil_pcie_awvalid),
+ .s_axil_awready(axil_pcie_awready),
+ .s_axil_wdata(axil_pcie_wdata),
+ .s_axil_wstrb(axil_pcie_wstrb),
+ .s_axil_wvalid(axil_pcie_wvalid),
+ .s_axil_wready(axil_pcie_wready),
+ .s_axil_bresp(axil_pcie_bresp),
+ .s_axil_bvalid(axil_pcie_bvalid),
+ .s_axil_bready(axil_pcie_bready),
+ .s_axil_araddr(axil_pcie_araddr),
+ .s_axil_arprot(axil_pcie_arprot),
+ .s_axil_arvalid(axil_pcie_arvalid),
+ .s_axil_arready(axil_pcie_arready),
+ .s_axil_rdata(axil_pcie_rdata),
+ .s_axil_rresp(axil_pcie_rresp),
+ .s_axil_rvalid(axil_pcie_rvalid),
+ .s_axil_rready(axil_pcie_rready),
+ .m_axil_awaddr(axil_if_awaddr),
+ .m_axil_awprot(axil_if_awprot),
+ .m_axil_awvalid(axil_if_awvalid),
+ .m_axil_awready(axil_if_awready),
+ .m_axil_wdata(axil_if_wdata),
+ .m_axil_wstrb(axil_if_wstrb),
+ .m_axil_wvalid(axil_if_wvalid),
+ .m_axil_wready(axil_if_wready),
+ .m_axil_bresp(axil_if_bresp),
+ .m_axil_bvalid(axil_if_bvalid),
+ .m_axil_bready(axil_if_bready),
+ .m_axil_araddr(axil_if_araddr),
+ .m_axil_arprot(axil_if_arprot),
+ .m_axil_arvalid(axil_if_arvalid),
+ .m_axil_arready(axil_if_arready),
+ .m_axil_rdata(axil_if_rdata),
+ .m_axil_rresp(axil_if_rresp),
+ .m_axil_rvalid(axil_if_rvalid),
+ .m_axil_rready(axil_if_rready)
+);
+
+axil_interconnect #(
+ .DATA_WIDTH(AXIL_DATA_WIDTH),
+ .ADDR_WIDTH(AXIL_ADDR_WIDTH),
+ .S_COUNT(IF_COUNT),
+ .M_COUNT(1),
+ .M_BASE_ADDR({24'h000000}),
+ .M_ADDR_WIDTH({1{IF_AXIL_ADDR_WIDTH}}),
+ .M_CONNECT_READ({1{1'b1}}),
+ .M_CONNECT_WRITE({1{1'b1}})
+)
+axil_csr_interconnect_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+ .s_axil_awaddr(axil_if_csr_awaddr),
+ .s_axil_awprot(axil_if_csr_awprot),
+ .s_axil_awvalid(axil_if_csr_awvalid),
+ .s_axil_awready(axil_if_csr_awready),
+ .s_axil_wdata(axil_if_csr_wdata),
+ .s_axil_wstrb(axil_if_csr_wstrb),
+ .s_axil_wvalid(axil_if_csr_wvalid),
+ .s_axil_wready(axil_if_csr_wready),
+ .s_axil_bresp(axil_if_csr_bresp),
+ .s_axil_bvalid(axil_if_csr_bvalid),
+ .s_axil_bready(axil_if_csr_bready),
+ .s_axil_araddr(axil_if_csr_araddr),
+ .s_axil_arprot(axil_if_csr_arprot),
+ .s_axil_arvalid(axil_if_csr_arvalid),
+ .s_axil_arready(axil_if_csr_arready),
+ .s_axil_rdata(axil_if_csr_rdata),
+ .s_axil_rresp(axil_if_csr_rresp),
+ .s_axil_rvalid(axil_if_csr_rvalid),
+ .s_axil_rready(axil_if_csr_rready),
+ .m_axil_awaddr(axil_csr_awaddr),
+ .m_axil_awprot(axil_csr_awprot),
+ .m_axil_awvalid(axil_csr_awvalid),
+ .m_axil_awready(axil_csr_awready),
+ .m_axil_wdata(axil_csr_wdata),
+ .m_axil_wstrb(axil_csr_wstrb),
+ .m_axil_wvalid(axil_csr_wvalid),
+ .m_axil_wready(axil_csr_wready),
+ .m_axil_bresp(axil_csr_bresp),
+ .m_axil_bvalid(axil_csr_bvalid),
+ .m_axil_bready(axil_csr_bready),
+ .m_axil_araddr(axil_csr_araddr),
+ .m_axil_arprot(axil_csr_arprot),
+ .m_axil_arvalid(axil_csr_arvalid),
+ .m_axil_arready(axil_csr_arready),
+ .m_axil_rdata(axil_csr_rdata),
+ .m_axil_rresp(axil_csr_rresp),
+ .m_axil_rvalid(axil_csr_rvalid),
+ .m_axil_rready(axil_csr_rready)
+);
+
+parameter IF_RAM_SEL_WIDTH = $clog2(PORTS_PER_IF+1);
+parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT);
+
+wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_pcie_addr;
+wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_read_desc_ram_sel;
+wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_read_desc_ram_addr;
+wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_read_desc_len;
+wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_tag;
+wire [IF_COUNT-1:0] if_pcie_dma_read_desc_valid;
+wire [IF_COUNT-1:0] if_pcie_dma_read_desc_ready;
+
+wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_read_desc_status_tag;
+wire [IF_COUNT-1:0] if_pcie_dma_read_desc_status_valid;
+
+wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_pcie_addr;
+wire [IF_COUNT*RAM_SEL_WIDTH-1:0] if_pcie_dma_write_desc_ram_sel;
+wire [IF_COUNT*RAM_ADDR_WIDTH-1:0] if_pcie_dma_write_desc_ram_addr;
+wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_dma_write_desc_len;
+wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_tag;
+wire [IF_COUNT-1:0] if_pcie_dma_write_desc_valid;
+wire [IF_COUNT-1:0] if_pcie_dma_write_desc_ready;
+
+wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_dma_write_desc_status_tag;
+wire [IF_COUNT-1:0] if_pcie_dma_write_desc_status_valid;
+
+wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_wr_cmd_sel;
+wire [IF_COUNT*SEG_COUNT*SEG_BE_WIDTH-1:0] if_dma_ram_wr_cmd_be;
+wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_wr_cmd_addr;
+wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_wr_cmd_data;
+wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_valid;
+wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_wr_cmd_ready;
+wire [IF_COUNT*SEG_COUNT*IF_RAM_SEL_WIDTH-1:0] if_dma_ram_rd_cmd_sel;
+wire [IF_COUNT*SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_dma_ram_rd_cmd_addr;
+wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_valid;
+wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_cmd_ready;
+wire [IF_COUNT*SEG_COUNT*SEG_DATA_WIDTH-1:0] if_dma_ram_rd_resp_data;
+wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_valid;
+wire [IF_COUNT*SEG_COUNT-1:0] if_dma_ram_rd_resp_ready;
+
+dma_if_mux #
+(
+ .PORTS(IF_COUNT),
+ .SEG_COUNT(SEG_COUNT),
+ .SEG_DATA_WIDTH(SEG_DATA_WIDTH),
+ .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
+ .SEG_BE_WIDTH(SEG_BE_WIDTH),
+ .S_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
+ .M_RAM_SEL_WIDTH(RAM_SEL_WIDTH),
+ .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
+ .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
+ .LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
+ .S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
+ .M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
+ .ARB_TYPE("ROUND_ROBIN"),
+ .LSB_PRIORITY("HIGH")
+)
+dma_if_mux_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ /*
+ * Read descriptor output (to DMA interface)
+ */
+ .m_axis_read_desc_dma_addr(pcie_dma_read_desc_pcie_addr),
+ .m_axis_read_desc_ram_sel(pcie_dma_read_desc_ram_sel),
+ .m_axis_read_desc_ram_addr(pcie_dma_read_desc_ram_addr),
+ .m_axis_read_desc_len(pcie_dma_read_desc_len),
+ .m_axis_read_desc_tag(pcie_dma_read_desc_tag),
+ .m_axis_read_desc_valid(pcie_dma_read_desc_valid),
+ .m_axis_read_desc_ready(pcie_dma_read_desc_ready),
+
+ /*
+ * Read descriptor status input (from DMA interface)
+ */
+ .s_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
+ .s_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
+
+ /*
+ * Read descriptor input
+ */
+ .s_axis_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr),
+ .s_axis_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel),
+ .s_axis_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr),
+ .s_axis_read_desc_len(if_pcie_dma_read_desc_len),
+ .s_axis_read_desc_tag(if_pcie_dma_read_desc_tag),
+ .s_axis_read_desc_valid(if_pcie_dma_read_desc_valid),
+ .s_axis_read_desc_ready(if_pcie_dma_read_desc_ready),
+
+ /*
+ * Read descriptor status output
+ */
+ .m_axis_read_desc_status_tag(if_pcie_dma_read_desc_status_tag),
+ .m_axis_read_desc_status_valid(if_pcie_dma_read_desc_status_valid),
+
+ /*
+ * Write descriptor output (to DMA interface)
+ */
+ .m_axis_write_desc_dma_addr(pcie_dma_write_desc_pcie_addr),
+ .m_axis_write_desc_ram_sel(pcie_dma_write_desc_ram_sel),
+ .m_axis_write_desc_ram_addr(pcie_dma_write_desc_ram_addr),
+ .m_axis_write_desc_len(pcie_dma_write_desc_len),
+ .m_axis_write_desc_tag(pcie_dma_write_desc_tag),
+ .m_axis_write_desc_valid(pcie_dma_write_desc_valid),
+ .m_axis_write_desc_ready(pcie_dma_write_desc_ready),
+
+ /*
+ * Write descriptor status input (from DMA interface)
+ */
+ .s_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
+ .s_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
+
+ /*
+ * Write descriptor input
+ */
+ .s_axis_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr),
+ .s_axis_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel),
+ .s_axis_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr),
+ .s_axis_write_desc_len(if_pcie_dma_write_desc_len),
+ .s_axis_write_desc_tag(if_pcie_dma_write_desc_tag),
+ .s_axis_write_desc_valid(if_pcie_dma_write_desc_valid),
+ .s_axis_write_desc_ready(if_pcie_dma_write_desc_ready),
+
+ /*
+ * Write descriptor status output
+ */
+ .m_axis_write_desc_status_tag(if_pcie_dma_write_desc_status_tag),
+ .m_axis_write_desc_status_valid(if_pcie_dma_write_desc_status_valid),
+
+ /*
+ * RAM interface (from DMA interface)
+ */
+ .if_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
+ .if_ram_wr_cmd_be(dma_ram_wr_cmd_be),
+ .if_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
+ .if_ram_wr_cmd_data(dma_ram_wr_cmd_data),
+ .if_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
+ .if_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
+ .if_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
+ .if_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
+ .if_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
+ .if_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
+ .if_ram_rd_resp_data(dma_ram_rd_resp_data),
+ .if_ram_rd_resp_valid(dma_ram_rd_resp_valid),
+ .if_ram_rd_resp_ready(dma_ram_rd_resp_ready),
+
+ /*
+ * RAM interface
+ */
+ .ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel),
+ .ram_wr_cmd_be(if_dma_ram_wr_cmd_be),
+ .ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr),
+ .ram_wr_cmd_data(if_dma_ram_wr_cmd_data),
+ .ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid),
+ .ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready),
+ .ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel),
+ .ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr),
+ .ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid),
+ .ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready),
+ .ram_rd_resp_data(if_dma_ram_rd_resp_data),
+ .ram_rd_resp_valid(if_dma_ram_rd_resp_valid),
+ .ram_rd_resp_ready(if_dma_ram_rd_resp_ready)
+);
+
+// PTP clock
+ptp_clock #(
+ .PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
+ .OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
+ .FNS_WIDTH(PTP_FNS_WIDTH),
+ .PERIOD_NS(PTP_PERIOD_NS),
+ .PERIOD_FNS(PTP_PERIOD_FNS),
+ .DRIFT_ENABLE(0)
+)
+ptp_clock_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ /*
+ * Timestamp inputs for synchronization
+ */
+ .input_ts_96(set_ptp_ts_96_reg),
+ .input_ts_96_valid(set_ptp_ts_96_valid_reg),
+ .input_ts_64(0),
+ .input_ts_64_valid(1'b0),
+
+ /*
+ * Period adjustment
+ */
+ .input_period_ns(set_ptp_period_ns_reg),
+ .input_period_fns(set_ptp_period_fns_reg),
+ .input_period_valid(set_ptp_period_valid_reg),
+
+ /*
+ * Offset adjustment
+ */
+ .input_adj_ns(set_ptp_offset_ns_reg),
+ .input_adj_fns(set_ptp_offset_fns_reg),
+ .input_adj_count(set_ptp_offset_count_reg),
+ .input_adj_valid(set_ptp_offset_valid_reg),
+ .input_adj_active(set_ptp_offset_active),
+
+ /*
+ * Drift adjustment
+ */
+ .input_drift_ns(0),
+ .input_drift_fns(0),
+ .input_drift_rate(0),
+ .input_drift_valid(0),
+
+ /*
+ * Timestamp outputs
+ */
+ .output_ts_96(ptp_ts_96),
+ .output_ts_64(),
+ .output_ts_step(ptp_ts_step),
+
+ /*
+ * PPS output
+ */
+ .output_pps(ptp_pps)
+);
+
+assign sma_out = ptp_perout_pulse;
+assign sma_out_en = 1'b0;
+assign sma_term_en = 1'b0;
+
+ptp_perout #(
+ .FNS_ENABLE(0),
+ .OUT_START_S(0),
+ .OUT_START_NS(0),
+ .OUT_START_FNS(0),
+ .OUT_PERIOD_S(1),
+ .OUT_PERIOD_NS(0),
+ .OUT_PERIOD_FNS(0),
+ .OUT_WIDTH_S(0),
+ .OUT_WIDTH_NS(500000000),
+ .OUT_WIDTH_FNS(0)
+)
+ptp_perout_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+ .input_ts_96(ptp_ts_96),
+ .input_ts_step(ptp_ts_step),
+ .enable(ptp_perout_enable_reg),
+ .input_start(set_ptp_perout_start_ts_96_reg),
+ .input_start_valid(set_ptp_perout_start_ts_96_valid_reg),
+ .input_period(set_ptp_perout_period_ts_96_reg),
+ .input_period_valid(set_ptp_perout_period_ts_96_valid_reg),
+ .input_width(set_ptp_perout_width_ts_96_reg),
+ .input_width_valid(set_ptp_perout_width_ts_96_valid_reg),
+ .locked(ptp_perout_locked),
+ .error(ptp_perout_error),
+ .output_pulse(ptp_perout_pulse)
+);
+
+reg [26:0] pps_led_counter_reg = 0;
+reg pps_led_reg = 0;
+
+always @(posedge clk_250mhz) begin
+ if (ptp_pps) begin
+ pps_led_counter_reg <= 125000000;
+ end else if (pps_led_counter_reg > 0) begin
+ pps_led_counter_reg <= pps_led_counter_reg - 1;
+ end
+
+ pps_led_reg <= pps_led_counter_reg > 0;
+end
+
+wire [PORT_COUNT-1:0] port_xgmii_tx_clk = {sfp_2_tx_clk, sfp_1_tx_clk};
+wire [PORT_COUNT-1:0] port_xgmii_tx_rst = {sfp_2_tx_rst, sfp_1_tx_rst};
+wire [PORT_COUNT-1:0] port_xgmii_rx_clk = {sfp_2_rx_clk, sfp_1_rx_clk};
+wire [PORT_COUNT-1:0] port_xgmii_rx_rst = {sfp_2_rx_rst, sfp_1_rx_rst};
+wire [PORT_COUNT*64-1:0] port_xgmii_txd;
+wire [PORT_COUNT*8-1:0] port_xgmii_txc;
+wire [PORT_COUNT*64-1:0] port_xgmii_rxd = {sfp_2_rxd, sfp_1_rxd};
+wire [PORT_COUNT*8-1:0] port_xgmii_rxc = {sfp_2_rxc, sfp_1_rxc};
+
+assign {sfp_2_txd, sfp_1_txd} = port_xgmii_txd;
+assign {sfp_2_txc, sfp_1_txc} = port_xgmii_txc;
+
+assign sfp_1_led = 2'b00;
+assign sfp_2_led = 2'b00;
+assign sma_led[0] = pps_led_reg;
+assign sma_led[1] = 1'b0;
+
+wire [IF_COUNT*32-1:0] if_msi_irq;
+
+assign msi_irq = if_msi_irq[31:0] | if_msi_irq[63:32];
+
+generate
+ genvar m, n;
+
+ for (n = 0; n < IF_COUNT; n = n + 1) begin : iface
+
+ wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata;
+ wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep;
+ wire [PORTS_PER_IF-1:0] tx_axis_tvalid;
+ wire [PORTS_PER_IF-1:0] tx_axis_tready;
+ wire [PORTS_PER_IF-1:0] tx_axis_tlast;
+ wire [PORTS_PER_IF-1:0] tx_axis_tuser;
+
+ wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
+ wire [PORTS_PER_IF-1:0] tx_ptp_ts_valid;
+ wire [PORTS_PER_IF-1:0] tx_ptp_ts_ready;
+
+ wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
+ wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
+ wire [PORTS_PER_IF-1:0] rx_axis_tvalid;
+ wire [PORTS_PER_IF-1:0] rx_axis_tready;
+ wire [PORTS_PER_IF-1:0] rx_axis_tlast;
+ wire [PORTS_PER_IF-1:0] rx_axis_tuser;
+
+ wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
+ wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid;
+ wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready;
+
+ interface #(
+ .PORTS(PORTS_PER_IF),
+ .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
+ .DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
+ .DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
+ .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
+ .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
+ .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
+ .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
+ .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
+ .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
+ .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
+ .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
+ .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
+ .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
+ .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
+ .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
+ .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
+ .TX_SCHEDULER(TX_SCHEDULER),
+ .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
+ .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
+ .INT_WIDTH(8),
+ .QUEUE_PTR_WIDTH(16),
+ .QUEUE_LOG_SIZE_WIDTH(4),
+ .PTP_TS_ENABLE(PTP_TS_ENABLE),
+ .PTP_TS_WIDTH(PTP_TS_WIDTH),
+ .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
+ .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
+ .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
+ .AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
+ .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
+ .SEG_COUNT(SEG_COUNT),
+ .SEG_DATA_WIDTH(SEG_DATA_WIDTH),
+ .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
+ .SEG_BE_WIDTH(SEG_BE_WIDTH),
+ .RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
+ .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
+ .RAM_PIPELINE(RAM_PIPELINE),
+ .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+ .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+ .MAX_TX_SIZE(MAX_TX_SIZE),
+ .MAX_RX_SIZE(MAX_RX_SIZE),
+ .TX_RAM_SIZE(TX_RAM_SIZE),
+ .RX_RAM_SIZE(RX_RAM_SIZE)
+ )
+ interface_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+
+ /*
+ * DMA read descriptor output
+ */
+ .m_axis_dma_read_desc_dma_addr(if_pcie_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
+ .m_axis_dma_read_desc_ram_sel(if_pcie_dma_read_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
+ .m_axis_dma_read_desc_ram_addr(if_pcie_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
+ .m_axis_dma_read_desc_len(if_pcie_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
+ .m_axis_dma_read_desc_tag(if_pcie_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
+ .m_axis_dma_read_desc_valid(if_pcie_dma_read_desc_valid[n]),
+ .m_axis_dma_read_desc_ready(if_pcie_dma_read_desc_ready[n]),
+
+ /*
+ * DMA read descriptor status input
+ */
+ .s_axis_dma_read_desc_status_tag(if_pcie_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
+ .s_axis_dma_read_desc_status_valid(if_pcie_dma_read_desc_status_valid[n]),
+
+ /*
+ * DMA write descriptor output
+ */
+ .m_axis_dma_write_desc_dma_addr(if_pcie_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
+ .m_axis_dma_write_desc_ram_sel(if_pcie_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
+ .m_axis_dma_write_desc_ram_addr(if_pcie_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
+ .m_axis_dma_write_desc_len(if_pcie_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]),
+ .m_axis_dma_write_desc_tag(if_pcie_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
+ .m_axis_dma_write_desc_valid(if_pcie_dma_write_desc_valid[n]),
+ .m_axis_dma_write_desc_ready(if_pcie_dma_write_desc_ready[n]),
+
+ /*
+ * DMA write descriptor status input
+ */
+ .s_axis_dma_write_desc_status_tag(if_pcie_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]),
+ .s_axis_dma_write_desc_status_valid(if_pcie_dma_write_desc_status_valid[n]),
+
+ /*
+ * AXI-Lite slave interface
+ */
+ .s_axil_awaddr(axil_if_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
+ .s_axil_awprot(axil_if_awprot[n*3 +: 3]),
+ .s_axil_awvalid(axil_if_awvalid[n]),
+ .s_axil_awready(axil_if_awready[n]),
+ .s_axil_wdata(axil_if_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
+ .s_axil_wstrb(axil_if_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]),
+ .s_axil_wvalid(axil_if_wvalid[n]),
+ .s_axil_wready(axil_if_wready[n]),
+ .s_axil_bresp(axil_if_bresp[n*2 +: 2]),
+ .s_axil_bvalid(axil_if_bvalid[n]),
+ .s_axil_bready(axil_if_bready[n]),
+ .s_axil_araddr(axil_if_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
+ .s_axil_arprot(axil_if_arprot[n*3 +: 3]),
+ .s_axil_arvalid(axil_if_arvalid[n]),
+ .s_axil_arready(axil_if_arready[n]),
+ .s_axil_rdata(axil_if_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
+ .s_axil_rresp(axil_if_rresp[n*2 +: 2]),
+ .s_axil_rvalid(axil_if_rvalid[n]),
+ .s_axil_rready(axil_if_rready[n]),
+
+ /*
+ * AXI-Lite master interface (passthrough for NIC control and status)
+ */
+ .m_axil_csr_awaddr(axil_if_csr_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
+ .m_axil_csr_awprot(axil_if_csr_awprot[n*3 +: 3]),
+ .m_axil_csr_awvalid(axil_if_csr_awvalid[n]),
+ .m_axil_csr_awready(axil_if_csr_awready[n]),
+ .m_axil_csr_wdata(axil_if_csr_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
+ .m_axil_csr_wstrb(axil_if_csr_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]),
+ .m_axil_csr_wvalid(axil_if_csr_wvalid[n]),
+ .m_axil_csr_wready(axil_if_csr_wready[n]),
+ .m_axil_csr_bresp(axil_if_csr_bresp[n*2 +: 2]),
+ .m_axil_csr_bvalid(axil_if_csr_bvalid[n]),
+ .m_axil_csr_bready(axil_if_csr_bready[n]),
+ .m_axil_csr_araddr(axil_if_csr_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
+ .m_axil_csr_arprot(axil_if_csr_arprot[n*3 +: 3]),
+ .m_axil_csr_arvalid(axil_if_csr_arvalid[n]),
+ .m_axil_csr_arready(axil_if_csr_arready[n]),
+ .m_axil_csr_rdata(axil_if_csr_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
+ .m_axil_csr_rresp(axil_if_csr_rresp[n*2 +: 2]),
+ .m_axil_csr_rvalid(axil_if_csr_rvalid[n]),
+ .m_axil_csr_rready(axil_if_csr_rready[n]),
+
+ /*
+ * RAM interface
+ */
+ .dma_ram_wr_cmd_sel(if_dma_ram_wr_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
+ .dma_ram_wr_cmd_be(if_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]),
+ .dma_ram_wr_cmd_addr(if_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
+ .dma_ram_wr_cmd_data(if_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
+ .dma_ram_wr_cmd_valid(if_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
+ .dma_ram_wr_cmd_ready(if_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
+ .dma_ram_rd_cmd_sel(if_dma_ram_rd_cmd_sel[SEG_COUNT*IF_RAM_SEL_WIDTH*n +: SEG_COUNT*IF_RAM_SEL_WIDTH]),
+ .dma_ram_rd_cmd_addr(if_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]),
+ .dma_ram_rd_cmd_valid(if_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]),
+ .dma_ram_rd_cmd_ready(if_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]),
+ .dma_ram_rd_resp_data(if_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]),
+ .dma_ram_rd_resp_valid(if_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]),
+ .dma_ram_rd_resp_ready(if_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]),
+
+ /*
+ * Transmit data output
+ */
+ .tx_axis_tdata(tx_axis_tdata),
+ .tx_axis_tkeep(tx_axis_tkeep),
+ .tx_axis_tvalid(tx_axis_tvalid),
+ .tx_axis_tready(tx_axis_tready),
+ .tx_axis_tlast(tx_axis_tlast),
+ .tx_axis_tuser(tx_axis_tuser),
+
+ /*
+ * Transmit timestamp input
+ */
+ .s_axis_tx_ptp_ts_96(tx_ptp_ts_96),
+ .s_axis_tx_ptp_ts_valid(tx_ptp_ts_valid),
+ .s_axis_tx_ptp_ts_ready(tx_ptp_ts_ready),
+
+ /*
+ * Receive data input
+ */
+ .rx_axis_tdata(rx_axis_tdata),
+ .rx_axis_tkeep(rx_axis_tkeep),
+ .rx_axis_tvalid(rx_axis_tvalid),
+ .rx_axis_tready(rx_axis_tready),
+ .rx_axis_tlast(rx_axis_tlast),
+ .rx_axis_tuser(rx_axis_tuser),
+
+ /*
+ * Receive timestamp input
+ */
+ .s_axis_rx_ptp_ts_96(rx_ptp_ts_96),
+ .s_axis_rx_ptp_ts_valid(rx_ptp_ts_valid),
+ .s_axis_rx_ptp_ts_ready(rx_ptp_ts_ready),
+
+ /*
+ * PTP clock
+ */
+ .ptp_ts_96(ptp_ts_96),
+ .ptp_ts_step(ptp_ts_step),
+
+ /*
+ * MSI interrupts
+ */
+ .msi_irq(if_msi_irq[n*32 +: 32])
+ );
+
+ for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : mac
+
+ eth_mac_10g_fifo #(
+ .DATA_WIDTH(64),
+ .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+ .AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
+ .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+ .ENABLE_PADDING(ENABLE_PADDING),
+ .ENABLE_DIC(ENABLE_DIC),
+ .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
+ .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+ .TX_FRAME_FIFO(1),
+ .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+ .RX_FRAME_FIFO(1),
+ .LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
+ .LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
+ .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
+ .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
+ .PTP_USE_SAMPLE_CLOCK(0),
+ .TX_PTP_TS_ENABLE(PTP_TS_ENABLE),
+ .RX_PTP_TS_ENABLE(PTP_TS_ENABLE),
+ .TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
+ .RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
+ .PTP_TS_WIDTH(PTP_TS_WIDTH),
+ .TX_PTP_TAG_ENABLE(0),
+ .PTP_TAG_WIDTH(16)
+ )
+ eth_mac_inst (
+ .rx_clk(port_xgmii_rx_clk[n*PORTS_PER_IF+m]),
+ .rx_rst(port_xgmii_rx_rst[n*PORTS_PER_IF+m]),
+ .tx_clk(port_xgmii_tx_clk[n*PORTS_PER_IF+m]),
+ .tx_rst(port_xgmii_tx_rst[n*PORTS_PER_IF+m]),
+ .logic_clk(clk_250mhz),
+ .logic_rst(rst_250mhz),
+ .ptp_sample_clk(clk_250mhz),
+
+ .tx_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
+ .tx_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
+ .tx_axis_tvalid(tx_axis_tvalid[m +: 1]),
+ .tx_axis_tready(tx_axis_tready[m +: 1]),
+ .tx_axis_tlast(tx_axis_tlast[m +: 1]),
+ .tx_axis_tuser(tx_axis_tuser[m +: 1]),
+
+ .s_axis_tx_ptp_ts_tag(0),
+ .s_axis_tx_ptp_ts_valid(0),
+ .s_axis_tx_ptp_ts_ready(),
+
+ .m_axis_tx_ptp_ts_96(tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+ .m_axis_tx_ptp_ts_tag(),
+ .m_axis_tx_ptp_ts_valid(tx_ptp_ts_valid[m +: 1]),
+ .m_axis_tx_ptp_ts_ready(tx_ptp_ts_ready[m +: 1]),
+
+ .rx_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
+ .rx_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
+ .rx_axis_tvalid(rx_axis_tvalid[m +: 1]),
+ .rx_axis_tready(rx_axis_tready[m +: 1]),
+ .rx_axis_tlast(rx_axis_tlast[m +: 1]),
+ .rx_axis_tuser(rx_axis_tuser[m +: 1]),
+
+ .m_axis_rx_ptp_ts_96(rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+ .m_axis_rx_ptp_ts_valid(rx_ptp_ts_valid[m +: 1]),
+ .m_axis_rx_ptp_ts_ready(rx_ptp_ts_ready[m +: 1]),
+
+ .xgmii_rxd(port_xgmii_rxd[(n*PORTS_PER_IF+m)*64 +: 64]),
+ .xgmii_rxc(port_xgmii_rxc[(n*PORTS_PER_IF+m)*8 +: 8]),
+ .xgmii_txd(port_xgmii_txd[(n*PORTS_PER_IF+m)*64 +: 64]),
+ .xgmii_txc(port_xgmii_txc[(n*PORTS_PER_IF+m)*8 +: 8]),
+
+ .tx_error_underflow(),
+ .tx_fifo_overflow(),
+ .tx_fifo_bad_frame(),
+ .tx_fifo_good_frame(),
+ .rx_error_bad_frame(),
+ .rx_error_bad_fcs(),
+ .rx_fifo_overflow(),
+ .rx_fifo_bad_frame(),
+ .rx_fifo_good_frame(),
+
+ .ptp_ts_96(ptp_ts_96),
+
+ .ifg_delay(8'd12)
+ );
+
+ end
+
+ end
+
+endgenerate
+
+endmodule
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_reset.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_reset.v
new file mode 100644
index 000000000..acbcf1c6e
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_reset.v
@@ -0,0 +1,52 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Synchronizes an active-high asynchronous reset signal to a given clock by
+ * using a pipeline of N registers.
+ */
+module sync_reset #(
+ parameter N=2 // depth of synchronizer
+)(
+ input wire clk,
+ input wire rst,
+ output wire sync_reset_out
+);
+
+reg [N-1:0] sync_reg = {N{1'b1}};
+
+assign sync_reset_out = sync_reg[N-1];
+
+always @(posedge clk or posedge rst) begin
+ if (rst)
+ sync_reg <= {N{1'b1}};
+ else
+ sync_reg <= {sync_reg[N-2:0], 1'b0};
+end
+
+endmodule
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v
new file mode 100644
index 000000000..b2a8ce3de
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/sync_signal.v
@@ -0,0 +1,58 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Synchronizes an asyncronous signal to a given clock by using a pipeline of
+ * two registers.
+ */
+module sync_signal #(
+ parameter WIDTH=1, // width of the input and output signals
+ parameter N=2 // depth of synchronizer
+)(
+ input wire clk,
+ input wire [WIDTH-1:0] in,
+ output wire [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] sync_reg[N-1:0];
+
+/*
+ * The synchronized output is the last register in the pipeline.
+ */
+assign out = sync_reg[N-1];
+
+integer k;
+
+always @(posedge clk) begin
+ sync_reg[0] <= in;
+ for (k = 1; k < N; k = k + 1) begin
+ sync_reg[k] <= sync_reg[k-1];
+ end
+end
+
+endmodule
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/axis_ep.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/axis_ep.py
new file mode 120000
index 000000000..385bb0300
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/axis_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/axis_ep.py
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/eth_ep.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/eth_ep.py
new file mode 120000
index 000000000..bac19feea
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/eth_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/eth_ep.py
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/ip_ep.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/ip_ep.py
new file mode 120000
index 000000000..6dfa928a7
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/ip_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/ip_ep.py
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/mqnic.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/mqnic.py
new file mode 120000
index 000000000..f2c96aec4
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/mqnic.py
@@ -0,0 +1 @@
+../../../../common/tb/mqnic.py
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie.py
new file mode 120000
index 000000000..abea2f963
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie.py
@@ -0,0 +1 @@
+../lib/pcie/tb/pcie.py
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_us.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_us.py
new file mode 120000
index 000000000..ef028ec29
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_us.py
@@ -0,0 +1 @@
+../lib/pcie/tb/pcie_us.py
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_usp.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_usp.py
new file mode 120000
index 000000000..8ce355a22
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/pcie_usp.py
@@ -0,0 +1 @@
+../lib/pcie/tb/pcie_usp.py
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py
new file mode 100755
index 000000000..517c85080
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py
@@ -0,0 +1,810 @@
+#!/usr/bin/env python
+"""
+
+Copyright 2019, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.
+
+"""
+
+from myhdl import *
+import os
+
+import pcie
+import pcie_us
+import xgmii_ep
+import axis_ep
+import eth_ep
+import udp_ep
+
+import struct
+
+import mqnic
+
+module = 'fpga_core'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/common/interface.v")
+srcs.append("../rtl/common/port.v")
+srcs.append("../rtl/common/cpl_write.v")
+srcs.append("../rtl/common/cpl_op_mux.v")
+srcs.append("../rtl/common/desc_fetch.v")
+srcs.append("../rtl/common/desc_op_mux.v")
+srcs.append("../rtl/common/queue_manager.v")
+srcs.append("../rtl/common/cpl_queue_manager.v")
+srcs.append("../rtl/common/tx_engine.v")
+srcs.append("../rtl/common/rx_engine.v")
+srcs.append("../rtl/common/tx_checksum.v")
+srcs.append("../rtl/common/rx_checksum.v")
+srcs.append("../rtl/common/tx_scheduler_rr.v")
+srcs.append("../rtl/common/tdma_scheduler.v")
+srcs.append("../rtl/common/event_mux.v")
+srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
+srcs.append("../lib/eth/rtl/eth_mac_10g.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
+srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
+srcs.append("../lib/eth/rtl/lfsr.v")
+srcs.append("../lib/eth/rtl/ptp_clock.v")
+srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
+srcs.append("../lib/eth/rtl/ptp_perout.v")
+srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
+srcs.append("../lib/axi/rtl/axil_interconnect.v")
+srcs.append("../lib/axi/rtl/arbiter.v")
+srcs.append("../lib/axi/rtl/priority_encoder.v")
+srcs.append("../lib/axis/rtl/axis_adapter.v")
+srcs.append("../lib/axis/rtl/axis_arb_mux.v")
+srcs.append("../lib/axis/rtl/axis_async_fifo.v")
+srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
+srcs.append("../lib/axis/rtl/axis_fifo.v")
+srcs.append("../lib/axis/rtl/axis_register.v")
+srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
+srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
+srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
+srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
+srcs.append("../lib/pcie/rtl/dma_if_mux.v")
+srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
+srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
+srcs.append("../lib/pcie/rtl/dma_psdpram.v")
+srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
+srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
+srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
+srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
+srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")
+srcs.append("../lib/pcie/rtl/pulse_merge.v")
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def frame_checksum(frame):
+ data = frame[14:]
+
+ csum = 0
+ odd = False
+
+ for b in data:
+ if odd:
+ csum += b
+ else:
+ csum += b << 8
+ odd = not odd
+
+ csum = (csum & 0xffff) + (csum >> 16)
+ csum = (csum & 0xffff) + (csum >> 16)
+
+ return csum
+
+def bench():
+
+ # Parameters
+ AXIS_PCIE_DATA_WIDTH = 256
+ AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32)
+ AXIS_PCIE_RC_USER_WIDTH = 75
+ AXIS_PCIE_RQ_USER_WIDTH = 60
+ AXIS_PCIE_CQ_USER_WIDTH = 85
+ AXIS_PCIE_CC_USER_WIDTH = 33
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ clk_156mhz = Signal(bool(0))
+ rst_156mhz = Signal(bool(0))
+ clk_250mhz = Signal(bool(0))
+ rst_250mhz = Signal(bool(0))
+ m_axis_rq_tready = Signal(bool(0))
+ s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
+ s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
+ s_axis_rc_tlast = Signal(bool(0))
+ s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
+ s_axis_rc_tvalid = Signal(bool(0))
+ s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
+ s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
+ s_axis_cq_tlast = Signal(bool(0))
+ s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
+ s_axis_cq_tvalid = Signal(bool(0))
+ m_axis_cc_tready = Signal(bool(0))
+ pcie_tfc_nph_av = Signal(intbv(0)[2:])
+ pcie_tfc_npd_av = Signal(intbv(0)[2:])
+ cfg_max_payload = Signal(intbv(0)[3:])
+ cfg_max_read_req = Signal(intbv(0)[3:])
+ cfg_mgmt_read_data = Signal(intbv(0)[32:])
+ cfg_mgmt_read_write_done = Signal(bool(0))
+ cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
+ cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:])
+ cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
+ cfg_interrupt_msi_mask_update = Signal(bool(0))
+ cfg_interrupt_msi_data = Signal(intbv(0)[32:])
+ cfg_interrupt_msi_sent = Signal(bool(0))
+ cfg_interrupt_msi_fail = Signal(bool(0))
+ sfp_1_tx_clk = Signal(bool(0))
+ sfp_1_tx_rst = Signal(bool(0))
+ sfp_1_rx_clk = Signal(bool(0))
+ sfp_1_rx_rst = Signal(bool(0))
+ sfp_1_rxd = Signal(intbv(0)[64:])
+ sfp_1_rxc = Signal(intbv(0)[8:])
+ sfp_2_tx_clk = Signal(bool(0))
+ sfp_2_tx_rst = Signal(bool(0))
+ sfp_2_rx_clk = Signal(bool(0))
+ sfp_2_rx_rst = Signal(bool(0))
+ sfp_2_rxd = Signal(intbv(0)[64:])
+ sfp_2_rxc = Signal(intbv(0)[8:])
+ sfp_i2c_scl_i = Signal(bool(1))
+ sfp_1_i2c_sda_i = Signal(bool(1))
+ sfp_2_i2c_sda_i = Signal(bool(1))
+ eeprom_i2c_scl_i = Signal(bool(1))
+ eeprom_i2c_sda_i = Signal(bool(1))
+ flash_dq_i = Signal(intbv(0)[16:])
+
+ # Outputs
+ sfp_1_led = Signal(intbv(0)[2:])
+ sfp_2_led = Signal(intbv(0)[2:])
+ sma_led = Signal(intbv(0)[2:])
+ m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
+ m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
+ m_axis_rq_tlast = Signal(bool(0))
+ m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
+ m_axis_rq_tvalid = Signal(bool(0))
+ s_axis_rc_tready = Signal(bool(0))
+ s_axis_cq_tready = Signal(bool(0))
+ m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
+ m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
+ m_axis_cc_tlast = Signal(bool(0))
+ m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:])
+ m_axis_cc_tvalid = Signal(bool(0))
+ status_error_cor = Signal(bool(0))
+ status_error_uncor = Signal(bool(0))
+ cfg_mgmt_addr = Signal(intbv(0)[19:])
+ cfg_mgmt_write = Signal(bool(0))
+ cfg_mgmt_write_data = Signal(intbv(0)[32:])
+ cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
+ cfg_mgmt_read = Signal(bool(0))
+ cfg_interrupt_msi_int = Signal(intbv(0)[32:])
+ cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
+ cfg_interrupt_msi_select = Signal(intbv(0)[4:])
+ cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:])
+ cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
+ cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
+ cfg_interrupt_msi_tph_present = Signal(bool(0))
+ cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
+ cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:])
+ cfg_interrupt_msi_function_number = Signal(intbv(0)[4:])
+ sfp_1_txd = Signal(intbv(0)[64:])
+ sfp_1_txc = Signal(intbv(0)[8:])
+ sfp_2_txd = Signal(intbv(0)[64:])
+ sfp_2_txc = Signal(intbv(0)[8:])
+ sfp_i2c_scl_o = Signal(bool(1))
+ sfp_i2c_scl_t = Signal(bool(1))
+ sfp_1_i2c_sda_o = Signal(bool(1))
+ sfp_1_i2c_sda_t = Signal(bool(1))
+ sfp_2_i2c_sda_o = Signal(bool(1))
+ sfp_2_i2c_sda_t = Signal(bool(1))
+ eeprom_i2c_scl_o = Signal(bool(1))
+ eeprom_i2c_scl_t = Signal(bool(1))
+ eeprom_i2c_sda_o = Signal(bool(1))
+ eeprom_i2c_sda_t = Signal(bool(1))
+ flash_dq_o = Signal(intbv(0)[16:])
+ flash_dq_oe = Signal(bool(0))
+ flash_addr = Signal(intbv(0)[23:])
+ flash_region = Signal(bool(0))
+ flash_region_oe = Signal(bool(0))
+ flash_ce_n = Signal(bool(1))
+ flash_oe_n = Signal(bool(1))
+ flash_we_n = Signal(bool(1))
+ flash_adv_n = Signal(bool(1))
+
+ # sources and sinks
+ sfp_1_source = xgmii_ep.XGMIISource()
+ sfp_1_source_logic = sfp_1_source.create_logic(sfp_1_rx_clk, sfp_1_rx_rst, txd=sfp_1_rxd, txc=sfp_1_rxc, name='sfp_1_source')
+
+ sfp_1_sink = xgmii_ep.XGMIISink()
+ sfp_1_sink_logic = sfp_1_sink.create_logic(sfp_1_tx_clk, sfp_1_tx_rst, rxd=sfp_1_txd, rxc=sfp_1_txc, name='sfp_1_sink')
+
+ sfp_2_source = xgmii_ep.XGMIISource()
+ sfp_2_source_logic = sfp_2_source.create_logic(sfp_2_rx_clk, sfp_2_rx_rst, txd=sfp_2_rxd, txc=sfp_2_rxc, name='sfp_2_source')
+
+ sfp_2_sink = xgmii_ep.XGMIISink()
+ sfp_2_sink_logic = sfp_2_sink.create_logic(sfp_2_tx_clk, sfp_2_tx_rst, rxd=sfp_2_txd, rxc=sfp_2_txc, name='sfp_2_sink')
+
+ # Clock and Reset Interface
+ user_clk=Signal(bool(0))
+ user_reset=Signal(bool(0))
+ sys_clk=Signal(bool(0))
+ sys_reset=Signal(bool(0))
+
+ # PCIe devices
+ rc = pcie.RootComplex()
+
+ rc.max_payload_size = 0x1 # 256 bytes
+ rc.max_read_request_size = 0x5 # 4096 bytes
+
+ driver = mqnic.Driver(rc)
+
+ dev = pcie_us.UltrascalePCIe()
+
+ dev.pcie_generation = 3
+ dev.pcie_link_width = 8
+ dev.user_clock_frequency = 256e6
+
+ dev.functions[0].msi_multiple_message_capable = 5
+
+ dev.functions[0].configure_bar(0, 16*1024*1024)
+ dev.functions[0].configure_bar(1, 16*1024*1024)
+
+ rc.make_port().connect(dev)
+
+ pcie_logic = dev.create_logic(
+ # Completer reQuest Interface
+ m_axis_cq_tdata=s_axis_cq_tdata,
+ m_axis_cq_tuser=s_axis_cq_tuser,
+ m_axis_cq_tlast=s_axis_cq_tlast,
+ m_axis_cq_tkeep=s_axis_cq_tkeep,
+ m_axis_cq_tvalid=s_axis_cq_tvalid,
+ m_axis_cq_tready=s_axis_cq_tready,
+ #pcie_cq_np_req=pcie_cq_np_req,
+ pcie_cq_np_req=Signal(bool(1)),
+ #pcie_cq_np_req_count=pcie_cq_np_req_count,
+
+ # Completer Completion Interface
+ s_axis_cc_tdata=m_axis_cc_tdata,
+ s_axis_cc_tuser=m_axis_cc_tuser,
+ s_axis_cc_tlast=m_axis_cc_tlast,
+ s_axis_cc_tkeep=m_axis_cc_tkeep,
+ s_axis_cc_tvalid=m_axis_cc_tvalid,
+ s_axis_cc_tready=m_axis_cc_tready,
+
+ # Requester reQuest Interface
+ s_axis_rq_tdata=m_axis_rq_tdata,
+ s_axis_rq_tuser=m_axis_rq_tuser,
+ s_axis_rq_tlast=m_axis_rq_tlast,
+ s_axis_rq_tkeep=m_axis_rq_tkeep,
+ s_axis_rq_tvalid=m_axis_rq_tvalid,
+ s_axis_rq_tready=m_axis_rq_tready,
+ #pcie_rq_seq_num=pcie_rq_seq_num,
+ #pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
+ #pcie_rq_tag=pcie_rq_tag,
+ #pcie_rq_tag_vld=pcie_rq_tag_vld,
+
+ # Requester Completion Interface
+ m_axis_rc_tdata=s_axis_rc_tdata,
+ m_axis_rc_tuser=s_axis_rc_tuser,
+ m_axis_rc_tlast=s_axis_rc_tlast,
+ m_axis_rc_tkeep=s_axis_rc_tkeep,
+ m_axis_rc_tvalid=s_axis_rc_tvalid,
+ m_axis_rc_tready=s_axis_rc_tready,
+
+ # Transmit Flow Control Interface
+ pcie_tfc_nph_av=pcie_tfc_nph_av,
+ pcie_tfc_npd_av=pcie_tfc_npd_av,
+
+ # Configuration Management Interface
+ cfg_mgmt_addr=cfg_mgmt_addr,
+ cfg_mgmt_write=cfg_mgmt_write,
+ cfg_mgmt_write_data=cfg_mgmt_write_data,
+ cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
+ cfg_mgmt_read=cfg_mgmt_read,
+ cfg_mgmt_read_data=cfg_mgmt_read_data,
+ cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
+ #cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access,
+
+ # Configuration Status Interface
+ #cfg_phy_link_down=cfg_phy_link_down,
+ #cfg_phy_link_status=cfg_phy_link_status,
+ #cfg_negotiated_width=cfg_negotiated_width,
+ #cfg_current_speed=cfg_current_speed,
+ cfg_max_payload=cfg_max_payload,
+ cfg_max_read_req=cfg_max_read_req,
+ #cfg_function_status=cfg_function_status,
+ #cfg_vf_status=cfg_vf_status,
+ #cfg_function_power_state=cfg_function_power_state,
+ #cfg_vf_power_state=cfg_vf_power_state,
+ #cfg_link_power_state=cfg_link_power_state,
+ #cfg_err_cor_out=cfg_err_cor_out,
+ #cfg_err_nonfatal_out=cfg_err_nonfatal_out,
+ #cfg_err_fatal_out=cfg_err_fatal_out,
+ #cfg_ltr_enable=cfg_ltr_enable,
+ #cfg_ltssm_state=cfg_ltssm_state,
+ #cfg_rcb_status=cfg_rcb_status,
+ #cfg_dpa_substate_change=cfg_dpa_substate_change,
+ #cfg_obff_enable=cfg_obff_enable,
+ #cfg_pl_status_change=cfg_pl_status_change,
+ #cfg_tph_requester_enable=cfg_tph_requester_enable,
+ #cfg_tph_st_mode=cfg_tph_st_mode,
+ #cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
+ #cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
+
+ # Configuration Received Message Interface
+ #cfg_msg_received=cfg_msg_received,
+ #cfg_msg_received_data=cfg_msg_received_data,
+ #cfg_msg_received_type=cfg_msg_received_type,
+
+ # Configuration Transmit Message Interface
+ #cfg_msg_transmit=cfg_msg_transmit,
+ #cfg_msg_transmit_type=cfg_msg_transmit_type,
+ #cfg_msg_transmit_data=cfg_msg_transmit_data,
+ #cfg_msg_transmit_done=cfg_msg_transmit_done,
+
+ # Configuration Flow Control Interface
+ #cfg_fc_ph=cfg_fc_ph,
+ #cfg_fc_pd=cfg_fc_pd,
+ #cfg_fc_nph=cfg_fc_nph,
+ #cfg_fc_npd=cfg_fc_npd,
+ #cfg_fc_cplh=cfg_fc_cplh,
+ #cfg_fc_cpld=cfg_fc_cpld,
+ #cfg_fc_sel=cfg_fc_sel,
+
+ # Per-Function Status Interface
+ #cfg_per_func_status_control=cfg_per_func_status_control,
+ #cfg_per_func_status_data=cfg_per_func_status_data,
+
+ # Configuration Control Interface
+ #cfg_hot_reset_in=cfg_hot_reset_in,
+ #cfg_hot_reset_out=cfg_hot_reset_out,
+ #cfg_config_space_enable=cfg_config_space_enable,
+ #cfg_per_function_update_done=cfg_per_function_update_done,
+ #cfg_per_function_number=cfg_per_function_number,
+ #cfg_per_function_output_request=cfg_per_function_output_request,
+ #cfg_dsn=cfg_dsn,
+ #cfg_ds_bus_number=cfg_ds_bus_number,
+ #cfg_ds_device_number=cfg_ds_device_number,
+ #cfg_ds_function_number=cfg_ds_function_number,
+ #cfg_power_state_change_ack=cfg_power_state_change_ack,
+ #cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
+ cfg_err_cor_in=status_error_cor,
+ cfg_err_uncor_in=status_error_uncor,
+ #cfg_flr_done=cfg_flr_done,
+ #cfg_vf_flr_done=cfg_vf_flr_done,
+ #cfg_flr_in_process=cfg_flr_in_process,
+ #cfg_vf_flr_in_process=cfg_vf_flr_in_process,
+ #cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
+ #cfg_link_training_enable=cfg_link_training_enable,
+
+ # Configuration Interrupt Controller Interface
+ #cfg_interrupt_int=cfg_interrupt_int,
+ #cfg_interrupt_sent=cfg_interrupt_sent,
+ #cfg_interrupt_pending=cfg_interrupt_pending,
+ cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
+ cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
+ cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
+ cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
+ cfg_interrupt_msi_data=cfg_interrupt_msi_data,
+ cfg_interrupt_msi_select=cfg_interrupt_msi_select,
+ cfg_interrupt_msi_int=cfg_interrupt_msi_int,
+ cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
+ cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
+ cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
+ cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
+ cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
+ #cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
+ #cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
+ #cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
+ #cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
+ #cfg_interrupt_msix_address=cfg_interrupt_msix_address,
+ #cfg_interrupt_msix_data=cfg_interrupt_msix_data,
+ #cfg_interrupt_msix_int=cfg_interrupt_msix_int,
+ #cfg_interrupt_msix_sent=cfg_interrupt_msix_sent,
+ #cfg_interrupt_msix_fail=cfg_interrupt_msix_fail,
+ cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
+ cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
+ cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
+ cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
+ cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
+
+ # Configuration Extend Interface
+ #cfg_ext_read_received=cfg_ext_read_received,
+ #cfg_ext_write_received=cfg_ext_write_received,
+ #cfg_ext_register_number=cfg_ext_register_number,
+ #cfg_ext_function_number=cfg_ext_function_number,
+ #cfg_ext_write_data=cfg_ext_write_data,
+ #cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
+ #cfg_ext_read_data=cfg_ext_read_data,
+ #cfg_ext_read_data_valid=cfg_ext_read_data_valid,
+
+ # Clock and Reset Interface
+ user_clk=user_clk,
+ user_reset=user_reset,
+ sys_clk=sys_clk,
+ sys_clk_gt=sys_clk,
+ sys_reset=sys_reset,
+ #pcie_perstn0_out=pcie_perstn0_out,
+ #pcie_perstn1_in=pcie_perstn1_in,
+ #pcie_perstn1_out=pcie_perstn1_out
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+ clk_156mhz=clk_156mhz,
+ rst_156mhz=rst_156mhz,
+ clk_250mhz=user_clk,
+ rst_250mhz=user_reset,
+ sfp_1_led=sfp_1_led,
+ sfp_2_led=sfp_2_led,
+ sma_led=sma_led,
+ m_axis_rq_tdata=m_axis_rq_tdata,
+ m_axis_rq_tkeep=m_axis_rq_tkeep,
+ m_axis_rq_tlast=m_axis_rq_tlast,
+ m_axis_rq_tready=m_axis_rq_tready,
+ m_axis_rq_tuser=m_axis_rq_tuser,
+ m_axis_rq_tvalid=m_axis_rq_tvalid,
+ s_axis_rc_tdata=s_axis_rc_tdata,
+ s_axis_rc_tkeep=s_axis_rc_tkeep,
+ s_axis_rc_tlast=s_axis_rc_tlast,
+ s_axis_rc_tready=s_axis_rc_tready,
+ s_axis_rc_tuser=s_axis_rc_tuser,
+ s_axis_rc_tvalid=s_axis_rc_tvalid,
+ s_axis_cq_tdata=s_axis_cq_tdata,
+ s_axis_cq_tkeep=s_axis_cq_tkeep,
+ s_axis_cq_tlast=s_axis_cq_tlast,
+ s_axis_cq_tready=s_axis_cq_tready,
+ s_axis_cq_tuser=s_axis_cq_tuser,
+ s_axis_cq_tvalid=s_axis_cq_tvalid,
+ m_axis_cc_tdata=m_axis_cc_tdata,
+ m_axis_cc_tkeep=m_axis_cc_tkeep,
+ m_axis_cc_tlast=m_axis_cc_tlast,
+ m_axis_cc_tready=m_axis_cc_tready,
+ m_axis_cc_tuser=m_axis_cc_tuser,
+ m_axis_cc_tvalid=m_axis_cc_tvalid,
+ pcie_tfc_nph_av=pcie_tfc_nph_av,
+ pcie_tfc_npd_av=pcie_tfc_npd_av,
+ cfg_max_payload=cfg_max_payload,
+ cfg_max_read_req=cfg_max_read_req,
+ cfg_mgmt_addr=cfg_mgmt_addr,
+ cfg_mgmt_write=cfg_mgmt_write,
+ cfg_mgmt_write_data=cfg_mgmt_write_data,
+ cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
+ cfg_mgmt_read=cfg_mgmt_read,
+ cfg_mgmt_read_data=cfg_mgmt_read_data,
+ cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
+ cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
+ cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
+ cfg_interrupt_msi_int=cfg_interrupt_msi_int,
+ cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
+ cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
+ cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
+ cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
+ cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
+ cfg_interrupt_msi_select=cfg_interrupt_msi_select,
+ cfg_interrupt_msi_data=cfg_interrupt_msi_data,
+ cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
+ cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
+ cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
+ cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
+ cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
+ cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
+ cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
+ status_error_cor=status_error_cor,
+ status_error_uncor=status_error_uncor,
+ sfp_1_tx_clk=sfp_1_tx_clk,
+ sfp_1_tx_rst=sfp_1_tx_rst,
+ sfp_1_txd=sfp_1_txd,
+ sfp_1_txc=sfp_1_txc,
+ sfp_1_rx_clk=sfp_1_rx_clk,
+ sfp_1_rx_rst=sfp_1_rx_rst,
+ sfp_1_rxd=sfp_1_rxd,
+ sfp_1_rxc=sfp_1_rxc,
+ sfp_2_tx_clk=sfp_2_tx_clk,
+ sfp_2_tx_rst=sfp_2_tx_rst,
+ sfp_2_txd=sfp_2_txd,
+ sfp_2_txc=sfp_2_txc,
+ sfp_2_rx_clk=sfp_2_rx_clk,
+ sfp_2_rx_rst=sfp_2_rx_rst,
+ sfp_2_rxd=sfp_2_rxd,
+ sfp_2_rxc=sfp_2_rxc,
+ sfp_i2c_scl_i=sfp_i2c_scl_i,
+ sfp_i2c_scl_o=sfp_i2c_scl_o,
+ sfp_i2c_scl_t=sfp_i2c_scl_t,
+ sfp_1_i2c_sda_i=sfp_1_i2c_sda_i,
+ sfp_1_i2c_sda_o=sfp_1_i2c_sda_o,
+ sfp_1_i2c_sda_t=sfp_1_i2c_sda_t,
+ sfp_2_i2c_sda_i=sfp_2_i2c_sda_i,
+ sfp_2_i2c_sda_o=sfp_2_i2c_sda_o,
+ sfp_2_i2c_sda_t=sfp_2_i2c_sda_t,
+ eeprom_i2c_scl_i=eeprom_i2c_scl_i,
+ eeprom_i2c_scl_o=eeprom_i2c_scl_o,
+ eeprom_i2c_scl_t=eeprom_i2c_scl_t,
+ eeprom_i2c_sda_i=eeprom_i2c_sda_i,
+ eeprom_i2c_sda_o=eeprom_i2c_sda_o,
+ eeprom_i2c_sda_t=eeprom_i2c_sda_t,
+ flash_dq_i=flash_dq_i,
+ flash_dq_o=flash_dq_o,
+ flash_dq_oe=flash_dq_oe,
+ flash_addr=flash_addr,
+ flash_region=flash_region,
+ flash_region_oe=flash_region_oe,
+ flash_ce_n=flash_ce_n,
+ flash_oe_n=flash_oe_n,
+ flash_we_n=flash_we_n,
+ flash_adv_n=flash_adv_n
+ )
+
+ @always(delay(5))
+ def clkgen():
+ clk.next = not clk
+
+ @always_comb
+ def clk_logic():
+ sys_clk.next = clk
+ sys_reset.next = not rst
+
+ sfp_1_tx_clk.next = clk
+ sfp_1_tx_rst.next = rst
+ sfp_1_rx_clk.next = clk
+ sfp_1_rx_rst.next = rst
+ sfp_2_tx_clk.next = clk
+ sfp_2_tx_rst.next = rst
+ sfp_2_rx_clk.next = clk
+ sfp_2_rx_rst.next = rst
+
+ loopback_enable = Signal(bool(0))
+
+ @instance
+ def loopback():
+ while True:
+
+ yield clk.posedge
+
+ if loopback_enable:
+ if not sfp_1_sink.empty():
+ pkt = sfp_1_sink.recv()
+ sfp_1_source.send(pkt)
+ if not sfp_2_sink.empty():
+ pkt = sfp_2_sink.recv()
+ sfp_2_source.send(pkt)
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ # testbench stimulus
+
+ current_tag = 1
+
+ yield clk.posedge
+ print("test 1: enumeration")
+ current_test.next = 1
+
+ yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
+
+ dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
+ dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
+
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x270, 0);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x274, 0);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x278, 0);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x27C, 0);
+
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x290, 0);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x294, 1000);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x298, 0);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x29C, 0);
+
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x280, 0);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x284, 2000);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x288, 0);
+ yield from rc.mem_write_dword(dev_pf0_bar0+0x28C, 0);
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: init NIC")
+ current_test.next = 2
+
+ yield from driver.init_dev(dev.functions[0].get_id())
+ yield from driver.interfaces[0].open()
+
+ # enable queues
+ yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0040, 0x00000001)
+ for k in range(32):
+ yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+4*k, 0x00000001)
+
+ yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: send and receive a packet")
+ current_test.next = 3
+
+ data = bytearray([x%256 for x in range(1024)])
+
+ yield from driver.interfaces[0].start_xmit(data, 0)
+
+ yield sfp_1_sink.wait()
+
+ pkt = sfp_1_sink.recv()
+ print(pkt)
+
+ sfp_1_source.send(pkt)
+
+ yield driver.interfaces[0].wait()
+
+ pkt = driver.interfaces[0].recv()
+
+ print(pkt)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: checksum tests")
+ current_test.next = 4
+
+ test_frame = udp_ep.UDPFrame()
+ test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
+ test_frame.eth_src_mac = 0x5A5152535455
+ test_frame.eth_type = 0x0800
+ test_frame.ip_version = 4
+ test_frame.ip_ihl = 5
+ test_frame.ip_length = None
+ test_frame.ip_identification = 0
+ test_frame.ip_flags = 2
+ test_frame.ip_fragment_offset = 0
+ test_frame.ip_ttl = 64
+ test_frame.ip_protocol = 0x11
+ test_frame.ip_header_checksum = None
+ test_frame.ip_source_ip = 0xc0a80164
+ test_frame.ip_dest_ip = 0xc0a80165
+ test_frame.udp_source_port = 1
+ test_frame.udp_dest_port = 2
+ test_frame.udp_length = None
+ test_frame.udp_checksum = None
+ test_frame.payload = bytearray((x%256 for x in range(256)))
+
+ test_frame.set_udp_pseudo_header_checksum()
+
+ axis_frame = test_frame.build_axis()
+
+ yield from driver.interfaces[0].start_xmit(axis_frame.data, 0, 34, 6)
+
+ yield sfp_1_sink.wait()
+
+ pkt = sfp_1_sink.recv()
+ print(pkt)
+
+ sfp_1_source.send(pkt)
+
+ yield driver.interfaces[0].wait()
+
+ pkt = driver.interfaces[0].recv()
+
+ print(pkt)
+
+ assert pkt.rx_checksum == frame_checksum(pkt.data)
+
+ check_frame = udp_ep.UDPFrame()
+ check_frame.parse_axis(pkt.data)
+
+ assert check_frame.verify_checksums()
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 5: multiple small packets")
+ current_test.next = 5
+
+ count = 64
+
+ pkts = [bytearray([(x+k)%256 for x in range(64)]) for k in range(count)]
+
+ loopback_enable.next = True
+
+ for p in pkts:
+ yield from driver.interfaces[0].start_xmit(p, 0)
+
+ for k in range(count):
+ pkt = driver.interfaces[0].recv()
+
+ if not pkt:
+ yield driver.interfaces[0].wait()
+ pkt = driver.interfaces[0].recv()
+
+ print(pkt)
+ assert pkt.data == pkts[k]
+ assert frame_checksum(pkt.data) == pkt.rx_checksum
+
+ loopback_enable.next = False
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 6: multiple large packets")
+ current_test.next = 6
+
+ count = 64
+
+ pkts = [bytearray([(x+k)%256 for x in range(1514)]) for k in range(count)]
+
+ loopback_enable.next = True
+
+ for p in pkts:
+ yield from driver.interfaces[0].start_xmit(p, 0)
+
+ for k in range(count):
+ pkt = driver.interfaces[0].recv()
+
+ if not pkt:
+ yield driver.interfaces[0].wait()
+ pkt = driver.interfaces[0].recv()
+
+ print(pkt)
+ assert pkt.data == pkts[k]
+ assert frame_checksum(pkt.data) == pkt.rx_checksum
+
+ loopback_enable.next = False
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v
new file mode 100644
index 000000000..3ef04a079
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v
@@ -0,0 +1,389 @@
+/*
+
+Copyright 2019, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for fpga_core
+ */
+module test_fpga_core;
+
+// Parameters
+parameter AXIS_PCIE_DATA_WIDTH = 256;
+parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
+parameter AXIS_PCIE_RC_USER_WIDTH = 75;
+parameter AXIS_PCIE_RQ_USER_WIDTH = 60;
+parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
+parameter AXIS_PCIE_CC_USER_WIDTH = 33;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg clk_156mhz = 0;
+reg rst_156mhz = 0;
+reg clk_250mhz = 0;
+reg rst_250mhz = 0;
+reg m_axis_rq_tready = 0;
+reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata = 0;
+reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep = 0;
+reg s_axis_rc_tlast = 0;
+reg [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser = 0;
+reg s_axis_rc_tvalid = 0;
+reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0;
+reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0;
+reg s_axis_cq_tlast = 0;
+reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
+reg s_axis_cq_tvalid = 0;
+reg m_axis_cc_tready = 0;
+reg [1:0] pcie_tfc_nph_av = 0;
+reg [1:0] pcie_tfc_npd_av = 0;
+reg [2:0] cfg_max_payload = 0;
+reg [2:0] cfg_max_read_req = 0;
+reg [31:0] cfg_mgmt_read_data = 0;
+reg cfg_mgmt_read_write_done = 0;
+reg [3:0] cfg_interrupt_msi_enable = 0;
+reg [7:0] cfg_interrupt_msi_vf_enable = 0;
+reg [11:0] cfg_interrupt_msi_mmenable = 0;
+reg cfg_interrupt_msi_mask_update = 0;
+reg [31:0] cfg_interrupt_msi_data = 0;
+reg cfg_interrupt_msi_sent = 0;
+reg cfg_interrupt_msi_fail = 0;
+reg sfp_1_tx_clk = 0;
+reg sfp_1_tx_rst = 0;
+reg sfp_1_rx_clk = 0;
+reg sfp_1_rx_rst = 0;
+reg [63:0] sfp_1_rxd = 0;
+reg [7:0] sfp_1_rxc = 0;
+reg sfp_2_tx_clk = 0;
+reg sfp_2_tx_rst = 0;
+reg sfp_2_rx_clk = 0;
+reg sfp_2_rx_rst = 0;
+reg [63:0] sfp_2_rxd = 0;
+reg [7:0] sfp_2_rxc = 0;
+reg sfp_i2c_scl_i = 1;
+reg sfp_1_i2c_sda_i = 1;
+reg sfp_2_i2c_sda_i = 1;
+reg eeprom_i2c_scl_i = 1;
+reg eeprom_i2c_sda_i = 1;
+reg [15:0] flash_dq_i = 0;
+
+// Outputs
+wire [1:0] sfp_1_led;
+wire [1:0] sfp_2_led;
+wire [1:0] sma_led;
+wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep;
+wire m_axis_rq_tlast;
+wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser;
+wire m_axis_rq_tvalid;
+wire s_axis_rc_tready;
+wire s_axis_cq_tready;
+wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep;
+wire m_axis_cc_tlast;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser;
+wire m_axis_cc_tvalid;
+wire [18:0] cfg_mgmt_addr;
+wire cfg_mgmt_write;
+wire [31:0] cfg_mgmt_write_data;
+wire [3:0] cfg_mgmt_byte_enable;
+wire cfg_mgmt_read;
+wire [3:0] cfg_interrupt_msi_select;
+wire [31:0] cfg_interrupt_msi_int;
+wire [31:0] cfg_interrupt_msi_pending_status;
+wire cfg_interrupt_msi_pending_status_data_enable;
+wire [3:0] cfg_interrupt_msi_pending_status_function_num;
+wire [2:0] cfg_interrupt_msi_attr;
+wire cfg_interrupt_msi_tph_present;
+wire [1:0] cfg_interrupt_msi_tph_type;
+wire [8:0] cfg_interrupt_msi_tph_st_tag;
+wire [3:0] cfg_interrupt_msi_function_number;
+wire status_error_cor;
+wire status_error_uncor;
+wire [63:0] sfp_1_txd;
+wire [7:0] sfp_1_txc;
+wire [63:0] sfp_2_txd;
+wire [7:0] sfp_2_txc;
+wire sfp_i2c_scl_o;
+wire sfp_i2c_scl_t;
+wire sfp_1_i2c_sda_o;
+wire sfp_1_i2c_sda_t;
+wire sfp_2_i2c_sda_o;
+wire sfp_2_i2c_sda_t;
+wire eeprom_i2c_scl_o;
+wire eeprom_i2c_scl_t;
+wire eeprom_i2c_sda_o;
+wire eeprom_i2c_sda_t;
+wire [15:0] flash_dq_o;
+wire flash_dq_oe;
+wire [22:0] flash_addr;
+wire flash_region;
+wire flash_region_oe;
+wire flash_ce_n;
+wire flash_oe_n;
+wire flash_we_n;
+wire flash_adv_n;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk_156mhz,
+ rst_156mhz,
+ clk_250mhz,
+ rst_250mhz,
+ current_test,
+ m_axis_rq_tready,
+ s_axis_rc_tdata,
+ s_axis_rc_tkeep,
+ s_axis_rc_tlast,
+ s_axis_rc_tuser,
+ s_axis_rc_tvalid,
+ s_axis_cq_tdata,
+ s_axis_cq_tkeep,
+ s_axis_cq_tlast,
+ s_axis_cq_tuser,
+ s_axis_cq_tvalid,
+ m_axis_cc_tready,
+ pcie_tfc_nph_av,
+ pcie_tfc_npd_av,
+ cfg_max_payload,
+ cfg_max_read_req,
+ cfg_mgmt_read_data,
+ cfg_mgmt_read_write_done,
+ cfg_interrupt_msi_enable,
+ cfg_interrupt_msi_vf_enable,
+ cfg_interrupt_msi_mmenable,
+ cfg_interrupt_msi_mask_update,
+ cfg_interrupt_msi_data,
+ cfg_interrupt_msi_sent,
+ cfg_interrupt_msi_fail,
+ sfp_1_tx_clk,
+ sfp_1_tx_rst,
+ sfp_1_rx_clk,
+ sfp_1_rx_rst,
+ sfp_1_rxd,
+ sfp_1_rxc,
+ sfp_2_tx_clk,
+ sfp_2_tx_rst,
+ sfp_2_rx_clk,
+ sfp_2_rx_rst,
+ sfp_2_rxd,
+ sfp_2_rxc,
+ sfp_i2c_scl_i,
+ sfp_1_i2c_sda_i,
+ sfp_2_i2c_sda_i,
+ eeprom_i2c_scl_i,
+ eeprom_i2c_sda_i,
+ flash_dq_i
+ );
+ $to_myhdl(
+ sfp_1_led,
+ sfp_2_led,
+ sma_led,
+ m_axis_rq_tdata,
+ m_axis_rq_tkeep,
+ m_axis_rq_tlast,
+ m_axis_rq_tuser,
+ m_axis_rq_tvalid,
+ s_axis_rc_tready,
+ s_axis_cq_tready,
+ m_axis_cc_tdata,
+ m_axis_cc_tkeep,
+ m_axis_cc_tlast,
+ m_axis_cc_tuser,
+ m_axis_cc_tvalid,
+ cfg_mgmt_addr,
+ cfg_mgmt_write,
+ cfg_mgmt_write_data,
+ cfg_mgmt_byte_enable,
+ cfg_mgmt_read,
+ cfg_interrupt_msi_select,
+ cfg_interrupt_msi_int,
+ cfg_interrupt_msi_pending_status,
+ cfg_interrupt_msi_pending_status_data_enable,
+ cfg_interrupt_msi_pending_status_function_num,
+ cfg_interrupt_msi_attr,
+ cfg_interrupt_msi_tph_present,
+ cfg_interrupt_msi_tph_type,
+ cfg_interrupt_msi_tph_st_tag,
+ cfg_interrupt_msi_function_number,
+ status_error_cor,
+ status_error_uncor,
+ sfp_1_txd,
+ sfp_1_txc,
+ sfp_2_txd,
+ sfp_2_txc,
+ sfp_i2c_scl_o,
+ sfp_i2c_scl_t,
+ sfp_1_i2c_sda_o,
+ sfp_1_i2c_sda_t,
+ sfp_2_i2c_sda_o,
+ sfp_2_i2c_sda_t,
+ eeprom_i2c_scl_o,
+ eeprom_i2c_scl_t,
+ eeprom_i2c_sda_o,
+ eeprom_i2c_sda_t,
+ flash_dq_o,
+ flash_dq_oe,
+ flash_addr,
+ flash_region,
+ flash_region_oe,
+ flash_ce_n,
+ flash_oe_n,
+ flash_we_n,
+ flash_adv_n
+ );
+
+ // dump file
+ $dumpfile("test_fpga_core.lxt");
+ $dumpvars(0, test_fpga_core);
+end
+
+fpga_core #(
+ .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+ .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+ .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+ .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+ .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+ .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
+)
+UUT (
+ .clk_156mhz(clk_156mhz),
+ .rst_156mhz(rst_156mhz),
+ .clk_250mhz(clk_250mhz),
+ .rst_250mhz(rst_250mhz),
+ .sfp_1_led(sfp_1_led),
+ .sfp_2_led(sfp_2_led),
+ .sma_led(sma_led),
+ .m_axis_rq_tdata(m_axis_rq_tdata),
+ .m_axis_rq_tkeep(m_axis_rq_tkeep),
+ .m_axis_rq_tlast(m_axis_rq_tlast),
+ .m_axis_rq_tready(m_axis_rq_tready),
+ .m_axis_rq_tuser(m_axis_rq_tuser),
+ .m_axis_rq_tvalid(m_axis_rq_tvalid),
+ .s_axis_rc_tdata(s_axis_rc_tdata),
+ .s_axis_rc_tkeep(s_axis_rc_tkeep),
+ .s_axis_rc_tlast(s_axis_rc_tlast),
+ .s_axis_rc_tready(s_axis_rc_tready),
+ .s_axis_rc_tuser(s_axis_rc_tuser),
+ .s_axis_rc_tvalid(s_axis_rc_tvalid),
+ .s_axis_cq_tdata(s_axis_cq_tdata),
+ .s_axis_cq_tkeep(s_axis_cq_tkeep),
+ .s_axis_cq_tlast(s_axis_cq_tlast),
+ .s_axis_cq_tready(s_axis_cq_tready),
+ .s_axis_cq_tuser(s_axis_cq_tuser),
+ .s_axis_cq_tvalid(s_axis_cq_tvalid),
+ .m_axis_cc_tdata(m_axis_cc_tdata),
+ .m_axis_cc_tkeep(m_axis_cc_tkeep),
+ .m_axis_cc_tlast(m_axis_cc_tlast),
+ .m_axis_cc_tready(m_axis_cc_tready),
+ .m_axis_cc_tuser(m_axis_cc_tuser),
+ .m_axis_cc_tvalid(m_axis_cc_tvalid),
+ .pcie_tfc_nph_av(pcie_tfc_nph_av),
+ .pcie_tfc_npd_av(pcie_tfc_npd_av),
+ .cfg_max_payload(cfg_max_payload),
+ .cfg_max_read_req(cfg_max_read_req),
+ .cfg_mgmt_addr(cfg_mgmt_addr),
+ .cfg_mgmt_write(cfg_mgmt_write),
+ .cfg_mgmt_write_data(cfg_mgmt_write_data),
+ .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+ .cfg_mgmt_read(cfg_mgmt_read),
+ .cfg_mgmt_read_data(cfg_mgmt_read_data),
+ .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+ .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+ .cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
+ .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+ .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+ .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+ .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+ .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+ .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+ .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+ .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+ .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+ .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+ .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+ .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+ .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+ .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+ .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+ .status_error_cor(status_error_cor),
+ .status_error_uncor(status_error_uncor),
+ .sfp_1_tx_clk(sfp_1_tx_clk),
+ .sfp_1_tx_rst(sfp_1_tx_rst),
+ .sfp_1_txd(sfp_1_txd),
+ .sfp_1_txc(sfp_1_txc),
+ .sfp_1_rx_clk(sfp_1_rx_clk),
+ .sfp_1_rx_rst(sfp_1_rx_rst),
+ .sfp_1_rxd(sfp_1_rxd),
+ .sfp_1_rxc(sfp_1_rxc),
+ .sfp_2_tx_clk(sfp_2_tx_clk),
+ .sfp_2_tx_rst(sfp_2_tx_rst),
+ .sfp_2_txd(sfp_2_txd),
+ .sfp_2_txc(sfp_2_txc),
+ .sfp_2_rx_clk(sfp_2_rx_clk),
+ .sfp_2_rx_rst(sfp_2_rx_rst),
+ .sfp_2_rxd(sfp_2_rxd),
+ .sfp_2_rxc(sfp_2_rxc),
+ .sfp_i2c_scl_i(sfp_i2c_scl_i),
+ .sfp_i2c_scl_o(sfp_i2c_scl_o),
+ .sfp_i2c_scl_t(sfp_i2c_scl_t),
+ .sfp_1_i2c_sda_i(sfp_1_i2c_sda_i),
+ .sfp_1_i2c_sda_o(sfp_1_i2c_sda_o),
+ .sfp_1_i2c_sda_t(sfp_1_i2c_sda_t),
+ .sfp_2_i2c_sda_i(sfp_2_i2c_sda_i),
+ .sfp_2_i2c_sda_o(sfp_2_i2c_sda_o),
+ .sfp_2_i2c_sda_t(sfp_2_i2c_sda_t),
+ .eeprom_i2c_scl_i(eeprom_i2c_scl_i),
+ .eeprom_i2c_scl_o(eeprom_i2c_scl_o),
+ .eeprom_i2c_scl_t(eeprom_i2c_scl_t),
+ .eeprom_i2c_sda_i(eeprom_i2c_sda_i),
+ .eeprom_i2c_sda_o(eeprom_i2c_sda_o),
+ .eeprom_i2c_sda_t(eeprom_i2c_sda_t),
+ .flash_dq_i(flash_dq_i),
+ .flash_dq_o(flash_dq_o),
+ .flash_dq_oe(flash_dq_oe),
+ .flash_addr(flash_addr),
+ .flash_region(flash_region),
+ .flash_region_oe(flash_region_oe),
+ .flash_ce_n(flash_ce_n),
+ .flash_oe_n(flash_oe_n),
+ .flash_we_n(flash_we_n),
+ .flash_adv_n(flash_adv_n)
+);
+
+endmodule
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/udp_ep.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/udp_ep.py
new file mode 120000
index 000000000..073c5d3c6
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/udp_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/udp_ep.py
\ No newline at end of file
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/xgmii_ep.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/xgmii_ep.py
new file mode 120000
index 000000000..63b6d3567
--- /dev/null
+++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/xgmii_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/xgmii_ep.py
\ No newline at end of file
diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h
index f2158ec17..f071d103b 100644
--- a/modules/mqnic/mqnic_hw.h
+++ b/modules/mqnic/mqnic_hw.h
@@ -48,6 +48,7 @@ either expressed or implied, of The Regents of the University of California.
#define MQNIC_BOARD_ID_VCU108 0x10ee806c
#define MQNIC_BOARD_ID_VCU118 0x10ee9076
#define MQNIC_BOARD_ID_EXANIC_X10 0x1ce40003
+#define MQNIC_BOARD_ID_EXANIC_X25 0x1ce40009
#define MQNIC_BOARD_ID_ADM_PCIE_9V3 0x41449003
// NIC CSRs
diff --git a/modules/mqnic/mqnic_i2c.c b/modules/mqnic/mqnic_i2c.c
index 65433377c..d6c5d499f 100644
--- a/modules/mqnic/mqnic_i2c.c
+++ b/modules/mqnic/mqnic_i2c.c
@@ -97,6 +97,7 @@ int mqnic_init_i2c(struct mqnic_dev *mqnic)
// eeprom i2c interface
switch (mqnic->board_id) {
case MQNIC_BOARD_ID_EXANIC_X10:
+ case MQNIC_BOARD_ID_EXANIC_X25:
case MQNIC_BOARD_ID_ADM_PCIE_9V3:
mqnic->eeprom_i2c_adap.owner = THIS_MODULE;
mqnic->eeprom_i2c_priv.mqnic = mqnic;