From f4a85616525a4e983a0129919832e177081f3715 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 21 Jul 2023 18:16:59 -0700 Subject: [PATCH] Add HTG-9200 + HTG 6x QSFP28 example design Signed-off-by: Alex Forencich --- .../HTG9200/fpga_fmc_htg_6qsfp_25g/README.md | 28 + .../fpga_fmc_htg_6qsfp_25g/common/vivado.mk | 137 + .../HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc | 1087 ++++ .../fpga_fmc_htg_6qsfp_25g/fpga/Makefile | 115 + .../fpga_fmc_htg_6qsfp_25g/fpga/config.tcl | 50 + .../fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile | 115 + .../fpga_10g/config.tcl | 50 + .../fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl | 76 + .../HTG9200/fpga_fmc_htg_6qsfp_25g/lib/eth | 1 + .../pll/HTG9200_161-9k2_161-Registers.txt | 412 ++ .../pll/HTG9200_161-9k2_161.slabtimeproj | Bin 0 -> 10192 bytes ...0_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt | 412 ++ ...00_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj | Bin 0 -> 10144 bytes .../pll/si5341_i2c_init.py | 606 +++ .../pll/si5341_i2c_init.v | 1600 ++++++ .../rtl/debounce_switch.v | 93 + .../rtl/eth_xcvr_phy_wrapper.v | 299 ++ .../HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v | 4676 +++++++++++++++++ .../fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v | 1213 +++++ .../fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v | 901 ++++ .../fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v | 62 + .../tb/fpga_core/Makefile | 95 + .../tb/fpga_core/test_fpga_core.py | 865 +++ 23 files changed, 12893 insertions(+) create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/README.md create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/common/vivado.mk create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl create mode 120000 example/HTG9200/fpga_fmc_htg_6qsfp_25g/lib/eth create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161-Registers.txt create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161.slabtimeproj create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj create mode 100755 example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile create mode 100644 example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/README.md b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/README.md new file mode 100644 index 000000000..7c285603e --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/README.md @@ -0,0 +1,28 @@ +# Verilog Ethernet HTG-9200 + HTG 6x QSFP28 FMC+ Example Design + +## Introduction + +This example design targets the HiTech Global HTG-9200 FPGA board with the HiTech Global HTG-FMC-X6QSFP28 FMC+ board installed on J9. + +The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. + +The design is configured to run all 15 QSFP28 modules synchronous to the GTY reference oscillator (U47) on the HTG-9200. This is done by forwarding the MGT reference clock for QSFP1 through the FPGA to the SYNC_C2M pins on the FMC+, which is connected as a reference input to the Si5341 PLL (U7) on the FMC+. + +* FPGA: xcvu9p-flgb2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver + +## How to build + +Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH. + +## How to test + +Run make program to program the HTG-9200 board with Vivado. Then run + + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/common/vivado.mk b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc new file mode 100644 index 000000000..119f122d1 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc @@ -0,0 +1,1087 @@ +# XDC constraints for the HiTech Global HTG-9200 board +# part: xcvu9p-flgb2104-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] + +# System clocks +# DDR4 clocks from U5 (200 MHz) +#set_property -dict {LOC C36 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_p] +#set_property -dict {LOC C37 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_n] +#create_clock -period 5.000 -name sys_clk_ddr4_a [get_ports sys_clk_ddr4_a_p] + +#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_b_p] +#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_b_n] +#create_clock -period 5.000 -name sys_clk_ddr4_b [get_ports sys_clk_ddr4_b_p] + +# refclk from U24 (200 MHz) +set_property -dict {LOC AV26 IOSTANDARD LVDS} [get_ports ref_clk_p] +set_property -dict {LOC AW26 IOSTANDARD LVDS} [get_ports ref_clk_n] +create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p] + +# 80 MHz EMCCLK +#set_property -dict {LOC AL27 IOSTANDARD LVCMOS18} [get_ports emc_clk] +#create_clock -period 12.5 -name emc_clk [get_ports emc_clk] + +# PLL control +set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}] +set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}] +set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}] +set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_lol_n}] +set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}] +set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}] +set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}] + +#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}] +#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}] + +set_false_path -to [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] +set_output_delay 0 [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] +set_false_path -from [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] +set_input_delay 0 [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] + +# LEDs +set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC BB24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC BC24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}] +set_property -dict {LOC BD24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}] +set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}] +set_property -dict {LOC BD25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}] +set_property -dict {LOC BC26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] +set_property -dict {LOC BC27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Push buttons +set_property -dict {LOC B31 IOSTANDARD LVCMOS12} [get_ports {btn[0]}] +set_property -dict {LOC C31 IOSTANDARD LVCMOS12} [get_ports {btn[1]}] + +set_false_path -from [get_ports {btn[*]}] +set_input_delay 0 [get_ports {btn[*]}] + +# DIP switches +set_property -dict {LOC P33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC K34 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC E35 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC H38 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] +set_property -dict {LOC D35 IOSTANDARD LVCMOS12} [get_ports {sw[4]}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12} [get_ports {sw[5]}] +set_property -dict {LOC E37 IOSTANDARD LVCMOS12} [get_ports {sw[6]}] +set_property -dict {LOC F38 IOSTANDARD LVCMOS12} [get_ports {sw[7]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# GPIO +#set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {gpio[0]}] +#set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {gpio[1]}] +#set_property -dict {LOC AU26 IOSTANDARD LVCMOS18} [get_ports {gpio[2]}] +#set_property -dict {LOC BD26 IOSTANDARD LVCMOS18} [get_ports {gpio[3]}] +#set_property -dict {LOC BE27 IOSTANDARD LVCMOS18} [get_ports {gpio[4]}] +#set_property -dict {LOC BE26 IOSTANDARD LVCMOS18} [get_ports {gpio[5]}] +#set_property -dict {LOC AU25 IOSTANDARD LVCMOS18} [get_ports {gpio[6]}] +#set_property -dict {LOC AR26 IOSTANDARD LVCMOS18} [get_ports {gpio[7]}] + +#set_false_path -to [get_ports {gpio[*]}] +#set_output_delay 0 [get_ports {gpio[*]}] + +# UART +set_property -dict {LOC BB27 IOSTANDARD LVCMOS18} [get_ports uart_txd] +set_property -dict {LOC AY27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rxd] +set_property -dict {LOC BC28 IOSTANDARD LVCMOS18} [get_ports uart_rts] +set_property -dict {LOC AY28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts] +set_property -dict {LOC AY26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rst_n] +set_property -dict {LOC BB26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_suspend_n] +#set_property -dict {LOC AW28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[0]}] +#set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[1]}] +#set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[2]}] +#set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[3]}] + +set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}] +set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}] +set_false_path -from [get_ports {uart_txd uart_rts}] +set_input_delay 0 [get_ports {uart_txd uart_rts}] + +# I2C +set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl] +set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda] +set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n] + +set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}] +set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}] + +# QSPI flash +#set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}] +#set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}] +#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}] +#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}] +#set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}] + +#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_false_path -from [get_ports {qspi_1_dq}] +#set_input_delay 0 [get_ports {qspi_1_dq}] + +# DDR4 A +# set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[0]}] +# set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[1]}] +# set_property -dict {LOC D34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[2]}] +# set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[3]}] +# set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[4]}] +# set_property -dict {LOC D38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[5]}] +# set_property -dict {LOC A39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[6]}] +# set_property -dict {LOC C38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[7]}] +# set_property -dict {LOC B39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[8]}] +# set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[9]}] +# set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[10]}] +# set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[11]}] +# set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[12]}] +# set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[13]}] +# set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[14]}] +# set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[15]}] +# set_property -dict {LOC E38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[16]}] + +# set_property -dict {LOC B34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_act_n}] +# set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_alert_n}] + +# set_property -dict {LOC C39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_ba[0]}] +# set_property -dict {LOC E39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_ba[1]}] +# set_property -dict {LOC B40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_bg[0]}] + +# set_property -dict {LOC D40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_cke}] +# set_property -dict {LOC A32 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_a_ck_t}] +# set_property -dict {LOC A33 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_a_ck_c}] +# set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_cs_n}] + +# set_property -dict {LOC N28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[0]}] +# set_property -dict {LOC N26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[1]}] +# set_property -dict {LOC R27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[2]}] +# set_property -dict {LOC P26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[3]}] +# set_property -dict {LOC P28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[4]}] +# set_property -dict {LOC R26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[5]}] +# set_property -dict {LOC T27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[6]}] +# set_property -dict {LOC T26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[7]}] +# set_property -dict {LOC H29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[8]}] +# set_property -dict {LOC G27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[9]}] +# set_property -dict {LOC D28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[10]}] +# set_property -dict {LOC F27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[11]}] +# set_property -dict {LOC G29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[12]}] +# set_property -dict {LOC G26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[13]}] +# set_property -dict {LOC E28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[14]}] +# set_property -dict {LOC E27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[15]}] +# set_property -dict {LOC H28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[16]}] +# set_property -dict {LOC L27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[17]}] +# set_property -dict {LOC J28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[18]}] +# set_property -dict {LOC H27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[19]}] +# set_property -dict {LOC J29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[20]}] +# set_property -dict {LOC M27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[21]}] +# set_property -dict {LOC K28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[22]}] +# set_property -dict {LOC J28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[23]}] +# set_property -dict {LOC E30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[24]}] +# set_property -dict {LOC B29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[25]}] +# set_property -dict {LOC A29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[26]}] +# set_property -dict {LOC C29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[27]}] +# set_property -dict {LOC D30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[28]}] +# set_property -dict {LOC B30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[29]}] +# set_property -dict {LOC A30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[30]}] +# set_property -dict {LOC D29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[31]}] +# set_property -dict {LOC T32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[32]}] +# set_property -dict {LOC T33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[33]}] +# set_property -dict {LOC U31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[34]}] +# set_property -dict {LOC U32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[35]}] +# set_property -dict {LOC V31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[36]}] +# set_property -dict {LOC R33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[37]}] +# set_property -dict {LOC U30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[38]}] +# set_property -dict {LOC T30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[39]}] +# set_property -dict {LOC F32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[40]}] +# set_property -dict {LOC E33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[41]}] +# set_property -dict {LOC E32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[42]}] +# set_property -dict {LOC F33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[43]}] +# set_property -dict {LOC G31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[44]}] +# set_property -dict {LOC H32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[45]}] +# set_property -dict {LOC H31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[46]}] +# set_property -dict {LOC G32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[47]}] +# set_property -dict {LOC R32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[48]}] +# set_property -dict {LOC P32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[49]}] +# set_property -dict {LOC R31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[50]}] +# set_property -dict {LOC N32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[51]}] +# set_property -dict {LOC N31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[52]}] +# set_property -dict {LOC N34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[53]}] +# set_property -dict {LOC P31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[54]}] +# set_property -dict {LOC N33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[55]}] +# set_property -dict {LOC L30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[56]}] +# set_property -dict {LOC K32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[57]}] +# set_property -dict {LOC M30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[58]}] +# set_property -dict {LOC K33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[59]}] +# set_property -dict {LOC J31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[60]}] +# set_property -dict {LOC L33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[61]}] +# set_property -dict {LOC K31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[62]}] +# set_property -dict {LOC L32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[63]}] +# set_property -dict {LOC J35 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[64]}] +# set_property -dict {LOC G34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[65]}] +# set_property -dict {LOC G37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[66]}] +# set_property -dict {LOC H34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[67]}] +# set_property -dict {LOC J36 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[68]}] +# set_property -dict {LOC F35 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[69]}] +# set_property -dict {LOC F37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[70]}] +# set_property -dict {LOC F34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[71]}] + +# set_property -dict {LOC P29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[0]}] +# set_property -dict {LOC N29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[0]}] +# set_property -dict {LOC F28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[1]}] +# set_property -dict {LOC F29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[1]}] +# set_property -dict {LOC K26 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[2]}] +# set_property -dict {LOC K27 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[2]}] +# set_property -dict {LOC A27 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[3]}] +# set_property -dict {LOC A28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[3]}] +# set_property -dict {LOC V32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[4]}] +# set_property -dict {LOC V33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[4]}] +# set_property -dict {LOC J33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[5]}] +# set_property -dict {LOC H33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[5]}] +# set_property -dict {LOC M34 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[6]}] +# set_property -dict {LOC L34 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[6]}] +# set_property -dict {LOC K30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[7]}] +# set_property -dict {LOC J30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[7]}] +# set_property -dict {LOC H36 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[8]}] +# set_property -dict {LOC G36 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[8]}] + +# set_property -dict {LOC T28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[0]}] +# set_property -dict {LOC J26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[1]}] +# set_property -dict {LOC M29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[2]}] +# set_property -dict {LOC C27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[3]}] +# set_property -dict {LOC U34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[4]}] +# set_property -dict {LOC G30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[5]}] +# set_property -dict {LOC R30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[6]}] +# set_property -dict {LOC M31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[7]}] +# set_property -dict {LOC H37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[8]}] + +# set_property -dict {LOC A34 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_odt}] +# set_property -dict {LOC E40 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_rst_n}] +# set_property -dict {LOC D31 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_par}] +# set_property -dict {LOC B37 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_ten}] + +# DDR4 B +# set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[0]}] +# set_property -dict {LOC BA35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[1]}] +# set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[2]}] +# set_property -dict {LOC BD34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[3]}] +# set_property -dict {LOC BC34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[4]}] +# set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[5]}] +# set_property -dict {LOC BE37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[6]}] +# set_property -dict {LOC BF38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[7]}] +# set_property -dict {LOC BF37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[8]}] +# set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[9]}] +# set_property -dict {LOC BD35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[10]}] +# set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[11]}] +# set_property -dict {LOC BD36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[12]}] +# set_property -dict {LOC BE38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[13]}] +# set_property -dict {LOC BB36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[14]}] +# set_property -dict {LOC BF40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[15]}] +# set_property -dict {LOC BE40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[16]}] + +# set_property -dict {LOC BF35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_act_n}] +# set_property -dict {LOC BD39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_alert_n}] + +# set_property -dict {LOC BB38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_ba[0]}] +# set_property -dict {LOC BD40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_ba[1]}] +# set_property -dict {LOC BC36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_bg[0]}] + +# set_property -dict {LOC BB35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_cke}] +# set_property -dict {LOC BB37 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_b_ck_t}] +# set_property -dict {LOC BC37 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_b_ck_c}] +# set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_cs_n}] + +# set_property -dict {LOC AP29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[0]}] +# set_property -dict {LOC AR30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[1]}] +# set_property -dict {LOC AN29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[2]}] +# set_property -dict {LOC AP30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[3]}] +# set_property -dict {LOC AL29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[4]}] +# set_property -dict {LOC AN31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[5]}] +# set_property -dict {LOC AL30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[6]}] +# set_property -dict {LOC AM31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[7]}] +# set_property -dict {LOC AT29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[8]}] +# set_property -dict {LOC AU32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[9]}] +# set_property -dict {LOC AU30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[10]}] +# set_property -dict {LOC AV31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[11]}] +# set_property -dict {LOC AT30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[12]}] +# set_property -dict {LOC AW31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[13]}] +# set_property -dict {LOC AU31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[14]}] +# set_property -dict {LOC AV32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[15]}] +# set_property -dict {LOC BB30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[16]}] +# set_property -dict {LOC AY32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[17]}] +# set_property -dict {LOC BA30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[18]}] +# set_property -dict {LOC AY30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[19]}] +# set_property -dict {LOC BA29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[20]}] +# set_property -dict {LOC AY31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[21]}] +# set_property -dict {LOC BB29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[22]}] +# set_property -dict {LOC BB31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[23]}] +# set_property -dict {LOC BF30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[24]}] +# set_property -dict {LOC BE32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[25]}] +# set_property -dict {LOC BD29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[26]}] +# set_property -dict {LOC BD33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[27]}] +# set_property -dict {LOC BE30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[28]}] +# set_property -dict {LOC BE33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[29]}] +# set_property -dict {LOC BC29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[30]}] +# set_property -dict {LOC BE31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[31]}] +# set_property -dict {LOC Y33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[32]}] +# set_property -dict {LOC W30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[33]}] +# set_property -dict {LOC W34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[34]}] +# set_property -dict {LOC Y32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[35]}] +# set_property -dict {LOC AA34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[36]}] +# set_property -dict {LOC Y30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[37]}] +# set_property -dict {LOC AB34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[38]}] +# set_property -dict {LOC W33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[39]}] +# set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[40]}] +# set_property -dict {LOC AG30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[41]}] +# set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[42]}] +# set_property -dict {LOC AK28 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[43]}] +# set_property -dict {LOC AK31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[44]}] +# set_property -dict {LOC AG29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[45]}] +# set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[46]}] +# set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[47]}] +# set_property -dict {LOC AC32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[48]}] +# set_property -dict {LOC AE33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[49]}] +# set_property -dict {LOC AC33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[50]}] +# set_property -dict {LOC AD34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[51]}] +# set_property -dict {LOC AC34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[52]}] +# set_property -dict {LOC AD33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[53]}] +# set_property -dict {LOC AE30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[54]}] +# set_property -dict {LOC AF30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[55]}] +# set_property -dict {LOC AF34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[56]}] +# set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[57]}] +# set_property -dict {LOC AH33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[58]}] +# set_property -dict {LOC AG32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[59]}] +# set_property -dict {LOC AF33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[60]}] +# set_property -dict {LOC AG31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[61]}] +# set_property -dict {LOC AF32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[62]}] +# set_property -dict {LOC AG34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[63]}] +# set_property -dict {LOC AN34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[64]}] +# set_property -dict {LOC AL34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[65]}] +# set_property -dict {LOC AP34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[66]}] +# set_property -dict {LOC AM32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[67]}] +# set_property -dict {LOC AR33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[68]}] +# set_property -dict {LOC AL32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[69]}] +# set_property -dict {LOC AP33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[70]}] +# set_property -dict {LOC AM34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[71]}] + +# set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[0]}] +# set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[0]}] +# set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[1]}] +# set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[1]}] +# set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[2]}] +# set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[2]}] +# set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[3]}] +# set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[3]}] +# set_property -dict {LOC W31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[4]}] +# set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[4]}] +# set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[5]}] +# set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[5]}] +# set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[6]}] +# set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[6]}] +# set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[7]}] +# set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[7]}] +# set_property -dict {LOC AN32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[8]}] +# set_property -dict {LOC AN33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[8]}] + +# set_property -dict {LOC AP31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[0]}] +# set_property -dict {LOC AW29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[1]}] +# set_property -dict {LOC BC31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[2]}] +# set_property -dict {LOC BF32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[3]}] +# set_property -dict {LOC AA32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[4]}] +# set_property -dict {LOC AJ27 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[5]}] +# set_property -dict {LOC AE31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[6]}] +# set_property -dict {LOC AH34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[7]}] +# set_property -dict {LOC AT33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[8]}] + +# set_property -dict {LOC BE35 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_odt}] +# set_property -dict {LOC AY36 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_rst_n}] +# set_property -dict {LOC AV33 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_par}] +# set_property -dict {LOC BF39 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_ten}] + +# QSFP28 Interfaces + +# QSFP 1 +set_property -dict {LOC G40 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC G41 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC J45 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC J46 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC E42 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC E43 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC H43 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC H44 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC C42 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC C43 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC F45 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC F46 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC A42 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC A43 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC D45 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC D46 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC K38 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK1P_133 from U48.28 OUT1_P +set_property -dict {LOC K39 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK1N_133 from U48.27 OUT1_N +set_property -dict {LOC BB20 IOSTANDARD LVCMOS18} [get_ports qsfp_1_resetl] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS18} [get_ports qsfp_1_modprsl] +set_property -dict {LOC BA20 IOSTANDARD LVCMOS18} [get_ports qsfp_1_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] + +# QSFP 2 +set_property -dict {LOC N40 } [get_ports {qsfp_2_tx_p[1]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N41 } [get_ports {qsfp_2_tx_n[1]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N45 } [get_ports {qsfp_2_rx_p[1]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N46 } [get_ports {qsfp_2_rx_n[1]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M38 } [get_ports {qsfp_2_tx_p[2]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M39 } [get_ports {qsfp_2_tx_n[2]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M43 } [get_ports {qsfp_2_rx_p[2]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M44 } [get_ports {qsfp_2_rx_n[2]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L40 } [get_ports {qsfp_2_tx_p[0]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L41 } [get_ports {qsfp_2_tx_n[0]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L45 } [get_ports {qsfp_2_rx_p[0]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L46 } [get_ports {qsfp_2_rx_n[0]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J40 } [get_ports {qsfp_2_tx_p[3]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J41 } [get_ports {qsfp_2_tx_n[3]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K43 } [get_ports {qsfp_2_rx_p[3]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K44 } [get_ports {qsfp_2_rx_n[3]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC R36 } [get_ports qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_132 from U48.35 OUT3_P +set_property -dict {LOC R37 } [get_ports qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_132 from U48.34 OUT3_N +set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports qsfp_2_resetl] +set_property -dict {LOC BD21 IOSTANDARD LVCMOS18} [get_ports qsfp_2_modprsl] +set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports qsfp_2_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_2_mgt_refclk [get_ports qsfp_2_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_2_mgt_refclk [get_ports qsfp_2_mgt_refclk_p] + +# QSFP 3 +set_property -dict {LOC U40 } [get_ports {qsfp_3_tx_p[1]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U41 } [get_ports {qsfp_3_tx_n[1]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U45 } [get_ports {qsfp_3_rx_p[1]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U46 } [get_ports {qsfp_3_rx_n[1]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T38 } [get_ports {qsfp_3_tx_p[2]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T39 } [get_ports {qsfp_3_tx_n[2]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T43 } [get_ports {qsfp_3_rx_p[2]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T44 } [get_ports {qsfp_3_rx_n[2]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R40 } [get_ports {qsfp_3_tx_p[0]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R41 } [get_ports {qsfp_3_tx_n[0]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R45 } [get_ports {qsfp_3_rx_p[0]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R46 } [get_ports {qsfp_3_rx_n[0]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P38 } [get_ports {qsfp_3_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P39 } [get_ports {qsfp_3_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P43 } [get_ports {qsfp_3_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P44 } [get_ports {qsfp_3_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC W36 } [get_ports qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_131 from U48.38 OUT4_P +set_property -dict {LOC W37 } [get_ports qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_131 from U48.37 OUT4_N +set_property -dict {LOC AY23 IOSTANDARD LVCMOS18} [get_ports qsfp_3_resetl] +set_property -dict {LOC AY22 IOSTANDARD LVCMOS18} [get_ports qsfp_3_modprsl] +set_property -dict {LOC BA22 IOSTANDARD LVCMOS18} [get_ports qsfp_3_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_3_mgt_refclk [get_ports qsfp_3_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_3_mgt_refclk [get_ports qsfp_3_mgt_refclk_p] + +# QSFP 4 +set_property -dict {LOC AA40} [get_ports {qsfp_4_tx_p[1]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA41} [get_ports {qsfp_4_tx_n[1]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA45} [get_ports {qsfp_4_rx_p[1]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA46} [get_ports {qsfp_4_rx_n[1]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y38 } [get_ports {qsfp_4_tx_p[2]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y39 } [get_ports {qsfp_4_tx_n[2]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y43 } [get_ports {qsfp_4_rx_p[2]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y44 } [get_ports {qsfp_4_rx_n[2]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W40 } [get_ports {qsfp_4_tx_p[0]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W41 } [get_ports {qsfp_4_tx_n[0]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W45 } [get_ports {qsfp_4_rx_p[0]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W46 } [get_ports {qsfp_4_rx_n[0]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V38 } [get_ports {qsfp_4_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V39 } [get_ports {qsfp_4_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V43 } [get_ports {qsfp_4_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V44 } [get_ports {qsfp_4_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AC36} [get_ports qsfp_4_mgt_refclk_p] ;# MGTREFCLK0P_130 from U48.42 OUT5_P +set_property -dict {LOC AC37} [get_ports qsfp_4_mgt_refclk_n] ;# MGTREFCLK0N_130 from U48.41 OUT5_N +set_property -dict {LOC BC22 IOSTANDARD LVCMOS18} [get_ports qsfp_4_resetl] +set_property -dict {LOC BB22 IOSTANDARD LVCMOS18} [get_ports qsfp_4_modprsl] +set_property -dict {LOC BA23 IOSTANDARD LVCMOS18} [get_ports qsfp_4_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_4_mgt_refclk [get_ports qsfp_4_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_4_mgt_refclk [get_ports qsfp_4_mgt_refclk_p] + +# QSFP 5 +set_property -dict {LOC AE40} [get_ports {qsfp_5_tx_p[1]}] ;# MGTYTXP0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE41} [get_ports {qsfp_5_tx_n[1]}] ;# MGTYTXN0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE45} [get_ports {qsfp_5_rx_p[1]}] ;# MGTYRXP0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE46} [get_ports {qsfp_5_rx_n[1]}] ;# MGTYRXN0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD38} [get_ports {qsfp_5_tx_p[2]}] ;# MGTYTXP1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD39} [get_ports {qsfp_5_tx_n[2]}] ;# MGTYTXN1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD43} [get_ports {qsfp_5_rx_p[2]}] ;# MGTYRXP1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD44} [get_ports {qsfp_5_rx_n[2]}] ;# MGTYRXN1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC40} [get_ports {qsfp_5_tx_p[3]}] ;# MGTYTXP2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC41} [get_ports {qsfp_5_tx_n[3]}] ;# MGTYTXN2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC45} [get_ports {qsfp_5_rx_p[3]}] ;# MGTYRXP2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC46} [get_ports {qsfp_5_rx_n[3]}] ;# MGTYRXN2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB38} [get_ports {qsfp_5_tx_p[0]}] ;# MGTYTXP3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB39} [get_ports {qsfp_5_tx_n[0]}] ;# MGTYTXN3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB43} [get_ports {qsfp_5_rx_p[0]}] ;# MGTYRXP3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB44} [get_ports {qsfp_5_rx_n[0]}] ;# MGTYRXN3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AG36} [get_ports qsfp_5_mgt_refclk_p] ;# MGTREFCLK0P_129 from U48.24 OUT0_P +set_property -dict {LOC AG37} [get_ports qsfp_5_mgt_refclk_n] ;# MGTREFCLK0N_129 from U48.23 OUT0_N +set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_resetl] +set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_modprsl] +set_property -dict {LOC BF23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_5_mgt_refclk [get_ports qsfp_5_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_5_mgt_refclk [get_ports qsfp_5_mgt_refclk_p] + +# QSFP 6 +set_property -dict {LOC AJ40} [get_ports {qsfp_6_tx_p[1]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ41} [get_ports {qsfp_6_tx_n[1]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ45} [get_ports {qsfp_6_rx_p[1]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ46} [get_ports {qsfp_6_rx_n[1]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH38} [get_ports {qsfp_6_tx_p[2]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH39} [get_ports {qsfp_6_tx_n[2]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH43} [get_ports {qsfp_6_rx_p[2]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH44} [get_ports {qsfp_6_rx_n[2]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG40} [get_ports {qsfp_6_tx_p[0]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG41} [get_ports {qsfp_6_tx_n[0]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG45} [get_ports {qsfp_6_rx_p[0]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG46} [get_ports {qsfp_6_rx_n[0]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF38} [get_ports {qsfp_6_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF39} [get_ports {qsfp_6_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF43} [get_ports {qsfp_6_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF44} [get_ports {qsfp_6_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AL36} [get_ports qsfp_6_mgt_refclk_p] ;# MGTREFCLK0P_128 from U48.59 OUT9_P +set_property -dict {LOC AL37} [get_ports qsfp_6_mgt_refclk_n] ;# MGTREFCLK0N_128 from U48.58 OUT9_N +set_property -dict {LOC AW24 IOSTANDARD LVCMOS18} [get_ports qsfp_6_resetl] +set_property -dict {LOC AR23 IOSTANDARD LVCMOS18} [get_ports qsfp_6_modprsl] +set_property -dict {LOC AV24 IOSTANDARD LVCMOS18} [get_ports qsfp_6_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_6_mgt_refclk [get_ports qsfp_6_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_6_mgt_refclk [get_ports qsfp_6_mgt_refclk_p] + +# QSFP 7 +set_property -dict {LOC AN40} [get_ports {qsfp_7_tx_p[1]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN41} [get_ports {qsfp_7_tx_n[1]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN45} [get_ports {qsfp_7_rx_p[1]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN46} [get_ports {qsfp_7_rx_n[1]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM38} [get_ports {qsfp_7_tx_p[2]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM39} [get_ports {qsfp_7_tx_n[2]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM43} [get_ports {qsfp_7_rx_p[2]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM44} [get_ports {qsfp_7_rx_n[2]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL40} [get_ports {qsfp_7_tx_p[0]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL41} [get_ports {qsfp_7_tx_n[0]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL45} [get_ports {qsfp_7_rx_p[0]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL46} [get_ports {qsfp_7_rx_n[0]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK38} [get_ports {qsfp_7_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK39} [get_ports {qsfp_7_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK43} [get_ports {qsfp_7_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK44} [get_ports {qsfp_7_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AR36} [get_ports qsfp_7_mgt_refclk_p] ;# MGTREFCLK0P_127 from U48.54 OUT8_P +set_property -dict {LOC AR37} [get_ports qsfp_7_mgt_refclk_n] ;# MGTREFCLK0N_127 from U48.53 OUT8_N +set_property -dict {LOC AU24 IOSTANDARD LVCMOS18} [get_ports qsfp_7_resetl] +set_property -dict {LOC AN23 IOSTANDARD LVCMOS18} [get_ports qsfp_7_modprsl] +set_property -dict {LOC AT24 IOSTANDARD LVCMOS18} [get_ports qsfp_7_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_7_mgt_refclk [get_ports qsfp_7_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_7_mgt_refclk [get_ports qsfp_7_mgt_refclk_p] + +# QSFP 8 +set_property -dict {LOC AU40} [get_ports {qsfp_8_tx_p[1]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU41} [get_ports {qsfp_8_tx_n[1]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU45} [get_ports {qsfp_8_rx_p[1]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU46} [get_ports {qsfp_8_rx_n[1]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT38} [get_ports {qsfp_8_tx_p[2]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT39} [get_ports {qsfp_8_tx_n[2]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT43} [get_ports {qsfp_8_rx_p[2]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT44} [get_ports {qsfp_8_rx_n[2]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR40} [get_ports {qsfp_8_tx_p[0]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR41} [get_ports {qsfp_8_tx_n[0]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR45} [get_ports {qsfp_8_rx_p[0]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR46} [get_ports {qsfp_8_rx_n[0]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP38} [get_ports {qsfp_8_tx_p[3]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP39} [get_ports {qsfp_8_tx_n[3]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP43} [get_ports {qsfp_8_rx_p[3]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP44} [get_ports {qsfp_8_rx_n[3]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AV38} [get_ports qsfp_8_mgt_refclk_p] ;# MGTREFCLK0P_126 from U48.45 OUT6_P +set_property -dict {LOC AV39} [get_ports qsfp_8_mgt_refclk_n] ;# MGTREFCLK0N_126 from U48.44 OUT6_N +set_property -dict {LOC AN24 IOSTANDARD LVCMOS18} [get_ports qsfp_8_resetl] +set_property -dict {LOC AP24 IOSTANDARD LVCMOS18} [get_ports qsfp_8_modprsl] +set_property -dict {LOC AP23 IOSTANDARD LVCMOS18} [get_ports qsfp_8_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_8_mgt_refclk [get_ports qsfp_8_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_8_mgt_refclk [get_ports qsfp_8_mgt_refclk_p] + +# QSFP 9 +set_property -dict {LOC BF42} [get_ports {qsfp_9_tx_p[1]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BF43} [get_ports {qsfp_9_tx_n[1]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BC45} [get_ports {qsfp_9_rx_p[1]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BC46} [get_ports {qsfp_9_rx_n[1]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD42} [get_ports {qsfp_9_tx_p[2]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD43} [get_ports {qsfp_9_tx_n[2]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA45} [get_ports {qsfp_9_rx_p[2]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA46} [get_ports {qsfp_9_rx_n[2]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB42} [get_ports {qsfp_9_tx_p[0]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB43} [get_ports {qsfp_9_tx_n[0]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW45} [get_ports {qsfp_9_rx_p[0]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW46} [get_ports {qsfp_9_rx_n[0]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW40} [get_ports {qsfp_9_tx_p[3]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW41} [get_ports {qsfp_9_tx_n[3]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV43} [get_ports {qsfp_9_rx_p[3]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV44} [get_ports {qsfp_9_rx_n[3]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA40} [get_ports qsfp_9_mgt_refclk_p] ;# MGTREFCLK0P_125 from U48.51 OUT7_P +set_property -dict {LOC BA41} [get_ports qsfp_9_mgt_refclk_n] ;# MGTREFCLK0N_125 from U48.50 OUT7_N +set_property -dict {LOC AM24 IOSTANDARD LVCMOS18} [get_ports qsfp_9_resetl] +set_property -dict {LOC AM22 IOSTANDARD LVCMOS18} [get_ports qsfp_9_modprsl] +set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports qsfp_9_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_9_mgt_refclk [get_ports qsfp_9_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_9_mgt_refclk [get_ports qsfp_9_mgt_refclk_p] + +# SMA (GTY) +#set_property -dict {LOC E9 } [get_ports {sma_tx_p[0]}] ;# MGTYTXP0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E8 } [get_ports {sma_tx_n[0]}] ;# MGTYTXN0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E4 } [get_ports {sma_rx_p[0]}] ;# MGTYRXP0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E3 } [get_ports {sma_rx_n[0]}] ;# MGTYRXN0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D7 } [get_ports {sma_tx_p[1]}] ;# MGTYTXP1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D6 } [get_ports {sma_tx_n[1]}] ;# MGTYTXN1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D2 } [get_ports {sma_rx_p[1]}] ;# MGTYRXP1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D1 } [get_ports {sma_rx_n[1]}] ;# MGTYRXN1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C9 } [get_ports {sma_tx_p[2]}] ;# MGTYTXP2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C8 } [get_ports {sma_tx_n[2]}] ;# MGTYTXN2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C4 } [get_ports {sma_rx_p[2]}] ;# MGTYRXP2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C3 } [get_ports {sma_rx_n[2]}] ;# MGTYRXN2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A9 } [get_ports {sma_tx_p[3]}] ;# MGTYTXP3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A8 } [get_ports {sma_tx_n[3]}] ;# MGTYTXN3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A5 } [get_ports {sma_rx_p[3]}] ;# MGTYRXP3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A4 } [get_ports {sma_rx_n[3]}] ;# MGTYRXN3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D11 } [get_ports sma_mgt_refclk_p] ;# MGTREFCLK0P_233 from X20 SMA CLKP +#set_property -dict {LOC D10 } [get_ports sma_mgt_refclk_n] ;# MGTREFCLK0N_233 from X19 SMA CLKN + +# 156.25 MHz MGT reference clock +#create_clock -period 6.400 -name sma_mgt_refclk [get_ports sma_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +#create_clock -period 6.206 -name sma_mgt_refclk [get_ports sma_mgt_refclk_p] + +# FireFly +#set_property -dict {LOC BF5 } [get_ports {ff_tx_p[0]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BF4 } [get_ports {ff_tx_n[0]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BC2 } [get_ports {ff_rx_p[0]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BC1 } [get_ports {ff_rx_n[0]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BD5 } [get_ports {ff_tx_p[2]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BD4 } [get_ports {ff_tx_n[2]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BA2 } [get_ports {ff_rx_p[2]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BA1 } [get_ports {ff_rx_n[2]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BB5 } [get_ports {ff_tx_p[1]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BB4 } [get_ports {ff_tx_n[1]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AW4 } [get_ports {ff_rx_p[1]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AW3 } [get_ports {ff_rx_n[1]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV7 } [get_ports {ff_tx_p[3]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV6 } [get_ports {ff_tx_n[3]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV2 } [get_ports {ff_rx_p[3]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV1 } [get_ports {ff_rx_n[3]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AU9 } [get_ports {ff_tx_p[5]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU8 } [get_ports {ff_tx_n[5]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU4 } [get_ports {ff_rx_p[5]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU3 } [get_ports {ff_rx_n[5]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT7 } [get_ports {ff_tx_p[7]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT6 } [get_ports {ff_tx_n[7]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT2 } [get_ports {ff_rx_p[7]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT1 } [get_ports {ff_rx_n[7]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR9 } [get_ports {ff_tx_p[4]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR8 } [get_ports {ff_tx_n[4]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR4 } [get_ports {ff_rx_p[4]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR3 } [get_ports {ff_rx_n[4]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP7 } [get_ports {ff_tx_p[6]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP6 } [get_ports {ff_tx_n[6]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP2 } [get_ports {ff_rx_p[6]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP1 } [get_ports {ff_rx_n[6]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AN9 } [get_ports {ff_tx_p[11]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN8 } [get_ports {ff_tx_n[11]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN4 } [get_ports {ff_rx_p[11]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN3 } [get_ports {ff_rx_n[11]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM7 } [get_ports {ff_tx_p[9]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM6 } [get_ports {ff_tx_n[9]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM2 } [get_ports {ff_rx_p[9]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM1 } [get_ports {ff_rx_n[9]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL9 } [get_ports {ff_tx_p[10]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL8 } [get_ports {ff_tx_n[10]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL4 } [get_ports {ff_rx_p[10]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL3 } [get_ports {ff_rx_n[10]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK7 } [get_ports {ff_tx_p[8]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK6 } [get_ports {ff_tx_n[8]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK2 } [get_ports {ff_rx_p[8]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK1 } [get_ports {ff_rx_n[8]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AP11} [get_ports ff_mgt_refclk_p] ;# MGTREFCLK1P_225 from U48.31 OUT2_P +#set_property -dict {LOC AP10} [get_ports ff_mgt_refclk_n] ;# MGTREFCLK1N_225 from U48.30 OUT2_N +#set_property -dict {LOC M22 IOSTANDARD LVCMOS18} [get_ports ff_tx_int_l] +#set_property -dict {LOC P21 IOSTANDARD LVCMOS18} [get_ports ff_tx_gpio] +#set_property -dict {LOC N23 IOSTANDARD LVCMOS18} [get_ports ff_tx_prsnt_l] +#set_property -dict {LOC N22 IOSTANDARD LVCMOS18} [get_ports ff_rx_int_l] +#set_property -dict {LOC R21 IOSTANDARD LVCMOS18} [get_ports ff_rx_gpio] +#set_property -dict {LOC P23 IOSTANDARD LVCMOS18} [get_ports ff_rx_prsnt_l] + +# 100 MHz MGT reference clock +#create_clock -period 10.000 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# 156.25 MHz MGT reference clock +#create_clock -period 6.400 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +#create_clock -period 6.206 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# FMC+ J9 +set_property -dict {LOC BA15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_lpmode] ;# J9.G9 LA00_P_CC +set_property -dict {LOC BA14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_resetl] ;# J9.G10 LA00_N_CC +set_property -dict {LOC AY13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_modprsl] ;# J9.D8 LA01_P_CC +set_property -dict {LOC BA13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_intl] ;# J9.D9 LA01_N_CC +set_property -dict {LOC AL15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_modsell] ;# J9.H7 LA02_P +set_property -dict {LOC AM15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_modprsl] ;# J9.H8 LA02_N +set_property -dict {LOC AN14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_intl] ;# J9.G12 LA03_P +set_property -dict {LOC AN13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_modsell] ;# J9.G13 LA03_N +set_property -dict {LOC AL14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_lpmode] ;# J9.H10 LA04_P +set_property -dict {LOC AM14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_resetl] ;# J9.H11 LA04_N +set_property -dict {LOC AP13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_modsell] ;# J9.D11 LA05_P +set_property -dict {LOC AR13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_intl] ;# J9.D12 LA05_N +set_property -dict {LOC AP15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_resetl] ;# J9.C10 LA06_P +set_property -dict {LOC AP14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_lpmode] ;# J9.C11 LA06_N +set_property -dict {LOC AU16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_modprsl] ;# J9.H13 LA07_P +set_property -dict {LOC AV16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_modsell] ;# J9.H14 LA07_N +set_property -dict {LOC AR16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_lpmode] ;# J9.G12 LA08_P +set_property -dict {LOC AR15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_intl] ;# J9.G13 LA08_N +set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_modprsl] ;# J9.D14 LA09_P +set_property -dict {LOC AU15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_modsell] ;# J9.D15 LA09_N +set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_resetl] ;# J9.C14 LA10_P +set_property -dict {LOC AV14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_lpmode] ;# J9.C15 LA10_N +set_property -dict {LOC BD15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_intl] ;# J9.H16 LA11_P +set_property -dict {LOC BD14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_modprsl] ;# J9.H17 LA11_N +set_property -dict {LOC AY12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_resetl] ;# J9.G15 LA12_P +set_property -dict {LOC AY11 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_lpmode] ;# J9.G16 LA12_N +set_property -dict {LOC BA12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_intl] ;# J9.D17 LA13_P +set_property -dict {LOC BB12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_modprsl] ;# J9.D18 LA13_N +set_property -dict {LOC BB15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_modsell] ;# J9.C18 LA14_P +set_property -dict {LOC BB14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_resetl] ;# J9.C19 LA14_N +set_property -dict {LOC BF14 IOSTANDARD LVCMOS18} [get_ports fmc_clk_finc] ;# J9.H19 LA15_P +set_property -dict {LOC BF13 IOSTANDARD LVCMOS18} [get_ports fmc_clk_fdec] ;# J9.H20 LA15_N +set_property -dict {LOC BD16 IOSTANDARD LVCMOS18} [get_ports fmc_clk_rst_n] ;# J9.G18 LA16_P +set_property -dict {LOC BE16 IOSTANDARD LVCMOS18} [get_ports fmc_clk_lol_n] ;# J9.G19 LA16_N +set_property -dict {LOC AT20 IOSTANDARD LVCMOS18} [get_ports fmc_clk_sync_n] ;# J9.D20 LA17_P_CC +set_property -dict {LOC AU20 IOSTANDARD LVCMOS18} [get_ports fmc_clk_intr_n] ;# J9.D21 LA17_N_CC +#set_property -dict {LOC AV19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[18]}] ;# J9.C22 LA18_P_CC +#set_property -dict {LOC AW19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[18]}] ;# J9.C23 LA18_N_CC +#set_property -dict {LOC AR17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[19]}] ;# J9.H22 LA19_P +#set_property -dict {LOC AT17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[19]}] ;# J9.H23 LA19_N +#set_property -dict {LOC AN18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[20]}] ;# J9.G21 LA20_P +#set_property -dict {LOC AN17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[20]}] ;# J9.G22 LA20_N +#set_property -dict {LOC AW20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[21]}] ;# J9.H25 LA21_P +#set_property -dict {LOC AY20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[21]}] ;# J9.H26 LA21_N +#set_property -dict {LOC AT19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[22]}] ;# J9.G24 LA22_P +#set_property -dict {LOC AU19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[22]}] ;# J9.G25 LA22_N +#set_property -dict {LOC AL17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[23]}] ;# J9.D23 LA23_P +#set_property -dict {LOC AM17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[23]}] ;# J9.D24 LA23_N +#set_property -dict {LOC AY17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[24]}] ;# J9.H28 LA24_P +#set_property -dict {LOC BA17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[24]}] ;# J9.H29 LA24_N +#set_property -dict {LOC AY18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[25]}] ;# J9.G27 LA25_P +#set_property -dict {LOC BA18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[25]}] ;# J9.G28 LA25_N +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[26]}] ;# J9.D26 LA26_P +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[26]}] ;# J9.D27 LA26_N +#set_property -dict {LOC AN19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[27]}] ;# J9.C26 LA27_P +#set_property -dict {LOC AP19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[27]}] ;# J9.C27 LA27_N +#set_property -dict {LOC BB17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[28]}] ;# J9.H31 LA28_P +#set_property -dict {LOC BC17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[28]}] ;# J9.H32 LA28_N +#set_property -dict {LOC BB19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[29]}] ;# J9.G30 LA29_P +#set_property -dict {LOC BC18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[29]}] ;# J9.G31 LA29_N +#set_property -dict {LOC BD18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[30]}] ;# J9.H34 LA30_P +#set_property -dict {LOC BE18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[30]}] ;# J9.H35 LA30_N +#set_property -dict {LOC BC19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[31]}] ;# J9.G33 LA31_P +#set_property -dict {LOC BD19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[31]}] ;# J9.G34 LA31_N +#set_property -dict {LOC BF19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[32]}] ;# J9.H37 LA32_P +#set_property -dict {LOC BF18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[32]}] ;# J9.H38 LA32_N +#set_property -dict {LOC BE17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[33]}] ;# J9.G36 LA33_P +#set_property -dict {LOC BF17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[33]}] ;# J9.G37 LA33_N + +#set_property -dict {LOC G14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[0]}] ;# J9.F4 HA00_P_CC +#set_property -dict {LOC F14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[0]}] ;# J9.F5 HA00_N_CC +#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[1]}] ;# J9.E2 HA01_P_CC +#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[1]}] ;# J9.E3 HA01_N_CC +#set_property -dict {LOC A14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[2]}] ;# J9.K7 HA02_P +#set_property -dict {LOC A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[2]}] ;# J9.K8 HA02_N +#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[3]}] ;# J9.J6 HA03_P +#set_property -dict {LOC A17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[3]}] ;# J9.J7 HA03_N +#set_property -dict {LOC C16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[4]}] ;# J9.F7 HA04_P +#set_property -dict {LOC B16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[4]}] ;# J9.F8 HA04_N +#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[5]}] ;# J9.E6 HA05_P +#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[5]}] ;# J9.E7 HA05_N +#set_property -dict {LOC G17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[6]}] ;# J9.K10 HA06_P +#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[6]}] ;# J9.K11 HA06_N +#set_property -dict {LOC D13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[7]}] ;# J9.J9 HA07_P +#set_property -dict {LOC C13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[7]}] ;# J9.J10 HA07_N +#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[8]}] ;# J9.F10 HA08_P +#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[8]}] ;# J9.F11 HA08_N +#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[9]}] ;# J9.E9 HA09_P +#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[9]}] ;# J9.E10 HA09_N +#set_property -dict {LOC R16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[10]}] ;# J9.K13 HA10_P +#set_property -dict {LOC P16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[10]}] ;# J9.K14 HA10_N +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[11]}] ;# J9.J12 HA11_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[11]}] ;# J9.J13 HA11_N +#set_property -dict {LOC H17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[12]}] ;# J9.F13 HA12_P +#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[12]}] ;# J9.F14 HA12_N +#set_property -dict {LOC J13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[13]}] ;# J9.E12 HA13_P +#set_property -dict {LOC H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[13]}] ;# J9.E13 HA13_N +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[14]}] ;# J9.J15 HA14_P +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[14]}] ;# J9.J16 HA14_N +#set_property -dict {LOC N16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[15]}] ;# J9.F14 HA15_P +#set_property -dict {LOC M16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[15]}] ;# J9.F16 HA15_N +#set_property -dict {LOC M14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[16]}] ;# J9.E15 HA16_P +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[16]}] ;# J9.E16 HA16_N +#set_property -dict {LOC J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[17]}] ;# J9.K16 HA17_P_CC +#set_property -dict {LOC H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[17]}] ;# J9.K17 HA17_N_CC +#set_property -dict {LOC J16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[18]}] ;# J9.J18 HA18_P_CC +#set_property -dict {LOC J15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[18]}] ;# J9.J19 HA18_N_CC +#set_property -dict {LOC F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[19]}] ;# J9.F19 HA19_P +#set_property -dict {LOC E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[19]}] ;# J9.F20 HA19_N +#set_property -dict {LOC K16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[20]}] ;# J9.E18 HA20_P +#set_property -dict {LOC K15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[20]}] ;# J9.E19 HA20_N +#set_property -dict {LOC C14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[21]}] ;# J9.K19 HA21_P +#set_property -dict {LOC B14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[21]}] ;# J9.K20 HA21_N +#set_property -dict {LOC R15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[22]}] ;# J9.J21 HA22_P +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[22]}] ;# J9.J22 HA22_N +#set_property -dict {LOC P13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[23]}] ;# J9.K22 HA23_P +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[23]}] ;# J9.K23 HA23_N + +#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[0]}] ;# J9.K25 HB00_P_CC +#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[0]}] ;# J9.K26 HB00_N_CC +#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[1]}] ;# J9.J24 HB01_P +#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[1]}] ;# J9.J25 HB01_N +#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[2]}] ;# J9.F22 HB02_P +#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[2]}] ;# J9.F23 HB02_N +#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[3]}] ;# J9.E21 HB03_P +#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[3]}] ;# J9.E22 HB03_N +#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[4]}] ;# J9.F25 HB04_P +#set_property -dict {LOC F17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[4]}] ;# J9.F26 HB04_N +#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[5]}] ;# J9.E24 HB05_P +#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[5]}] ;# J9.E25 HB05_N +#set_property -dict {LOC J20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[6]}] ;# J9.K28 HB06_P_CC +#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[6]}] ;# J9.K29 HB06_N_CC +#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[7]}] ;# J9.J27 HB07_P +#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[7]}] ;# J9.J28 HB07_N +#set_property -dict {LOC J21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[8]}] ;# J9.F28 HB08_P +#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[8]}] ;# J9.F29 HB08_N +#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[9]}] ;# J9.E27 HB09_P +#set_property -dict {LOC G19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[9]}] ;# J9.E28 HB09_N +#set_property -dict {LOC P19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[10]}] ;# J9.K31 HB10_P +#set_property -dict {LOC N19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[10]}] ;# J9.K32 HB10_N +#set_property -dict {LOC L17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[11]}] ;# J9.J30 HB11_P +#set_property -dict {LOC K17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[11]}] ;# J9.J31 HB11_N +#set_property -dict {LOC L19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[12]}] ;# J9.F31 HB12_P +#set_property -dict {LOC L18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[12]}] ;# J9.F32 HB12_N +#set_property -dict {LOC N17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[13]}] ;# J9.E30 HB13_P +#set_property -dict {LOC M17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[13]}] ;# J9.E31 HB13_N +#set_property -dict {LOC N21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[14]}] ;# J9.K34 HB14_P +#set_property -dict {LOC M21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[14]}] ;# J9.K35 HB14_N +#set_property -dict {LOC R20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[15]}] ;# J9.J33 HB15_P +#set_property -dict {LOC P20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[15]}] ;# J9.J34 HB15_N +#set_property -dict {LOC L20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[16]}] ;# J9.F34 HB16_P +#set_property -dict {LOC K20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[16]}] ;# J9.F35 HB16_N +#set_property -dict {LOC K18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[17]}] ;# J9.K37 HB17_P_CC +#set_property -dict {LOC J18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[17]}] ;# J9.K38 HB17_N_CC +#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[18]}] ;# J9.J36 HB18_P +#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[18]}] ;# J9.J37 HB18_N +#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[19]}] ;# J9.E33 HB19_P +#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[19]}] ;# J9.E34 HB19_N +#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[20]}] ;# J9.F37 HB20_P +#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[20]}] ;# J9.F38 HB20_N +#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[21]}] ;# J9.E36 HB21_P +#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[21]}] ;# J9.E37 HB21_N + +#set_property -dict {LOC AW14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_p}] ;# J9.H4 CLK0_M2C_P +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_n}] ;# J9.H5 CLK0_M2C_N +#set_property -dict {LOC AV18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_p}] ;# J9.G2 CLK1_M2C_P +#set_property -dict {LOC AW18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_n}] ;# J9.G3 CLK1_M2C_N + +#set_property -dict {LOC G25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_p}] ;# J9.L32 USER_DEF0_P +#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_n}] ;# J9.L33 USER_DEF0_N +#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_p}] ;# J9.L24 REFCLK_M2C_P +#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_n}] ;# J9.L25 REFCLK_M2C_N +set_property -dict {LOC E23 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_p}] ;# J9.L16 SYNC_C2M_P +set_property -dict {LOC E22 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_n}] ;# J9.L17 SYNC_C2M_N +#set_property -dict {LOC J24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_p}] ;# J9.L28 SYNC_M2C_P +#set_property -dict {LOC H24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_n}] ;# J9.L29 SYNC_M2C_N + +#set_property -dict {LOC AV23 IOSTANDARD LVCMOS18} [get_ports {fmc_pg_m2c}] ;# J9.F1 PG_M2C +#set_property -dict {LOC AW23 IOSTANDARD LVCMOS18} [get_ports {fmc_prsnt_m2c_l}] ;# J9.H2 PRSNT_M2C_L +#set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {fmc_hspc_prsnt_m2c_l}] ;# J9.Z1 HSPC_PRSNT_M2C_L + +set_property -dict {LOC Y7 } [get_ports {fmc_qsfp_1_tx_p[0]}] ;# MGTYTXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C2 DP0_C2M_P +set_property -dict {LOC Y6 } [get_ports {fmc_qsfp_1_tx_n[0]}] ;# MGTYTXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C3 DP0_C2M_N +set_property -dict {LOC Y2 } [get_ports {fmc_qsfp_1_rx_p[0]}] ;# MGTYRXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C6 DP0_M2C_P +set_property -dict {LOC Y1 } [get_ports {fmc_qsfp_1_rx_n[0]}] ;# MGTYRXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C7 DP0_M2C_N +set_property -dict {LOC V7 } [get_ports {fmc_qsfp_1_tx_p[2]}] ;# MGTYTXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A22 DP1_C2M_P +set_property -dict {LOC V6 } [get_ports {fmc_qsfp_1_tx_n[2]}] ;# MGTYTXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A23 DP1_C2M_N +set_property -dict {LOC V2 } [get_ports {fmc_qsfp_1_rx_p[2]}] ;# MGTYRXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A2 DP1_M2C_P +set_property -dict {LOC V1 } [get_ports {fmc_qsfp_1_rx_n[2]}] ;# MGTYRXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A3 DP1_M2C_N +set_property -dict {LOC W9 } [get_ports {fmc_qsfp_1_tx_p[1]}] ;# MGTYTXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A26 DP2_C2M_P +set_property -dict {LOC W8 } [get_ports {fmc_qsfp_1_tx_n[1]}] ;# MGTYTXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A27 DP2_C2M_N +set_property -dict {LOC W4 } [get_ports {fmc_qsfp_1_rx_p[1]}] ;# MGTYRXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A6 DP2_M2C_P +set_property -dict {LOC W3 } [get_ports {fmc_qsfp_1_rx_n[1]}] ;# MGTYRXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A7 DP2_M2C_N +set_property -dict {LOC AA9 } [get_ports {fmc_qsfp_1_tx_p[3]}] ;# MGTYTXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A30 DP3_C2M_P +set_property -dict {LOC AA8 } [get_ports {fmc_qsfp_1_tx_n[3]}] ;# MGTYTXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A31 DP3_C2M_N +set_property -dict {LOC AA4 } [get_ports {fmc_qsfp_1_rx_p[3]}] ;# MGTYRXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A10 DP3_M2C_P +set_property -dict {LOC AA3 } [get_ports {fmc_qsfp_1_rx_n[3]}] ;# MGTYRXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A11 DP3_M2C_N +set_property -dict {LOC Y11 } [get_ports fmc_qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_229 from J9.D4 GBTCLK0_M2C_P +set_property -dict {LOC Y10 } [get_ports fmc_qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_229 from J9.D5 GBTCLK0_M2C_N +#set_property -dict {LOC V11 } [get_ports fmc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_229 from U27.14 OUT3 +#set_property -dict {LOC V10 } [get_ports fmc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_229 from U27.13 OUT3B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_1_mgt_refclk [get_ports fmc_qsfp_1_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_0_1 [get_ports fmc_mgt_refclk_0_1_p] + +set_property -dict {LOC AC9 } [get_ports {fmc_qsfp_6_tx_p[1]}] ;# MGTYTXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A34 DP4_C2M_P +set_property -dict {LOC AC8 } [get_ports {fmc_qsfp_6_tx_n[1]}] ;# MGTYTXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A35 DP4_C2M_N +set_property -dict {LOC AC4 } [get_ports {fmc_qsfp_6_rx_p[1]}] ;# MGTYRXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A14 DP4_M2C_P +set_property -dict {LOC AC3 } [get_ports {fmc_qsfp_6_rx_n[1]}] ;# MGTYRXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A15 DP4_M2C_N +set_property -dict {LOC AE9 } [get_ports {fmc_qsfp_6_tx_p[0]}] ;# MGTYTXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A38 DP5_C2M_P +set_property -dict {LOC AE8 } [get_ports {fmc_qsfp_6_tx_n[0]}] ;# MGTYTXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A39 DP5_C2M_N +set_property -dict {LOC AE4 } [get_ports {fmc_qsfp_6_rx_p[0]}] ;# MGTYRXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A18 DP5_M2C_P +set_property -dict {LOC AE3 } [get_ports {fmc_qsfp_6_rx_n[0]}] ;# MGTYRXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A19 DP5_M2C_N +set_property -dict {LOC AD7 } [get_ports {fmc_qsfp_6_tx_p[2]}] ;# MGTYTXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B36 DP6_C2M_P +set_property -dict {LOC AD6 } [get_ports {fmc_qsfp_6_tx_n[2]}] ;# MGTYTXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B37 DP6_C2M_N +set_property -dict {LOC AD2 } [get_ports {fmc_qsfp_6_rx_p[2]}] ;# MGTYRXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B16 DP6_M2C_P +set_property -dict {LOC AD1 } [get_ports {fmc_qsfp_6_rx_n[2]}] ;# MGTYRXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B17 DP6_M2C_N +set_property -dict {LOC AB7 } [get_ports {fmc_qsfp_6_tx_p[3]}] ;# MGTYTXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B32 DP7_C2M_P +set_property -dict {LOC AB6 } [get_ports {fmc_qsfp_6_tx_n[3]}] ;# MGTYTXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B33 DP7_C2M_N +set_property -dict {LOC AB2 } [get_ports {fmc_qsfp_6_rx_p[3]}] ;# MGTYRXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B12 DP7_M2C_P +set_property -dict {LOC AB1 } [get_ports {fmc_qsfp_6_rx_n[3]}] ;# MGTYRXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B13 DP7_M2C_N +set_property -dict {LOC AD11} [get_ports fmc_qsfp_6_mgt_refclk_p] ;# MGTREFCLK0P_228 from J9.B20 GBTCLK1_M2C_P +set_property -dict {LOC AD10} [get_ports fmc_qsfp_6_mgt_refclk_n] ;# MGTREFCLK0N_228 from J9.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_6_mgt_refclk [get_ports fmc_qsfp_6_mgt_refclk_p] + +set_property -dict {LOC L9 } [get_ports {fmc_qsfp_4_tx_p[3]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B28 DP8_C2M_P +set_property -dict {LOC L8 } [get_ports {fmc_qsfp_4_tx_n[3]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B29 DP8_C2M_N +set_property -dict {LOC L4 } [get_ports {fmc_qsfp_4_rx_p[3]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B8 DP8_M2C_P +set_property -dict {LOC L3 } [get_ports {fmc_qsfp_4_rx_n[3]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B9 DP8_M2C_N +set_property -dict {LOC K7 } [get_ports {fmc_qsfp_4_tx_p[2]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B24 DP9_C2M_P +set_property -dict {LOC K6 } [get_ports {fmc_qsfp_4_tx_n[2]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B25 DP9_C2M_N +set_property -dict {LOC K2 } [get_ports {fmc_qsfp_4_rx_p[2]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B4 DP9_M2C_P +set_property -dict {LOC K1 } [get_ports {fmc_qsfp_4_rx_n[2]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B5 DP9_M2C_N +set_property -dict {LOC M7 } [get_ports {fmc_qsfp_4_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z24 DP10_C2M_P +set_property -dict {LOC M6 } [get_ports {fmc_qsfp_4_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z25 DP10_C2M_N +set_property -dict {LOC M2 } [get_ports {fmc_qsfp_4_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y10 DP10_M2C_P +set_property -dict {LOC M1 } [get_ports {fmc_qsfp_4_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y11 DP10_M2C_N +set_property -dict {LOC N9 } [get_ports {fmc_qsfp_4_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y26 DP11_C2M_P +set_property -dict {LOC N8 } [get_ports {fmc_qsfp_4_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y27 DP11_C2M_N +set_property -dict {LOC N4 } [get_ports {fmc_qsfp_4_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z12 DP11_M2C_P +set_property -dict {LOC N3 } [get_ports {fmc_qsfp_4_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z13 DP11_M2C_N +set_property -dict {LOC M11 } [get_ports fmc_qsfp_4_mgt_refclk_p] ;# MGTREFCLK0P_231 from J9.L12 GBTCLK2_M2C_P +set_property -dict {LOC M10 } [get_ports fmc_qsfp_4_mgt_refclk_n] ;# MGTREFCLK0N_231 from J9.L13 GBTCLK2_M2C_N +#set_property -dict {LOC K11 } [get_ports fmc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_231 from U27.17 OUT2 +#set_property -dict {LOC K10 } [get_ports fmc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_231 from U27.16 OUT2B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_4_mgt_refclk [get_ports fmc_qsfp_4_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_2_1 [get_ports fmc_mgt_refclk_2_1_p] + +set_property -dict {LOC P7 } [get_ports {fmc_qsfp_3_tx_p[2]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z28 DP12_C2M_P +set_property -dict {LOC P6 } [get_ports {fmc_qsfp_3_tx_n[2]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z29 DP12_C2M_N +set_property -dict {LOC P2 } [get_ports {fmc_qsfp_3_rx_p[2]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y14 DP12_M2C_P +set_property -dict {LOC P1 } [get_ports {fmc_qsfp_3_rx_n[2]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y15 DP12_M2C_N +set_property -dict {LOC R9 } [get_ports {fmc_qsfp_3_tx_p[3]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y30 DP13_C2M_P +set_property -dict {LOC R8 } [get_ports {fmc_qsfp_3_tx_n[3]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y31 DP13_C2M_N +set_property -dict {LOC R4 } [get_ports {fmc_qsfp_3_rx_p[3]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z16 DP13_M2C_P +set_property -dict {LOC R3 } [get_ports {fmc_qsfp_3_rx_n[3]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z17 DP13_M2C_N +set_property -dict {LOC T7 } [get_ports {fmc_qsfp_3_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M18 DP14_C2M_P +set_property -dict {LOC T6 } [get_ports {fmc_qsfp_3_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M19 DP14_C2M_N +set_property -dict {LOC T2 } [get_ports {fmc_qsfp_3_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y18 DP14_M2C_P +set_property -dict {LOC T1 } [get_ports {fmc_qsfp_3_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y19 DP14_M2C_N +set_property -dict {LOC U9 } [get_ports {fmc_qsfp_3_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M22 DP15_C2M_P +set_property -dict {LOC U8 } [get_ports {fmc_qsfp_3_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M23 DP15_C2M_N +set_property -dict {LOC U4 } [get_ports {fmc_qsfp_3_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y22 DP15_M2C_P +set_property -dict {LOC U3 } [get_ports {fmc_qsfp_3_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y23 DP15_M2C_N +set_property -dict {LOC T11 } [get_ports fmc_qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_230 from J9.L8 GBTCLK3_M2C_P +set_property -dict {LOC T10 } [get_ports fmc_qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_230 from J9.L9 GBTCLK3_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_3_mgt_refclk [get_ports fmc_qsfp_3_mgt_refclk_p] + +set_property -dict {LOC AF7 } [get_ports {fmc_qsfp_5_tx_p[3]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M26 DP16_C2M_P +set_property -dict {LOC AF6 } [get_ports {fmc_qsfp_5_tx_n[3]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M27 DP16_C2M_N +set_property -dict {LOC AF2 } [get_ports {fmc_qsfp_5_rx_p[3]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z32 DP16_M2C_P +set_property -dict {LOC AF1 } [get_ports {fmc_qsfp_5_rx_n[3]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z33 DP16_M2C_N +set_property -dict {LOC AG9 } [get_ports {fmc_qsfp_5_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M30 DP17_C2M_P +set_property -dict {LOC AG8 } [get_ports {fmc_qsfp_5_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M31 DP17_C2M_N +set_property -dict {LOC AG4 } [get_ports {fmc_qsfp_5_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y34 DP17_M2C_P +set_property -dict {LOC AG3 } [get_ports {fmc_qsfp_5_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y35 DP17_M2C_N +set_property -dict {LOC AH7 } [get_ports {fmc_qsfp_5_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M34 DP18_C2M_P +set_property -dict {LOC AH6 } [get_ports {fmc_qsfp_5_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M35 DP18_C2M_N +set_property -dict {LOC AH2 } [get_ports {fmc_qsfp_5_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z36 DP18_M2C_P +set_property -dict {LOC AH1 } [get_ports {fmc_qsfp_5_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z37 DP18_M2C_N +set_property -dict {LOC AJ9 } [get_ports {fmc_qsfp_5_tx_p[0]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M38 DP19_C2M_P +set_property -dict {LOC AJ8 } [get_ports {fmc_qsfp_5_tx_n[0]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M39 DP19_C2M_N +set_property -dict {LOC AJ4 } [get_ports {fmc_qsfp_5_rx_p[0]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y38 DP19_M2C_P +set_property -dict {LOC AJ3 } [get_ports {fmc_qsfp_5_rx_n[0]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y39 DP19_M2C_N +set_property -dict {LOC AH11} [get_ports fmc_qsfp_5_mgt_refclk_p] ;# MGTREFCLK0P_227 from J9.L4 GBTCLK4_M2C_P +set_property -dict {LOC AH10} [get_ports fmc_qsfp_5_mgt_refclk_n] ;# MGTREFCLK0N_227 from J9.L5 GBTCLK4_M2C_N +#set_property -dict {LOC AF11} [get_ports fmc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_227 from U27.11 OUT4 +#set_property -dict {LOC AF10} [get_ports fmc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_227 from U27.12 OUT4B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_5_mgt_refclk [get_ports fmc_qsfp_5_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_4_1 [get_ports fmc_mgt_refclk_4_1_p] + +set_property -dict {LOC J9 } [get_ports {fmc_qsfp_2_tx_p[3]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z8 DP20_C2M_P +set_property -dict {LOC J8 } [get_ports {fmc_qsfp_2_tx_n[3]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z9 DP20_C2M_N +set_property -dict {LOC J4 } [get_ports {fmc_qsfp_2_rx_p[3]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M14 DP20_M2C_P +set_property -dict {LOC J3 } [get_ports {fmc_qsfp_2_rx_n[3]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M15 DP20_M2C_N +set_property -dict {LOC H7 } [get_ports {fmc_qsfp_2_tx_p[2]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y6 DP21_C2M_P +set_property -dict {LOC H6 } [get_ports {fmc_qsfp_2_tx_n[2]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y7 DP21_C2M_N +set_property -dict {LOC H2 } [get_ports {fmc_qsfp_2_rx_p[2]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M10 DP21_M2C_P +set_property -dict {LOC H1 } [get_ports {fmc_qsfp_2_rx_n[2]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M11 DP21_M2C_N +set_property -dict {LOC G9 } [get_ports {fmc_qsfp_2_tx_p[0]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z4 DP22_C2M_P +set_property -dict {LOC G8 } [get_ports {fmc_qsfp_2_tx_n[0]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z5 DP22_C2M_N +set_property -dict {LOC G4 } [get_ports {fmc_qsfp_2_rx_p[0]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M6 DP22_M2C_P +set_property -dict {LOC G3 } [get_ports {fmc_qsfp_2_rx_n[0]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M7 DP22_M2C_N +set_property -dict {LOC F7 } [get_ports {fmc_qsfp_2_tx_p[1]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y2 DP23_C2M_P +set_property -dict {LOC F6 } [get_ports {fmc_qsfp_2_tx_n[1]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y3 DP23_C2M_N +set_property -dict {LOC F2 } [get_ports {fmc_qsfp_2_rx_p[1]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M2 DP23_M2C_P +set_property -dict {LOC F1 } [get_ports {fmc_qsfp_2_rx_n[1]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M3 DP23_M2C_N +set_property -dict {LOC H11 } [get_ports fmc_qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_232 from J9.Z20 GBTCLK5_M2C_P +set_property -dict {LOC H10 } [get_ports fmc_qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_232 from J9.Z21 GBTCLK5_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_2_mgt_refclk [get_ports fmc_qsfp_2_mgt_refclk_p] diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile new file mode 100644 index 000000000..578e97b42 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile @@ -0,0 +1,115 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/i2c_master.v +SYN_FILES += pll/si5341_i2c_init.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile new file mode 100644 index 000000000..578e97b42 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile @@ -0,0 +1,115 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/i2c_master.v +SYN_FILES += pll/si5341_i2c_init.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl new file mode 100644 index 000000000..cecca12f7 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl @@ -0,0 +1,76 @@ +# Copyright (c) 2021 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +set base_name {eth_xcvr_gt} + +set preset {GTY-10GBASE-R} + +set freerun_freq {125} +set line_rate {10.3125} +set refclk_freq {161.1328125} +set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set user_data_width {64} +set int_data_width $user_data_width +set extra_ports [list] +set extra_pll_ports [list {qpll0lock_out}] + +set config [dict create] + +dict set config TX_LINE_RATE $line_rate +dict set config TX_REFCLK_FREQUENCY $refclk_freq +dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config TX_USER_DATA_WIDTH $user_data_width +dict set config TX_INT_DATA_WIDTH $int_data_width +dict set config RX_LINE_RATE $line_rate +dict set config RX_REFCLK_FREQUENCY $refclk_freq +dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config RX_USER_DATA_WIDTH $user_data_width +dict set config RX_INT_DATA_WIDTH $int_data_width +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {CORE} +dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_TX_USER_CLOCKING {CORE} +dict set config LOCATE_RX_USER_CLOCKING {CORE} +dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} +dict set config FREERUN_FREQUENCY $freerun_freq +dict set config DISABLE_LOC_XDC {1} + +proc create_gtwizard_ip {name preset config} { + create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name + set ip [get_ips $name] + set_property CONFIG.preset $preset $ip + set config_list {} + dict for {name value} $config { + lappend config_list "CONFIG.${name}" $value + } + set_property -dict $config_list $ip +} + +# variant with channel and common +dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] +dict set config LOCATE_COMMON {CORE} + +create_gtwizard_ip "${base_name}_full" $preset $config + +# variant with channel only +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {EXAMPLE_DESIGN} + +create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/lib/eth b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/lib/eth new file mode 120000 index 000000000..11a54ed36 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/lib/eth @@ -0,0 +1 @@ +../../../../ \ No newline at end of file diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161-Registers.txt b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161-Registers.txt new file mode 100644 index 000000000..bd345341b --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161-Registers.txt @@ -0,0 +1,412 @@ +# Si534x/7x/8x/9x Registers Script +# +# Part: Si5341 +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj +# Design ID: 9k2_161 +# Includes Pre/Post Download Control Register Writes: Yes +# Die Revision: B1 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:38:53 GMT-07:00 +Address,Data +# +# Start configuration preamble +0x0B24,0xC0 +0x0B25,0x00 +# Rev D stuck divider fix +0x0502,0x01 +0x0505,0x03 +0x0957,0x17 +0x0B4E,0x1A +# End configuration preamble +# +# Delay 300 msec +# Delay is worst case time for device to complete any calibration +# that is running due to device state change previous to this script +# being processed. +# +# Start configuration registers +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x74 +0x0017,0xD0 +0x0018,0xFF +0x0021,0x0B +0x0022,0x00 +0x002B,0x02 +0x002C,0x33 +0x002D,0x05 +0x002E,0xAE +0x002F,0x00 +0x0030,0xAE +0x0031,0x00 +0x0032,0x00 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0xAE +0x0037,0x00 +0x0038,0xAE +0x0039,0x00 +0x003A,0x00 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x0041,0x07 +0x0042,0x07 +0x0043,0x00 +0x0044,0x00 +0x009E,0x00 +0x0102,0x01 +0x0108,0x06 +0x0109,0x09 +0x010A,0x3B +0x010B,0x28 +0x010D,0x06 +0x010E,0x09 +0x010F,0x3B +0x0110,0x28 +0x0112,0x02 +0x0113,0x09 +0x0114,0x3B +0x0115,0x29 +0x0117,0x06 +0x0118,0x09 +0x0119,0x3B +0x011A,0x28 +0x011C,0x06 +0x011D,0x09 +0x011E,0x3B +0x011F,0x28 +0x0121,0x06 +0x0122,0x09 +0x0123,0x3B +0x0124,0x28 +0x0126,0x06 +0x0127,0x09 +0x0128,0x3B +0x0129,0x28 +0x012B,0x06 +0x012C,0x09 +0x012D,0x3B +0x012E,0x28 +0x0130,0x06 +0x0131,0x09 +0x0132,0x3B +0x0133,0x28 +0x013A,0x06 +0x013B,0x09 +0x013C,0x3B +0x013D,0x28 +0x013F,0x00 +0x0140,0x00 +0x0141,0x40 +0x0206,0x00 +0x0208,0x02 +0x0209,0x00 +0x020A,0x00 +0x020B,0x00 +0x020C,0x00 +0x020D,0x00 +0x020E,0x01 +0x020F,0x00 +0x0210,0x00 +0x0211,0x00 +0x0212,0x02 +0x0213,0x00 +0x0214,0x00 +0x0215,0x00 +0x0216,0x00 +0x0217,0x00 +0x0218,0x01 +0x0219,0x00 +0x021A,0x00 +0x021B,0x00 +0x021C,0x00 +0x021D,0x00 +0x021E,0x00 +0x021F,0x00 +0x0220,0x00 +0x0221,0x00 +0x0222,0x00 +0x0223,0x00 +0x0224,0x00 +0x0225,0x00 +0x0226,0x00 +0x0227,0x00 +0x0228,0x00 +0x0229,0x00 +0x022A,0x00 +0x022B,0x00 +0x022C,0x00 +0x022D,0x00 +0x022E,0x00 +0x022F,0x00 +0x0235,0x00 +0x0236,0x00 +0x0237,0x00 +0x0238,0x90 +0x0239,0x54 +0x023A,0x00 +0x023B,0x00 +0x023C,0x00 +0x023D,0x00 +0x023E,0x80 +0x024A,0x00 +0x024B,0x00 +0x024C,0x00 +0x024D,0x00 +0x024E,0x00 +0x024F,0x00 +0x0250,0x03 +0x0251,0x00 +0x0252,0x00 +0x0253,0x00 +0x0254,0x00 +0x0255,0x00 +0x0256,0x00 +0x0257,0x00 +0x0258,0x00 +0x0259,0x00 +0x025A,0x00 +0x025B,0x00 +0x025C,0x00 +0x025D,0x00 +0x025E,0x00 +0x025F,0x00 +0x0260,0x00 +0x0261,0x00 +0x0262,0x00 +0x0263,0x00 +0x0264,0x00 +0x0268,0x00 +0x0269,0x00 +0x026A,0x00 +0x026B,0x39 +0x026C,0x6B +0x026D,0x32 +0x026E,0x5F +0x026F,0x31 +0x0270,0x36 +0x0271,0x31 +0x0272,0x00 +0x0302,0x00 +0x0303,0x00 +0x0304,0x00 +0x0305,0x80 +0x0306,0x14 +0x0307,0x00 +0x0308,0x00 +0x0309,0x00 +0x030A,0x00 +0x030B,0x80 +0x030C,0x00 +0x030D,0x00 +0x030E,0x00 +0x030F,0x10 +0x0310,0x42 +0x0311,0x08 +0x0312,0x00 +0x0313,0x00 +0x0314,0x00 +0x0315,0x00 +0x0316,0x80 +0x0317,0x00 +0x0318,0x00 +0x0319,0x00 +0x031A,0x00 +0x031B,0x00 +0x031C,0x00 +0x031D,0x00 +0x031E,0x00 +0x031F,0x00 +0x0320,0x00 +0x0321,0x00 +0x0322,0x00 +0x0323,0x00 +0x0324,0x00 +0x0325,0x00 +0x0326,0x00 +0x0327,0x00 +0x0328,0x00 +0x0329,0x00 +0x032A,0x00 +0x032B,0x00 +0x032C,0x00 +0x032D,0x00 +0x032E,0x00 +0x032F,0x00 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 +0x0333,0x00 +0x0334,0x00 +0x0335,0x00 +0x0336,0x00 +0x0337,0x00 +0x0338,0x00 +0x0339,0x1F +0x033B,0x00 +0x033C,0x00 +0x033D,0x00 +0x033E,0x00 +0x033F,0x00 +0x0340,0x00 +0x0341,0x00 +0x0342,0x00 +0x0343,0x00 +0x0344,0x00 +0x0345,0x00 +0x0346,0x00 +0x0347,0x00 +0x0348,0x00 +0x0349,0x00 +0x034A,0x00 +0x034B,0x00 +0x034C,0x00 +0x034D,0x00 +0x034E,0x00 +0x034F,0x00 +0x0350,0x00 +0x0351,0x00 +0x0352,0x00 +0x0353,0x00 +0x0354,0x00 +0x0355,0x00 +0x0356,0x00 +0x0357,0x00 +0x0358,0x00 +0x0359,0x00 +0x035A,0x00 +0x035B,0x00 +0x035C,0x00 +0x035D,0x00 +0x035E,0x00 +0x035F,0x00 +0x0360,0x00 +0x0361,0x00 +0x0362,0x00 +0x0802,0x00 +0x0803,0x00 +0x0804,0x00 +0x0805,0x00 +0x0806,0x00 +0x0807,0x00 +0x0808,0x00 +0x0809,0x00 +0x080A,0x00 +0x080B,0x00 +0x080C,0x00 +0x080D,0x00 +0x080E,0x00 +0x080F,0x00 +0x0810,0x00 +0x0811,0x00 +0x0812,0x00 +0x0813,0x00 +0x0814,0x00 +0x0815,0x00 +0x0816,0x00 +0x0817,0x00 +0x0818,0x00 +0x0819,0x00 +0x081A,0x00 +0x081B,0x00 +0x081C,0x00 +0x081D,0x00 +0x081E,0x00 +0x081F,0x00 +0x0820,0x00 +0x0821,0x00 +0x0822,0x00 +0x0823,0x00 +0x0824,0x00 +0x0825,0x00 +0x0826,0x00 +0x0827,0x00 +0x0828,0x00 +0x0829,0x00 +0x082A,0x00 +0x082B,0x00 +0x082C,0x00 +0x082D,0x00 +0x082E,0x00 +0x082F,0x00 +0x0830,0x00 +0x0831,0x00 +0x0832,0x00 +0x0833,0x00 +0x0834,0x00 +0x0835,0x00 +0x0836,0x00 +0x0837,0x00 +0x0838,0x00 +0x0839,0x00 +0x083A,0x00 +0x083B,0x00 +0x083C,0x00 +0x083D,0x00 +0x083E,0x00 +0x083F,0x00 +0x0840,0x00 +0x0841,0x00 +0x0842,0x00 +0x0843,0x00 +0x0844,0x00 +0x0845,0x00 +0x0846,0x00 +0x0847,0x00 +0x0848,0x00 +0x0849,0x00 +0x084A,0x00 +0x084B,0x00 +0x084C,0x00 +0x084D,0x00 +0x084E,0x00 +0x084F,0x00 +0x0850,0x00 +0x0851,0x00 +0x0852,0x00 +0x0853,0x00 +0x0854,0x00 +0x0855,0x00 +0x0856,0x00 +0x0857,0x00 +0x0858,0x00 +0x0859,0x00 +0x085A,0x00 +0x085B,0x00 +0x085C,0x00 +0x085D,0x00 +0x085E,0x00 +0x085F,0x00 +0x0860,0x00 +0x0861,0x00 +0x090E,0x00 +0x091C,0x04 +0x0943,0x00 +0x0949,0x03 +0x094A,0x30 +0x094E,0x49 +0x094F,0x02 +0x095E,0x00 +0x0A02,0x00 +0x0A03,0x03 +0x0A04,0x01 +0x0A05,0x03 +0x0A14,0x00 +0x0A1A,0x00 +0x0A20,0x00 +0x0A26,0x00 +0x0A2C,0x00 +0x0B44,0x0F +0x0B4A,0x1C +0x0B57,0xA5 +0x0B58,0x00 +# End configuration registers +# +# Start configuration postamble +0x001C,0x01 +0x0B24,0xC3 +0x0B25,0x02 +# End configuration postamble diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161.slabtimeproj b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161.slabtimeproj new file mode 100644 index 0000000000000000000000000000000000000000..2d660f8f657a2939f3ecfa2d822879e4269e0f7a GIT binary patch literal 10192 zcmV;>CokB<528U>x=CYLX%=gE^WxUfM8zt=NFnSS4o`9=a4zDl?K8sT^ zmW4nP@=K@-FyO=U-OHIK!!cg6GiQ?v>46+{VC7SdGdI|(sV~)dHLt4J;|pER_>|CM`lTIN!`})2)ZJYlqr`J6oK@@G4{A}$5Ji> z@tlBxj%ZM6MoRW^Zqt9|J?wZNoeA3@Dh(g-*;PlDI(hBkQhk>0d;dPIsynp4F0c(Y@PtMHG%kOcK2 z`i-4EQScI@*^ku!Wd%F$!=#1nqxo5x$79We%r(M?q*stHV%Q6tzV7Yac^&gU52icQ zTg9(80Kji_V2D=UDF+@JyPb#ba4po0LZQY3!vZ8_>3T6oYwk|iiVelT=*ToC)u#ZqMWZH2AUhmUjgbO*6v4p;341Re!S$L#O z(Rk{KIV$hQyt` zzo?N=*Gk$|DVJt(axvTQ3ypqQe#;=rfV=@sGa(FRkfM6^vc~Aez4cwj_I+SRyN>7uxNs15w$@BK{-Ip%OR2ZdF&=ep(=R)A|pCP#cD?YDSB!oLsx0W zHAE}c8ex!^+_a_XJaDJzGz(o@;^@eCzuk-oo~UaqLYGV{v$s=8G57X4(yS)nB^Wup z!Apbr9$k%x{f{jIlS5lA{oS)sTzsNTu9DX(D$#3-`!>Ew?Wk)nrpkuDGRO3plE=eL zh>*Q8aR6dppB6oN4$-C+MWi=1g|l=R7n{{_n$&%4HzeMA-mL@!I-4a&Jg_{auymHE zz0j~AG!fl;BWi+E3V?DNTb~$;OnCF3suQE(pM^^M!f3f^l%qD&KY>QY_hu^7_by`Z zVG0uqt;pWuCvd0~5lG8cd(85h}fILSa@pgplOX>BNtLmHgu!K?T zh{?k4cu(C=s*%!T!v8~HY%Y)9EGnb2c(vT6ESIlto@6TuO0JkctqL&=!2x1|_HIwV zBUQRc0(HeM?)y9tjBKG@Cy<*;Yr9(lycg(b|oEv1!ku(k1 z67Bx-ws;(ul5cJpq<{}eipk|L=|T;s196mzKgyhjjmA?>6s9!Rwie_$dDZc39A$Y^ zMQFR?Vp~b0Sx!^Q-(6M8K}vi=8T9I5^#`7=fOb@z>p49bR-{t`^t}gju%Gthu9XZA zkNY#(BGjU$)ZxvLv2V4=K9fxmJ-rO4@^3wVy6fCRJw;_Vvk{>PsM0MBcf1~l`GspXlA2&NTYQ?Xd}1}%76XX!OSn&Pftoi(T3n<|0Ak0 zV+Q4{*?eEsxN<3 zFD3{_D^IYx2+VnkJVX0+f$$>->4xW!E>ds|;8>-E1`W0Fc-r!5|NOv(i~>H$^Mss$ zUyPd3WV)(0?>02`qnZTNAYzLc?B>#Ry&gVSqo7$cBJmY$Z@;euJ(9i&?3UdI>B!i+ z?dWQll!{c)kwr;TRXDnD_2O?;`~IJ^x34R+!f20Q957!S{L#~O4SFo`U=NCW^1N-l4&qq))6G(NwC`nrvm zRKYU1N^H`-xb2IpY(SCi7>i4Iq+49uD@h*jnqhx_d(lRN+BWhtksC4( zezdzsHgRKa06eQJuAO;O@M>x?9U;RJqmEf=VPZz+h!#>8!N&*XMe+`{eWHX56zfM&0QgVK(DPqA7LM34-P<;z zhI}a|fro%i(DYtW}_b8hL3dv~KI5bC3{+79$^o z`>eJWCJ&OZitS6R2U#d=1Ib9u=zLJ)Zd6#|Z2<>=8sKoUZS?(rJa{XW?0^1|Fy~-O z_-Ru*erSe`6?ohFmaUyzVlXt@H`md^h1T5jPO_wtttP;@f@kByRKx*e`-lU#zhdSh zX6`7ae|5J+OOZ*`FTScS>EicyC#hWvcY*AK2)6PXEM`S|T191nvA%&VH)H%IvrS%( z$-F}X0aLh^xoXC6Eqqr=7VdPtSM+>7&ZEA`-kdN<(;1zx@?Le!{xQp`{(X}cv0LF2 zEGGSV2X`;5*&8D(*i545OWU0I##WrTqZ?Gzm1DeH>j~}w%(5zPH*ACB&rE(`k|f*| z2V{S**sG58T+xOLgA+ZOec5Wq2Qe<@WgCt;0DN`HTSk|6x%-9PitTbD;imVT4rN$$VbOh>POMiH*XoAE~?4ibkqxE z(GeIZ+1cyw)iLqKcJ9@EIz_*UDctlN*RrYcvM@eem+pp$eyH_zypoGNu*g$uTU3vQ zp|2zRJ7V=7C2zENNks{T&{DEGKq$z^qUBUVc4`mO@P9svn>Xd9(>Rb3WulTv&w13$ zO>FsshtSVU%*14cr&ho(RSg)Hh03vvGbH_8U}Lg1A=8h!rb5=GW6hC>&QE^G;~qUx zG$R}7saUe2mTeEWb_vb&Ouq7#SKZdx_mzDjap>HY6a)@WrbV-itRz{ckBIJCJt?LqN?}em?ttG+7aU+y%Xe6})aA=dm^8Mwpx^BVyR}y=px1|aTWz)H- zD!UrVOfghB5}McSq*&ldn&FKQ^XHmF=<5pjVayXgm)665^e$mT)?3cjMFgd}_KgD% zSs_-Y3d3C_K71_yx}8FK`m^u-f3>BL4rU`>Y_EwxLswGtC26hGrff73R## z7DBl>6I}_`wPU28Zzt?`(aJ#0dIaTZSc3LeWP5{(=5+>$h=Q@O6yXel9!sdGJd8+U zB(-BXGquuH=868yD=!!hW9p)stiu5{mjjh~2Jw8@(j8Qnw|wXkL5Pust@w&7Vi6XB zJUL-Bz1*V4AyKl>BJX912;ED!D^bmI`<(5*5#Z9AD;Q00BFEud%TN1E{5C3=4TjFC z+ysLzlEblh(DW3ASB7n~a$YPI+!>^Ptt4?zamPe8lnvko0prPo=53<;?D7oN=1pj; zq&g{=H8~Lq9^qiX60^Urr3BXEEec5alEM-54p^ySpvT)_>OqJ=4yR;xQjZ)<>j<|! zu34|^CyNrqjR$-r6tok|1S{MyUOn+)>uNm$^=(>w3WajO?Sy$XD zrydIt5Y9G~0$KZ6&2>uOZXog^EBW39R?wh}cN1-c(y$1LZ5G?U?k>{7OKSiSp#bn- zYxSE%G;*2@Laf-2^FycxRB$u6{sUlPqzDfw+G5J|yQ+TLbk%T6mh(5&<})!gGep9q zGEDk}b+^;14!yOY!d{zu!T>)Oexdzr^!Ly(c z+s14^t~eTg{Ld&Hwj>}+oxmvbJ$TVCr)`JkvVS*KQ7AJ?&~HuE zUi4fQ2~b=1&NFs|*k9l}7%lW44;*+SC|0{&A8DuoX)dO6!MT&`jumCPke6Vouj$7b zsFaEx(muD_xpn^dUiT-~P)M{~dF&#TmwnxHqjsc|v!eYx?9*+)`Z}l$E7}kVJ4~$2 znQ4u%Hy-05p|p=O7_t-#ClZXY!M<(kLm!(WI-?|~ zJNXmMf@Ie6klTTwwoEF!(43X1vljl3G6HPq&VD1FPvw^>nsj9`>xS`3X`WVNCz%fMA<#ZmZ7sE=Q;WP_4-btF z>|)%q^*1mG4x4gmUBo=l%*|c^^dLv#3>Mk_nnv;56nQPH$%X+qsSCtvT<{n=UQeE~ zx36F?v~bJmzVKHRA21*BSjsz{3B9U=uzrF02Z8!FxJXyZL50-jBPG5k0e7SbgsJX% zfUCiAEsT}6V%L{?0Yhc3Y${Wm@rhe46=>j(#ZsTGFlD5IpZ8tfb|a!&X>pb7D&Hh= zynrL8hKE=b^<$S=Ond9X;R>(UY67(b6qjI=c3nJ+1=$H}l_&Z<@LA6@A5fijKkGy2 zAQ9t_kvliAXx#?tsi|#hc6Fz$tw2@FqTjGdGL&8aWqt-k7^_7<{8>n#I)$QSI-|R6 z!Q%#A@?;kVPVKidV7AkoT9#cMF=o+Qto!e6jgKln&P`yW@1})@h;dPYLZaIs)%l^i$?4h@+kH^(ZEaFa&yT&QH1gN&0 zXvhUY$RHnaa__Vtz8~Ypli3(kwI^EqcCc;Dy&Mn7UHbbbbuV zkY;l9(4~Pst|ea7kYzz9lVU!&2pNV1SbEPK6ikjsrB?-&rhWTS_e~1MSSXZ0TRJT{ zk)~_ioRFohA$=YX)i63&UCekc(% z1!Y9ypcBPtze33BdEqfea^eVdvx{~wcvZjTCHIEclvqUs`V#fb+KexG6N3&ebb9Sp z1NKk9<@{o>k%BR}7yu6fTpui<-h6RKkM;g=IUw%OzZsxwP=+XXvh4*nWNpmV(HgbH73&9Pbo!743ZVs4B1OQ?(CnaotUF`+`n5WlI)(@h6diTy`07 zv<4n*$GAS6`PTYsn|fB-mNDH$xiD-sy7S~{w@f`(7`$DMcb@=33amSm9KxAE$iG?7 zCptwysgS&GA8Q9F;>IePd~sxkZz;_w7dNi%7DE~tD_r1kWUmYw@Ii||G1QhP@-q;$ z7q4r%`3gqVDnr0aZ7@}j*2(V4>A(j`tyk>Di#a8Ho;>j8)0(ECw7ey|GfI~A{2`ol z7Hg)SlcWu>&{#cvkR0^DerbFVgC`DlE_AHr{2zJXmIE2;X@cu+0ifH8ys&ALA5L z8T$;Po_H#^tRC8mLuIEM+heeURKRqk38L3-A(f|KaA1OCXIH72J3vJNrs3KJ7^_lt zX$6Pid&A1wY2kB3-AZ`$_P}*H$Fv7_OI=;hyICfiu?1DX?Ht(53$7Jjous7%{`kk+ zs?eTM)dNN~LeKbHFaX$PO1$$yu7NVhYo>dgak5*Lcj|Svd4)4R)Iy|29CbQd8>u0{ z5=`D1Wu6H)SJ<#4hC5F#wd_+OcWJLowH0phD(wM@H%XV9)ZnT7O0zYB& z{xrjbzvN8GoCph}zhGOfoQ8g@?>IAb6-FwyLgmqc`Cz70M{XM{Ji)|EkJsx}VAbXA z^c^yIOE6bSE$~PY&FaK4`&wdHsngK947)Dur8mK>YN^` zu%Zf>c(Y(R`ev=K41mBgc%IEjpRc_=4;drbsJQl{&|=DCh*{chge{~~9=vVFrhG~$ ziVU=n>?8zIZ{KF3R0Dlh708QVbXx)ka4^SUUw`feXMyPqH(yGfwtS*AH|r=C@jlD% zq``QI+}YrVG;+^K?14c}Q3#Fu0#u=nghPy^wp7Ro7|}9FaVfA#oR-ZT^O;Jn0uZT? zS0I#F#~m;9JiF>=JpG^N7p^IQck%T^q)JQrp~y}uL&1Idqt)*+&R^pRh!qsNNU1v2 z_dvH*LR#$H>zsU(#UcjKmPNP8;}EXSNG1Jv@*z zL1*;l_uZX45xhx1ER)21#tthP;69)u9KcaA4^Ym1JUnQfW=HJ4dXJoF8hAkywbR?P zHK~Osu{Dh~IXjej97c%Y8`6(lRFO+OI@cmY6{OGD&RZp(x)oyJTR2Joo&hv2iXk{q z&tRT<=f*AcF~28aIl)$IF0xV0e8>S}{QH3gBV*uu&#!L-NOWWwv(YTmEx5Iyvar+9 z&+r2i{3AJEj7f}#wWS$sDn)4?=*noN=~I&Ov$+T8Z-cx zJE(u6CLzls+IY&cWLTvtWe~9u?p({HlBEwASL1E=to&ST0brUO+Z(T~x%iy`Q+6Qc zVjO7ge*kJCIE2F>n(?2pGycZvjkcyOKuogYYSs0n3@UmJhjneOd$% ztp3kP_|#Q^yiJ6^3WVU+0amie40mi>{y{ClA$T$S1vR{c&%L4ymBDD`F z8Y8MU5M-m?Y1txtlN<&r>zd;;j;RD4ArO1&Tw+z_an#F#PrMqL`g)sG=}PF?dDws# z(jhqc0+H2@W0XVqjoc1H6S!}I=+%8R(%p||4W6V@z8X7u6|06Tl3&Co&_kn-d8HdJ zH`ky7TIpo`%h`m3isQIs3H~0`ZaY!j5;^D?pDZ$uJ;u9IWksU-pUHIxSkEC3cW*Pq z3!*y7Q7**wuwzkP?4MTgHLmuLcU+z2G`{BqGq^7%1(a zkd!4UsPgkD(EhR^6(>=^dO>wyP&8qRBs%SBm7;3mc9&oHbu+2^uJ0XXOaujL)ty;~ zM1zdX6h${H5tzr5Nj&-DS-#cOpBv30{|sKtqza3IsD7J-)$h@K2pZs8B59a7>a68+ z*D!5#1>b=I?U=piQB25M*1OU9rN_htNFp^_SX0&Pk$|$!@OrqQdGZ>T5PGA&(<5Wt)Dw;X%lq4vmHMyh9S^?5da(+LyFg-RJpUsAS^=}@ z3l@8(iM|x^mwM&#$yUS`SB&|~^>EGt0nT45tW?98^yZRi0aEJ1a+BSVSe)jE*Xta; z8TIB9iz<`g>6*VjtRL7OOGvmw^0o2?0^Tq6U4Uk!iRle+=lHoi+7(VCePjgM`FPpO z&a9KB6p$(1W0cyUw7Ph=Bi6#fb%X>n0#mxo+uai>jAXhCY5G%??#@2+9bwp!y%n(< z&M9!mP)?fFaV-!F#fWZ&Ou*D|KvZb|lxCA_KH`vWju~RWms3}HBdF`*8!!|S4lnypChtB_Z0m4*PAXuprXCux2zU-U!Yy)3Dj57zX=W+fO0ODR|pW*owRM#880cZ^PRR|%vanzlAN=g!|X#R zMY)Vd%{M1t(&?g7$?@ZMZE%wt!9QEA;7bg5TT=_<_ENo$E#fseDnURl(VCI=m*U>$ zw3)J~^PnUeTP{g6HAn4KG@2uI8#r?%zD2DuK+Yu<;n!PpH<@W8tTUxowD-*iS42Lq zX+90A#JjASJ}(aYd#Hi%@n^SG9XaL`_)TYgHUmU1)|6>cMI`wwq95^HRwS5TZ^ZNY zPzkQ60XuYxE|y=xnpej$rd2IZ>4z={Yov=aj;Vx2t_RsWYJ)(|8{A z1xVu*P_~G)3?8>xe=hvn0W`M2)}rglfQz>4wfHj5FcfeD#Xw4$q`;~uu&zw{$+!0q zRWW*`Tri}YLfAGl?H1D1YZ~jnI?1ny@;6l~Sc;@O@XT>^37MtfVkmT!%N}+ClDZMX z4)OU`2_kt|=7y0Vy;KxxpMT^;^HJ0Op|#?`U&rQa-%`qB4s#(1`y?skP~h&VD9zFi zJ9O?Sozo0%MWE{2xn~;dyOTgoM5xFld&6cIPC^A z4teZf43Tr*a$^C<9wT*<$fYB^e?K|=WbYJs6QTP@W6_Q2gYFJph!E1+#cb;DTq4#B z^H#fE+i6m20qrPfgDOOB_yvd|vwHUh)C)2?Z~Y5ayammg65@P2UTajXtgPo$TTgPZ zi}VvVSG~d8aQFI&!{1dXikD`*7!$*^Y~5Ci${=FV1yv?s2l((DoEipVZYsv>2sX06 zA|4>Ihk6(ge*8%PY7{wo-{7-4L0Rs$`ykH=ZKOmVt!GW<8s^A<7egOG3k@+c4Ho)s zZxo!AydP|K+KU-Ht)f8&s}<~+=$%tCRbZ%a(z>$ot|pZ3isINJeT2aanUMS7h|xOQ zfV}T>BXNB6Io~j_;RG?q1ab@IwaK1;c&<`mxKBA_6A}L$+V2a%<+pQ~PKpXW-gi`NCcSb^ z&hXC+ZrXWuSP-Z-?DJ|DAoBypO#nyDIVc5OE|@JFf-6lfgYXG+thAC%!N17kK8Gd= zKcTSz`Ipv8yHP%*AoyEB5L;cIj$vug9Wl&@AlVbi)I3(3fLP zEN$9eEK?T*J{<*I7hzD#HaW~IZMC8^pADq}+g`(n_~79U?~gcay8B-r0cR5uhve1@ zSO#5fHM23+HssRCUDAC1SiW^zDCRU-g1I~M{6SHAe9gzKAz|PpI+|{*r|nP^lT#kd z2M)B(eIoFv5VGP>H9c6-AeFG5TV;D_cb(^owdO@7%8}QgD60185*(sab_K(x95ERO zF1Ov%QAH`l34l+85bhMu6xh;U*AzAvdK?yWi2oxE)VJ;5kjx)dWse!RUm*fjO9YR& zr!a(LJ=YNH-MTR2C_qjHh4Qwvf@0wS9B*oqh_8T5aws$3-JbP+r@8?j^@ zmHlj`9BnZ3+%NCY4(^zg5FnFjlK)_iuKXb>@~ooUTSod+dVERAwD?VZ2S1V|J3UFY zC&Q8QsB8yD@QneLOR(4bN9POgKf?R96}2CM8meJEv$qJH(r52DEA`E`hiB{CJHpwW zm6os>;49ofge9E)U zH1_v;%rOM5ypWS2rqrG@Hxdu{jWR+O*7g}qWfXu)BjKJwxEa6JiLOXylc4t2@by#^ zYH+Y9)%2-Tk|l2_xuY=3(MDBmHVW!pPlOd=(w0=yBM`saM`C92yz+_7O->F+O3 z*@d@LdaT#h79>%H5?1ino~cf6O@FO`x}(lo@h3?kr8iDG&uC~3;c>t4er^B_P zGGoonk zSNK#(J5m|C@lj-!8H|Y65Ic-@*+;Qn?(py^!#;)K34n-}B4qZe1;? zC~{oV-Gw?2(!=&MvtSN>@U&wMm*6Qw2^h>$T>&=ra_Gy9aj2E#HAJVDH0mK)Yhxy+ zY0gGWys|Owf7g>e_W{Xx1v$MqLQ%Fk|I}9g)SbkrFWnB{Gmz|t-z~5^!)nLMNe8yD z7-j5?!$+j5HG)JO5~ht|*il_Oukr|JV$1)rcA(-T!uW|20ek(LQKeWZhhaj~5<6`z z;>!fL=9|IaiA4{+siFpA?-h8*hQ)G-KYf4Zxoa*PjCPQ0T~mAnKN28xqtQ;z-r@06 z+5v1uHKH>XqEO;99GH!t8e71b5G1_zc*e4I{axnwGSZU-wX1rVY7chpWeC2iEOr-E K)z;X^30uK*f28aH literal 0 HcmV?d00001 diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt new file mode 100644 index 000000000..ac46ab6da --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt @@ -0,0 +1,412 @@ +# Si534x/7x/8x/9x Registers Script +# +# Part: Si5341 +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_fmc_htg_6qsfp_25g\pll\HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj +# Design ID: HTG6Q161 +# Includes Pre/Post Download Control Register Writes: Yes +# Die Revision: B1 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:56:52 GMT-07:00 +Address,Data +# +# Start configuration preamble +0x0B24,0xC0 +0x0B25,0x00 +# Rev D stuck divider fix +0x0502,0x01 +0x0505,0x03 +0x0957,0x17 +0x0B4E,0x1A +# End configuration preamble +# +# Delay 300 msec +# Delay is worst case time for device to complete any calibration +# that is running due to device state change previous to this script +# being processed. +# +# Start configuration registers +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x74 +0x0017,0xD0 +0x0018,0xFF +0x0021,0x0D +0x0022,0x00 +0x002B,0x02 +0x002C,0x34 +0x002D,0x10 +0x002E,0x00 +0x002F,0x00 +0x0030,0x00 +0x0031,0x00 +0x0032,0xA8 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0x00 +0x0037,0x00 +0x0038,0x00 +0x0039,0x00 +0x003A,0xA8 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x0041,0x00 +0x0042,0x00 +0x0043,0x07 +0x0044,0x00 +0x009E,0x00 +0x0102,0x01 +0x0108,0x06 +0x0109,0x09 +0x010A,0x33 +0x010B,0x08 +0x010D,0x06 +0x010E,0x09 +0x010F,0x33 +0x0110,0x08 +0x0112,0x06 +0x0113,0x09 +0x0114,0x33 +0x0115,0x08 +0x0117,0x06 +0x0118,0x09 +0x0119,0x33 +0x011A,0x08 +0x011C,0x06 +0x011D,0x09 +0x011E,0x33 +0x011F,0x08 +0x0121,0x06 +0x0122,0x09 +0x0123,0x33 +0x0124,0x08 +0x0126,0x06 +0x0127,0x09 +0x0128,0x33 +0x0129,0x08 +0x012B,0x06 +0x012C,0x09 +0x012D,0x33 +0x012E,0x08 +0x0130,0x06 +0x0131,0x09 +0x0132,0x33 +0x0133,0x08 +0x013A,0x01 +0x013B,0x09 +0x013C,0x3B +0x013D,0x28 +0x013F,0x00 +0x0140,0x00 +0x0141,0x40 +0x0206,0x00 +0x0208,0x00 +0x0209,0x00 +0x020A,0x00 +0x020B,0x00 +0x020C,0x00 +0x020D,0x00 +0x020E,0x00 +0x020F,0x00 +0x0210,0x00 +0x0211,0x00 +0x0212,0x00 +0x0213,0x00 +0x0214,0x00 +0x0215,0x00 +0x0216,0x00 +0x0217,0x00 +0x0218,0x00 +0x0219,0x00 +0x021A,0x00 +0x021B,0x00 +0x021C,0x02 +0x021D,0x00 +0x021E,0x00 +0x021F,0x00 +0x0220,0x00 +0x0221,0x00 +0x0222,0x01 +0x0223,0x00 +0x0224,0x00 +0x0225,0x00 +0x0226,0x00 +0x0227,0x00 +0x0228,0x00 +0x0229,0x00 +0x022A,0x00 +0x022B,0x00 +0x022C,0x00 +0x022D,0x00 +0x022E,0x00 +0x022F,0x00 +0x0235,0x00 +0x0236,0x00 +0x0237,0x00 +0x0238,0x00 +0x0239,0x52 +0x023A,0x00 +0x023B,0x00 +0x023C,0x00 +0x023D,0x00 +0x023E,0x80 +0x024A,0x00 +0x024B,0x00 +0x024C,0x00 +0x024D,0x00 +0x024E,0x00 +0x024F,0x00 +0x0250,0x00 +0x0251,0x00 +0x0252,0x00 +0x0253,0x00 +0x0254,0x00 +0x0255,0x00 +0x0256,0x00 +0x0257,0x00 +0x0258,0x00 +0x0259,0x00 +0x025A,0x00 +0x025B,0x00 +0x025C,0x00 +0x025D,0x00 +0x025E,0x00 +0x025F,0x00 +0x0260,0x00 +0x0261,0x00 +0x0262,0x00 +0x0263,0x00 +0x0264,0x00 +0x0268,0x00 +0x0269,0x00 +0x026A,0x00 +0x026B,0x48 +0x026C,0x54 +0x026D,0x47 +0x026E,0x36 +0x026F,0x51 +0x0270,0x31 +0x0271,0x36 +0x0272,0x31 +0x0302,0x00 +0x0303,0x00 +0x0304,0x00 +0x0305,0x80 +0x0306,0x14 +0x0307,0x00 +0x0308,0x00 +0x0309,0x00 +0x030A,0x00 +0x030B,0x80 +0x030C,0x00 +0x030D,0x00 +0x030E,0x00 +0x030F,0x00 +0x0310,0x00 +0x0311,0x00 +0x0312,0x00 +0x0313,0x00 +0x0314,0x00 +0x0315,0x00 +0x0316,0x00 +0x0317,0x00 +0x0318,0x00 +0x0319,0x00 +0x031A,0x00 +0x031B,0x00 +0x031C,0x00 +0x031D,0x00 +0x031E,0x00 +0x031F,0x00 +0x0320,0x00 +0x0321,0x00 +0x0322,0x00 +0x0323,0x00 +0x0324,0x00 +0x0325,0x00 +0x0326,0x00 +0x0327,0x00 +0x0328,0x00 +0x0329,0x00 +0x032A,0x00 +0x032B,0x00 +0x032C,0x00 +0x032D,0x00 +0x032E,0x00 +0x032F,0x00 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 +0x0333,0x00 +0x0334,0x00 +0x0335,0x00 +0x0336,0x00 +0x0337,0x00 +0x0338,0x00 +0x0339,0x1F +0x033B,0x00 +0x033C,0x00 +0x033D,0x00 +0x033E,0x00 +0x033F,0x00 +0x0340,0x00 +0x0341,0x00 +0x0342,0x00 +0x0343,0x00 +0x0344,0x00 +0x0345,0x00 +0x0346,0x00 +0x0347,0x00 +0x0348,0x00 +0x0349,0x00 +0x034A,0x00 +0x034B,0x00 +0x034C,0x00 +0x034D,0x00 +0x034E,0x00 +0x034F,0x00 +0x0350,0x00 +0x0351,0x00 +0x0352,0x00 +0x0353,0x00 +0x0354,0x00 +0x0355,0x00 +0x0356,0x00 +0x0357,0x00 +0x0358,0x00 +0x0359,0x00 +0x035A,0x00 +0x035B,0x00 +0x035C,0x00 +0x035D,0x00 +0x035E,0x00 +0x035F,0x00 +0x0360,0x00 +0x0361,0x00 +0x0362,0x00 +0x0802,0x00 +0x0803,0x00 +0x0804,0x00 +0x0805,0x00 +0x0806,0x00 +0x0807,0x00 +0x0808,0x00 +0x0809,0x00 +0x080A,0x00 +0x080B,0x00 +0x080C,0x00 +0x080D,0x00 +0x080E,0x00 +0x080F,0x00 +0x0810,0x00 +0x0811,0x00 +0x0812,0x00 +0x0813,0x00 +0x0814,0x00 +0x0815,0x00 +0x0816,0x00 +0x0817,0x00 +0x0818,0x00 +0x0819,0x00 +0x081A,0x00 +0x081B,0x00 +0x081C,0x00 +0x081D,0x00 +0x081E,0x00 +0x081F,0x00 +0x0820,0x00 +0x0821,0x00 +0x0822,0x00 +0x0823,0x00 +0x0824,0x00 +0x0825,0x00 +0x0826,0x00 +0x0827,0x00 +0x0828,0x00 +0x0829,0x00 +0x082A,0x00 +0x082B,0x00 +0x082C,0x00 +0x082D,0x00 +0x082E,0x00 +0x082F,0x00 +0x0830,0x00 +0x0831,0x00 +0x0832,0x00 +0x0833,0x00 +0x0834,0x00 +0x0835,0x00 +0x0836,0x00 +0x0837,0x00 +0x0838,0x00 +0x0839,0x00 +0x083A,0x00 +0x083B,0x00 +0x083C,0x00 +0x083D,0x00 +0x083E,0x00 +0x083F,0x00 +0x0840,0x00 +0x0841,0x00 +0x0842,0x00 +0x0843,0x00 +0x0844,0x00 +0x0845,0x00 +0x0846,0x00 +0x0847,0x00 +0x0848,0x00 +0x0849,0x00 +0x084A,0x00 +0x084B,0x00 +0x084C,0x00 +0x084D,0x00 +0x084E,0x00 +0x084F,0x00 +0x0850,0x00 +0x0851,0x00 +0x0852,0x00 +0x0853,0x00 +0x0854,0x00 +0x0855,0x00 +0x0856,0x00 +0x0857,0x00 +0x0858,0x00 +0x0859,0x00 +0x085A,0x00 +0x085B,0x00 +0x085C,0x00 +0x085D,0x00 +0x085E,0x00 +0x085F,0x00 +0x0860,0x00 +0x0861,0x00 +0x090E,0x00 +0x091C,0x04 +0x0943,0x00 +0x0949,0x04 +0x094A,0x40 +0x094E,0x49 +0x094F,0x02 +0x095E,0x00 +0x0A02,0x00 +0x0A03,0x01 +0x0A04,0x01 +0x0A05,0x01 +0x0A14,0x00 +0x0A1A,0x00 +0x0A20,0x00 +0x0A26,0x00 +0x0A2C,0x00 +0x0B44,0x0F +0x0B4A,0x1E +0x0B57,0xA0 +0x0B58,0x00 +# End configuration registers +# +# Start configuration postamble +0x001C,0x01 +0x0B24,0xC3 +0x0B25,0x02 +# End configuration postamble diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj new file mode 100644 index 0000000000000000000000000000000000000000..3af140b284cf8842ae692f4c985b18e4c97d58ef GIT binary patch literal 10144 zcmV;RCtuiI+b~CiUs-(@Z_9ZY_xgHH3?@PN-VEqIS+Qoi>UyM5+3=jbQ2N+;j>&HU zU`?~7(i&uzEf)_>2*hPE?w!G&GwUzgkDd5$pE=;z`pBS5 z09Nhk)(0d`17JhZsIE?rbT+|dw1N66*CS-bR!P+)suZ+y4_9Erf_&u3_!oqSbH>dx;+in>8vYRU*hmxd+I zEOEtIB!}1P)UxeyN8Ggu-^662+9HILwV}KpEi}!fkLk)~-$bBzSs9qucGBO{SS7^! z2CW9~IO{qA&Wh6u?1Qdx>T)tQ7Q_kxr2YPh_5t2Pwdo#cWO?zqnPcQg=EKA6L@b*# zhi4FX+dAM87wgs3$vMyRSga%hp7qr(1KY9j;%H9(lOG;EqM$W+$&AHrL=_iE&<+$l z35`mR{W^}rT#j^Y11psiWKLqjsKsjbPbaY#&bccYeLZ5$GnH4_a(M=JLasQAU~#GgVJ?Z2wCLoDQD!-0EwD}PW005G@wr`o?&R3Mp>^CyxF$0;aeI-MA&$JlHYohlK?)3iJv{H|-nLhr zHqv42j8f3w$o&^rn2m^^u_-eFW3mGGgCXHjtX(3SvVe`k@Lhzr5uQGb$I-`qF8AhQALt#iq#sx9lv@%AR#Ze{(6O#2CITb<6 zW(3Q_%C@=7)`=8SG~=JFsh1iw&G30#4yfq@|1-yM+oQC+`|fWL_AprT0mx_30601~ zHcE_=)0cLKyzqlB*rOELJ!Ei-zfzv|45}@9SmhCnQqICOv*kLxl?a&hr}L zEYT`$eQ9$Y#RPXdq2OQUSK-eyNEqvGnjWb9(qbX8@kRELY(n?+Ja}H-c7)5XE}H-S z=C+uEc`S2staf?go%9x<4Mi`eiC*+j(W0HoT6Iw%#-w%V7oKaRO9!nzJCxyxDG344 z6y^LtNt81dE1!{0zqVwJ#5af?%dI+|4@Yg9Rif3xSx| zeG@AK7plMWe`Kw0PI#{;%>4Zw>l;hg(Vu*3hDYHR#uio&sB-D@XD`=aIZ8G8>~PCU zWy$X9#a~oWmg&a?dkNWJ+HNyXdNS=tS3c_%`XL1j49e4q>s4K=yr6em@hDF85a=p8 z4NLTyawxn_O4v$I7)~TgLY|#<9|cIqEOQj1W4U>6Jf=ZZ++z23n`a<;aggDP-D?~63N5Qv%u zy=q)`5L2xXW`FrAn)7TeH+lFaxUGV;Vy&0dVlOQ_&H}lwcYuvuqmvz`PdlX1MI3b! ze#HkZY3^n|xDjRvEwct^{mUZ($;qXlo9rnxv6Vh$X~HS03L~~JsZwPiv5fhTG; zp`U}f})yptSmnD>#ru$zG&zp~PP3BxQ@BkEy zRZPbnARaOpb(&l-YrB!1-yRu#M9NB3VX@??AFka|(NJ&it-m})Sjg)m!n2+r-t(4i z1q$^D4*H21N}&vL>e7i*u^9xuD!{O*HDuZ>Q(W-2Ac^`)>+@qrQ7TWAAk#kd2cgaM zeP79i$kCHeaLV&uIlq-xvs>4lVv}>tFAFTk2^|nO%uMc-VN)~n_k{mtuQ9dFtXH?6 zqs(SpSf^fiOtRH!*pESGGFmUdul2L%f?)B zlPO8JA0zEfjSl~##;^$A6VPqOn$N-Hh7GMtxH0(lT!8@ij2oBIEzhu9253e;W)Lp< z^kT~_JcwET_-pSVvWawtUEBv9We|!#(T}-TO>h9vlyEl_?K10|@P1pZ;{YIFpkaXlvBwq@>&pPpGQ#cpl zDo6Wztu`qd`mc1@yqgx)(#v>4i_5Z>7y)x9`i4W%7sx*BF3ZuS5Y#9Gh=m6ti#U`f zj&!rfO)r(~CoWiF)2&}g@!L)!JGMg`%x~c$`D9|L(FF*n&%2!?Z_OjmHAvL zwK4jnZEC!X5g93ko^)m=A;Vfe&280YIG%XaDa4_P5!EuwU zIm3;+MLO-D4Y~<8;q9yAtg?YaDbwTPQ2`QjXJ^jpfc!xgrek*#5GXw$Ntdw6>`&LD}Z!UEUQ zti~23TJZN)X{O$(_AI7A7GH`VzuE9U=i9)R1Mt`MM2Mn>3bH@_R)oyEg_6BVx=npj z>1n!8dcvp=kTzvPdmY7o^L>CJIq(`!e2c!*eIP|fNNbQxaV(!|oC<{|_)-Y58rS%* zyLlTSUFg#TnTWboO-zwHHF-h*qv3}ScH7QvySOsjW}CB~DlUmJt@FaOSO0JPEHGN@ zH3Z~y5H_I%ppSS7Nek~kO~m*wFJK|Z=|BoXr-}5OjTk#vVz1<)!+#i0EmhESkZLta zmg#H1dZ8ZL{HZip>qc1IuXnKgeSyHfVv|M2cnn-jxZ4E|yzL1>yt>IS_}w{|4Aq9Z z4rlA|Kg^(Muw>g$c zq!i{lEn%o2U)VeB?7vs){$6ms2_J%LZI za;H6K$)zJg*1F#+$hrg}Db#O~+)#_0e3B`PABJ~wubar9WVzF|rJ0ixeV{fgBu^i; zj4Drc5Bu)r_@h^#k<)oU+&HOq%Cnr`LW$BEfDl2dJabqCCnY(N_c*5$zhQ+v!9oLS zyQPg^p4bW*KIyekSd%A3$Z|$fEQv!WoM1epI!<;rSuAke(;xec$OUlGsS^qsmM;ML zf`1W-`KVF5)TM$GO2%t1SfmcjRHR1C&xvHvx{{>%Lg<-ZefWHKZlGmi;eE?o_jX(S zer)0pag8v3!^&aW!iGY@rqy!t#)qtRjU7fc`NIXa1F)8fG_o9pD3AU6@xct@2c0b9 zB$cQtT*%;ZN>4wo;VfrH###5`2{?2%Yq_7YePd!mC(teDcTk0ill-h~<2N(!s5PV^ z-Fpc?HJ5KeFT=SbmSW3D+ZQkz1gEvb-c4q?XSp<2=9M*7jmi;7j?`w}2C*ZFcy!J= z3PGMgvBd~}v%K)NPf7g=xwt^ajVh^+KqABSQkOrP>mM^=yQ6iO0qutGnJsv;mEB@r zR)x5`^1`xube0#3P2T8v)JRLW^(`OWtz_Bjna8<9i%y2VX3555=dBnx zV`RV2%;~3Nq)pI^84I(BR4{cKm`LJTrinF6JCQ9-;rW(u^yeW^r0W?19@C6N)yFjc z5XT~@@Q?$|gfmq@`82#opfb&AQ_um(``S^c!i!Z{Y?%j1Z%ZmoNzD1#ah2e{La zqV))U9*)G!v(it8sHRa1*+AS~S5$ejVaP4Ma&crGQ*+LN_JV+^65t66%c6GH zr1eh=oR&cACfo|xV?YD#^hl7KH(=&M*F7UPUNlA?sCS^$I~-mTr|8e>-2fA)Y01E( zn%U(%dj_WLFu`!28Lpt;<&9F<267B57(&Y0ryy{Tq&=U0fAWVxA}{4Km0z7ob0!d= z$0@|Tn&JZwiP!5lQZFteY>SlJV}7ytGLqr8vyS$|Ox@^raA8$~(CMyvaek815vis$ z>Ad-?rh>2&{Rh}tMN_|cVi7lmZqDyu56n}s-uDL{$bWq_5p6ZR8u@@@3)&QRgat6} z4$pN5SN!>%=x{PmdMm`A9l`=bYFqi-qLaa6O6G+?A*1yO;tUJV@8$6`E(stpRD}}> z>5>BIPP1yWQHOucvDOvOZX^!IlX!|&Y&xsBCU#qkf~-Tu~u$K7Lf^Ol9#3^&FM zdP=pGVFE%-Dvh!GtD?t8EH9va(pdK$rLy}UV2HnW$)6AzVI%N-#L0AAq{Ju}PsOS*iAqXT0?gHHdbZ?tj$2^In_Zdk-MQ_$(aZI-3O)L?Ho{^96|D7eyGQWoh}XG+99 zx`H(I!)FNhxKkB_{+nkvcGl97U*@o(7=+YT{aQ&M6d1p>40qDQ;5Eihz5#y%R&^(W^=#u&efa9v{vZO7kLdIwG^u==jaC^`|GvV!N|hkvL{xfDp8p?Sm%DA1 zIb2i?lMSmekUctEh0Rwc7jEr!{Ddl+R|6eFHjn&znXne92*qPgba4-^gzs#$75uWt zgA&mur6NKiRZjV{iyM`+D?e4mzL!2|FN0tFqxrRX(N&KJ?{DBWip9j$yAJsT{@kUvu={U5?~e2tCi)^HCeIA?`83?SZxPup`I7fZZBZeT{=qA zS74E=*d|g^x{HK*d2nJY z)vSZXZ?KwQC|M4b9bm;eU=QY1)tII!6p$e&!w7P!3f{K|^<}^C;9$1$7bdz)G4MqB zdw{on>ee=Fh-3{donz|Pq79gibn5B9J{FEZa+V>}ihPb$Ued(aVUVvou82m^`dj?3 zN;4g8jSSE_!~Dlf;KyaUG`Lc=e9}8S zfSnF*My)^Sqtq=BH=&7GRqNp@0j-OmSkm?+Q;US48?~j~C6oTZNl#N^5ehEb&8y;K z2j`y;SJnBk=PpPC{*Xi+cSnDDg1v61BXi~t1?f2$#KI@74Hi=nywL%CmGKCq6Xk() zw`3oAs+)=#%W@%R=f9V1z0b|z&N0%jcHAKO!P3Qfw;7xowS-ChjY1qU-ep>-Tl8K( z0&~4m;|Ttm!6?qoopoheDXb~>Y!j@%sLX$Eghi#o_Rkw6``|{HvFWMdR};c^yq;|U zGyhO9E+OmgC>ULu?Pc*ilfiyZ?0LZStn;5_e19pTu9@FtFC*+ZNj=5)U|Y&t%=?%F z)~mKf55@gzTaHC`;Z?kEdzvI58#~}BK2vUb08Q5|+>jv0e94`#PF?ax#0t^ui3T>1 zR1_^1RuTnK7mCt&o#}4>R-cOT5S)>ismY#yYGAXWn8`9_iO$-;cm-rCN-&yAcI`gv zdk39965rNfE9(qGm1EqaIT!7tUvXzoFcoq zZW*#xdP;Wd?7mv)4|iF~(ArtYc#;PCR~`CQ<*Rl~Pt| zYdTE7UW7D43jbxijhkI818=*v#R^^{d-uZwwh)Rl=c|@-kwj2vdj;b_H+*(p9l?2t z4%DlOyFjN*U(xw1M-9<>->kYH(KTlf+<=m+%2R_rW~=bG8`VS4R6~~VdLnXv!TLIr zxeUkZZ2_$Z5f_YrO$2*!rX3&arB#>wnU!~mZj4hmG)Gb-LnC7(aUv(-_AEbcXev8_ zyj_-KbSlmJt<{+k`+DVmHcV!dIQn_5FfhB$;~6KyEl^{y?x;hITCIp~cA=lR;kTo+ z5p7c0Kt#sV#D35UmX}#{2Vr|;^9d3dAH)o`N^g#OKep)au}mD{_ZfvkZp*?csGtj= z@dXRg);YA&>?6UUS7aX}M{~}f8C@7lwzfwiY*5^+$u!;MC>iBG7GyqsjZ|nrIg!Kw zu!$frQ3%+4%0_nEUKT&5XtH;DOiL3n3KcXF{I6x~ zRs^25)Pob~4%UTPvLc>dlNB{hNE>>BtyXIh$;F>nF?9d@887Ykt5bj*@fk4Ap^u*z zXUh9$Vh-HhGAejv8RrTb${?0cZP*ENTm^O}!|XeO+l89ZT2fRKR-^;J^*F5r^cPla zpCE?www1;;+H-Xw={z|7%#|=TR4iTlpY&h?r(eSxaS`F>smD*^g8Ef30utBY1KOx2 zA4)%Y*M`5^(riE6HQ44q1jkaJMuXKagG^WzOuK8virHi@F4Hm}fYPk{mOQ`JJ!RDl z-eerqD%>%WJf%a>Mxk0XcXNgLC~gPzA2?UA;3CbYGQ>Nt@dqLFsWJ)a(XKS(m2g9j zlsquYIEGsvdqILGIXN2uVoeWmM+FQYf%p^P-Z$~^>`_WU=C?otSTm*YtIhkz@w0w@ zAP!}6y@t}&wQar+DvZkwSb=7EQ8iJhNs=Q?3?>(0Q_xqzM_kTVscruA+E)106L+^V zwJlxJdBOR$ETmXd=GlM5B9@wFNYF5!N?Z1Sw)&3pzO`@3q0l-c^9&wr-vDr>>m=ja z2vL8Q3Z+?l;BM5$j*ZL;+JNSW8Ub+Zo{CO~*;jcs?)v^(@vjtVsX`awvg>=UDxH2k($O*i{lT5$%u2Y_7{4SW@p^ z+|h;ZM$$@7KvWf^ygl&7J|?>3@5k+sZ4BCaM7UvR@?DP{5Jy}{>ppOdi< z*(aFQ@|{ltx*(>*HM-kSSLN{ZFEpIFi$_-8kYXSA#8Dq8z*^P!hbz5w}p4Nzap5Xw~aj#Xt=|8wvS&gvY-!IXjlV^|lucu~O?0F2~>MQtlk zdxGKINCM1zs;+`Z#MUj+w1$jj-LWF=sz?i3c|Ofzo-ykBVx`E3G*z0~CKG2G14m2v z1m$ZX=k02UqBnEhOh(0vA4B~5<-yI_w)|}{V`$_>L!&zf-9U8pGFM6?TYoJ8eoh(W z%(bn)lSz_?VZ3$gZ|Wmo%|X0IKK0xe!GRwPtzkCP4}KZS)3K=+tFQyO24)lS=9poH zPP#mRRF|&cEE*l)pE9RCI7j4sq8O+IJ0F1SC+6`|b89rv(<`zMc@znPjLYg;^SS4P zExLvT#A$5Bw`co)$Y)Uk6hhm4-3m7duPfdoPJ)GsJ_SBEj?S`i?1(K<8DKZ&esL@J zHm~`~{_p!K0}wl#Y8h3Etm%GD#R~+%*MwRF9Cj25<1p^fn|hjOS!6lv+*9 zs7ly#%cc2MG8avl<}G{h;ro7$q|elR_IcTC)e1=xeWVcMG77rhV{XG9nPH%$P)~+x zZ7yqj0FbpYspUfuvNJTaVlPSiUS-9P(DH4)VN5=gS0!4G*VIrDiXaOS!Mc~M5`s)e z#S>+|fxCm%X6GAHwH16fDue}or6`BYVa%b4`JlYX7f;fh+;GTlTeQk~UQ1gn><Ju}6r(*jkcEdbL&OU#e*e_d|RSK;l*{G{@F)77t@9D~d=9bgno}sVoDX_Q$Q9Y!+zi zgZ+Ze3*tn5tiOe+uhdy8h`$Jfd$!GnXtnWBL@{<6?%fg+=6dfXor3vX0S+kl64quJ zV>ve#MjG&>8d+KEiQF@G5gC-k;_?pYyhYAR;>?(GtyAWbpFFK{(LD3ejMUIkaKl}p zM<+!QE`dI11Fe&bScTLXk3aC3|G!Q&K9PijNMP*sCSsa4%Yr@@;*xHqCjJU>^7Yo_ z^`PM%YuQttOycPNfo={uR6D9UWK_}K+w9?Bu^Zz@4Yo4*l&`Xe>Mwl5@@uEvs9Gy@ z{zTJskXJu>G)gBjV2{#@bA^%~W^6Pvc?mt&6SEeB4UW@8W-129gUFGsl5aP48JxKG zCB;|JCa|&yMpR!#gF-x5fR;8R!Zf9# z_AjTv%BF0&8!j>4iw!(LJf7yVa1E(i3YHq-m5>aCH3Q{x|A%6NNxl|HzlNwKYP9LA z1nga-PD-9K3CHXXQaNLNt>L{lRdguxpJdgDjyKbaBT&~&Mi3aPCgrO$4Q6M58@ zjBnsy&G4PV5FYY94D5zt9kOJW_%o55?!X)1X2g?yT#2%;MD6{iV`J|K{%nfmyNK=_ zLO}d|f={9tsJJrYmNZq0o8vIIu{A;c#3oMk%zY4ynFE*sg_X|y_4Ghx5nP4^YzZ#A zKg8|Umh=Z(dX*FM#Uv4QM6#{t%f2#mLE}=0{D)hI=6Q1&ABO<`FQ zF_+3bMqe@2gr+noFUDa4rIh;@093OD=n{e7w@8n%lxM%DnaKXKtuQpiQ0E1qYu-t5 zq(!qiv^1gY-ejV%ejDTZcG~XlkcnCsnO6v57z?Jnm&wrT2 zGZ@jOVanu__3b{SVHIWVu5Ddg&cg|bSVuA8-0WIL_y*JOu{E{d-MP8&Bz1)oq~WeR z7*PT!9IsvdxAW5O#wWmcaI4s47h{A(Au>LDy+RP2ir{sA z1FuTXS5;0-`L$9lSng0lt%2UdqH0vv-4XdU+}HQvi||(!=9*=#Jf`7w<132-Md_q3 z;;~eYxdfh5HFUMK3<7TLwG@%C05GKb=aq9DdydHDGj|{>fhgM@eX7_$ktrQ=wqKle zlGP}h&?HX2NBUEcjfcRB*M&g4`&T}?oJ<`j4Yao6joQy557A6Z?1>?eb**QGEloKQ zn?vo(>R4Xs|KUZ$0CTw12un+bO)Coe50=Xpb?C$iTQx7^LgrP-2(W|esdGf+v>w4P zKaNIkq}V1UoG6fWXQk|zicJHp9DS2!4;V0$?s|hvWp0H6jCMLs$p7TkTv)BX01VVa zI+5OJW=zjR%KfD1#tI-9H&5HIL5~sL=EP1LgQU5dB9UTjmswt;=b}~nWZb@# zV)Fn=#z<?cP8DH2RC%c@xGRZoj~~dq;R5a7n0=J3>RNMPqaF8EA

> 8) & 0xff + data = int(d[1], 0) + + if page != cur_page: + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append("{1'b1, 8'h01};") + cmds.append(f"{{1'b1, 8'h{page:02x}}}; // set page {page:#04x}") + cur_page = page + cur_addr = None + + if addr != cur_addr: + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{addr & 0xff:02x}}};") + cur_addr = addr + + cmds.append(f"{{1'b1, 8'h{data:02x}}}; // write {data:#04x} to {addr:#06x}") + cur_addr += 1 + + return cmds + + +def mux_cmds(val, dev_addr): + cmds = [] + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{val:02x}}};") + cmds.append("9'b001000001; // I2C stop") + return cmds + + +def main(): + cmds = [] + + cmds.append("// Initial delay") + cmds.append("9'b000010110; // delay 30 ms") + + # Si5341 on HTG 9200 + cmds.append("// Set muxes to select U48 Si5341 on HTG-9200") + cmds.extend(mux_cmds(0x00, 0x70)) + cmds.extend(mux_cmds(0x04, 0x71)) + + cmds.extend(si5341_cmds("HTG9200_161-9k2_161-Registers.txt", 0x77)) + + # Si5341 on FMC+ + cmds.append("// Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28") + cmds.extend(mux_cmds(0x00, 0x70)) + cmds.extend(mux_cmds(0x02, 0x71)) + + cmds.extend(si5341_cmds("HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt", 0x77)) + + generate(cmds) + + +def generate(cmds=None, name=None, output=None): + if cmds is None: + raise Exception("Command list is required") + + if name is None: + name = "si5341_i2c_init" + + if output is None: + output = name + ".v" + + print(f"Generating Si5341 I2C init module {name}...") + + cmds.append("9'd0; // end") + + cmd_str = "" + cmd_count = 0 + + for cmd in cmds: + if cmd.startswith('//'): + cmd_str += f" {cmd}\n" + else: + cmd_str += f" init_data[{cmd_count}] = {cmd}\n" + cmd_count += 1 + + t = Template(u"""/* + +Copyright (c) 2015-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * {{name}} + */ +module {{name}} ( + input wire clk, + input wire rst, + + /* + * I2C master interface + */ + output wire [6:0] m_axis_cmd_address, + output wire m_axis_cmd_start, + output wire m_axis_cmd_read, + output wire m_axis_cmd_write, + output wire m_axis_cmd_write_multiple, + output wire m_axis_cmd_stop, + output wire m_axis_cmd_valid, + input wire m_axis_cmd_ready, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * Status + */ + output wire busy, + + /* + * Configuration + */ + input wire start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000000 stop + +*/ + +// init_data ROM +localparam INIT_DATA_LEN = {{cmd_count}}; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin +{{cmd_str-}} +end + +localparam [3:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +parameter AW = $clog2(INIT_DATA_LEN); + +reg [8:0] init_data_reg = 9'd0; + +reg [AW-1:0] address_reg = {AW{1'b0}}, address_next; +reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next; +reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next; + +reg [6:0] cur_address_reg = 7'd0, cur_address_next; + +reg [31:0] delay_counter_reg = 32'd0, delay_counter_next; + +reg [6:0] m_axis_cmd_address_reg = 7'd0, m_axis_cmd_address_next; +reg m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +reg m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +reg m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +reg m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; + +reg start_flag_reg = 1'b0, start_flag_next; + +reg busy_reg = 1'b0; + +assign m_axis_cmd_address = m_axis_cmd_address_reg; +assign m_axis_cmd_start = m_axis_cmd_start_reg; +assign m_axis_cmd_read = 1'b0; +assign m_axis_cmd_write = m_axis_cmd_write_reg; +assign m_axis_cmd_write_multiple = 1'b0; +assign m_axis_cmd_stop = m_axis_cmd_stop_reg; +assign m_axis_cmd_valid = m_axis_cmd_valid_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = 1'b1; + +assign busy = busy_reg; + +always @* begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_write_next = m_axis_cmd_write_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg & ~m_axis_cmd_ready; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd_valid | m_axis_data_tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (~start_flag_reg & start) begin + address_next = {AW{1'b0}}; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + start_flag_reg <= start & start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= 9'd0; + + address_reg <= {AW{1'b0}}; + address_ptr_reg <= {AW{1'b0}}; + data_ptr_reg <= {AW{1'b0}}; + + cur_address_reg <= 7'd0; + + delay_counter_reg <= 32'd0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_data_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall + +""") + + print(f"Writing file '{output}'...") + + with open(output, 'w') as f: + f.write(t.render( + cmd_str=cmd_str, + cmd_count=cmd_count, + name=name + )) + f.flush() + + print("Done") + + +if __name__ == "__main__": + main() diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v new file mode 100644 index 000000000..f67fd21fa --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v @@ -0,0 +1,1600 @@ +/* + +Copyright (c) 2015-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * si5341_i2c_init + */ +module si5341_i2c_init ( + input wire clk, + input wire rst, + + /* + * I2C master interface + */ + output wire [6:0] m_axis_cmd_address, + output wire m_axis_cmd_start, + output wire m_axis_cmd_read, + output wire m_axis_cmd_write, + output wire m_axis_cmd_write_multiple, + output wire m_axis_cmd_stop, + output wire m_axis_cmd_valid, + input wire m_axis_cmd_ready, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * Status + */ + output wire busy, + + /* + * Configuration + */ + input wire start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000000 stop + +*/ + +// init_data ROM +localparam INIT_DATA_LEN = 1070; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin + // Initial delay + init_data[0] = 9'b000010110; // delay 30 ms + // Set muxes to select U48 Si5341 on HTG-9200 + init_data[1] = {2'b01, 7'h70}; + init_data[2] = {1'b1, 8'h00}; + init_data[3] = 9'b001000001; // I2C stop + init_data[4] = {2'b01, 7'h71}; + init_data[5] = {1'b1, 8'h04}; + init_data[6] = 9'b001000001; // I2C stop + // Si534x/7x/8x/9x Registers Script + // + // Part: Si5341 + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj + // Design ID: 9k2_161 + // Includes Pre/Post Download Control Register Writes: Yes + // Die Revision: B1 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:38:53 GMT-07:00 + // + // Start configuration preamble + init_data[7] = {2'b01, 7'h77}; + init_data[8] = {1'b1, 8'h01}; + init_data[9] = {1'b1, 8'h0b}; // set page 0x0b + init_data[10] = {2'b01, 7'h77}; + init_data[11] = {1'b1, 8'h24}; + init_data[12] = {1'b1, 8'hc0}; // write 0xc0 to 0x0b24 + init_data[13] = {1'b1, 8'h00}; // write 0x00 to 0x0b25 + // Rev D stuck divider fix + init_data[14] = {2'b01, 7'h77}; + init_data[15] = {1'b1, 8'h01}; + init_data[16] = {1'b1, 8'h05}; // set page 0x05 + init_data[17] = {2'b01, 7'h77}; + init_data[18] = {1'b1, 8'h02}; + init_data[19] = {1'b1, 8'h01}; // write 0x01 to 0x0502 + init_data[20] = {2'b01, 7'h77}; + init_data[21] = {1'b1, 8'h05}; + init_data[22] = {1'b1, 8'h03}; // write 0x03 to 0x0505 + init_data[23] = {2'b01, 7'h77}; + init_data[24] = {1'b1, 8'h01}; + init_data[25] = {1'b1, 8'h09}; // set page 0x09 + init_data[26] = {2'b01, 7'h77}; + init_data[27] = {1'b1, 8'h57}; + init_data[28] = {1'b1, 8'h17}; // write 0x17 to 0x0957 + init_data[29] = {2'b01, 7'h77}; + init_data[30] = {1'b1, 8'h01}; + init_data[31] = {1'b1, 8'h0b}; // set page 0x0b + init_data[32] = {2'b01, 7'h77}; + init_data[33] = {1'b1, 8'h4e}; + init_data[34] = {1'b1, 8'h1a}; // write 0x1a to 0x0b4e + // End configuration preamble + // + // Delay 300 msec + init_data[35] = 9'b000011010; // delay 300 ms + // Delay is worst case time for device to complete any calibration + // that is running due to device state change previous to this script + // being processed. + // + // Start configuration registers + init_data[36] = {2'b01, 7'h77}; + init_data[37] = {1'b1, 8'h01}; + init_data[38] = {1'b1, 8'h00}; // set page 0x00 + init_data[39] = {2'b01, 7'h77}; + init_data[40] = {1'b1, 8'h06}; + init_data[41] = {1'b1, 8'h00}; // write 0x00 to 0x0006 + init_data[42] = {1'b1, 8'h00}; // write 0x00 to 0x0007 + init_data[43] = {1'b1, 8'h00}; // write 0x00 to 0x0008 + init_data[44] = {2'b01, 7'h77}; + init_data[45] = {1'b1, 8'h0b}; + init_data[46] = {1'b1, 8'h74}; // write 0x74 to 0x000b + init_data[47] = {2'b01, 7'h77}; + init_data[48] = {1'b1, 8'h17}; + init_data[49] = {1'b1, 8'hd0}; // write 0xd0 to 0x0017 + init_data[50] = {1'b1, 8'hff}; // write 0xff to 0x0018 + init_data[51] = {2'b01, 7'h77}; + init_data[52] = {1'b1, 8'h21}; + init_data[53] = {1'b1, 8'h0b}; // write 0x0b to 0x0021 + init_data[54] = {1'b1, 8'h00}; // write 0x00 to 0x0022 + init_data[55] = {2'b01, 7'h77}; + init_data[56] = {1'b1, 8'h2b}; + init_data[57] = {1'b1, 8'h02}; // write 0x02 to 0x002b + init_data[58] = {1'b1, 8'h33}; // write 0x33 to 0x002c + init_data[59] = {1'b1, 8'h05}; // write 0x05 to 0x002d + init_data[60] = {1'b1, 8'hae}; // write 0xae to 0x002e + init_data[61] = {1'b1, 8'h00}; // write 0x00 to 0x002f + init_data[62] = {1'b1, 8'hae}; // write 0xae to 0x0030 + init_data[63] = {1'b1, 8'h00}; // write 0x00 to 0x0031 + init_data[64] = {1'b1, 8'h00}; // write 0x00 to 0x0032 + init_data[65] = {1'b1, 8'h00}; // write 0x00 to 0x0033 + init_data[66] = {1'b1, 8'h00}; // write 0x00 to 0x0034 + init_data[67] = {1'b1, 8'h00}; // write 0x00 to 0x0035 + init_data[68] = {1'b1, 8'hae}; // write 0xae to 0x0036 + init_data[69] = {1'b1, 8'h00}; // write 0x00 to 0x0037 + init_data[70] = {1'b1, 8'hae}; // write 0xae to 0x0038 + init_data[71] = {1'b1, 8'h00}; // write 0x00 to 0x0039 + init_data[72] = {1'b1, 8'h00}; // write 0x00 to 0x003a + init_data[73] = {1'b1, 8'h00}; // write 0x00 to 0x003b + init_data[74] = {1'b1, 8'h00}; // write 0x00 to 0x003c + init_data[75] = {1'b1, 8'h00}; // write 0x00 to 0x003d + init_data[76] = {2'b01, 7'h77}; + init_data[77] = {1'b1, 8'h41}; + init_data[78] = {1'b1, 8'h07}; // write 0x07 to 0x0041 + init_data[79] = {1'b1, 8'h07}; // write 0x07 to 0x0042 + init_data[80] = {1'b1, 8'h00}; // write 0x00 to 0x0043 + init_data[81] = {1'b1, 8'h00}; // write 0x00 to 0x0044 + init_data[82] = {2'b01, 7'h77}; + init_data[83] = {1'b1, 8'h9e}; + init_data[84] = {1'b1, 8'h00}; // write 0x00 to 0x009e + init_data[85] = {2'b01, 7'h77}; + init_data[86] = {1'b1, 8'h01}; + init_data[87] = {1'b1, 8'h01}; // set page 0x01 + init_data[88] = {2'b01, 7'h77}; + init_data[89] = {1'b1, 8'h02}; + init_data[90] = {1'b1, 8'h01}; // write 0x01 to 0x0102 + init_data[91] = {2'b01, 7'h77}; + init_data[92] = {1'b1, 8'h08}; + init_data[93] = {1'b1, 8'h06}; // write 0x06 to 0x0108 + init_data[94] = {1'b1, 8'h09}; // write 0x09 to 0x0109 + init_data[95] = {1'b1, 8'h3b}; // write 0x3b to 0x010a + init_data[96] = {1'b1, 8'h28}; // write 0x28 to 0x010b + init_data[97] = {2'b01, 7'h77}; + init_data[98] = {1'b1, 8'h0d}; + init_data[99] = {1'b1, 8'h06}; // write 0x06 to 0x010d + init_data[100] = {1'b1, 8'h09}; // write 0x09 to 0x010e + init_data[101] = {1'b1, 8'h3b}; // write 0x3b to 0x010f + init_data[102] = {1'b1, 8'h28}; // write 0x28 to 0x0110 + init_data[103] = {2'b01, 7'h77}; + init_data[104] = {1'b1, 8'h12}; + init_data[105] = {1'b1, 8'h02}; // write 0x02 to 0x0112 + init_data[106] = {1'b1, 8'h09}; // write 0x09 to 0x0113 + init_data[107] = {1'b1, 8'h3b}; // write 0x3b to 0x0114 + init_data[108] = {1'b1, 8'h29}; // write 0x29 to 0x0115 + init_data[109] = {2'b01, 7'h77}; + init_data[110] = {1'b1, 8'h17}; + init_data[111] = {1'b1, 8'h06}; // write 0x06 to 0x0117 + init_data[112] = {1'b1, 8'h09}; // write 0x09 to 0x0118 + init_data[113] = {1'b1, 8'h3b}; // write 0x3b to 0x0119 + init_data[114] = {1'b1, 8'h28}; // write 0x28 to 0x011a + init_data[115] = {2'b01, 7'h77}; + init_data[116] = {1'b1, 8'h1c}; + init_data[117] = {1'b1, 8'h06}; // write 0x06 to 0x011c + init_data[118] = {1'b1, 8'h09}; // write 0x09 to 0x011d + init_data[119] = {1'b1, 8'h3b}; // write 0x3b to 0x011e + init_data[120] = {1'b1, 8'h28}; // write 0x28 to 0x011f + init_data[121] = {2'b01, 7'h77}; + init_data[122] = {1'b1, 8'h21}; + init_data[123] = {1'b1, 8'h06}; // write 0x06 to 0x0121 + init_data[124] = {1'b1, 8'h09}; // write 0x09 to 0x0122 + init_data[125] = {1'b1, 8'h3b}; // write 0x3b to 0x0123 + init_data[126] = {1'b1, 8'h28}; // write 0x28 to 0x0124 + init_data[127] = {2'b01, 7'h77}; + init_data[128] = {1'b1, 8'h26}; + init_data[129] = {1'b1, 8'h06}; // write 0x06 to 0x0126 + init_data[130] = {1'b1, 8'h09}; // write 0x09 to 0x0127 + init_data[131] = {1'b1, 8'h3b}; // write 0x3b to 0x0128 + init_data[132] = {1'b1, 8'h28}; // write 0x28 to 0x0129 + init_data[133] = {2'b01, 7'h77}; + init_data[134] = {1'b1, 8'h2b}; + init_data[135] = {1'b1, 8'h06}; // write 0x06 to 0x012b + init_data[136] = {1'b1, 8'h09}; // write 0x09 to 0x012c + init_data[137] = {1'b1, 8'h3b}; // write 0x3b to 0x012d + init_data[138] = {1'b1, 8'h28}; // write 0x28 to 0x012e + init_data[139] = {2'b01, 7'h77}; + init_data[140] = {1'b1, 8'h30}; + init_data[141] = {1'b1, 8'h06}; // write 0x06 to 0x0130 + init_data[142] = {1'b1, 8'h09}; // write 0x09 to 0x0131 + init_data[143] = {1'b1, 8'h3b}; // write 0x3b to 0x0132 + init_data[144] = {1'b1, 8'h28}; // write 0x28 to 0x0133 + init_data[145] = {2'b01, 7'h77}; + init_data[146] = {1'b1, 8'h3a}; + init_data[147] = {1'b1, 8'h06}; // write 0x06 to 0x013a + init_data[148] = {1'b1, 8'h09}; // write 0x09 to 0x013b + init_data[149] = {1'b1, 8'h3b}; // write 0x3b to 0x013c + init_data[150] = {1'b1, 8'h28}; // write 0x28 to 0x013d + init_data[151] = {2'b01, 7'h77}; + init_data[152] = {1'b1, 8'h3f}; + init_data[153] = {1'b1, 8'h00}; // write 0x00 to 0x013f + init_data[154] = {1'b1, 8'h00}; // write 0x00 to 0x0140 + init_data[155] = {1'b1, 8'h40}; // write 0x40 to 0x0141 + init_data[156] = {2'b01, 7'h77}; + init_data[157] = {1'b1, 8'h01}; + init_data[158] = {1'b1, 8'h02}; // set page 0x02 + init_data[159] = {2'b01, 7'h77}; + init_data[160] = {1'b1, 8'h06}; + init_data[161] = {1'b1, 8'h00}; // write 0x00 to 0x0206 + init_data[162] = {2'b01, 7'h77}; + init_data[163] = {1'b1, 8'h08}; + init_data[164] = {1'b1, 8'h02}; // write 0x02 to 0x0208 + init_data[165] = {1'b1, 8'h00}; // write 0x00 to 0x0209 + init_data[166] = {1'b1, 8'h00}; // write 0x00 to 0x020a + init_data[167] = {1'b1, 8'h00}; // write 0x00 to 0x020b + init_data[168] = {1'b1, 8'h00}; // write 0x00 to 0x020c + init_data[169] = {1'b1, 8'h00}; // write 0x00 to 0x020d + init_data[170] = {1'b1, 8'h01}; // write 0x01 to 0x020e + init_data[171] = {1'b1, 8'h00}; // write 0x00 to 0x020f + init_data[172] = {1'b1, 8'h00}; // write 0x00 to 0x0210 + init_data[173] = {1'b1, 8'h00}; // write 0x00 to 0x0211 + init_data[174] = {1'b1, 8'h02}; // write 0x02 to 0x0212 + init_data[175] = {1'b1, 8'h00}; // write 0x00 to 0x0213 + init_data[176] = {1'b1, 8'h00}; // write 0x00 to 0x0214 + init_data[177] = {1'b1, 8'h00}; // write 0x00 to 0x0215 + init_data[178] = {1'b1, 8'h00}; // write 0x00 to 0x0216 + init_data[179] = {1'b1, 8'h00}; // write 0x00 to 0x0217 + init_data[180] = {1'b1, 8'h01}; // write 0x01 to 0x0218 + init_data[181] = {1'b1, 8'h00}; // write 0x00 to 0x0219 + init_data[182] = {1'b1, 8'h00}; // write 0x00 to 0x021a + init_data[183] = {1'b1, 8'h00}; // write 0x00 to 0x021b + init_data[184] = {1'b1, 8'h00}; // write 0x00 to 0x021c + init_data[185] = {1'b1, 8'h00}; // write 0x00 to 0x021d + init_data[186] = {1'b1, 8'h00}; // write 0x00 to 0x021e + init_data[187] = {1'b1, 8'h00}; // write 0x00 to 0x021f + init_data[188] = {1'b1, 8'h00}; // write 0x00 to 0x0220 + init_data[189] = {1'b1, 8'h00}; // write 0x00 to 0x0221 + init_data[190] = {1'b1, 8'h00}; // write 0x00 to 0x0222 + init_data[191] = {1'b1, 8'h00}; // write 0x00 to 0x0223 + init_data[192] = {1'b1, 8'h00}; // write 0x00 to 0x0224 + init_data[193] = {1'b1, 8'h00}; // write 0x00 to 0x0225 + init_data[194] = {1'b1, 8'h00}; // write 0x00 to 0x0226 + init_data[195] = {1'b1, 8'h00}; // write 0x00 to 0x0227 + init_data[196] = {1'b1, 8'h00}; // write 0x00 to 0x0228 + init_data[197] = {1'b1, 8'h00}; // write 0x00 to 0x0229 + init_data[198] = {1'b1, 8'h00}; // write 0x00 to 0x022a + init_data[199] = {1'b1, 8'h00}; // write 0x00 to 0x022b + init_data[200] = {1'b1, 8'h00}; // write 0x00 to 0x022c + init_data[201] = {1'b1, 8'h00}; // write 0x00 to 0x022d + init_data[202] = {1'b1, 8'h00}; // write 0x00 to 0x022e + init_data[203] = {1'b1, 8'h00}; // write 0x00 to 0x022f + init_data[204] = {2'b01, 7'h77}; + init_data[205] = {1'b1, 8'h35}; + init_data[206] = {1'b1, 8'h00}; // write 0x00 to 0x0235 + init_data[207] = {1'b1, 8'h00}; // write 0x00 to 0x0236 + init_data[208] = {1'b1, 8'h00}; // write 0x00 to 0x0237 + init_data[209] = {1'b1, 8'h90}; // write 0x90 to 0x0238 + init_data[210] = {1'b1, 8'h54}; // write 0x54 to 0x0239 + init_data[211] = {1'b1, 8'h00}; // write 0x00 to 0x023a + init_data[212] = {1'b1, 8'h00}; // write 0x00 to 0x023b + init_data[213] = {1'b1, 8'h00}; // write 0x00 to 0x023c + init_data[214] = {1'b1, 8'h00}; // write 0x00 to 0x023d + init_data[215] = {1'b1, 8'h80}; // write 0x80 to 0x023e + init_data[216] = {2'b01, 7'h77}; + init_data[217] = {1'b1, 8'h4a}; + init_data[218] = {1'b1, 8'h00}; // write 0x00 to 0x024a + init_data[219] = {1'b1, 8'h00}; // write 0x00 to 0x024b + init_data[220] = {1'b1, 8'h00}; // write 0x00 to 0x024c + init_data[221] = {1'b1, 8'h00}; // write 0x00 to 0x024d + init_data[222] = {1'b1, 8'h00}; // write 0x00 to 0x024e + init_data[223] = {1'b1, 8'h00}; // write 0x00 to 0x024f + init_data[224] = {1'b1, 8'h03}; // write 0x03 to 0x0250 + init_data[225] = {1'b1, 8'h00}; // write 0x00 to 0x0251 + init_data[226] = {1'b1, 8'h00}; // write 0x00 to 0x0252 + init_data[227] = {1'b1, 8'h00}; // write 0x00 to 0x0253 + init_data[228] = {1'b1, 8'h00}; // write 0x00 to 0x0254 + init_data[229] = {1'b1, 8'h00}; // write 0x00 to 0x0255 + init_data[230] = {1'b1, 8'h00}; // write 0x00 to 0x0256 + init_data[231] = {1'b1, 8'h00}; // write 0x00 to 0x0257 + init_data[232] = {1'b1, 8'h00}; // write 0x00 to 0x0258 + init_data[233] = {1'b1, 8'h00}; // write 0x00 to 0x0259 + init_data[234] = {1'b1, 8'h00}; // write 0x00 to 0x025a + init_data[235] = {1'b1, 8'h00}; // write 0x00 to 0x025b + init_data[236] = {1'b1, 8'h00}; // write 0x00 to 0x025c + init_data[237] = {1'b1, 8'h00}; // write 0x00 to 0x025d + init_data[238] = {1'b1, 8'h00}; // write 0x00 to 0x025e + init_data[239] = {1'b1, 8'h00}; // write 0x00 to 0x025f + init_data[240] = {1'b1, 8'h00}; // write 0x00 to 0x0260 + init_data[241] = {1'b1, 8'h00}; // write 0x00 to 0x0261 + init_data[242] = {1'b1, 8'h00}; // write 0x00 to 0x0262 + init_data[243] = {1'b1, 8'h00}; // write 0x00 to 0x0263 + init_data[244] = {1'b1, 8'h00}; // write 0x00 to 0x0264 + init_data[245] = {2'b01, 7'h77}; + init_data[246] = {1'b1, 8'h68}; + init_data[247] = {1'b1, 8'h00}; // write 0x00 to 0x0268 + init_data[248] = {1'b1, 8'h00}; // write 0x00 to 0x0269 + init_data[249] = {1'b1, 8'h00}; // write 0x00 to 0x026a + init_data[250] = {1'b1, 8'h39}; // write 0x39 to 0x026b + init_data[251] = {1'b1, 8'h6b}; // write 0x6b to 0x026c + init_data[252] = {1'b1, 8'h32}; // write 0x32 to 0x026d + init_data[253] = {1'b1, 8'h5f}; // write 0x5f to 0x026e + init_data[254] = {1'b1, 8'h31}; // write 0x31 to 0x026f + init_data[255] = {1'b1, 8'h36}; // write 0x36 to 0x0270 + init_data[256] = {1'b1, 8'h31}; // write 0x31 to 0x0271 + init_data[257] = {1'b1, 8'h00}; // write 0x00 to 0x0272 + init_data[258] = {2'b01, 7'h77}; + init_data[259] = {1'b1, 8'h01}; + init_data[260] = {1'b1, 8'h03}; // set page 0x03 + init_data[261] = {2'b01, 7'h77}; + init_data[262] = {1'b1, 8'h02}; + init_data[263] = {1'b1, 8'h00}; // write 0x00 to 0x0302 + init_data[264] = {1'b1, 8'h00}; // write 0x00 to 0x0303 + init_data[265] = {1'b1, 8'h00}; // write 0x00 to 0x0304 + init_data[266] = {1'b1, 8'h80}; // write 0x80 to 0x0305 + init_data[267] = {1'b1, 8'h14}; // write 0x14 to 0x0306 + init_data[268] = {1'b1, 8'h00}; // write 0x00 to 0x0307 + init_data[269] = {1'b1, 8'h00}; // write 0x00 to 0x0308 + init_data[270] = {1'b1, 8'h00}; // write 0x00 to 0x0309 + init_data[271] = {1'b1, 8'h00}; // write 0x00 to 0x030a + init_data[272] = {1'b1, 8'h80}; // write 0x80 to 0x030b + init_data[273] = {1'b1, 8'h00}; // write 0x00 to 0x030c + init_data[274] = {1'b1, 8'h00}; // write 0x00 to 0x030d + init_data[275] = {1'b1, 8'h00}; // write 0x00 to 0x030e + init_data[276] = {1'b1, 8'h10}; // write 0x10 to 0x030f + init_data[277] = {1'b1, 8'h42}; // write 0x42 to 0x0310 + init_data[278] = {1'b1, 8'h08}; // write 0x08 to 0x0311 + init_data[279] = {1'b1, 8'h00}; // write 0x00 to 0x0312 + init_data[280] = {1'b1, 8'h00}; // write 0x00 to 0x0313 + init_data[281] = {1'b1, 8'h00}; // write 0x00 to 0x0314 + init_data[282] = {1'b1, 8'h00}; // write 0x00 to 0x0315 + init_data[283] = {1'b1, 8'h80}; // write 0x80 to 0x0316 + init_data[284] = {1'b1, 8'h00}; // write 0x00 to 0x0317 + init_data[285] = {1'b1, 8'h00}; // write 0x00 to 0x0318 + init_data[286] = {1'b1, 8'h00}; // write 0x00 to 0x0319 + init_data[287] = {1'b1, 8'h00}; // write 0x00 to 0x031a + init_data[288] = {1'b1, 8'h00}; // write 0x00 to 0x031b + init_data[289] = {1'b1, 8'h00}; // write 0x00 to 0x031c + init_data[290] = {1'b1, 8'h00}; // write 0x00 to 0x031d + init_data[291] = {1'b1, 8'h00}; // write 0x00 to 0x031e + init_data[292] = {1'b1, 8'h00}; // write 0x00 to 0x031f + init_data[293] = {1'b1, 8'h00}; // write 0x00 to 0x0320 + init_data[294] = {1'b1, 8'h00}; // write 0x00 to 0x0321 + init_data[295] = {1'b1, 8'h00}; // write 0x00 to 0x0322 + init_data[296] = {1'b1, 8'h00}; // write 0x00 to 0x0323 + init_data[297] = {1'b1, 8'h00}; // write 0x00 to 0x0324 + init_data[298] = {1'b1, 8'h00}; // write 0x00 to 0x0325 + init_data[299] = {1'b1, 8'h00}; // write 0x00 to 0x0326 + init_data[300] = {1'b1, 8'h00}; // write 0x00 to 0x0327 + init_data[301] = {1'b1, 8'h00}; // write 0x00 to 0x0328 + init_data[302] = {1'b1, 8'h00}; // write 0x00 to 0x0329 + init_data[303] = {1'b1, 8'h00}; // write 0x00 to 0x032a + init_data[304] = {1'b1, 8'h00}; // write 0x00 to 0x032b + init_data[305] = {1'b1, 8'h00}; // write 0x00 to 0x032c + init_data[306] = {1'b1, 8'h00}; // write 0x00 to 0x032d + init_data[307] = {1'b1, 8'h00}; // write 0x00 to 0x032e + init_data[308] = {1'b1, 8'h00}; // write 0x00 to 0x032f + init_data[309] = {1'b1, 8'h00}; // write 0x00 to 0x0330 + init_data[310] = {1'b1, 8'h00}; // write 0x00 to 0x0331 + init_data[311] = {1'b1, 8'h00}; // write 0x00 to 0x0332 + init_data[312] = {1'b1, 8'h00}; // write 0x00 to 0x0333 + init_data[313] = {1'b1, 8'h00}; // write 0x00 to 0x0334 + init_data[314] = {1'b1, 8'h00}; // write 0x00 to 0x0335 + init_data[315] = {1'b1, 8'h00}; // write 0x00 to 0x0336 + init_data[316] = {1'b1, 8'h00}; // write 0x00 to 0x0337 + init_data[317] = {1'b1, 8'h00}; // write 0x00 to 0x0338 + init_data[318] = {1'b1, 8'h1f}; // write 0x1f to 0x0339 + init_data[319] = {2'b01, 7'h77}; + init_data[320] = {1'b1, 8'h3b}; + init_data[321] = {1'b1, 8'h00}; // write 0x00 to 0x033b + init_data[322] = {1'b1, 8'h00}; // write 0x00 to 0x033c + init_data[323] = {1'b1, 8'h00}; // write 0x00 to 0x033d + init_data[324] = {1'b1, 8'h00}; // write 0x00 to 0x033e + init_data[325] = {1'b1, 8'h00}; // write 0x00 to 0x033f + init_data[326] = {1'b1, 8'h00}; // write 0x00 to 0x0340 + init_data[327] = {1'b1, 8'h00}; // write 0x00 to 0x0341 + init_data[328] = {1'b1, 8'h00}; // write 0x00 to 0x0342 + init_data[329] = {1'b1, 8'h00}; // write 0x00 to 0x0343 + init_data[330] = {1'b1, 8'h00}; // write 0x00 to 0x0344 + init_data[331] = {1'b1, 8'h00}; // write 0x00 to 0x0345 + init_data[332] = {1'b1, 8'h00}; // write 0x00 to 0x0346 + init_data[333] = {1'b1, 8'h00}; // write 0x00 to 0x0347 + init_data[334] = {1'b1, 8'h00}; // write 0x00 to 0x0348 + init_data[335] = {1'b1, 8'h00}; // write 0x00 to 0x0349 + init_data[336] = {1'b1, 8'h00}; // write 0x00 to 0x034a + init_data[337] = {1'b1, 8'h00}; // write 0x00 to 0x034b + init_data[338] = {1'b1, 8'h00}; // write 0x00 to 0x034c + init_data[339] = {1'b1, 8'h00}; // write 0x00 to 0x034d + init_data[340] = {1'b1, 8'h00}; // write 0x00 to 0x034e + init_data[341] = {1'b1, 8'h00}; // write 0x00 to 0x034f + init_data[342] = {1'b1, 8'h00}; // write 0x00 to 0x0350 + init_data[343] = {1'b1, 8'h00}; // write 0x00 to 0x0351 + init_data[344] = {1'b1, 8'h00}; // write 0x00 to 0x0352 + init_data[345] = {1'b1, 8'h00}; // write 0x00 to 0x0353 + init_data[346] = {1'b1, 8'h00}; // write 0x00 to 0x0354 + init_data[347] = {1'b1, 8'h00}; // write 0x00 to 0x0355 + init_data[348] = {1'b1, 8'h00}; // write 0x00 to 0x0356 + init_data[349] = {1'b1, 8'h00}; // write 0x00 to 0x0357 + init_data[350] = {1'b1, 8'h00}; // write 0x00 to 0x0358 + init_data[351] = {1'b1, 8'h00}; // write 0x00 to 0x0359 + init_data[352] = {1'b1, 8'h00}; // write 0x00 to 0x035a + init_data[353] = {1'b1, 8'h00}; // write 0x00 to 0x035b + init_data[354] = {1'b1, 8'h00}; // write 0x00 to 0x035c + init_data[355] = {1'b1, 8'h00}; // write 0x00 to 0x035d + init_data[356] = {1'b1, 8'h00}; // write 0x00 to 0x035e + init_data[357] = {1'b1, 8'h00}; // write 0x00 to 0x035f + init_data[358] = {1'b1, 8'h00}; // write 0x00 to 0x0360 + init_data[359] = {1'b1, 8'h00}; // write 0x00 to 0x0361 + init_data[360] = {1'b1, 8'h00}; // write 0x00 to 0x0362 + init_data[361] = {2'b01, 7'h77}; + init_data[362] = {1'b1, 8'h01}; + init_data[363] = {1'b1, 8'h08}; // set page 0x08 + init_data[364] = {2'b01, 7'h77}; + init_data[365] = {1'b1, 8'h02}; + init_data[366] = {1'b1, 8'h00}; // write 0x00 to 0x0802 + init_data[367] = {1'b1, 8'h00}; // write 0x00 to 0x0803 + init_data[368] = {1'b1, 8'h00}; // write 0x00 to 0x0804 + init_data[369] = {1'b1, 8'h00}; // write 0x00 to 0x0805 + init_data[370] = {1'b1, 8'h00}; // write 0x00 to 0x0806 + init_data[371] = {1'b1, 8'h00}; // write 0x00 to 0x0807 + init_data[372] = {1'b1, 8'h00}; // write 0x00 to 0x0808 + init_data[373] = {1'b1, 8'h00}; // write 0x00 to 0x0809 + init_data[374] = {1'b1, 8'h00}; // write 0x00 to 0x080a + init_data[375] = {1'b1, 8'h00}; // write 0x00 to 0x080b + init_data[376] = {1'b1, 8'h00}; // write 0x00 to 0x080c + init_data[377] = {1'b1, 8'h00}; // write 0x00 to 0x080d + init_data[378] = {1'b1, 8'h00}; // write 0x00 to 0x080e + init_data[379] = {1'b1, 8'h00}; // write 0x00 to 0x080f + init_data[380] = {1'b1, 8'h00}; // write 0x00 to 0x0810 + init_data[381] = {1'b1, 8'h00}; // write 0x00 to 0x0811 + init_data[382] = {1'b1, 8'h00}; // write 0x00 to 0x0812 + init_data[383] = {1'b1, 8'h00}; // write 0x00 to 0x0813 + init_data[384] = {1'b1, 8'h00}; // write 0x00 to 0x0814 + init_data[385] = {1'b1, 8'h00}; // write 0x00 to 0x0815 + init_data[386] = {1'b1, 8'h00}; // write 0x00 to 0x0816 + init_data[387] = {1'b1, 8'h00}; // write 0x00 to 0x0817 + init_data[388] = {1'b1, 8'h00}; // write 0x00 to 0x0818 + init_data[389] = {1'b1, 8'h00}; // write 0x00 to 0x0819 + init_data[390] = {1'b1, 8'h00}; // write 0x00 to 0x081a + init_data[391] = {1'b1, 8'h00}; // write 0x00 to 0x081b + init_data[392] = {1'b1, 8'h00}; // write 0x00 to 0x081c + init_data[393] = {1'b1, 8'h00}; // write 0x00 to 0x081d + init_data[394] = {1'b1, 8'h00}; // write 0x00 to 0x081e + init_data[395] = {1'b1, 8'h00}; // write 0x00 to 0x081f + init_data[396] = {1'b1, 8'h00}; // write 0x00 to 0x0820 + init_data[397] = {1'b1, 8'h00}; // write 0x00 to 0x0821 + init_data[398] = {1'b1, 8'h00}; // write 0x00 to 0x0822 + init_data[399] = {1'b1, 8'h00}; // write 0x00 to 0x0823 + init_data[400] = {1'b1, 8'h00}; // write 0x00 to 0x0824 + init_data[401] = {1'b1, 8'h00}; // write 0x00 to 0x0825 + init_data[402] = {1'b1, 8'h00}; // write 0x00 to 0x0826 + init_data[403] = {1'b1, 8'h00}; // write 0x00 to 0x0827 + init_data[404] = {1'b1, 8'h00}; // write 0x00 to 0x0828 + init_data[405] = {1'b1, 8'h00}; // write 0x00 to 0x0829 + init_data[406] = {1'b1, 8'h00}; // write 0x00 to 0x082a + init_data[407] = {1'b1, 8'h00}; // write 0x00 to 0x082b + init_data[408] = {1'b1, 8'h00}; // write 0x00 to 0x082c + init_data[409] = {1'b1, 8'h00}; // write 0x00 to 0x082d + init_data[410] = {1'b1, 8'h00}; // write 0x00 to 0x082e + init_data[411] = {1'b1, 8'h00}; // write 0x00 to 0x082f + init_data[412] = {1'b1, 8'h00}; // write 0x00 to 0x0830 + init_data[413] = {1'b1, 8'h00}; // write 0x00 to 0x0831 + init_data[414] = {1'b1, 8'h00}; // write 0x00 to 0x0832 + init_data[415] = {1'b1, 8'h00}; // write 0x00 to 0x0833 + init_data[416] = {1'b1, 8'h00}; // write 0x00 to 0x0834 + init_data[417] = {1'b1, 8'h00}; // write 0x00 to 0x0835 + init_data[418] = {1'b1, 8'h00}; // write 0x00 to 0x0836 + init_data[419] = {1'b1, 8'h00}; // write 0x00 to 0x0837 + init_data[420] = {1'b1, 8'h00}; // write 0x00 to 0x0838 + init_data[421] = {1'b1, 8'h00}; // write 0x00 to 0x0839 + init_data[422] = {1'b1, 8'h00}; // write 0x00 to 0x083a + init_data[423] = {1'b1, 8'h00}; // write 0x00 to 0x083b + init_data[424] = {1'b1, 8'h00}; // write 0x00 to 0x083c + init_data[425] = {1'b1, 8'h00}; // write 0x00 to 0x083d + init_data[426] = {1'b1, 8'h00}; // write 0x00 to 0x083e + init_data[427] = {1'b1, 8'h00}; // write 0x00 to 0x083f + init_data[428] = {1'b1, 8'h00}; // write 0x00 to 0x0840 + init_data[429] = {1'b1, 8'h00}; // write 0x00 to 0x0841 + init_data[430] = {1'b1, 8'h00}; // write 0x00 to 0x0842 + init_data[431] = {1'b1, 8'h00}; // write 0x00 to 0x0843 + init_data[432] = {1'b1, 8'h00}; // write 0x00 to 0x0844 + init_data[433] = {1'b1, 8'h00}; // write 0x00 to 0x0845 + init_data[434] = {1'b1, 8'h00}; // write 0x00 to 0x0846 + init_data[435] = {1'b1, 8'h00}; // write 0x00 to 0x0847 + init_data[436] = {1'b1, 8'h00}; // write 0x00 to 0x0848 + init_data[437] = {1'b1, 8'h00}; // write 0x00 to 0x0849 + init_data[438] = {1'b1, 8'h00}; // write 0x00 to 0x084a + init_data[439] = {1'b1, 8'h00}; // write 0x00 to 0x084b + init_data[440] = {1'b1, 8'h00}; // write 0x00 to 0x084c + init_data[441] = {1'b1, 8'h00}; // write 0x00 to 0x084d + init_data[442] = {1'b1, 8'h00}; // write 0x00 to 0x084e + init_data[443] = {1'b1, 8'h00}; // write 0x00 to 0x084f + init_data[444] = {1'b1, 8'h00}; // write 0x00 to 0x0850 + init_data[445] = {1'b1, 8'h00}; // write 0x00 to 0x0851 + init_data[446] = {1'b1, 8'h00}; // write 0x00 to 0x0852 + init_data[447] = {1'b1, 8'h00}; // write 0x00 to 0x0853 + init_data[448] = {1'b1, 8'h00}; // write 0x00 to 0x0854 + init_data[449] = {1'b1, 8'h00}; // write 0x00 to 0x0855 + init_data[450] = {1'b1, 8'h00}; // write 0x00 to 0x0856 + init_data[451] = {1'b1, 8'h00}; // write 0x00 to 0x0857 + init_data[452] = {1'b1, 8'h00}; // write 0x00 to 0x0858 + init_data[453] = {1'b1, 8'h00}; // write 0x00 to 0x0859 + init_data[454] = {1'b1, 8'h00}; // write 0x00 to 0x085a + init_data[455] = {1'b1, 8'h00}; // write 0x00 to 0x085b + init_data[456] = {1'b1, 8'h00}; // write 0x00 to 0x085c + init_data[457] = {1'b1, 8'h00}; // write 0x00 to 0x085d + init_data[458] = {1'b1, 8'h00}; // write 0x00 to 0x085e + init_data[459] = {1'b1, 8'h00}; // write 0x00 to 0x085f + init_data[460] = {1'b1, 8'h00}; // write 0x00 to 0x0860 + init_data[461] = {1'b1, 8'h00}; // write 0x00 to 0x0861 + init_data[462] = {2'b01, 7'h77}; + init_data[463] = {1'b1, 8'h01}; + init_data[464] = {1'b1, 8'h09}; // set page 0x09 + init_data[465] = {2'b01, 7'h77}; + init_data[466] = {1'b1, 8'h0e}; + init_data[467] = {1'b1, 8'h00}; // write 0x00 to 0x090e + init_data[468] = {2'b01, 7'h77}; + init_data[469] = {1'b1, 8'h1c}; + init_data[470] = {1'b1, 8'h04}; // write 0x04 to 0x091c + init_data[471] = {2'b01, 7'h77}; + init_data[472] = {1'b1, 8'h43}; + init_data[473] = {1'b1, 8'h00}; // write 0x00 to 0x0943 + init_data[474] = {2'b01, 7'h77}; + init_data[475] = {1'b1, 8'h49}; + init_data[476] = {1'b1, 8'h03}; // write 0x03 to 0x0949 + init_data[477] = {1'b1, 8'h30}; // write 0x30 to 0x094a + init_data[478] = {2'b01, 7'h77}; + init_data[479] = {1'b1, 8'h4e}; + init_data[480] = {1'b1, 8'h49}; // write 0x49 to 0x094e + init_data[481] = {1'b1, 8'h02}; // write 0x02 to 0x094f + init_data[482] = {2'b01, 7'h77}; + init_data[483] = {1'b1, 8'h5e}; + init_data[484] = {1'b1, 8'h00}; // write 0x00 to 0x095e + init_data[485] = {2'b01, 7'h77}; + init_data[486] = {1'b1, 8'h01}; + init_data[487] = {1'b1, 8'h0a}; // set page 0x0a + init_data[488] = {2'b01, 7'h77}; + init_data[489] = {1'b1, 8'h02}; + init_data[490] = {1'b1, 8'h00}; // write 0x00 to 0x0a02 + init_data[491] = {1'b1, 8'h03}; // write 0x03 to 0x0a03 + init_data[492] = {1'b1, 8'h01}; // write 0x01 to 0x0a04 + init_data[493] = {1'b1, 8'h03}; // write 0x03 to 0x0a05 + init_data[494] = {2'b01, 7'h77}; + init_data[495] = {1'b1, 8'h14}; + init_data[496] = {1'b1, 8'h00}; // write 0x00 to 0x0a14 + init_data[497] = {2'b01, 7'h77}; + init_data[498] = {1'b1, 8'h1a}; + init_data[499] = {1'b1, 8'h00}; // write 0x00 to 0x0a1a + init_data[500] = {2'b01, 7'h77}; + init_data[501] = {1'b1, 8'h20}; + init_data[502] = {1'b1, 8'h00}; // write 0x00 to 0x0a20 + init_data[503] = {2'b01, 7'h77}; + init_data[504] = {1'b1, 8'h26}; + init_data[505] = {1'b1, 8'h00}; // write 0x00 to 0x0a26 + init_data[506] = {2'b01, 7'h77}; + init_data[507] = {1'b1, 8'h2c}; + init_data[508] = {1'b1, 8'h00}; // write 0x00 to 0x0a2c + init_data[509] = {2'b01, 7'h77}; + init_data[510] = {1'b1, 8'h01}; + init_data[511] = {1'b1, 8'h0b}; // set page 0x0b + init_data[512] = {2'b01, 7'h77}; + init_data[513] = {1'b1, 8'h44}; + init_data[514] = {1'b1, 8'h0f}; // write 0x0f to 0x0b44 + init_data[515] = {2'b01, 7'h77}; + init_data[516] = {1'b1, 8'h4a}; + init_data[517] = {1'b1, 8'h1c}; // write 0x1c to 0x0b4a + init_data[518] = {2'b01, 7'h77}; + init_data[519] = {1'b1, 8'h57}; + init_data[520] = {1'b1, 8'ha5}; // write 0xa5 to 0x0b57 + init_data[521] = {1'b1, 8'h00}; // write 0x00 to 0x0b58 + // End configuration registers + // + // Start configuration postamble + init_data[522] = {2'b01, 7'h77}; + init_data[523] = {1'b1, 8'h01}; + init_data[524] = {1'b1, 8'h00}; // set page 0x00 + init_data[525] = {2'b01, 7'h77}; + init_data[526] = {1'b1, 8'h1c}; + init_data[527] = {1'b1, 8'h01}; // write 0x01 to 0x001c + init_data[528] = {2'b01, 7'h77}; + init_data[529] = {1'b1, 8'h01}; + init_data[530] = {1'b1, 8'h0b}; // set page 0x0b + init_data[531] = {2'b01, 7'h77}; + init_data[532] = {1'b1, 8'h24}; + init_data[533] = {1'b1, 8'hc3}; // write 0xc3 to 0x0b24 + init_data[534] = {1'b1, 8'h02}; // write 0x02 to 0x0b25 + // End configuration postamble + // Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28 + init_data[535] = {2'b01, 7'h70}; + init_data[536] = {1'b1, 8'h00}; + init_data[537] = 9'b001000001; // I2C stop + init_data[538] = {2'b01, 7'h71}; + init_data[539] = {1'b1, 8'h02}; + init_data[540] = 9'b001000001; // I2C stop + // Si534x/7x/8x/9x Registers Script + // + // Part: Si5341 + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_fmc_htg_6qsfp_25g\pll\HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj + // Design ID: HTG6Q161 + // Includes Pre/Post Download Control Register Writes: Yes + // Die Revision: B1 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:56:52 GMT-07:00 + // + // Start configuration preamble + init_data[541] = {2'b01, 7'h77}; + init_data[542] = {1'b1, 8'h01}; + init_data[543] = {1'b1, 8'h0b}; // set page 0x0b + init_data[544] = {2'b01, 7'h77}; + init_data[545] = {1'b1, 8'h24}; + init_data[546] = {1'b1, 8'hc0}; // write 0xc0 to 0x0b24 + init_data[547] = {1'b1, 8'h00}; // write 0x00 to 0x0b25 + // Rev D stuck divider fix + init_data[548] = {2'b01, 7'h77}; + init_data[549] = {1'b1, 8'h01}; + init_data[550] = {1'b1, 8'h05}; // set page 0x05 + init_data[551] = {2'b01, 7'h77}; + init_data[552] = {1'b1, 8'h02}; + init_data[553] = {1'b1, 8'h01}; // write 0x01 to 0x0502 + init_data[554] = {2'b01, 7'h77}; + init_data[555] = {1'b1, 8'h05}; + init_data[556] = {1'b1, 8'h03}; // write 0x03 to 0x0505 + init_data[557] = {2'b01, 7'h77}; + init_data[558] = {1'b1, 8'h01}; + init_data[559] = {1'b1, 8'h09}; // set page 0x09 + init_data[560] = {2'b01, 7'h77}; + init_data[561] = {1'b1, 8'h57}; + init_data[562] = {1'b1, 8'h17}; // write 0x17 to 0x0957 + init_data[563] = {2'b01, 7'h77}; + init_data[564] = {1'b1, 8'h01}; + init_data[565] = {1'b1, 8'h0b}; // set page 0x0b + init_data[566] = {2'b01, 7'h77}; + init_data[567] = {1'b1, 8'h4e}; + init_data[568] = {1'b1, 8'h1a}; // write 0x1a to 0x0b4e + // End configuration preamble + // + // Delay 300 msec + init_data[569] = 9'b000011010; // delay 300 ms + // Delay is worst case time for device to complete any calibration + // that is running due to device state change previous to this script + // being processed. + // + // Start configuration registers + init_data[570] = {2'b01, 7'h77}; + init_data[571] = {1'b1, 8'h01}; + init_data[572] = {1'b1, 8'h00}; // set page 0x00 + init_data[573] = {2'b01, 7'h77}; + init_data[574] = {1'b1, 8'h06}; + init_data[575] = {1'b1, 8'h00}; // write 0x00 to 0x0006 + init_data[576] = {1'b1, 8'h00}; // write 0x00 to 0x0007 + init_data[577] = {1'b1, 8'h00}; // write 0x00 to 0x0008 + init_data[578] = {2'b01, 7'h77}; + init_data[579] = {1'b1, 8'h0b}; + init_data[580] = {1'b1, 8'h74}; // write 0x74 to 0x000b + init_data[581] = {2'b01, 7'h77}; + init_data[582] = {1'b1, 8'h17}; + init_data[583] = {1'b1, 8'hd0}; // write 0xd0 to 0x0017 + init_data[584] = {1'b1, 8'hff}; // write 0xff to 0x0018 + init_data[585] = {2'b01, 7'h77}; + init_data[586] = {1'b1, 8'h21}; + init_data[587] = {1'b1, 8'h0d}; // write 0x0d to 0x0021 + init_data[588] = {1'b1, 8'h00}; // write 0x00 to 0x0022 + init_data[589] = {2'b01, 7'h77}; + init_data[590] = {1'b1, 8'h2b}; + init_data[591] = {1'b1, 8'h02}; // write 0x02 to 0x002b + init_data[592] = {1'b1, 8'h34}; // write 0x34 to 0x002c + init_data[593] = {1'b1, 8'h10}; // write 0x10 to 0x002d + init_data[594] = {1'b1, 8'h00}; // write 0x00 to 0x002e + init_data[595] = {1'b1, 8'h00}; // write 0x00 to 0x002f + init_data[596] = {1'b1, 8'h00}; // write 0x00 to 0x0030 + init_data[597] = {1'b1, 8'h00}; // write 0x00 to 0x0031 + init_data[598] = {1'b1, 8'ha8}; // write 0xa8 to 0x0032 + init_data[599] = {1'b1, 8'h00}; // write 0x00 to 0x0033 + init_data[600] = {1'b1, 8'h00}; // write 0x00 to 0x0034 + init_data[601] = {1'b1, 8'h00}; // write 0x00 to 0x0035 + init_data[602] = {1'b1, 8'h00}; // write 0x00 to 0x0036 + init_data[603] = {1'b1, 8'h00}; // write 0x00 to 0x0037 + init_data[604] = {1'b1, 8'h00}; // write 0x00 to 0x0038 + init_data[605] = {1'b1, 8'h00}; // write 0x00 to 0x0039 + init_data[606] = {1'b1, 8'ha8}; // write 0xa8 to 0x003a + init_data[607] = {1'b1, 8'h00}; // write 0x00 to 0x003b + init_data[608] = {1'b1, 8'h00}; // write 0x00 to 0x003c + init_data[609] = {1'b1, 8'h00}; // write 0x00 to 0x003d + init_data[610] = {2'b01, 7'h77}; + init_data[611] = {1'b1, 8'h41}; + init_data[612] = {1'b1, 8'h00}; // write 0x00 to 0x0041 + init_data[613] = {1'b1, 8'h00}; // write 0x00 to 0x0042 + init_data[614] = {1'b1, 8'h07}; // write 0x07 to 0x0043 + init_data[615] = {1'b1, 8'h00}; // write 0x00 to 0x0044 + init_data[616] = {2'b01, 7'h77}; + init_data[617] = {1'b1, 8'h9e}; + init_data[618] = {1'b1, 8'h00}; // write 0x00 to 0x009e + init_data[619] = {2'b01, 7'h77}; + init_data[620] = {1'b1, 8'h01}; + init_data[621] = {1'b1, 8'h01}; // set page 0x01 + init_data[622] = {2'b01, 7'h77}; + init_data[623] = {1'b1, 8'h02}; + init_data[624] = {1'b1, 8'h01}; // write 0x01 to 0x0102 + init_data[625] = {2'b01, 7'h77}; + init_data[626] = {1'b1, 8'h08}; + init_data[627] = {1'b1, 8'h06}; // write 0x06 to 0x0108 + init_data[628] = {1'b1, 8'h09}; // write 0x09 to 0x0109 + init_data[629] = {1'b1, 8'h33}; // write 0x33 to 0x010a + init_data[630] = {1'b1, 8'h08}; // write 0x08 to 0x010b + init_data[631] = {2'b01, 7'h77}; + init_data[632] = {1'b1, 8'h0d}; + init_data[633] = {1'b1, 8'h06}; // write 0x06 to 0x010d + init_data[634] = {1'b1, 8'h09}; // write 0x09 to 0x010e + init_data[635] = {1'b1, 8'h33}; // write 0x33 to 0x010f + init_data[636] = {1'b1, 8'h08}; // write 0x08 to 0x0110 + init_data[637] = {2'b01, 7'h77}; + init_data[638] = {1'b1, 8'h12}; + init_data[639] = {1'b1, 8'h06}; // write 0x06 to 0x0112 + init_data[640] = {1'b1, 8'h09}; // write 0x09 to 0x0113 + init_data[641] = {1'b1, 8'h33}; // write 0x33 to 0x0114 + init_data[642] = {1'b1, 8'h08}; // write 0x08 to 0x0115 + init_data[643] = {2'b01, 7'h77}; + init_data[644] = {1'b1, 8'h17}; + init_data[645] = {1'b1, 8'h06}; // write 0x06 to 0x0117 + init_data[646] = {1'b1, 8'h09}; // write 0x09 to 0x0118 + init_data[647] = {1'b1, 8'h33}; // write 0x33 to 0x0119 + init_data[648] = {1'b1, 8'h08}; // write 0x08 to 0x011a + init_data[649] = {2'b01, 7'h77}; + init_data[650] = {1'b1, 8'h1c}; + init_data[651] = {1'b1, 8'h06}; // write 0x06 to 0x011c + init_data[652] = {1'b1, 8'h09}; // write 0x09 to 0x011d + init_data[653] = {1'b1, 8'h33}; // write 0x33 to 0x011e + init_data[654] = {1'b1, 8'h08}; // write 0x08 to 0x011f + init_data[655] = {2'b01, 7'h77}; + init_data[656] = {1'b1, 8'h21}; + init_data[657] = {1'b1, 8'h06}; // write 0x06 to 0x0121 + init_data[658] = {1'b1, 8'h09}; // write 0x09 to 0x0122 + init_data[659] = {1'b1, 8'h33}; // write 0x33 to 0x0123 + init_data[660] = {1'b1, 8'h08}; // write 0x08 to 0x0124 + init_data[661] = {2'b01, 7'h77}; + init_data[662] = {1'b1, 8'h26}; + init_data[663] = {1'b1, 8'h06}; // write 0x06 to 0x0126 + init_data[664] = {1'b1, 8'h09}; // write 0x09 to 0x0127 + init_data[665] = {1'b1, 8'h33}; // write 0x33 to 0x0128 + init_data[666] = {1'b1, 8'h08}; // write 0x08 to 0x0129 + init_data[667] = {2'b01, 7'h77}; + init_data[668] = {1'b1, 8'h2b}; + init_data[669] = {1'b1, 8'h06}; // write 0x06 to 0x012b + init_data[670] = {1'b1, 8'h09}; // write 0x09 to 0x012c + init_data[671] = {1'b1, 8'h33}; // write 0x33 to 0x012d + init_data[672] = {1'b1, 8'h08}; // write 0x08 to 0x012e + init_data[673] = {2'b01, 7'h77}; + init_data[674] = {1'b1, 8'h30}; + init_data[675] = {1'b1, 8'h06}; // write 0x06 to 0x0130 + init_data[676] = {1'b1, 8'h09}; // write 0x09 to 0x0131 + init_data[677] = {1'b1, 8'h33}; // write 0x33 to 0x0132 + init_data[678] = {1'b1, 8'h08}; // write 0x08 to 0x0133 + init_data[679] = {2'b01, 7'h77}; + init_data[680] = {1'b1, 8'h3a}; + init_data[681] = {1'b1, 8'h01}; // write 0x01 to 0x013a + init_data[682] = {1'b1, 8'h09}; // write 0x09 to 0x013b + init_data[683] = {1'b1, 8'h3b}; // write 0x3b to 0x013c + init_data[684] = {1'b1, 8'h28}; // write 0x28 to 0x013d + init_data[685] = {2'b01, 7'h77}; + init_data[686] = {1'b1, 8'h3f}; + init_data[687] = {1'b1, 8'h00}; // write 0x00 to 0x013f + init_data[688] = {1'b1, 8'h00}; // write 0x00 to 0x0140 + init_data[689] = {1'b1, 8'h40}; // write 0x40 to 0x0141 + init_data[690] = {2'b01, 7'h77}; + init_data[691] = {1'b1, 8'h01}; + init_data[692] = {1'b1, 8'h02}; // set page 0x02 + init_data[693] = {2'b01, 7'h77}; + init_data[694] = {1'b1, 8'h06}; + init_data[695] = {1'b1, 8'h00}; // write 0x00 to 0x0206 + init_data[696] = {2'b01, 7'h77}; + init_data[697] = {1'b1, 8'h08}; + init_data[698] = {1'b1, 8'h00}; // write 0x00 to 0x0208 + init_data[699] = {1'b1, 8'h00}; // write 0x00 to 0x0209 + init_data[700] = {1'b1, 8'h00}; // write 0x00 to 0x020a + init_data[701] = {1'b1, 8'h00}; // write 0x00 to 0x020b + init_data[702] = {1'b1, 8'h00}; // write 0x00 to 0x020c + init_data[703] = {1'b1, 8'h00}; // write 0x00 to 0x020d + init_data[704] = {1'b1, 8'h00}; // write 0x00 to 0x020e + init_data[705] = {1'b1, 8'h00}; // write 0x00 to 0x020f + init_data[706] = {1'b1, 8'h00}; // write 0x00 to 0x0210 + init_data[707] = {1'b1, 8'h00}; // write 0x00 to 0x0211 + init_data[708] = {1'b1, 8'h00}; // write 0x00 to 0x0212 + init_data[709] = {1'b1, 8'h00}; // write 0x00 to 0x0213 + init_data[710] = {1'b1, 8'h00}; // write 0x00 to 0x0214 + init_data[711] = {1'b1, 8'h00}; // write 0x00 to 0x0215 + init_data[712] = {1'b1, 8'h00}; // write 0x00 to 0x0216 + init_data[713] = {1'b1, 8'h00}; // write 0x00 to 0x0217 + init_data[714] = {1'b1, 8'h00}; // write 0x00 to 0x0218 + init_data[715] = {1'b1, 8'h00}; // write 0x00 to 0x0219 + init_data[716] = {1'b1, 8'h00}; // write 0x00 to 0x021a + init_data[717] = {1'b1, 8'h00}; // write 0x00 to 0x021b + init_data[718] = {1'b1, 8'h02}; // write 0x02 to 0x021c + init_data[719] = {1'b1, 8'h00}; // write 0x00 to 0x021d + init_data[720] = {1'b1, 8'h00}; // write 0x00 to 0x021e + init_data[721] = {1'b1, 8'h00}; // write 0x00 to 0x021f + init_data[722] = {1'b1, 8'h00}; // write 0x00 to 0x0220 + init_data[723] = {1'b1, 8'h00}; // write 0x00 to 0x0221 + init_data[724] = {1'b1, 8'h01}; // write 0x01 to 0x0222 + init_data[725] = {1'b1, 8'h00}; // write 0x00 to 0x0223 + init_data[726] = {1'b1, 8'h00}; // write 0x00 to 0x0224 + init_data[727] = {1'b1, 8'h00}; // write 0x00 to 0x0225 + init_data[728] = {1'b1, 8'h00}; // write 0x00 to 0x0226 + init_data[729] = {1'b1, 8'h00}; // write 0x00 to 0x0227 + init_data[730] = {1'b1, 8'h00}; // write 0x00 to 0x0228 + init_data[731] = {1'b1, 8'h00}; // write 0x00 to 0x0229 + init_data[732] = {1'b1, 8'h00}; // write 0x00 to 0x022a + init_data[733] = {1'b1, 8'h00}; // write 0x00 to 0x022b + init_data[734] = {1'b1, 8'h00}; // write 0x00 to 0x022c + init_data[735] = {1'b1, 8'h00}; // write 0x00 to 0x022d + init_data[736] = {1'b1, 8'h00}; // write 0x00 to 0x022e + init_data[737] = {1'b1, 8'h00}; // write 0x00 to 0x022f + init_data[738] = {2'b01, 7'h77}; + init_data[739] = {1'b1, 8'h35}; + init_data[740] = {1'b1, 8'h00}; // write 0x00 to 0x0235 + init_data[741] = {1'b1, 8'h00}; // write 0x00 to 0x0236 + init_data[742] = {1'b1, 8'h00}; // write 0x00 to 0x0237 + init_data[743] = {1'b1, 8'h00}; // write 0x00 to 0x0238 + init_data[744] = {1'b1, 8'h52}; // write 0x52 to 0x0239 + init_data[745] = {1'b1, 8'h00}; // write 0x00 to 0x023a + init_data[746] = {1'b1, 8'h00}; // write 0x00 to 0x023b + init_data[747] = {1'b1, 8'h00}; // write 0x00 to 0x023c + init_data[748] = {1'b1, 8'h00}; // write 0x00 to 0x023d + init_data[749] = {1'b1, 8'h80}; // write 0x80 to 0x023e + init_data[750] = {2'b01, 7'h77}; + init_data[751] = {1'b1, 8'h4a}; + init_data[752] = {1'b1, 8'h00}; // write 0x00 to 0x024a + init_data[753] = {1'b1, 8'h00}; // write 0x00 to 0x024b + init_data[754] = {1'b1, 8'h00}; // write 0x00 to 0x024c + init_data[755] = {1'b1, 8'h00}; // write 0x00 to 0x024d + init_data[756] = {1'b1, 8'h00}; // write 0x00 to 0x024e + init_data[757] = {1'b1, 8'h00}; // write 0x00 to 0x024f + init_data[758] = {1'b1, 8'h00}; // write 0x00 to 0x0250 + init_data[759] = {1'b1, 8'h00}; // write 0x00 to 0x0251 + init_data[760] = {1'b1, 8'h00}; // write 0x00 to 0x0252 + init_data[761] = {1'b1, 8'h00}; // write 0x00 to 0x0253 + init_data[762] = {1'b1, 8'h00}; // write 0x00 to 0x0254 + init_data[763] = {1'b1, 8'h00}; // write 0x00 to 0x0255 + init_data[764] = {1'b1, 8'h00}; // write 0x00 to 0x0256 + init_data[765] = {1'b1, 8'h00}; // write 0x00 to 0x0257 + init_data[766] = {1'b1, 8'h00}; // write 0x00 to 0x0258 + init_data[767] = {1'b1, 8'h00}; // write 0x00 to 0x0259 + init_data[768] = {1'b1, 8'h00}; // write 0x00 to 0x025a + init_data[769] = {1'b1, 8'h00}; // write 0x00 to 0x025b + init_data[770] = {1'b1, 8'h00}; // write 0x00 to 0x025c + init_data[771] = {1'b1, 8'h00}; // write 0x00 to 0x025d + init_data[772] = {1'b1, 8'h00}; // write 0x00 to 0x025e + init_data[773] = {1'b1, 8'h00}; // write 0x00 to 0x025f + init_data[774] = {1'b1, 8'h00}; // write 0x00 to 0x0260 + init_data[775] = {1'b1, 8'h00}; // write 0x00 to 0x0261 + init_data[776] = {1'b1, 8'h00}; // write 0x00 to 0x0262 + init_data[777] = {1'b1, 8'h00}; // write 0x00 to 0x0263 + init_data[778] = {1'b1, 8'h00}; // write 0x00 to 0x0264 + init_data[779] = {2'b01, 7'h77}; + init_data[780] = {1'b1, 8'h68}; + init_data[781] = {1'b1, 8'h00}; // write 0x00 to 0x0268 + init_data[782] = {1'b1, 8'h00}; // write 0x00 to 0x0269 + init_data[783] = {1'b1, 8'h00}; // write 0x00 to 0x026a + init_data[784] = {1'b1, 8'h48}; // write 0x48 to 0x026b + init_data[785] = {1'b1, 8'h54}; // write 0x54 to 0x026c + init_data[786] = {1'b1, 8'h47}; // write 0x47 to 0x026d + init_data[787] = {1'b1, 8'h36}; // write 0x36 to 0x026e + init_data[788] = {1'b1, 8'h51}; // write 0x51 to 0x026f + init_data[789] = {1'b1, 8'h31}; // write 0x31 to 0x0270 + init_data[790] = {1'b1, 8'h36}; // write 0x36 to 0x0271 + init_data[791] = {1'b1, 8'h31}; // write 0x31 to 0x0272 + init_data[792] = {2'b01, 7'h77}; + init_data[793] = {1'b1, 8'h01}; + init_data[794] = {1'b1, 8'h03}; // set page 0x03 + init_data[795] = {2'b01, 7'h77}; + init_data[796] = {1'b1, 8'h02}; + init_data[797] = {1'b1, 8'h00}; // write 0x00 to 0x0302 + init_data[798] = {1'b1, 8'h00}; // write 0x00 to 0x0303 + init_data[799] = {1'b1, 8'h00}; // write 0x00 to 0x0304 + init_data[800] = {1'b1, 8'h80}; // write 0x80 to 0x0305 + init_data[801] = {1'b1, 8'h14}; // write 0x14 to 0x0306 + init_data[802] = {1'b1, 8'h00}; // write 0x00 to 0x0307 + init_data[803] = {1'b1, 8'h00}; // write 0x00 to 0x0308 + init_data[804] = {1'b1, 8'h00}; // write 0x00 to 0x0309 + init_data[805] = {1'b1, 8'h00}; // write 0x00 to 0x030a + init_data[806] = {1'b1, 8'h80}; // write 0x80 to 0x030b + init_data[807] = {1'b1, 8'h00}; // write 0x00 to 0x030c + init_data[808] = {1'b1, 8'h00}; // write 0x00 to 0x030d + init_data[809] = {1'b1, 8'h00}; // write 0x00 to 0x030e + init_data[810] = {1'b1, 8'h00}; // write 0x00 to 0x030f + init_data[811] = {1'b1, 8'h00}; // write 0x00 to 0x0310 + init_data[812] = {1'b1, 8'h00}; // write 0x00 to 0x0311 + init_data[813] = {1'b1, 8'h00}; // write 0x00 to 0x0312 + init_data[814] = {1'b1, 8'h00}; // write 0x00 to 0x0313 + init_data[815] = {1'b1, 8'h00}; // write 0x00 to 0x0314 + init_data[816] = {1'b1, 8'h00}; // write 0x00 to 0x0315 + init_data[817] = {1'b1, 8'h00}; // write 0x00 to 0x0316 + init_data[818] = {1'b1, 8'h00}; // write 0x00 to 0x0317 + init_data[819] = {1'b1, 8'h00}; // write 0x00 to 0x0318 + init_data[820] = {1'b1, 8'h00}; // write 0x00 to 0x0319 + init_data[821] = {1'b1, 8'h00}; // write 0x00 to 0x031a + init_data[822] = {1'b1, 8'h00}; // write 0x00 to 0x031b + init_data[823] = {1'b1, 8'h00}; // write 0x00 to 0x031c + init_data[824] = {1'b1, 8'h00}; // write 0x00 to 0x031d + init_data[825] = {1'b1, 8'h00}; // write 0x00 to 0x031e + init_data[826] = {1'b1, 8'h00}; // write 0x00 to 0x031f + init_data[827] = {1'b1, 8'h00}; // write 0x00 to 0x0320 + init_data[828] = {1'b1, 8'h00}; // write 0x00 to 0x0321 + init_data[829] = {1'b1, 8'h00}; // write 0x00 to 0x0322 + init_data[830] = {1'b1, 8'h00}; // write 0x00 to 0x0323 + init_data[831] = {1'b1, 8'h00}; // write 0x00 to 0x0324 + init_data[832] = {1'b1, 8'h00}; // write 0x00 to 0x0325 + init_data[833] = {1'b1, 8'h00}; // write 0x00 to 0x0326 + init_data[834] = {1'b1, 8'h00}; // write 0x00 to 0x0327 + init_data[835] = {1'b1, 8'h00}; // write 0x00 to 0x0328 + init_data[836] = {1'b1, 8'h00}; // write 0x00 to 0x0329 + init_data[837] = {1'b1, 8'h00}; // write 0x00 to 0x032a + init_data[838] = {1'b1, 8'h00}; // write 0x00 to 0x032b + init_data[839] = {1'b1, 8'h00}; // write 0x00 to 0x032c + init_data[840] = {1'b1, 8'h00}; // write 0x00 to 0x032d + init_data[841] = {1'b1, 8'h00}; // write 0x00 to 0x032e + init_data[842] = {1'b1, 8'h00}; // write 0x00 to 0x032f + init_data[843] = {1'b1, 8'h00}; // write 0x00 to 0x0330 + init_data[844] = {1'b1, 8'h00}; // write 0x00 to 0x0331 + init_data[845] = {1'b1, 8'h00}; // write 0x00 to 0x0332 + init_data[846] = {1'b1, 8'h00}; // write 0x00 to 0x0333 + init_data[847] = {1'b1, 8'h00}; // write 0x00 to 0x0334 + init_data[848] = {1'b1, 8'h00}; // write 0x00 to 0x0335 + init_data[849] = {1'b1, 8'h00}; // write 0x00 to 0x0336 + init_data[850] = {1'b1, 8'h00}; // write 0x00 to 0x0337 + init_data[851] = {1'b1, 8'h00}; // write 0x00 to 0x0338 + init_data[852] = {1'b1, 8'h1f}; // write 0x1f to 0x0339 + init_data[853] = {2'b01, 7'h77}; + init_data[854] = {1'b1, 8'h3b}; + init_data[855] = {1'b1, 8'h00}; // write 0x00 to 0x033b + init_data[856] = {1'b1, 8'h00}; // write 0x00 to 0x033c + init_data[857] = {1'b1, 8'h00}; // write 0x00 to 0x033d + init_data[858] = {1'b1, 8'h00}; // write 0x00 to 0x033e + init_data[859] = {1'b1, 8'h00}; // write 0x00 to 0x033f + init_data[860] = {1'b1, 8'h00}; // write 0x00 to 0x0340 + init_data[861] = {1'b1, 8'h00}; // write 0x00 to 0x0341 + init_data[862] = {1'b1, 8'h00}; // write 0x00 to 0x0342 + init_data[863] = {1'b1, 8'h00}; // write 0x00 to 0x0343 + init_data[864] = {1'b1, 8'h00}; // write 0x00 to 0x0344 + init_data[865] = {1'b1, 8'h00}; // write 0x00 to 0x0345 + init_data[866] = {1'b1, 8'h00}; // write 0x00 to 0x0346 + init_data[867] = {1'b1, 8'h00}; // write 0x00 to 0x0347 + init_data[868] = {1'b1, 8'h00}; // write 0x00 to 0x0348 + init_data[869] = {1'b1, 8'h00}; // write 0x00 to 0x0349 + init_data[870] = {1'b1, 8'h00}; // write 0x00 to 0x034a + init_data[871] = {1'b1, 8'h00}; // write 0x00 to 0x034b + init_data[872] = {1'b1, 8'h00}; // write 0x00 to 0x034c + init_data[873] = {1'b1, 8'h00}; // write 0x00 to 0x034d + init_data[874] = {1'b1, 8'h00}; // write 0x00 to 0x034e + init_data[875] = {1'b1, 8'h00}; // write 0x00 to 0x034f + init_data[876] = {1'b1, 8'h00}; // write 0x00 to 0x0350 + init_data[877] = {1'b1, 8'h00}; // write 0x00 to 0x0351 + init_data[878] = {1'b1, 8'h00}; // write 0x00 to 0x0352 + init_data[879] = {1'b1, 8'h00}; // write 0x00 to 0x0353 + init_data[880] = {1'b1, 8'h00}; // write 0x00 to 0x0354 + init_data[881] = {1'b1, 8'h00}; // write 0x00 to 0x0355 + init_data[882] = {1'b1, 8'h00}; // write 0x00 to 0x0356 + init_data[883] = {1'b1, 8'h00}; // write 0x00 to 0x0357 + init_data[884] = {1'b1, 8'h00}; // write 0x00 to 0x0358 + init_data[885] = {1'b1, 8'h00}; // write 0x00 to 0x0359 + init_data[886] = {1'b1, 8'h00}; // write 0x00 to 0x035a + init_data[887] = {1'b1, 8'h00}; // write 0x00 to 0x035b + init_data[888] = {1'b1, 8'h00}; // write 0x00 to 0x035c + init_data[889] = {1'b1, 8'h00}; // write 0x00 to 0x035d + init_data[890] = {1'b1, 8'h00}; // write 0x00 to 0x035e + init_data[891] = {1'b1, 8'h00}; // write 0x00 to 0x035f + init_data[892] = {1'b1, 8'h00}; // write 0x00 to 0x0360 + init_data[893] = {1'b1, 8'h00}; // write 0x00 to 0x0361 + init_data[894] = {1'b1, 8'h00}; // write 0x00 to 0x0362 + init_data[895] = {2'b01, 7'h77}; + init_data[896] = {1'b1, 8'h01}; + init_data[897] = {1'b1, 8'h08}; // set page 0x08 + init_data[898] = {2'b01, 7'h77}; + init_data[899] = {1'b1, 8'h02}; + init_data[900] = {1'b1, 8'h00}; // write 0x00 to 0x0802 + init_data[901] = {1'b1, 8'h00}; // write 0x00 to 0x0803 + init_data[902] = {1'b1, 8'h00}; // write 0x00 to 0x0804 + init_data[903] = {1'b1, 8'h00}; // write 0x00 to 0x0805 + init_data[904] = {1'b1, 8'h00}; // write 0x00 to 0x0806 + init_data[905] = {1'b1, 8'h00}; // write 0x00 to 0x0807 + init_data[906] = {1'b1, 8'h00}; // write 0x00 to 0x0808 + init_data[907] = {1'b1, 8'h00}; // write 0x00 to 0x0809 + init_data[908] = {1'b1, 8'h00}; // write 0x00 to 0x080a + init_data[909] = {1'b1, 8'h00}; // write 0x00 to 0x080b + init_data[910] = {1'b1, 8'h00}; // write 0x00 to 0x080c + init_data[911] = {1'b1, 8'h00}; // write 0x00 to 0x080d + init_data[912] = {1'b1, 8'h00}; // write 0x00 to 0x080e + init_data[913] = {1'b1, 8'h00}; // write 0x00 to 0x080f + init_data[914] = {1'b1, 8'h00}; // write 0x00 to 0x0810 + init_data[915] = {1'b1, 8'h00}; // write 0x00 to 0x0811 + init_data[916] = {1'b1, 8'h00}; // write 0x00 to 0x0812 + init_data[917] = {1'b1, 8'h00}; // write 0x00 to 0x0813 + init_data[918] = {1'b1, 8'h00}; // write 0x00 to 0x0814 + init_data[919] = {1'b1, 8'h00}; // write 0x00 to 0x0815 + init_data[920] = {1'b1, 8'h00}; // write 0x00 to 0x0816 + init_data[921] = {1'b1, 8'h00}; // write 0x00 to 0x0817 + init_data[922] = {1'b1, 8'h00}; // write 0x00 to 0x0818 + init_data[923] = {1'b1, 8'h00}; // write 0x00 to 0x0819 + init_data[924] = {1'b1, 8'h00}; // write 0x00 to 0x081a + init_data[925] = {1'b1, 8'h00}; // write 0x00 to 0x081b + init_data[926] = {1'b1, 8'h00}; // write 0x00 to 0x081c + init_data[927] = {1'b1, 8'h00}; // write 0x00 to 0x081d + init_data[928] = {1'b1, 8'h00}; // write 0x00 to 0x081e + init_data[929] = {1'b1, 8'h00}; // write 0x00 to 0x081f + init_data[930] = {1'b1, 8'h00}; // write 0x00 to 0x0820 + init_data[931] = {1'b1, 8'h00}; // write 0x00 to 0x0821 + init_data[932] = {1'b1, 8'h00}; // write 0x00 to 0x0822 + init_data[933] = {1'b1, 8'h00}; // write 0x00 to 0x0823 + init_data[934] = {1'b1, 8'h00}; // write 0x00 to 0x0824 + init_data[935] = {1'b1, 8'h00}; // write 0x00 to 0x0825 + init_data[936] = {1'b1, 8'h00}; // write 0x00 to 0x0826 + init_data[937] = {1'b1, 8'h00}; // write 0x00 to 0x0827 + init_data[938] = {1'b1, 8'h00}; // write 0x00 to 0x0828 + init_data[939] = {1'b1, 8'h00}; // write 0x00 to 0x0829 + init_data[940] = {1'b1, 8'h00}; // write 0x00 to 0x082a + init_data[941] = {1'b1, 8'h00}; // write 0x00 to 0x082b + init_data[942] = {1'b1, 8'h00}; // write 0x00 to 0x082c + init_data[943] = {1'b1, 8'h00}; // write 0x00 to 0x082d + init_data[944] = {1'b1, 8'h00}; // write 0x00 to 0x082e + init_data[945] = {1'b1, 8'h00}; // write 0x00 to 0x082f + init_data[946] = {1'b1, 8'h00}; // write 0x00 to 0x0830 + init_data[947] = {1'b1, 8'h00}; // write 0x00 to 0x0831 + init_data[948] = {1'b1, 8'h00}; // write 0x00 to 0x0832 + init_data[949] = {1'b1, 8'h00}; // write 0x00 to 0x0833 + init_data[950] = {1'b1, 8'h00}; // write 0x00 to 0x0834 + init_data[951] = {1'b1, 8'h00}; // write 0x00 to 0x0835 + init_data[952] = {1'b1, 8'h00}; // write 0x00 to 0x0836 + init_data[953] = {1'b1, 8'h00}; // write 0x00 to 0x0837 + init_data[954] = {1'b1, 8'h00}; // write 0x00 to 0x0838 + init_data[955] = {1'b1, 8'h00}; // write 0x00 to 0x0839 + init_data[956] = {1'b1, 8'h00}; // write 0x00 to 0x083a + init_data[957] = {1'b1, 8'h00}; // write 0x00 to 0x083b + init_data[958] = {1'b1, 8'h00}; // write 0x00 to 0x083c + init_data[959] = {1'b1, 8'h00}; // write 0x00 to 0x083d + init_data[960] = {1'b1, 8'h00}; // write 0x00 to 0x083e + init_data[961] = {1'b1, 8'h00}; // write 0x00 to 0x083f + init_data[962] = {1'b1, 8'h00}; // write 0x00 to 0x0840 + init_data[963] = {1'b1, 8'h00}; // write 0x00 to 0x0841 + init_data[964] = {1'b1, 8'h00}; // write 0x00 to 0x0842 + init_data[965] = {1'b1, 8'h00}; // write 0x00 to 0x0843 + init_data[966] = {1'b1, 8'h00}; // write 0x00 to 0x0844 + init_data[967] = {1'b1, 8'h00}; // write 0x00 to 0x0845 + init_data[968] = {1'b1, 8'h00}; // write 0x00 to 0x0846 + init_data[969] = {1'b1, 8'h00}; // write 0x00 to 0x0847 + init_data[970] = {1'b1, 8'h00}; // write 0x00 to 0x0848 + init_data[971] = {1'b1, 8'h00}; // write 0x00 to 0x0849 + init_data[972] = {1'b1, 8'h00}; // write 0x00 to 0x084a + init_data[973] = {1'b1, 8'h00}; // write 0x00 to 0x084b + init_data[974] = {1'b1, 8'h00}; // write 0x00 to 0x084c + init_data[975] = {1'b1, 8'h00}; // write 0x00 to 0x084d + init_data[976] = {1'b1, 8'h00}; // write 0x00 to 0x084e + init_data[977] = {1'b1, 8'h00}; // write 0x00 to 0x084f + init_data[978] = {1'b1, 8'h00}; // write 0x00 to 0x0850 + init_data[979] = {1'b1, 8'h00}; // write 0x00 to 0x0851 + init_data[980] = {1'b1, 8'h00}; // write 0x00 to 0x0852 + init_data[981] = {1'b1, 8'h00}; // write 0x00 to 0x0853 + init_data[982] = {1'b1, 8'h00}; // write 0x00 to 0x0854 + init_data[983] = {1'b1, 8'h00}; // write 0x00 to 0x0855 + init_data[984] = {1'b1, 8'h00}; // write 0x00 to 0x0856 + init_data[985] = {1'b1, 8'h00}; // write 0x00 to 0x0857 + init_data[986] = {1'b1, 8'h00}; // write 0x00 to 0x0858 + init_data[987] = {1'b1, 8'h00}; // write 0x00 to 0x0859 + init_data[988] = {1'b1, 8'h00}; // write 0x00 to 0x085a + init_data[989] = {1'b1, 8'h00}; // write 0x00 to 0x085b + init_data[990] = {1'b1, 8'h00}; // write 0x00 to 0x085c + init_data[991] = {1'b1, 8'h00}; // write 0x00 to 0x085d + init_data[992] = {1'b1, 8'h00}; // write 0x00 to 0x085e + init_data[993] = {1'b1, 8'h00}; // write 0x00 to 0x085f + init_data[994] = {1'b1, 8'h00}; // write 0x00 to 0x0860 + init_data[995] = {1'b1, 8'h00}; // write 0x00 to 0x0861 + init_data[996] = {2'b01, 7'h77}; + init_data[997] = {1'b1, 8'h01}; + init_data[998] = {1'b1, 8'h09}; // set page 0x09 + init_data[999] = {2'b01, 7'h77}; + init_data[1000] = {1'b1, 8'h0e}; + init_data[1001] = {1'b1, 8'h00}; // write 0x00 to 0x090e + init_data[1002] = {2'b01, 7'h77}; + init_data[1003] = {1'b1, 8'h1c}; + init_data[1004] = {1'b1, 8'h04}; // write 0x04 to 0x091c + init_data[1005] = {2'b01, 7'h77}; + init_data[1006] = {1'b1, 8'h43}; + init_data[1007] = {1'b1, 8'h00}; // write 0x00 to 0x0943 + init_data[1008] = {2'b01, 7'h77}; + init_data[1009] = {1'b1, 8'h49}; + init_data[1010] = {1'b1, 8'h04}; // write 0x04 to 0x0949 + init_data[1011] = {1'b1, 8'h40}; // write 0x40 to 0x094a + init_data[1012] = {2'b01, 7'h77}; + init_data[1013] = {1'b1, 8'h4e}; + init_data[1014] = {1'b1, 8'h49}; // write 0x49 to 0x094e + init_data[1015] = {1'b1, 8'h02}; // write 0x02 to 0x094f + init_data[1016] = {2'b01, 7'h77}; + init_data[1017] = {1'b1, 8'h5e}; + init_data[1018] = {1'b1, 8'h00}; // write 0x00 to 0x095e + init_data[1019] = {2'b01, 7'h77}; + init_data[1020] = {1'b1, 8'h01}; + init_data[1021] = {1'b1, 8'h0a}; // set page 0x0a + init_data[1022] = {2'b01, 7'h77}; + init_data[1023] = {1'b1, 8'h02}; + init_data[1024] = {1'b1, 8'h00}; // write 0x00 to 0x0a02 + init_data[1025] = {1'b1, 8'h01}; // write 0x01 to 0x0a03 + init_data[1026] = {1'b1, 8'h01}; // write 0x01 to 0x0a04 + init_data[1027] = {1'b1, 8'h01}; // write 0x01 to 0x0a05 + init_data[1028] = {2'b01, 7'h77}; + init_data[1029] = {1'b1, 8'h14}; + init_data[1030] = {1'b1, 8'h00}; // write 0x00 to 0x0a14 + init_data[1031] = {2'b01, 7'h77}; + init_data[1032] = {1'b1, 8'h1a}; + init_data[1033] = {1'b1, 8'h00}; // write 0x00 to 0x0a1a + init_data[1034] = {2'b01, 7'h77}; + init_data[1035] = {1'b1, 8'h20}; + init_data[1036] = {1'b1, 8'h00}; // write 0x00 to 0x0a20 + init_data[1037] = {2'b01, 7'h77}; + init_data[1038] = {1'b1, 8'h26}; + init_data[1039] = {1'b1, 8'h00}; // write 0x00 to 0x0a26 + init_data[1040] = {2'b01, 7'h77}; + init_data[1041] = {1'b1, 8'h2c}; + init_data[1042] = {1'b1, 8'h00}; // write 0x00 to 0x0a2c + init_data[1043] = {2'b01, 7'h77}; + init_data[1044] = {1'b1, 8'h01}; + init_data[1045] = {1'b1, 8'h0b}; // set page 0x0b + init_data[1046] = {2'b01, 7'h77}; + init_data[1047] = {1'b1, 8'h44}; + init_data[1048] = {1'b1, 8'h0f}; // write 0x0f to 0x0b44 + init_data[1049] = {2'b01, 7'h77}; + init_data[1050] = {1'b1, 8'h4a}; + init_data[1051] = {1'b1, 8'h1e}; // write 0x1e to 0x0b4a + init_data[1052] = {2'b01, 7'h77}; + init_data[1053] = {1'b1, 8'h57}; + init_data[1054] = {1'b1, 8'ha0}; // write 0xa0 to 0x0b57 + init_data[1055] = {1'b1, 8'h00}; // write 0x00 to 0x0b58 + // End configuration registers + // + // Start configuration postamble + init_data[1056] = {2'b01, 7'h77}; + init_data[1057] = {1'b1, 8'h01}; + init_data[1058] = {1'b1, 8'h00}; // set page 0x00 + init_data[1059] = {2'b01, 7'h77}; + init_data[1060] = {1'b1, 8'h1c}; + init_data[1061] = {1'b1, 8'h01}; // write 0x01 to 0x001c + init_data[1062] = {2'b01, 7'h77}; + init_data[1063] = {1'b1, 8'h01}; + init_data[1064] = {1'b1, 8'h0b}; // set page 0x0b + init_data[1065] = {2'b01, 7'h77}; + init_data[1066] = {1'b1, 8'h24}; + init_data[1067] = {1'b1, 8'hc3}; // write 0xc3 to 0x0b24 + init_data[1068] = {1'b1, 8'h02}; // write 0x02 to 0x0b25 + // End configuration postamble + init_data[1069] = 9'd0; // end +end + +localparam [3:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +parameter AW = $clog2(INIT_DATA_LEN); + +reg [8:0] init_data_reg = 9'd0; + +reg [AW-1:0] address_reg = {AW{1'b0}}, address_next; +reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next; +reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next; + +reg [6:0] cur_address_reg = 7'd0, cur_address_next; + +reg [31:0] delay_counter_reg = 32'd0, delay_counter_next; + +reg [6:0] m_axis_cmd_address_reg = 7'd0, m_axis_cmd_address_next; +reg m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +reg m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +reg m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +reg m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; + +reg start_flag_reg = 1'b0, start_flag_next; + +reg busy_reg = 1'b0; + +assign m_axis_cmd_address = m_axis_cmd_address_reg; +assign m_axis_cmd_start = m_axis_cmd_start_reg; +assign m_axis_cmd_read = 1'b0; +assign m_axis_cmd_write = m_axis_cmd_write_reg; +assign m_axis_cmd_write_multiple = 1'b0; +assign m_axis_cmd_stop = m_axis_cmd_stop_reg; +assign m_axis_cmd_valid = m_axis_cmd_valid_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = 1'b1; + +assign busy = busy_reg; + +always @* begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_write_next = m_axis_cmd_write_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg & ~m_axis_cmd_ready; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd_valid | m_axis_data_tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (~start_flag_reg & start) begin + address_next = {AW{1'b0}}; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + start_flag_reg <= start & start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= 9'd0; + + address_reg <= {AW{1'b0}}; + address_ptr_reg <= {AW{1'b0}}; + data_ptr_reg <= {AW{1'b0}}; + + cur_address_reg <= 7'd0; + + delay_counter_reg <= 32'd0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_data_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v new file mode 100644 index 000000000..f63a5a2e9 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v @@ -0,0 +1,93 @@ +/* + +Copyright (c) 2014-2017 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + +/* + * Synchronizes switch and button inputs with a slow sampled shift register + */ +module debounce_switch #( + parameter WIDTH=1, // width of the input and output signals + parameter N=3, // length of shift register + parameter RATE=125000 // clock division factor +)( + input wire clk, + input wire rst, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [23:0] cnt_reg = 24'd0; + +reg [N-1:0] debounce_reg[WIDTH-1:0]; + +reg [WIDTH-1:0] state; + +/* + * The synchronized output is the state register + */ +assign out = state; + +integer k; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cnt_reg <= 0; + state <= 0; + + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= 0; + end + end else begin + if (cnt_reg < RATE) begin + cnt_reg <= cnt_reg + 24'd1; + end else begin + cnt_reg <= 24'd0; + end + + if (cnt_reg == 24'd0) begin + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; + end + end + + for (k = 0; k < WIDTH; k = k + 1) begin + if (|debounce_reg[k] == 0) begin + state[k] <= 0; + end else if (&debounce_reg[k] == 1) begin + state[k] <= 1; + end else begin + state[k] <= state[k]; + end + end + end +end + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v new file mode 100644 index 000000000..acac5e3f9 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v @@ -0,0 +1,299 @@ +/* + +Copyright (c) 2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY wrapper + */ +module eth_xcvr_phy_wrapper # +( + parameter HAS_COMMON = 1, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL out + */ + input wire xcvr_gtrefclk00_in, + output wire xcvr_qpll0lock_out, + output wire xcvr_qpll0outclk_out, + output wire xcvr_qpll0outrefclk_out, + + /* + * PLL in + */ + input wire xcvr_qpll0lock_in, + output wire xcvr_qpll0reset_out, + input wire xcvr_qpll0clk_in, + input wire xcvr_qpll0refclk_in, + + /* + * Serial data + */ + output wire xcvr_txp, + output wire xcvr_txn, + input wire xcvr_rxp, + input wire xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_tx_clk, + output wire phy_tx_rst, + input wire [DATA_WIDTH-1:0] phy_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_xgmii_txc, + output wire phy_rx_clk, + output wire phy_rx_rst, + output wire [DATA_WIDTH-1:0] phy_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc, + output wire phy_tx_bad_block, + output wire [6:0] phy_rx_error_count, + output wire phy_rx_bad_block, + output wire phy_rx_sequence_error, + output wire phy_rx_block_lock, + output wire phy_rx_high_ber, + input wire phy_tx_prbs31_enable, + input wire phy_rx_prbs31_enable +); + +wire phy_rx_reset_req; + +wire gt_reset_tx_datapath = 1'b0; +wire gt_reset_rx_datapath = phy_rx_reset_req; + +wire gt_reset_tx_done; +wire gt_reset_rx_done; + +wire [5:0] gt_txheader; +wire [63:0] gt_txdata; +wire gt_rxgearboxslip; +wire [5:0] gt_rxheader; +wire [1:0] gt_rxheadervalid; +wire [63:0] gt_rxdata; +wire [1:0] gt_rxdatavalid; + +generate + +if (HAS_COMMON) begin : xcvr + + eth_xcvr_gt_full + eth_xcvr_gt_full_inst ( + // Common + .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), + .gtwiz_reset_all_in(xcvr_ctrl_rst), + .gtpowergood_out(xcvr_gtpowergood_out), + + // PLL + .gtrefclk00_in(xcvr_gtrefclk00_in), + .qpll0lock_out(xcvr_qpll0lock_out), + .qpll0outclk_out(xcvr_qpll0outclk_out), + .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + + // Serial data + .gtytxp_out(xcvr_txp), + .gtytxn_out(xcvr_txn), + .gtyrxp_in(xcvr_rxp), + .gtyrxn_in(xcvr_rxn), + + // Transmit + .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_srcclk_out(), + .gtwiz_userclk_tx_usrclk_out(), + .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), + .gtwiz_userclk_tx_active_out(), + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .txpmaresetdone_out(), + .txprgdivresetdone_out(), + + .gtwiz_userdata_tx_in(gt_txdata), + .txheader_in(gt_txheader), + .txsequence_in(7'b0), + + // Receive + .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_srcclk_out(), + .gtwiz_userclk_rx_usrclk_out(), + .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), + .gtwiz_userclk_rx_active_out(), + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), + .gtwiz_reset_rx_cdr_stable_out(), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), + .rxpmaresetdone_out(), + .rxprgdivresetdone_out(), + + .rxgearboxslip_in(gt_rxgearboxslip), + .gtwiz_userdata_rx_out(gt_rxdata), + .rxdatavalid_out(gt_rxdatavalid), + .rxheader_out(gt_rxheader), + .rxheadervalid_out(gt_rxheadervalid), + .rxstartofseq_out() + ); + +end else begin : xcvr + + eth_xcvr_gt_channel + eth_xcvr_gt_channel_inst ( + // Common + .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), + .gtwiz_reset_all_in(xcvr_ctrl_rst), + .gtpowergood_out(xcvr_gtpowergood_out), + + // PLL + .gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in), + .gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out), + .qpll0clk_in(xcvr_qpll0clk_in), + .qpll0refclk_in(xcvr_qpll0refclk_in), + .qpll1clk_in(1'b0), + .qpll1refclk_in(1'b0), + + // Serial data + .gtytxp_out(xcvr_txp), + .gtytxn_out(xcvr_txn), + .gtyrxp_in(xcvr_rxp), + .gtyrxn_in(xcvr_rxn), + + // Transmit + .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_srcclk_out(), + .gtwiz_userclk_tx_usrclk_out(), + .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), + .gtwiz_userclk_tx_active_out(), + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .txpmaresetdone_out(), + .txprgdivresetdone_out(), + + .gtwiz_userdata_tx_in(gt_txdata), + .txheader_in(gt_txheader), + .txsequence_in(7'b0), + + // Receive + .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_srcclk_out(), + .gtwiz_userclk_rx_usrclk_out(), + .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), + .gtwiz_userclk_rx_active_out(), + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), + .gtwiz_reset_rx_cdr_stable_out(), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), + .rxpmaresetdone_out(), + .rxprgdivresetdone_out(), + + .rxgearboxslip_in(gt_rxgearboxslip), + .gtwiz_userdata_rx_out(gt_rxdata), + .rxdatavalid_out(gt_rxdatavalid), + .rxheader_out(gt_rxheader), + .rxheadervalid_out(gt_rxheadervalid), + .rxstartofseq_out() + ); + +end + +endgenerate + +sync_reset #( + .N(4) +) +tx_reset_sync_inst ( + .clk(phy_tx_clk), + .rst(!gt_reset_tx_done), + .out(phy_tx_rst) +); + +sync_reset #( + .N(4) +) +rx_reset_sync_inst ( + .clk(phy_rx_clk), + .rst(!gt_reset_rx_done), + .out(phy_rx_rst) +); + +eth_phy_10g #( + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .BIT_REVERSE(1), + .SCRAMBLER_DISABLE(0), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +phy_inst ( + .tx_clk(phy_tx_clk), + .tx_rst(phy_tx_rst), + .rx_clk(phy_rx_clk), + .rx_rst(phy_rx_rst), + .xgmii_txd(phy_xgmii_txd), + .xgmii_txc(phy_xgmii_txc), + .xgmii_rxd(phy_xgmii_rxd), + .xgmii_rxc(phy_xgmii_rxc), + .serdes_tx_data(gt_txdata), + .serdes_tx_hdr(gt_txheader), + .serdes_rx_data(gt_rxdata), + .serdes_rx_hdr(gt_rxheader), + .serdes_rx_bitslip(gt_rxgearboxslip), + .serdes_rx_reset_req(phy_rx_reset_req), + .tx_bad_block(phy_tx_bad_block), + .rx_error_count(phy_rx_error_count), + .rx_bad_block(phy_rx_bad_block), + .rx_sequence_error(phy_rx_sequence_error), + .rx_block_lock(phy_rx_block_lock), + .rx_high_ber(phy_rx_high_ber), + .tx_prbs31_enable(phy_tx_prbs31_enable), + .rx_prbs31_enable(phy_rx_prbs31_enable) +); + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v new file mode 100644 index 000000000..637495b66 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v @@ -0,0 +1,4676 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga ( + /* + * Clock: 200 MHz LVDS + */ + input wire ref_clk_p, + input wire ref_clk_n, + + output wire clk_gty2_fdec, + output wire clk_gty2_finc, + input wire clk_gty2_intr_n, + input wire clk_gty2_lol_n, + output wire clk_gty2_oe_n, + output wire clk_gty2_sync_n, + output wire clk_gty2_rst_n, + + /* + * GPIO + */ + input wire [1:0] btn, + input wire [7:0] sw, + output wire [7:0] led, + + /* + * I2C for board management + */ + inout wire i2c_main_scl, + inout wire i2c_main_sda, + output wire i2c_main_rst_n, + + /* + * UART: 115200 bps, 8N1 + */ + output wire uart_rxd, + input wire uart_txd, + input wire uart_rts, + output wire uart_cts, + output wire uart_rst_n, + output wire uart_suspend_n, + + /* + * Ethernet: QSFP28 + */ + output wire [3:0] qsfp_1_tx_p, + output wire [3:0] qsfp_1_tx_n, + input wire [3:0] qsfp_1_rx_p, + input wire [3:0] qsfp_1_rx_n, + input wire qsfp_1_mgt_refclk_p, + input wire qsfp_1_mgt_refclk_n, + output wire qsfp_1_resetl, + input wire qsfp_1_modprsl, + input wire qsfp_1_intl, + + output wire [3:0] qsfp_2_tx_p, + output wire [3:0] qsfp_2_tx_n, + input wire [3:0] qsfp_2_rx_p, + input wire [3:0] qsfp_2_rx_n, + input wire qsfp_2_mgt_refclk_p, + input wire qsfp_2_mgt_refclk_n, + output wire qsfp_2_resetl, + input wire qsfp_2_modprsl, + input wire qsfp_2_intl, + + output wire [3:0] qsfp_3_tx_p, + output wire [3:0] qsfp_3_tx_n, + input wire [3:0] qsfp_3_rx_p, + input wire [3:0] qsfp_3_rx_n, + input wire qsfp_3_mgt_refclk_p, + input wire qsfp_3_mgt_refclk_n, + output wire qsfp_3_resetl, + input wire qsfp_3_modprsl, + input wire qsfp_3_intl, + + output wire [3:0] qsfp_4_tx_p, + output wire [3:0] qsfp_4_tx_n, + input wire [3:0] qsfp_4_rx_p, + input wire [3:0] qsfp_4_rx_n, + input wire qsfp_4_mgt_refclk_p, + input wire qsfp_4_mgt_refclk_n, + output wire qsfp_4_resetl, + input wire qsfp_4_modprsl, + input wire qsfp_4_intl, + + output wire [3:0] qsfp_5_tx_p, + output wire [3:0] qsfp_5_tx_n, + input wire [3:0] qsfp_5_rx_p, + input wire [3:0] qsfp_5_rx_n, + input wire qsfp_5_mgt_refclk_p, + input wire qsfp_5_mgt_refclk_n, + output wire qsfp_5_resetl, + input wire qsfp_5_modprsl, + input wire qsfp_5_intl, + + output wire [3:0] qsfp_6_tx_p, + output wire [3:0] qsfp_6_tx_n, + input wire [3:0] qsfp_6_rx_p, + input wire [3:0] qsfp_6_rx_n, + input wire qsfp_6_mgt_refclk_p, + input wire qsfp_6_mgt_refclk_n, + output wire qsfp_6_resetl, + input wire qsfp_6_modprsl, + input wire qsfp_6_intl, + + output wire [3:0] qsfp_7_tx_p, + output wire [3:0] qsfp_7_tx_n, + input wire [3:0] qsfp_7_rx_p, + input wire [3:0] qsfp_7_rx_n, + input wire qsfp_7_mgt_refclk_p, + input wire qsfp_7_mgt_refclk_n, + output wire qsfp_7_resetl, + input wire qsfp_7_modprsl, + input wire qsfp_7_intl, + + output wire [3:0] qsfp_8_tx_p, + output wire [3:0] qsfp_8_tx_n, + input wire [3:0] qsfp_8_rx_p, + input wire [3:0] qsfp_8_rx_n, + input wire qsfp_8_mgt_refclk_p, + input wire qsfp_8_mgt_refclk_n, + output wire qsfp_8_resetl, + input wire qsfp_8_modprsl, + input wire qsfp_8_intl, + + output wire [3:0] qsfp_9_tx_p, + output wire [3:0] qsfp_9_tx_n, + input wire [3:0] qsfp_9_rx_p, + input wire [3:0] qsfp_9_rx_n, + input wire qsfp_9_mgt_refclk_p, + input wire qsfp_9_mgt_refclk_n, + output wire qsfp_9_resetl, + input wire qsfp_9_modprsl, + input wire qsfp_9_intl, + + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + output wire [3:0] fmc_qsfp_1_tx_p, + output wire [3:0] fmc_qsfp_1_tx_n, + input wire [3:0] fmc_qsfp_1_rx_p, + input wire [3:0] fmc_qsfp_1_rx_n, + input wire fmc_qsfp_1_mgt_refclk_p, + input wire fmc_qsfp_1_mgt_refclk_n, + output wire fmc_qsfp_1_modsell, + output wire fmc_qsfp_1_resetl, + input wire fmc_qsfp_1_modprsl, + input wire fmc_qsfp_1_intl, + output wire fmc_qsfp_1_lpmode, + + output wire [3:0] fmc_qsfp_2_tx_p, + output wire [3:0] fmc_qsfp_2_tx_n, + input wire [3:0] fmc_qsfp_2_rx_p, + input wire [3:0] fmc_qsfp_2_rx_n, + input wire fmc_qsfp_2_mgt_refclk_p, + input wire fmc_qsfp_2_mgt_refclk_n, + output wire fmc_qsfp_2_modsell, + output wire fmc_qsfp_2_resetl, + input wire fmc_qsfp_2_modprsl, + input wire fmc_qsfp_2_intl, + output wire fmc_qsfp_2_lpmode, + + output wire [3:0] fmc_qsfp_3_tx_p, + output wire [3:0] fmc_qsfp_3_tx_n, + input wire [3:0] fmc_qsfp_3_rx_p, + input wire [3:0] fmc_qsfp_3_rx_n, + input wire fmc_qsfp_3_mgt_refclk_p, + input wire fmc_qsfp_3_mgt_refclk_n, + output wire fmc_qsfp_3_modsell, + output wire fmc_qsfp_3_resetl, + input wire fmc_qsfp_3_modprsl, + input wire fmc_qsfp_3_intl, + output wire fmc_qsfp_3_lpmode, + + output wire [3:0] fmc_qsfp_4_tx_p, + output wire [3:0] fmc_qsfp_4_tx_n, + input wire [3:0] fmc_qsfp_4_rx_p, + input wire [3:0] fmc_qsfp_4_rx_n, + input wire fmc_qsfp_4_mgt_refclk_p, + input wire fmc_qsfp_4_mgt_refclk_n, + output wire fmc_qsfp_4_modsell, + output wire fmc_qsfp_4_resetl, + input wire fmc_qsfp_4_modprsl, + input wire fmc_qsfp_4_intl, + output wire fmc_qsfp_4_lpmode, + + output wire [3:0] fmc_qsfp_5_tx_p, + output wire [3:0] fmc_qsfp_5_tx_n, + input wire [3:0] fmc_qsfp_5_rx_p, + input wire [3:0] fmc_qsfp_5_rx_n, + input wire fmc_qsfp_5_mgt_refclk_p, + input wire fmc_qsfp_5_mgt_refclk_n, + output wire fmc_qsfp_5_modsell, + output wire fmc_qsfp_5_resetl, + input wire fmc_qsfp_5_modprsl, + input wire fmc_qsfp_5_intl, + output wire fmc_qsfp_5_lpmode, + + output wire [3:0] fmc_qsfp_6_tx_p, + output wire [3:0] fmc_qsfp_6_tx_n, + input wire [3:0] fmc_qsfp_6_rx_p, + input wire [3:0] fmc_qsfp_6_rx_n, + input wire fmc_qsfp_6_mgt_refclk_p, + input wire fmc_qsfp_6_mgt_refclk_n, + output wire fmc_qsfp_6_modsell, + output wire fmc_qsfp_6_resetl, + input wire fmc_qsfp_6_modprsl, + input wire fmc_qsfp_6_intl, + output wire fmc_qsfp_6_lpmode, + + output wire fmc_clk_finc, + output wire fmc_clk_fdec, + output wire fmc_clk_rst_n, + input wire fmc_clk_lol_n, + output wire fmc_clk_sync_n, + input wire fmc_clk_intr_n, + + output wire fmc_sync_c2m_p, + output wire fmc_sync_c2m_n +); + +// Clock and reset + +wire ref_clk_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +// Internal 156.25 MHz clock +wire clk_156mhz_int; +wire rst_156mhz_int; + +wire mmcm_rst = ~btn[0]; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +ref_clk_ibufg_inst ( + .O (ref_clk_ibufg), + .I (ref_clk_p), + .IB (ref_clk_n) +); + +// MMCM instance +// 200 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 5, D = 1 sets Fvco = 1000 MHz (in range) +// Divide by 8 to get output frequency of 125 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(5), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(5.0), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(ref_clk_ibufg), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire btn_int; +wire [7:0] sw_int; + +debounce_switch #( + .WIDTH(9), + .N(4), + .RATE(125000) +) +debounce_switch_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .in({btn[1], + sw}), + .out({btn_int, + sw_int}) +); + +wire uart_txd_int; +wire uart_rts_int; + +sync_signal #( + .WIDTH(2), + .N(2) +) +sync_signal_inst ( + .clk(clk_125mhz_int), + .in({uart_txd, uart_rts}), + .out({uart_txd_int, uart_rts_int}) +); + +wire i2c_scl_i; +wire i2c_scl_o; +wire i2c_scl_t; +wire i2c_sda_i; +wire i2c_sda_o; +wire i2c_sda_t; + +assign i2c_scl_i = i2c_main_scl; +assign i2c_main_scl = i2c_scl_t ? 1'bz : i2c_scl_o; +assign i2c_sda_i = i2c_main_sda; +assign i2c_main_sda = i2c_sda_t ? 1'bz : i2c_sda_o; +assign i2c_main_rst_n = 1'b1; + +// Si5341 init +wire [6:0] si5341_i2c_cmd_address; +wire si5341_i2c_cmd_start; +wire si5341_i2c_cmd_read; +wire si5341_i2c_cmd_write; +wire si5341_i2c_cmd_write_multiple; +wire si5341_i2c_cmd_stop; +wire si5341_i2c_cmd_valid; +wire si5341_i2c_cmd_ready; + +wire [7:0] si5341_i2c_data_tdata; +wire si5341_i2c_data_tvalid; +wire si5341_i2c_data_tready; +wire si5341_i2c_data_tlast; + +wire si5341_i2c_busy; + +i2c_master +si5341_i2c_master_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .s_axis_cmd_address(si5341_i2c_cmd_address), + .s_axis_cmd_start(si5341_i2c_cmd_start), + .s_axis_cmd_read(si5341_i2c_cmd_read), + .s_axis_cmd_write(si5341_i2c_cmd_write), + .s_axis_cmd_write_multiple(si5341_i2c_cmd_write_multiple), + .s_axis_cmd_stop(si5341_i2c_cmd_stop), + .s_axis_cmd_valid(si5341_i2c_cmd_valid), + .s_axis_cmd_ready(si5341_i2c_cmd_ready), + .s_axis_data_tdata(si5341_i2c_data_tdata), + .s_axis_data_tvalid(si5341_i2c_data_tvalid), + .s_axis_data_tready(si5341_i2c_data_tready), + .s_axis_data_tlast(si5341_i2c_data_tlast), + .m_axis_data_tdata(), + .m_axis_data_tvalid(), + .m_axis_data_tready(1'b1), + .m_axis_data_tlast(), + .scl_i(i2c_scl_i), + .scl_o(i2c_scl_o), + .scl_t(i2c_scl_t), + .sda_i(i2c_sda_i), + .sda_o(i2c_sda_o), + .sda_t(i2c_sda_t), + .busy(), + .bus_control(), + .bus_active(), + .missed_ack(), + .prescale(312), + .stop_on_idle(1) +); + +si5341_i2c_init +si5341_i2c_init_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .m_axis_cmd_address(si5341_i2c_cmd_address), + .m_axis_cmd_start(si5341_i2c_cmd_start), + .m_axis_cmd_read(si5341_i2c_cmd_read), + .m_axis_cmd_write(si5341_i2c_cmd_write), + .m_axis_cmd_write_multiple(si5341_i2c_cmd_write_multiple), + .m_axis_cmd_stop(si5341_i2c_cmd_stop), + .m_axis_cmd_valid(si5341_i2c_cmd_valid), + .m_axis_cmd_ready(si5341_i2c_cmd_ready), + .m_axis_data_tdata(si5341_i2c_data_tdata), + .m_axis_data_tvalid(si5341_i2c_data_tvalid), + .m_axis_data_tready(si5341_i2c_data_tready), + .m_axis_data_tlast(si5341_i2c_data_tlast), + .busy(si5341_i2c_busy), + .start(1'b1) +); + +assign clk_gty2_fdec = 1'b0; +assign clk_gty2_finc = 1'b0; +assign clk_gty2_oe_n = 1'b0; +assign clk_gty2_sync_n = 1'b1; +assign clk_gty2_rst_n = btn[0]; + +assign fmc_clk_finc = 1'b0; +assign fmc_clk_fdec = 1'b0; +assign fmc_clk_rst_n = btn[0]; +assign fmc_clk_sync_n = 1'b1; + +// XGMII 10G PHY +wire qsfp_reset = rst_125mhz_int || si5341_i2c_busy || !clk_gty2_lol_n; +wire fmc_qsfp_reset = rst_125mhz_int || si5341_i2c_busy || !fmc_clk_lol_n; + +// QSFP 1 +assign qsfp_1_resetl = 1'b1; + +wire qsfp_1_tx_clk_1_int; +wire qsfp_1_tx_rst_1_int; +wire [63:0] qsfp_1_txd_1_int; +wire [7:0] qsfp_1_txc_1_int; +wire qsfp_1_rx_clk_1_int; +wire qsfp_1_rx_rst_1_int; +wire [63:0] qsfp_1_rxd_1_int; +wire [7:0] qsfp_1_rxc_1_int; +wire qsfp_1_tx_clk_2_int; +wire qsfp_1_tx_rst_2_int; +wire [63:0] qsfp_1_txd_2_int; +wire [7:0] qsfp_1_txc_2_int; +wire qsfp_1_rx_clk_2_int; +wire qsfp_1_rx_rst_2_int; +wire [63:0] qsfp_1_rxd_2_int; +wire [7:0] qsfp_1_rxc_2_int; +wire qsfp_1_tx_clk_3_int; +wire qsfp_1_tx_rst_3_int; +wire [63:0] qsfp_1_txd_3_int; +wire [7:0] qsfp_1_txc_3_int; +wire qsfp_1_rx_clk_3_int; +wire qsfp_1_rx_rst_3_int; +wire [63:0] qsfp_1_rxd_3_int; +wire [7:0] qsfp_1_rxc_3_int; +wire qsfp_1_tx_clk_4_int; +wire qsfp_1_tx_rst_4_int; +wire [63:0] qsfp_1_txd_4_int; +wire [7:0] qsfp_1_txc_4_int; +wire qsfp_1_rx_clk_4_int; +wire qsfp_1_rx_rst_4_int; +wire [63:0] qsfp_1_rxd_4_int; +wire [7:0] qsfp_1_rxc_4_int; + +assign clk_156mhz_int = qsfp_1_tx_clk_1_int; +assign rst_156mhz_int = qsfp_1_tx_rst_1_int; + +wire qsfp_1_rx_block_lock_1; +wire qsfp_1_rx_block_lock_2; +wire qsfp_1_rx_block_lock_3; +wire qsfp_1_rx_block_lock_4; + +wire qsfp_1_gtpowergood; + +wire qsfp_1_mgt_refclk; +wire qsfp_1_mgt_refclk_int; +wire qsfp_1_mgt_refclk_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst ( + .I (qsfp_1_mgt_refclk_p), + .IB (qsfp_1_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_1_mgt_refclk), + .ODIV2 (qsfp_1_mgt_refclk_int) +); + +BUFG_GT bufg_gt_qsfp_1_mgt_refclk_inst ( + .CE (qsfp_1_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_1_mgt_refclk_int), + .O (qsfp_1_mgt_refclk_bufg) +); + +// forward MGT ref clock to PLL on FMC+ board +OBUFDS obufds_fmc_refclk_inst ( + .I(qsfp_1_mgt_refclk_bufg), + .O(fmc_sync_c2m_p), + .OB(fmc_sync_c2m_n) +); + +wire qsfp_1_qpll0lock; +wire qsfp_1_qpll0outclk; +wire qsfp_1_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_1_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(qsfp_1_gtpowergood), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_1_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_1_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_1_tx_p[0]), + .xcvr_txn(qsfp_1_tx_n[0]), + .xcvr_rxp(qsfp_1_rx_p[0]), + .xcvr_rxn(qsfp_1_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_1_tx_clk_1_int), + .phy_tx_rst(qsfp_1_tx_rst_1_int), + .phy_xgmii_txd(qsfp_1_txd_1_int), + .phy_xgmii_txc(qsfp_1_txc_1_int), + .phy_rx_clk(qsfp_1_rx_clk_1_int), + .phy_rx_rst(qsfp_1_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_1_rxd_1_int), + .phy_xgmii_rxc(qsfp_1_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_1_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_1_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_1_tx_p[1]), + .xcvr_txn(qsfp_1_tx_n[1]), + .xcvr_rxp(qsfp_1_rx_p[1]), + .xcvr_rxn(qsfp_1_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_1_tx_clk_2_int), + .phy_tx_rst(qsfp_1_tx_rst_2_int), + .phy_xgmii_txd(qsfp_1_txd_2_int), + .phy_xgmii_txc(qsfp_1_txc_2_int), + .phy_rx_clk(qsfp_1_rx_clk_2_int), + .phy_rx_rst(qsfp_1_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_1_rxd_2_int), + .phy_xgmii_rxc(qsfp_1_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_1_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_1_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_1_tx_p[2]), + .xcvr_txn(qsfp_1_tx_n[2]), + .xcvr_rxp(qsfp_1_rx_p[2]), + .xcvr_rxn(qsfp_1_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_1_tx_clk_3_int), + .phy_tx_rst(qsfp_1_tx_rst_3_int), + .phy_xgmii_txd(qsfp_1_txd_3_int), + .phy_xgmii_txc(qsfp_1_txc_3_int), + .phy_rx_clk(qsfp_1_rx_clk_3_int), + .phy_rx_rst(qsfp_1_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_1_rxd_3_int), + .phy_xgmii_rxc(qsfp_1_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_1_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_1_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_1_tx_p[3]), + .xcvr_txn(qsfp_1_tx_n[3]), + .xcvr_rxp(qsfp_1_rx_p[3]), + .xcvr_rxn(qsfp_1_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_1_tx_clk_4_int), + .phy_tx_rst(qsfp_1_tx_rst_4_int), + .phy_xgmii_txd(qsfp_1_txd_4_int), + .phy_xgmii_txc(qsfp_1_txc_4_int), + .phy_rx_clk(qsfp_1_rx_clk_4_int), + .phy_rx_rst(qsfp_1_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_1_rxd_4_int), + .phy_xgmii_rxc(qsfp_1_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_1_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 2 +assign qsfp_2_resetl = 1'b1; + +wire qsfp_2_tx_clk_1_int; +wire qsfp_2_tx_rst_1_int; +wire [63:0] qsfp_2_txd_1_int; +wire [7:0] qsfp_2_txc_1_int; +wire qsfp_2_rx_clk_1_int; +wire qsfp_2_rx_rst_1_int; +wire [63:0] qsfp_2_rxd_1_int; +wire [7:0] qsfp_2_rxc_1_int; +wire qsfp_2_tx_clk_2_int; +wire qsfp_2_tx_rst_2_int; +wire [63:0] qsfp_2_txd_2_int; +wire [7:0] qsfp_2_txc_2_int; +wire qsfp_2_rx_clk_2_int; +wire qsfp_2_rx_rst_2_int; +wire [63:0] qsfp_2_rxd_2_int; +wire [7:0] qsfp_2_rxc_2_int; +wire qsfp_2_tx_clk_3_int; +wire qsfp_2_tx_rst_3_int; +wire [63:0] qsfp_2_txd_3_int; +wire [7:0] qsfp_2_txc_3_int; +wire qsfp_2_rx_clk_3_int; +wire qsfp_2_rx_rst_3_int; +wire [63:0] qsfp_2_rxd_3_int; +wire [7:0] qsfp_2_rxc_3_int; +wire qsfp_2_tx_clk_4_int; +wire qsfp_2_tx_rst_4_int; +wire [63:0] qsfp_2_txd_4_int; +wire [7:0] qsfp_2_txc_4_int; +wire qsfp_2_rx_clk_4_int; +wire qsfp_2_rx_rst_4_int; +wire [63:0] qsfp_2_rxd_4_int; +wire [7:0] qsfp_2_rxc_4_int; + +wire qsfp_2_rx_block_lock_1; +wire qsfp_2_rx_block_lock_2; +wire qsfp_2_rx_block_lock_3; +wire qsfp_2_rx_block_lock_4; + +wire qsfp_2_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_2_mgt_refclk_inst ( + .I (qsfp_2_mgt_refclk_p), + .IB (qsfp_2_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_2_mgt_refclk), + .ODIV2 () +); + +wire qsfp_2_qpll0lock; +wire qsfp_2_qpll0outclk; +wire qsfp_2_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_2_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_2_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_2_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_2_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_2_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_2_tx_p[0]), + .xcvr_txn(qsfp_2_tx_n[0]), + .xcvr_rxp(qsfp_2_rx_p[0]), + .xcvr_rxn(qsfp_2_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_2_tx_clk_1_int), + .phy_tx_rst(qsfp_2_tx_rst_1_int), + .phy_xgmii_txd(qsfp_2_txd_1_int), + .phy_xgmii_txc(qsfp_2_txc_1_int), + .phy_rx_clk(qsfp_2_rx_clk_1_int), + .phy_rx_rst(qsfp_2_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_2_rxd_1_int), + .phy_xgmii_rxc(qsfp_2_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_2_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_2_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_2_tx_p[1]), + .xcvr_txn(qsfp_2_tx_n[1]), + .xcvr_rxp(qsfp_2_rx_p[1]), + .xcvr_rxn(qsfp_2_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_2_tx_clk_2_int), + .phy_tx_rst(qsfp_2_tx_rst_2_int), + .phy_xgmii_txd(qsfp_2_txd_2_int), + .phy_xgmii_txc(qsfp_2_txc_2_int), + .phy_rx_clk(qsfp_2_rx_clk_2_int), + .phy_rx_rst(qsfp_2_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_2_rxd_2_int), + .phy_xgmii_rxc(qsfp_2_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_2_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_2_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_2_tx_p[2]), + .xcvr_txn(qsfp_2_tx_n[2]), + .xcvr_rxp(qsfp_2_rx_p[2]), + .xcvr_rxn(qsfp_2_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_2_tx_clk_3_int), + .phy_tx_rst(qsfp_2_tx_rst_3_int), + .phy_xgmii_txd(qsfp_2_txd_3_int), + .phy_xgmii_txc(qsfp_2_txc_3_int), + .phy_rx_clk(qsfp_2_rx_clk_3_int), + .phy_rx_rst(qsfp_2_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_2_rxd_3_int), + .phy_xgmii_rxc(qsfp_2_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_2_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_2_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_2_tx_p[3]), + .xcvr_txn(qsfp_2_tx_n[3]), + .xcvr_rxp(qsfp_2_rx_p[3]), + .xcvr_rxn(qsfp_2_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_2_tx_clk_4_int), + .phy_tx_rst(qsfp_2_tx_rst_4_int), + .phy_xgmii_txd(qsfp_2_txd_4_int), + .phy_xgmii_txc(qsfp_2_txc_4_int), + .phy_rx_clk(qsfp_2_rx_clk_4_int), + .phy_rx_rst(qsfp_2_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_2_rxd_4_int), + .phy_xgmii_rxc(qsfp_2_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_2_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 3 +assign qsfp_3_resetl = 1'b1; + +wire qsfp_3_tx_clk_1_int; +wire qsfp_3_tx_rst_1_int; +wire [63:0] qsfp_3_txd_1_int; +wire [7:0] qsfp_3_txc_1_int; +wire qsfp_3_rx_clk_1_int; +wire qsfp_3_rx_rst_1_int; +wire [63:0] qsfp_3_rxd_1_int; +wire [7:0] qsfp_3_rxc_1_int; +wire qsfp_3_tx_clk_2_int; +wire qsfp_3_tx_rst_2_int; +wire [63:0] qsfp_3_txd_2_int; +wire [7:0] qsfp_3_txc_2_int; +wire qsfp_3_rx_clk_2_int; +wire qsfp_3_rx_rst_2_int; +wire [63:0] qsfp_3_rxd_2_int; +wire [7:0] qsfp_3_rxc_2_int; +wire qsfp_3_tx_clk_3_int; +wire qsfp_3_tx_rst_3_int; +wire [63:0] qsfp_3_txd_3_int; +wire [7:0] qsfp_3_txc_3_int; +wire qsfp_3_rx_clk_3_int; +wire qsfp_3_rx_rst_3_int; +wire [63:0] qsfp_3_rxd_3_int; +wire [7:0] qsfp_3_rxc_3_int; +wire qsfp_3_tx_clk_4_int; +wire qsfp_3_tx_rst_4_int; +wire [63:0] qsfp_3_txd_4_int; +wire [7:0] qsfp_3_txc_4_int; +wire qsfp_3_rx_clk_4_int; +wire qsfp_3_rx_rst_4_int; +wire [63:0] qsfp_3_rxd_4_int; +wire [7:0] qsfp_3_rxc_4_int; + +wire qsfp_3_rx_block_lock_1; +wire qsfp_3_rx_block_lock_2; +wire qsfp_3_rx_block_lock_3; +wire qsfp_3_rx_block_lock_4; + +wire qsfp_3_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_3_mgt_refclk_inst ( + .I (qsfp_3_mgt_refclk_p), + .IB (qsfp_3_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_3_mgt_refclk), + .ODIV2 () +); + +wire qsfp_3_qpll0lock; +wire qsfp_3_qpll0outclk; +wire qsfp_3_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_3_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_3_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_3_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_3_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_3_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_3_tx_p[0]), + .xcvr_txn(qsfp_3_tx_n[0]), + .xcvr_rxp(qsfp_3_rx_p[0]), + .xcvr_rxn(qsfp_3_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_3_tx_clk_1_int), + .phy_tx_rst(qsfp_3_tx_rst_1_int), + .phy_xgmii_txd(qsfp_3_txd_1_int), + .phy_xgmii_txc(qsfp_3_txc_1_int), + .phy_rx_clk(qsfp_3_rx_clk_1_int), + .phy_rx_rst(qsfp_3_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_3_rxd_1_int), + .phy_xgmii_rxc(qsfp_3_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_3_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_3_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_3_tx_p[1]), + .xcvr_txn(qsfp_3_tx_n[1]), + .xcvr_rxp(qsfp_3_rx_p[1]), + .xcvr_rxn(qsfp_3_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_3_tx_clk_2_int), + .phy_tx_rst(qsfp_3_tx_rst_2_int), + .phy_xgmii_txd(qsfp_3_txd_2_int), + .phy_xgmii_txc(qsfp_3_txc_2_int), + .phy_rx_clk(qsfp_3_rx_clk_2_int), + .phy_rx_rst(qsfp_3_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_3_rxd_2_int), + .phy_xgmii_rxc(qsfp_3_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_3_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_3_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_3_tx_p[2]), + .xcvr_txn(qsfp_3_tx_n[2]), + .xcvr_rxp(qsfp_3_rx_p[2]), + .xcvr_rxn(qsfp_3_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_3_tx_clk_3_int), + .phy_tx_rst(qsfp_3_tx_rst_3_int), + .phy_xgmii_txd(qsfp_3_txd_3_int), + .phy_xgmii_txc(qsfp_3_txc_3_int), + .phy_rx_clk(qsfp_3_rx_clk_3_int), + .phy_rx_rst(qsfp_3_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_3_rxd_3_int), + .phy_xgmii_rxc(qsfp_3_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_3_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_3_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_3_tx_p[3]), + .xcvr_txn(qsfp_3_tx_n[3]), + .xcvr_rxp(qsfp_3_rx_p[3]), + .xcvr_rxn(qsfp_3_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_3_tx_clk_4_int), + .phy_tx_rst(qsfp_3_tx_rst_4_int), + .phy_xgmii_txd(qsfp_3_txd_4_int), + .phy_xgmii_txc(qsfp_3_txc_4_int), + .phy_rx_clk(qsfp_3_rx_clk_4_int), + .phy_rx_rst(qsfp_3_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_3_rxd_4_int), + .phy_xgmii_rxc(qsfp_3_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_3_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 4 +assign qsfp_4_resetl = 1'b1; + +wire qsfp_4_tx_clk_1_int; +wire qsfp_4_tx_rst_1_int; +wire [63:0] qsfp_4_txd_1_int; +wire [7:0] qsfp_4_txc_1_int; +wire qsfp_4_rx_clk_1_int; +wire qsfp_4_rx_rst_1_int; +wire [63:0] qsfp_4_rxd_1_int; +wire [7:0] qsfp_4_rxc_1_int; +wire qsfp_4_tx_clk_2_int; +wire qsfp_4_tx_rst_2_int; +wire [63:0] qsfp_4_txd_2_int; +wire [7:0] qsfp_4_txc_2_int; +wire qsfp_4_rx_clk_2_int; +wire qsfp_4_rx_rst_2_int; +wire [63:0] qsfp_4_rxd_2_int; +wire [7:0] qsfp_4_rxc_2_int; +wire qsfp_4_tx_clk_3_int; +wire qsfp_4_tx_rst_3_int; +wire [63:0] qsfp_4_txd_3_int; +wire [7:0] qsfp_4_txc_3_int; +wire qsfp_4_rx_clk_3_int; +wire qsfp_4_rx_rst_3_int; +wire [63:0] qsfp_4_rxd_3_int; +wire [7:0] qsfp_4_rxc_3_int; +wire qsfp_4_tx_clk_4_int; +wire qsfp_4_tx_rst_4_int; +wire [63:0] qsfp_4_txd_4_int; +wire [7:0] qsfp_4_txc_4_int; +wire qsfp_4_rx_clk_4_int; +wire qsfp_4_rx_rst_4_int; +wire [63:0] qsfp_4_rxd_4_int; +wire [7:0] qsfp_4_rxc_4_int; + +wire qsfp_4_rx_block_lock_1; +wire qsfp_4_rx_block_lock_2; +wire qsfp_4_rx_block_lock_3; +wire qsfp_4_rx_block_lock_4; + +wire qsfp_4_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_4_mgt_refclk_inst ( + .I (qsfp_4_mgt_refclk_p), + .IB (qsfp_4_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_4_mgt_refclk), + .ODIV2 () +); + +wire qsfp_4_qpll0lock; +wire qsfp_4_qpll0outclk; +wire qsfp_4_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_4_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_4_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_4_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_4_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_4_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_4_tx_p[0]), + .xcvr_txn(qsfp_4_tx_n[0]), + .xcvr_rxp(qsfp_4_rx_p[0]), + .xcvr_rxn(qsfp_4_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_4_tx_clk_1_int), + .phy_tx_rst(qsfp_4_tx_rst_1_int), + .phy_xgmii_txd(qsfp_4_txd_1_int), + .phy_xgmii_txc(qsfp_4_txc_1_int), + .phy_rx_clk(qsfp_4_rx_clk_1_int), + .phy_rx_rst(qsfp_4_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_4_rxd_1_int), + .phy_xgmii_rxc(qsfp_4_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_4_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_4_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_4_tx_p[1]), + .xcvr_txn(qsfp_4_tx_n[1]), + .xcvr_rxp(qsfp_4_rx_p[1]), + .xcvr_rxn(qsfp_4_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_4_tx_clk_2_int), + .phy_tx_rst(qsfp_4_tx_rst_2_int), + .phy_xgmii_txd(qsfp_4_txd_2_int), + .phy_xgmii_txc(qsfp_4_txc_2_int), + .phy_rx_clk(qsfp_4_rx_clk_2_int), + .phy_rx_rst(qsfp_4_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_4_rxd_2_int), + .phy_xgmii_rxc(qsfp_4_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_4_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_4_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_4_tx_p[2]), + .xcvr_txn(qsfp_4_tx_n[2]), + .xcvr_rxp(qsfp_4_rx_p[2]), + .xcvr_rxn(qsfp_4_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_4_tx_clk_3_int), + .phy_tx_rst(qsfp_4_tx_rst_3_int), + .phy_xgmii_txd(qsfp_4_txd_3_int), + .phy_xgmii_txc(qsfp_4_txc_3_int), + .phy_rx_clk(qsfp_4_rx_clk_3_int), + .phy_rx_rst(qsfp_4_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_4_rxd_3_int), + .phy_xgmii_rxc(qsfp_4_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_4_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_4_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_4_tx_p[3]), + .xcvr_txn(qsfp_4_tx_n[3]), + .xcvr_rxp(qsfp_4_rx_p[3]), + .xcvr_rxn(qsfp_4_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_4_tx_clk_4_int), + .phy_tx_rst(qsfp_4_tx_rst_4_int), + .phy_xgmii_txd(qsfp_4_txd_4_int), + .phy_xgmii_txc(qsfp_4_txc_4_int), + .phy_rx_clk(qsfp_4_rx_clk_4_int), + .phy_rx_rst(qsfp_4_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_4_rxd_4_int), + .phy_xgmii_rxc(qsfp_4_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_4_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 5 +assign qsfp_5_resetl = 1'b1; + +wire qsfp_5_tx_clk_1_int; +wire qsfp_5_tx_rst_1_int; +wire [63:0] qsfp_5_txd_1_int; +wire [7:0] qsfp_5_txc_1_int; +wire qsfp_5_rx_clk_1_int; +wire qsfp_5_rx_rst_1_int; +wire [63:0] qsfp_5_rxd_1_int; +wire [7:0] qsfp_5_rxc_1_int; +wire qsfp_5_tx_clk_2_int; +wire qsfp_5_tx_rst_2_int; +wire [63:0] qsfp_5_txd_2_int; +wire [7:0] qsfp_5_txc_2_int; +wire qsfp_5_rx_clk_2_int; +wire qsfp_5_rx_rst_2_int; +wire [63:0] qsfp_5_rxd_2_int; +wire [7:0] qsfp_5_rxc_2_int; +wire qsfp_5_tx_clk_3_int; +wire qsfp_5_tx_rst_3_int; +wire [63:0] qsfp_5_txd_3_int; +wire [7:0] qsfp_5_txc_3_int; +wire qsfp_5_rx_clk_3_int; +wire qsfp_5_rx_rst_3_int; +wire [63:0] qsfp_5_rxd_3_int; +wire [7:0] qsfp_5_rxc_3_int; +wire qsfp_5_tx_clk_4_int; +wire qsfp_5_tx_rst_4_int; +wire [63:0] qsfp_5_txd_4_int; +wire [7:0] qsfp_5_txc_4_int; +wire qsfp_5_rx_clk_4_int; +wire qsfp_5_rx_rst_4_int; +wire [63:0] qsfp_5_rxd_4_int; +wire [7:0] qsfp_5_rxc_4_int; + +wire qsfp_5_rx_block_lock_1; +wire qsfp_5_rx_block_lock_2; +wire qsfp_5_rx_block_lock_3; +wire qsfp_5_rx_block_lock_4; + +wire qsfp_5_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_5_mgt_refclk_inst ( + .I (qsfp_5_mgt_refclk_p), + .IB (qsfp_5_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_5_mgt_refclk), + .ODIV2 () +); + +wire qsfp_5_qpll0lock; +wire qsfp_5_qpll0outclk; +wire qsfp_5_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_5_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_5_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_5_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_5_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_5_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_5_tx_p[0]), + .xcvr_txn(qsfp_5_tx_n[0]), + .xcvr_rxp(qsfp_5_rx_p[0]), + .xcvr_rxn(qsfp_5_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_5_tx_clk_1_int), + .phy_tx_rst(qsfp_5_tx_rst_1_int), + .phy_xgmii_txd(qsfp_5_txd_1_int), + .phy_xgmii_txc(qsfp_5_txc_1_int), + .phy_rx_clk(qsfp_5_rx_clk_1_int), + .phy_rx_rst(qsfp_5_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_5_rxd_1_int), + .phy_xgmii_rxc(qsfp_5_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_5_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_5_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_5_tx_p[1]), + .xcvr_txn(qsfp_5_tx_n[1]), + .xcvr_rxp(qsfp_5_rx_p[1]), + .xcvr_rxn(qsfp_5_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_5_tx_clk_2_int), + .phy_tx_rst(qsfp_5_tx_rst_2_int), + .phy_xgmii_txd(qsfp_5_txd_2_int), + .phy_xgmii_txc(qsfp_5_txc_2_int), + .phy_rx_clk(qsfp_5_rx_clk_2_int), + .phy_rx_rst(qsfp_5_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_5_rxd_2_int), + .phy_xgmii_rxc(qsfp_5_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_5_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_5_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_5_tx_p[2]), + .xcvr_txn(qsfp_5_tx_n[2]), + .xcvr_rxp(qsfp_5_rx_p[2]), + .xcvr_rxn(qsfp_5_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_5_tx_clk_3_int), + .phy_tx_rst(qsfp_5_tx_rst_3_int), + .phy_xgmii_txd(qsfp_5_txd_3_int), + .phy_xgmii_txc(qsfp_5_txc_3_int), + .phy_rx_clk(qsfp_5_rx_clk_3_int), + .phy_rx_rst(qsfp_5_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_5_rxd_3_int), + .phy_xgmii_rxc(qsfp_5_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_5_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_5_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_5_tx_p[3]), + .xcvr_txn(qsfp_5_tx_n[3]), + .xcvr_rxp(qsfp_5_rx_p[3]), + .xcvr_rxn(qsfp_5_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_5_tx_clk_4_int), + .phy_tx_rst(qsfp_5_tx_rst_4_int), + .phy_xgmii_txd(qsfp_5_txd_4_int), + .phy_xgmii_txc(qsfp_5_txc_4_int), + .phy_rx_clk(qsfp_5_rx_clk_4_int), + .phy_rx_rst(qsfp_5_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_5_rxd_4_int), + .phy_xgmii_rxc(qsfp_5_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_5_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 6 +assign qsfp_6_resetl = 1'b1; + +wire qsfp_6_tx_clk_1_int; +wire qsfp_6_tx_rst_1_int; +wire [63:0] qsfp_6_txd_1_int; +wire [7:0] qsfp_6_txc_1_int; +wire qsfp_6_rx_clk_1_int; +wire qsfp_6_rx_rst_1_int; +wire [63:0] qsfp_6_rxd_1_int; +wire [7:0] qsfp_6_rxc_1_int; +wire qsfp_6_tx_clk_2_int; +wire qsfp_6_tx_rst_2_int; +wire [63:0] qsfp_6_txd_2_int; +wire [7:0] qsfp_6_txc_2_int; +wire qsfp_6_rx_clk_2_int; +wire qsfp_6_rx_rst_2_int; +wire [63:0] qsfp_6_rxd_2_int; +wire [7:0] qsfp_6_rxc_2_int; +wire qsfp_6_tx_clk_3_int; +wire qsfp_6_tx_rst_3_int; +wire [63:0] qsfp_6_txd_3_int; +wire [7:0] qsfp_6_txc_3_int; +wire qsfp_6_rx_clk_3_int; +wire qsfp_6_rx_rst_3_int; +wire [63:0] qsfp_6_rxd_3_int; +wire [7:0] qsfp_6_rxc_3_int; +wire qsfp_6_tx_clk_4_int; +wire qsfp_6_tx_rst_4_int; +wire [63:0] qsfp_6_txd_4_int; +wire [7:0] qsfp_6_txc_4_int; +wire qsfp_6_rx_clk_4_int; +wire qsfp_6_rx_rst_4_int; +wire [63:0] qsfp_6_rxd_4_int; +wire [7:0] qsfp_6_rxc_4_int; + +wire qsfp_6_rx_block_lock_1; +wire qsfp_6_rx_block_lock_2; +wire qsfp_6_rx_block_lock_3; +wire qsfp_6_rx_block_lock_4; + +wire qsfp_6_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_6_mgt_refclk_inst ( + .I (qsfp_6_mgt_refclk_p), + .IB (qsfp_6_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_6_mgt_refclk), + .ODIV2 () +); + +wire qsfp_6_qpll0lock; +wire qsfp_6_qpll0outclk; +wire qsfp_6_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_6_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_6_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_6_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_6_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_6_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_6_tx_p[0]), + .xcvr_txn(qsfp_6_tx_n[0]), + .xcvr_rxp(qsfp_6_rx_p[0]), + .xcvr_rxn(qsfp_6_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_6_tx_clk_1_int), + .phy_tx_rst(qsfp_6_tx_rst_1_int), + .phy_xgmii_txd(qsfp_6_txd_1_int), + .phy_xgmii_txc(qsfp_6_txc_1_int), + .phy_rx_clk(qsfp_6_rx_clk_1_int), + .phy_rx_rst(qsfp_6_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_6_rxd_1_int), + .phy_xgmii_rxc(qsfp_6_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_6_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_6_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_6_tx_p[1]), + .xcvr_txn(qsfp_6_tx_n[1]), + .xcvr_rxp(qsfp_6_rx_p[1]), + .xcvr_rxn(qsfp_6_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_6_tx_clk_2_int), + .phy_tx_rst(qsfp_6_tx_rst_2_int), + .phy_xgmii_txd(qsfp_6_txd_2_int), + .phy_xgmii_txc(qsfp_6_txc_2_int), + .phy_rx_clk(qsfp_6_rx_clk_2_int), + .phy_rx_rst(qsfp_6_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_6_rxd_2_int), + .phy_xgmii_rxc(qsfp_6_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_6_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_6_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_6_tx_p[2]), + .xcvr_txn(qsfp_6_tx_n[2]), + .xcvr_rxp(qsfp_6_rx_p[2]), + .xcvr_rxn(qsfp_6_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_6_tx_clk_3_int), + .phy_tx_rst(qsfp_6_tx_rst_3_int), + .phy_xgmii_txd(qsfp_6_txd_3_int), + .phy_xgmii_txc(qsfp_6_txc_3_int), + .phy_rx_clk(qsfp_6_rx_clk_3_int), + .phy_rx_rst(qsfp_6_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_6_rxd_3_int), + .phy_xgmii_rxc(qsfp_6_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_6_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_6_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_6_tx_p[3]), + .xcvr_txn(qsfp_6_tx_n[3]), + .xcvr_rxp(qsfp_6_rx_p[3]), + .xcvr_rxn(qsfp_6_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_6_tx_clk_4_int), + .phy_tx_rst(qsfp_6_tx_rst_4_int), + .phy_xgmii_txd(qsfp_6_txd_4_int), + .phy_xgmii_txc(qsfp_6_txc_4_int), + .phy_rx_clk(qsfp_6_rx_clk_4_int), + .phy_rx_rst(qsfp_6_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_6_rxd_4_int), + .phy_xgmii_rxc(qsfp_6_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_6_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 7 +assign qsfp_7_resetl = 1'b1; + +wire qsfp_7_tx_clk_1_int; +wire qsfp_7_tx_rst_1_int; +wire [63:0] qsfp_7_txd_1_int; +wire [7:0] qsfp_7_txc_1_int; +wire qsfp_7_rx_clk_1_int; +wire qsfp_7_rx_rst_1_int; +wire [63:0] qsfp_7_rxd_1_int; +wire [7:0] qsfp_7_rxc_1_int; +wire qsfp_7_tx_clk_2_int; +wire qsfp_7_tx_rst_2_int; +wire [63:0] qsfp_7_txd_2_int; +wire [7:0] qsfp_7_txc_2_int; +wire qsfp_7_rx_clk_2_int; +wire qsfp_7_rx_rst_2_int; +wire [63:0] qsfp_7_rxd_2_int; +wire [7:0] qsfp_7_rxc_2_int; +wire qsfp_7_tx_clk_3_int; +wire qsfp_7_tx_rst_3_int; +wire [63:0] qsfp_7_txd_3_int; +wire [7:0] qsfp_7_txc_3_int; +wire qsfp_7_rx_clk_3_int; +wire qsfp_7_rx_rst_3_int; +wire [63:0] qsfp_7_rxd_3_int; +wire [7:0] qsfp_7_rxc_3_int; +wire qsfp_7_tx_clk_4_int; +wire qsfp_7_tx_rst_4_int; +wire [63:0] qsfp_7_txd_4_int; +wire [7:0] qsfp_7_txc_4_int; +wire qsfp_7_rx_clk_4_int; +wire qsfp_7_rx_rst_4_int; +wire [63:0] qsfp_7_rxd_4_int; +wire [7:0] qsfp_7_rxc_4_int; + +wire qsfp_7_rx_block_lock_1; +wire qsfp_7_rx_block_lock_2; +wire qsfp_7_rx_block_lock_3; +wire qsfp_7_rx_block_lock_4; + +wire qsfp_7_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_7_mgt_refclk_inst ( + .I (qsfp_7_mgt_refclk_p), + .IB (qsfp_7_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_7_mgt_refclk), + .ODIV2 () +); + +wire qsfp_7_qpll0lock; +wire qsfp_7_qpll0outclk; +wire qsfp_7_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_7_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_7_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_7_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_7_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_7_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_7_tx_p[0]), + .xcvr_txn(qsfp_7_tx_n[0]), + .xcvr_rxp(qsfp_7_rx_p[0]), + .xcvr_rxn(qsfp_7_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_7_tx_clk_1_int), + .phy_tx_rst(qsfp_7_tx_rst_1_int), + .phy_xgmii_txd(qsfp_7_txd_1_int), + .phy_xgmii_txc(qsfp_7_txc_1_int), + .phy_rx_clk(qsfp_7_rx_clk_1_int), + .phy_rx_rst(qsfp_7_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_7_rxd_1_int), + .phy_xgmii_rxc(qsfp_7_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_7_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_7_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_7_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_7_tx_p[1]), + .xcvr_txn(qsfp_7_tx_n[1]), + .xcvr_rxp(qsfp_7_rx_p[1]), + .xcvr_rxn(qsfp_7_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_7_tx_clk_2_int), + .phy_tx_rst(qsfp_7_tx_rst_2_int), + .phy_xgmii_txd(qsfp_7_txd_2_int), + .phy_xgmii_txc(qsfp_7_txc_2_int), + .phy_rx_clk(qsfp_7_rx_clk_2_int), + .phy_rx_rst(qsfp_7_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_7_rxd_2_int), + .phy_xgmii_rxc(qsfp_7_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_7_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_7_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_7_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_7_tx_p[2]), + .xcvr_txn(qsfp_7_tx_n[2]), + .xcvr_rxp(qsfp_7_rx_p[2]), + .xcvr_rxn(qsfp_7_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_7_tx_clk_3_int), + .phy_tx_rst(qsfp_7_tx_rst_3_int), + .phy_xgmii_txd(qsfp_7_txd_3_int), + .phy_xgmii_txc(qsfp_7_txc_3_int), + .phy_rx_clk(qsfp_7_rx_clk_3_int), + .phy_rx_rst(qsfp_7_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_7_rxd_3_int), + .phy_xgmii_rxc(qsfp_7_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_7_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_7_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_7_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_7_tx_p[3]), + .xcvr_txn(qsfp_7_tx_n[3]), + .xcvr_rxp(qsfp_7_rx_p[3]), + .xcvr_rxn(qsfp_7_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_7_tx_clk_4_int), + .phy_tx_rst(qsfp_7_tx_rst_4_int), + .phy_xgmii_txd(qsfp_7_txd_4_int), + .phy_xgmii_txc(qsfp_7_txc_4_int), + .phy_rx_clk(qsfp_7_rx_clk_4_int), + .phy_rx_rst(qsfp_7_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_7_rxd_4_int), + .phy_xgmii_rxc(qsfp_7_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_7_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 8 +assign qsfp_8_resetl = 1'b1; + +wire qsfp_8_tx_clk_1_int; +wire qsfp_8_tx_rst_1_int; +wire [63:0] qsfp_8_txd_1_int; +wire [7:0] qsfp_8_txc_1_int; +wire qsfp_8_rx_clk_1_int; +wire qsfp_8_rx_rst_1_int; +wire [63:0] qsfp_8_rxd_1_int; +wire [7:0] qsfp_8_rxc_1_int; +wire qsfp_8_tx_clk_2_int; +wire qsfp_8_tx_rst_2_int; +wire [63:0] qsfp_8_txd_2_int; +wire [7:0] qsfp_8_txc_2_int; +wire qsfp_8_rx_clk_2_int; +wire qsfp_8_rx_rst_2_int; +wire [63:0] qsfp_8_rxd_2_int; +wire [7:0] qsfp_8_rxc_2_int; +wire qsfp_8_tx_clk_3_int; +wire qsfp_8_tx_rst_3_int; +wire [63:0] qsfp_8_txd_3_int; +wire [7:0] qsfp_8_txc_3_int; +wire qsfp_8_rx_clk_3_int; +wire qsfp_8_rx_rst_3_int; +wire [63:0] qsfp_8_rxd_3_int; +wire [7:0] qsfp_8_rxc_3_int; +wire qsfp_8_tx_clk_4_int; +wire qsfp_8_tx_rst_4_int; +wire [63:0] qsfp_8_txd_4_int; +wire [7:0] qsfp_8_txc_4_int; +wire qsfp_8_rx_clk_4_int; +wire qsfp_8_rx_rst_4_int; +wire [63:0] qsfp_8_rxd_4_int; +wire [7:0] qsfp_8_rxc_4_int; + +wire qsfp_8_rx_block_lock_1; +wire qsfp_8_rx_block_lock_2; +wire qsfp_8_rx_block_lock_3; +wire qsfp_8_rx_block_lock_4; + +wire qsfp_8_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_8_mgt_refclk_inst ( + .I (qsfp_8_mgt_refclk_p), + .IB (qsfp_8_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_8_mgt_refclk), + .ODIV2 () +); + +wire qsfp_8_qpll0lock; +wire qsfp_8_qpll0outclk; +wire qsfp_8_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_8_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_8_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_8_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_8_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_8_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_8_tx_p[0]), + .xcvr_txn(qsfp_8_tx_n[0]), + .xcvr_rxp(qsfp_8_rx_p[0]), + .xcvr_rxn(qsfp_8_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_8_tx_clk_1_int), + .phy_tx_rst(qsfp_8_tx_rst_1_int), + .phy_xgmii_txd(qsfp_8_txd_1_int), + .phy_xgmii_txc(qsfp_8_txc_1_int), + .phy_rx_clk(qsfp_8_rx_clk_1_int), + .phy_rx_rst(qsfp_8_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_8_rxd_1_int), + .phy_xgmii_rxc(qsfp_8_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_8_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_8_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_8_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_8_tx_p[1]), + .xcvr_txn(qsfp_8_tx_n[1]), + .xcvr_rxp(qsfp_8_rx_p[1]), + .xcvr_rxn(qsfp_8_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_8_tx_clk_2_int), + .phy_tx_rst(qsfp_8_tx_rst_2_int), + .phy_xgmii_txd(qsfp_8_txd_2_int), + .phy_xgmii_txc(qsfp_8_txc_2_int), + .phy_rx_clk(qsfp_8_rx_clk_2_int), + .phy_rx_rst(qsfp_8_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_8_rxd_2_int), + .phy_xgmii_rxc(qsfp_8_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_8_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_8_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_8_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_8_tx_p[2]), + .xcvr_txn(qsfp_8_tx_n[2]), + .xcvr_rxp(qsfp_8_rx_p[2]), + .xcvr_rxn(qsfp_8_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_8_tx_clk_3_int), + .phy_tx_rst(qsfp_8_tx_rst_3_int), + .phy_xgmii_txd(qsfp_8_txd_3_int), + .phy_xgmii_txc(qsfp_8_txc_3_int), + .phy_rx_clk(qsfp_8_rx_clk_3_int), + .phy_rx_rst(qsfp_8_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_8_rxd_3_int), + .phy_xgmii_rxc(qsfp_8_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_8_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_8_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_8_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_8_tx_p[3]), + .xcvr_txn(qsfp_8_tx_n[3]), + .xcvr_rxp(qsfp_8_rx_p[3]), + .xcvr_rxn(qsfp_8_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_8_tx_clk_4_int), + .phy_tx_rst(qsfp_8_tx_rst_4_int), + .phy_xgmii_txd(qsfp_8_txd_4_int), + .phy_xgmii_txc(qsfp_8_txc_4_int), + .phy_rx_clk(qsfp_8_rx_clk_4_int), + .phy_rx_rst(qsfp_8_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_8_rxd_4_int), + .phy_xgmii_rxc(qsfp_8_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_8_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 9 +assign qsfp_9_resetl = 1'b1; + +wire qsfp_9_tx_clk_1_int; +wire qsfp_9_tx_rst_1_int; +wire [63:0] qsfp_9_txd_1_int; +wire [7:0] qsfp_9_txc_1_int; +wire qsfp_9_rx_clk_1_int; +wire qsfp_9_rx_rst_1_int; +wire [63:0] qsfp_9_rxd_1_int; +wire [7:0] qsfp_9_rxc_1_int; +wire qsfp_9_tx_clk_2_int; +wire qsfp_9_tx_rst_2_int; +wire [63:0] qsfp_9_txd_2_int; +wire [7:0] qsfp_9_txc_2_int; +wire qsfp_9_rx_clk_2_int; +wire qsfp_9_rx_rst_2_int; +wire [63:0] qsfp_9_rxd_2_int; +wire [7:0] qsfp_9_rxc_2_int; +wire qsfp_9_tx_clk_3_int; +wire qsfp_9_tx_rst_3_int; +wire [63:0] qsfp_9_txd_3_int; +wire [7:0] qsfp_9_txc_3_int; +wire qsfp_9_rx_clk_3_int; +wire qsfp_9_rx_rst_3_int; +wire [63:0] qsfp_9_rxd_3_int; +wire [7:0] qsfp_9_rxc_3_int; +wire qsfp_9_tx_clk_4_int; +wire qsfp_9_tx_rst_4_int; +wire [63:0] qsfp_9_txd_4_int; +wire [7:0] qsfp_9_txc_4_int; +wire qsfp_9_rx_clk_4_int; +wire qsfp_9_rx_rst_4_int; +wire [63:0] qsfp_9_rxd_4_int; +wire [7:0] qsfp_9_rxc_4_int; + +wire qsfp_9_rx_block_lock_1; +wire qsfp_9_rx_block_lock_2; +wire qsfp_9_rx_block_lock_3; +wire qsfp_9_rx_block_lock_4; + +wire qsfp_9_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_9_mgt_refclk_inst ( + .I (qsfp_9_mgt_refclk_p), + .IB (qsfp_9_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_9_mgt_refclk), + .ODIV2 () +); + +wire qsfp_9_qpll0lock; +wire qsfp_9_qpll0outclk; +wire qsfp_9_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_9_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_9_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_9_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_9_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_9_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_9_tx_p[0]), + .xcvr_txn(qsfp_9_tx_n[0]), + .xcvr_rxp(qsfp_9_rx_p[0]), + .xcvr_rxn(qsfp_9_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_9_tx_clk_1_int), + .phy_tx_rst(qsfp_9_tx_rst_1_int), + .phy_xgmii_txd(qsfp_9_txd_1_int), + .phy_xgmii_txc(qsfp_9_txc_1_int), + .phy_rx_clk(qsfp_9_rx_clk_1_int), + .phy_rx_rst(qsfp_9_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_9_rxd_1_int), + .phy_xgmii_rxc(qsfp_9_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_9_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_9_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_9_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_9_tx_p[1]), + .xcvr_txn(qsfp_9_tx_n[1]), + .xcvr_rxp(qsfp_9_rx_p[1]), + .xcvr_rxn(qsfp_9_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_9_tx_clk_2_int), + .phy_tx_rst(qsfp_9_tx_rst_2_int), + .phy_xgmii_txd(qsfp_9_txd_2_int), + .phy_xgmii_txc(qsfp_9_txc_2_int), + .phy_rx_clk(qsfp_9_rx_clk_2_int), + .phy_rx_rst(qsfp_9_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_9_rxd_2_int), + .phy_xgmii_rxc(qsfp_9_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_9_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_9_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_9_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_9_tx_p[2]), + .xcvr_txn(qsfp_9_tx_n[2]), + .xcvr_rxp(qsfp_9_rx_p[2]), + .xcvr_rxn(qsfp_9_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_9_tx_clk_3_int), + .phy_tx_rst(qsfp_9_tx_rst_3_int), + .phy_xgmii_txd(qsfp_9_txd_3_int), + .phy_xgmii_txc(qsfp_9_txc_3_int), + .phy_rx_clk(qsfp_9_rx_clk_3_int), + .phy_rx_rst(qsfp_9_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_9_rxd_3_int), + .phy_xgmii_rxc(qsfp_9_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_9_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_9_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_9_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_9_tx_p[3]), + .xcvr_txn(qsfp_9_tx_n[3]), + .xcvr_rxp(qsfp_9_rx_p[3]), + .xcvr_rxn(qsfp_9_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_9_tx_clk_4_int), + .phy_tx_rst(qsfp_9_tx_rst_4_int), + .phy_xgmii_txd(qsfp_9_txd_4_int), + .phy_xgmii_txc(qsfp_9_txc_4_int), + .phy_rx_clk(qsfp_9_rx_clk_4_int), + .phy_rx_rst(qsfp_9_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_9_rxd_4_int), + .phy_xgmii_rxc(qsfp_9_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_9_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 1 +assign fmc_qsfp_1_modsell = 1'b1; +assign fmc_qsfp_1_resetl = 1'b1; +assign fmc_qsfp_1_lpmode = 1'b0; + +wire fmc_qsfp_1_tx_clk_1_int; +wire fmc_qsfp_1_tx_rst_1_int; +wire [63:0] fmc_qsfp_1_txd_1_int; +wire [7:0] fmc_qsfp_1_txc_1_int; +wire fmc_qsfp_1_rx_clk_1_int; +wire fmc_qsfp_1_rx_rst_1_int; +wire [63:0] fmc_qsfp_1_rxd_1_int; +wire [7:0] fmc_qsfp_1_rxc_1_int; +wire fmc_qsfp_1_tx_clk_2_int; +wire fmc_qsfp_1_tx_rst_2_int; +wire [63:0] fmc_qsfp_1_txd_2_int; +wire [7:0] fmc_qsfp_1_txc_2_int; +wire fmc_qsfp_1_rx_clk_2_int; +wire fmc_qsfp_1_rx_rst_2_int; +wire [63:0] fmc_qsfp_1_rxd_2_int; +wire [7:0] fmc_qsfp_1_rxc_2_int; +wire fmc_qsfp_1_tx_clk_3_int; +wire fmc_qsfp_1_tx_rst_3_int; +wire [63:0] fmc_qsfp_1_txd_3_int; +wire [7:0] fmc_qsfp_1_txc_3_int; +wire fmc_qsfp_1_rx_clk_3_int; +wire fmc_qsfp_1_rx_rst_3_int; +wire [63:0] fmc_qsfp_1_rxd_3_int; +wire [7:0] fmc_qsfp_1_rxc_3_int; +wire fmc_qsfp_1_tx_clk_4_int; +wire fmc_qsfp_1_tx_rst_4_int; +wire [63:0] fmc_qsfp_1_txd_4_int; +wire [7:0] fmc_qsfp_1_txc_4_int; +wire fmc_qsfp_1_rx_clk_4_int; +wire fmc_qsfp_1_rx_rst_4_int; +wire [63:0] fmc_qsfp_1_rxd_4_int; +wire [7:0] fmc_qsfp_1_rxc_4_int; + +wire fmc_qsfp_1_rx_block_lock_1; +wire fmc_qsfp_1_rx_block_lock_2; +wire fmc_qsfp_1_rx_block_lock_3; +wire fmc_qsfp_1_rx_block_lock_4; + +wire fmc_qsfp_1_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_1_mgt_refclk_inst ( + .I (fmc_qsfp_1_mgt_refclk_p), + .IB (fmc_qsfp_1_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_1_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_1_qpll0lock; +wire fmc_qsfp_1_qpll0outclk; +wire fmc_qsfp_1_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_1_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_1_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_1_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_1_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_1_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_1_tx_p[0]), + .xcvr_txn(fmc_qsfp_1_tx_n[0]), + .xcvr_rxp(fmc_qsfp_1_rx_p[0]), + .xcvr_rxn(fmc_qsfp_1_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_1_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_1_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_1_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_1_txc_1_int), + .phy_rx_clk(fmc_qsfp_1_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_1_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_1_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_1_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_1_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_1_tx_p[1]), + .xcvr_txn(fmc_qsfp_1_tx_n[1]), + .xcvr_rxp(fmc_qsfp_1_rx_p[1]), + .xcvr_rxn(fmc_qsfp_1_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_1_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_1_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_1_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_1_txc_2_int), + .phy_rx_clk(fmc_qsfp_1_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_1_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_1_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_1_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_1_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_1_tx_p[2]), + .xcvr_txn(fmc_qsfp_1_tx_n[2]), + .xcvr_rxp(fmc_qsfp_1_rx_p[2]), + .xcvr_rxn(fmc_qsfp_1_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_1_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_1_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_1_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_1_txc_3_int), + .phy_rx_clk(fmc_qsfp_1_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_1_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_1_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_1_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_1_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_1_tx_p[3]), + .xcvr_txn(fmc_qsfp_1_tx_n[3]), + .xcvr_rxp(fmc_qsfp_1_rx_p[3]), + .xcvr_rxn(fmc_qsfp_1_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_1_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_1_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_1_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_1_txc_4_int), + .phy_rx_clk(fmc_qsfp_1_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_1_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_1_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_1_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 2 +assign fmc_qsfp_2_modsell = 1'b1; +assign fmc_qsfp_2_resetl = 1'b1; +assign fmc_qsfp_2_lpmode = 1'b0; + +wire fmc_qsfp_2_tx_clk_1_int; +wire fmc_qsfp_2_tx_rst_1_int; +wire [63:0] fmc_qsfp_2_txd_1_int; +wire [7:0] fmc_qsfp_2_txc_1_int; +wire fmc_qsfp_2_rx_clk_1_int; +wire fmc_qsfp_2_rx_rst_1_int; +wire [63:0] fmc_qsfp_2_rxd_1_int; +wire [7:0] fmc_qsfp_2_rxc_1_int; +wire fmc_qsfp_2_tx_clk_2_int; +wire fmc_qsfp_2_tx_rst_2_int; +wire [63:0] fmc_qsfp_2_txd_2_int; +wire [7:0] fmc_qsfp_2_txc_2_int; +wire fmc_qsfp_2_rx_clk_2_int; +wire fmc_qsfp_2_rx_rst_2_int; +wire [63:0] fmc_qsfp_2_rxd_2_int; +wire [7:0] fmc_qsfp_2_rxc_2_int; +wire fmc_qsfp_2_tx_clk_3_int; +wire fmc_qsfp_2_tx_rst_3_int; +wire [63:0] fmc_qsfp_2_txd_3_int; +wire [7:0] fmc_qsfp_2_txc_3_int; +wire fmc_qsfp_2_rx_clk_3_int; +wire fmc_qsfp_2_rx_rst_3_int; +wire [63:0] fmc_qsfp_2_rxd_3_int; +wire [7:0] fmc_qsfp_2_rxc_3_int; +wire fmc_qsfp_2_tx_clk_4_int; +wire fmc_qsfp_2_tx_rst_4_int; +wire [63:0] fmc_qsfp_2_txd_4_int; +wire [7:0] fmc_qsfp_2_txc_4_int; +wire fmc_qsfp_2_rx_clk_4_int; +wire fmc_qsfp_2_rx_rst_4_int; +wire [63:0] fmc_qsfp_2_rxd_4_int; +wire [7:0] fmc_qsfp_2_rxc_4_int; + +wire fmc_qsfp_2_rx_block_lock_1; +wire fmc_qsfp_2_rx_block_lock_2; +wire fmc_qsfp_2_rx_block_lock_3; +wire fmc_qsfp_2_rx_block_lock_4; + +wire fmc_qsfp_2_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_2_mgt_refclk_inst ( + .I (fmc_qsfp_2_mgt_refclk_p), + .IB (fmc_qsfp_2_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_2_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_2_qpll0lock; +wire fmc_qsfp_2_qpll0outclk; +wire fmc_qsfp_2_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_2_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_2_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_2_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_2_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_2_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_2_tx_p[0]), + .xcvr_txn(fmc_qsfp_2_tx_n[0]), + .xcvr_rxp(fmc_qsfp_2_rx_p[0]), + .xcvr_rxn(fmc_qsfp_2_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_2_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_2_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_2_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_2_txc_1_int), + .phy_rx_clk(fmc_qsfp_2_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_2_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_2_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_2_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_2_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_2_tx_p[1]), + .xcvr_txn(fmc_qsfp_2_tx_n[1]), + .xcvr_rxp(fmc_qsfp_2_rx_p[1]), + .xcvr_rxn(fmc_qsfp_2_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_2_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_2_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_2_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_2_txc_2_int), + .phy_rx_clk(fmc_qsfp_2_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_2_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_2_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_2_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_2_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_2_tx_p[2]), + .xcvr_txn(fmc_qsfp_2_tx_n[2]), + .xcvr_rxp(fmc_qsfp_2_rx_p[2]), + .xcvr_rxn(fmc_qsfp_2_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_2_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_2_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_2_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_2_txc_3_int), + .phy_rx_clk(fmc_qsfp_2_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_2_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_2_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_2_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_2_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_2_tx_p[3]), + .xcvr_txn(fmc_qsfp_2_tx_n[3]), + .xcvr_rxp(fmc_qsfp_2_rx_p[3]), + .xcvr_rxn(fmc_qsfp_2_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_2_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_2_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_2_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_2_txc_4_int), + .phy_rx_clk(fmc_qsfp_2_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_2_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_2_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_2_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 3 +assign fmc_qsfp_3_modsell = 1'b1; +assign fmc_qsfp_3_resetl = 1'b1; +assign fmc_qsfp_3_lpmode = 1'b0; + +wire fmc_qsfp_3_tx_clk_1_int; +wire fmc_qsfp_3_tx_rst_1_int; +wire [63:0] fmc_qsfp_3_txd_1_int; +wire [7:0] fmc_qsfp_3_txc_1_int; +wire fmc_qsfp_3_rx_clk_1_int; +wire fmc_qsfp_3_rx_rst_1_int; +wire [63:0] fmc_qsfp_3_rxd_1_int; +wire [7:0] fmc_qsfp_3_rxc_1_int; +wire fmc_qsfp_3_tx_clk_2_int; +wire fmc_qsfp_3_tx_rst_2_int; +wire [63:0] fmc_qsfp_3_txd_2_int; +wire [7:0] fmc_qsfp_3_txc_2_int; +wire fmc_qsfp_3_rx_clk_2_int; +wire fmc_qsfp_3_rx_rst_2_int; +wire [63:0] fmc_qsfp_3_rxd_2_int; +wire [7:0] fmc_qsfp_3_rxc_2_int; +wire fmc_qsfp_3_tx_clk_3_int; +wire fmc_qsfp_3_tx_rst_3_int; +wire [63:0] fmc_qsfp_3_txd_3_int; +wire [7:0] fmc_qsfp_3_txc_3_int; +wire fmc_qsfp_3_rx_clk_3_int; +wire fmc_qsfp_3_rx_rst_3_int; +wire [63:0] fmc_qsfp_3_rxd_3_int; +wire [7:0] fmc_qsfp_3_rxc_3_int; +wire fmc_qsfp_3_tx_clk_4_int; +wire fmc_qsfp_3_tx_rst_4_int; +wire [63:0] fmc_qsfp_3_txd_4_int; +wire [7:0] fmc_qsfp_3_txc_4_int; +wire fmc_qsfp_3_rx_clk_4_int; +wire fmc_qsfp_3_rx_rst_4_int; +wire [63:0] fmc_qsfp_3_rxd_4_int; +wire [7:0] fmc_qsfp_3_rxc_4_int; + +wire fmc_qsfp_3_rx_block_lock_1; +wire fmc_qsfp_3_rx_block_lock_2; +wire fmc_qsfp_3_rx_block_lock_3; +wire fmc_qsfp_3_rx_block_lock_4; + +wire fmc_qsfp_3_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_3_mgt_refclk_inst ( + .I (fmc_qsfp_3_mgt_refclk_p), + .IB (fmc_qsfp_3_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_3_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_3_qpll0lock; +wire fmc_qsfp_3_qpll0outclk; +wire fmc_qsfp_3_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_3_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_3_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_3_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_3_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_3_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_3_tx_p[0]), + .xcvr_txn(fmc_qsfp_3_tx_n[0]), + .xcvr_rxp(fmc_qsfp_3_rx_p[0]), + .xcvr_rxn(fmc_qsfp_3_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_3_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_3_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_3_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_3_txc_1_int), + .phy_rx_clk(fmc_qsfp_3_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_3_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_3_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_3_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_3_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_3_tx_p[1]), + .xcvr_txn(fmc_qsfp_3_tx_n[1]), + .xcvr_rxp(fmc_qsfp_3_rx_p[1]), + .xcvr_rxn(fmc_qsfp_3_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_3_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_3_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_3_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_3_txc_2_int), + .phy_rx_clk(fmc_qsfp_3_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_3_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_3_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_3_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_3_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_3_tx_p[2]), + .xcvr_txn(fmc_qsfp_3_tx_n[2]), + .xcvr_rxp(fmc_qsfp_3_rx_p[2]), + .xcvr_rxn(fmc_qsfp_3_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_3_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_3_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_3_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_3_txc_3_int), + .phy_rx_clk(fmc_qsfp_3_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_3_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_3_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_3_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_3_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_3_tx_p[3]), + .xcvr_txn(fmc_qsfp_3_tx_n[3]), + .xcvr_rxp(fmc_qsfp_3_rx_p[3]), + .xcvr_rxn(fmc_qsfp_3_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_3_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_3_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_3_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_3_txc_4_int), + .phy_rx_clk(fmc_qsfp_3_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_3_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_3_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_3_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 4 +assign fmc_qsfp_4_modsell = 1'b1; +assign fmc_qsfp_4_resetl = 1'b1; +assign fmc_qsfp_4_lpmode = 1'b0; + +wire fmc_qsfp_4_tx_clk_1_int; +wire fmc_qsfp_4_tx_rst_1_int; +wire [63:0] fmc_qsfp_4_txd_1_int; +wire [7:0] fmc_qsfp_4_txc_1_int; +wire fmc_qsfp_4_rx_clk_1_int; +wire fmc_qsfp_4_rx_rst_1_int; +wire [63:0] fmc_qsfp_4_rxd_1_int; +wire [7:0] fmc_qsfp_4_rxc_1_int; +wire fmc_qsfp_4_tx_clk_2_int; +wire fmc_qsfp_4_tx_rst_2_int; +wire [63:0] fmc_qsfp_4_txd_2_int; +wire [7:0] fmc_qsfp_4_txc_2_int; +wire fmc_qsfp_4_rx_clk_2_int; +wire fmc_qsfp_4_rx_rst_2_int; +wire [63:0] fmc_qsfp_4_rxd_2_int; +wire [7:0] fmc_qsfp_4_rxc_2_int; +wire fmc_qsfp_4_tx_clk_3_int; +wire fmc_qsfp_4_tx_rst_3_int; +wire [63:0] fmc_qsfp_4_txd_3_int; +wire [7:0] fmc_qsfp_4_txc_3_int; +wire fmc_qsfp_4_rx_clk_3_int; +wire fmc_qsfp_4_rx_rst_3_int; +wire [63:0] fmc_qsfp_4_rxd_3_int; +wire [7:0] fmc_qsfp_4_rxc_3_int; +wire fmc_qsfp_4_tx_clk_4_int; +wire fmc_qsfp_4_tx_rst_4_int; +wire [63:0] fmc_qsfp_4_txd_4_int; +wire [7:0] fmc_qsfp_4_txc_4_int; +wire fmc_qsfp_4_rx_clk_4_int; +wire fmc_qsfp_4_rx_rst_4_int; +wire [63:0] fmc_qsfp_4_rxd_4_int; +wire [7:0] fmc_qsfp_4_rxc_4_int; + +wire fmc_qsfp_4_rx_block_lock_1; +wire fmc_qsfp_4_rx_block_lock_2; +wire fmc_qsfp_4_rx_block_lock_3; +wire fmc_qsfp_4_rx_block_lock_4; + +wire fmc_qsfp_4_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_4_mgt_refclk_inst ( + .I (fmc_qsfp_4_mgt_refclk_p), + .IB (fmc_qsfp_4_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_4_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_4_qpll0lock; +wire fmc_qsfp_4_qpll0outclk; +wire fmc_qsfp_4_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_4_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_4_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_4_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_4_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_4_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_4_tx_p[0]), + .xcvr_txn(fmc_qsfp_4_tx_n[0]), + .xcvr_rxp(fmc_qsfp_4_rx_p[0]), + .xcvr_rxn(fmc_qsfp_4_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_4_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_4_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_4_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_4_txc_1_int), + .phy_rx_clk(fmc_qsfp_4_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_4_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_4_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_4_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_4_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_4_tx_p[1]), + .xcvr_txn(fmc_qsfp_4_tx_n[1]), + .xcvr_rxp(fmc_qsfp_4_rx_p[1]), + .xcvr_rxn(fmc_qsfp_4_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_4_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_4_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_4_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_4_txc_2_int), + .phy_rx_clk(fmc_qsfp_4_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_4_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_4_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_4_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_4_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_4_tx_p[2]), + .xcvr_txn(fmc_qsfp_4_tx_n[2]), + .xcvr_rxp(fmc_qsfp_4_rx_p[2]), + .xcvr_rxn(fmc_qsfp_4_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_4_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_4_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_4_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_4_txc_3_int), + .phy_rx_clk(fmc_qsfp_4_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_4_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_4_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_4_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_4_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_4_tx_p[3]), + .xcvr_txn(fmc_qsfp_4_tx_n[3]), + .xcvr_rxp(fmc_qsfp_4_rx_p[3]), + .xcvr_rxn(fmc_qsfp_4_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_4_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_4_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_4_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_4_txc_4_int), + .phy_rx_clk(fmc_qsfp_4_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_4_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_4_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_4_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 5 +assign fmc_qsfp_5_modsell = 1'b1; +assign fmc_qsfp_5_resetl = 1'b1; +assign fmc_qsfp_5_lpmode = 1'b0; + +wire fmc_qsfp_5_tx_clk_1_int; +wire fmc_qsfp_5_tx_rst_1_int; +wire [63:0] fmc_qsfp_5_txd_1_int; +wire [7:0] fmc_qsfp_5_txc_1_int; +wire fmc_qsfp_5_rx_clk_1_int; +wire fmc_qsfp_5_rx_rst_1_int; +wire [63:0] fmc_qsfp_5_rxd_1_int; +wire [7:0] fmc_qsfp_5_rxc_1_int; +wire fmc_qsfp_5_tx_clk_2_int; +wire fmc_qsfp_5_tx_rst_2_int; +wire [63:0] fmc_qsfp_5_txd_2_int; +wire [7:0] fmc_qsfp_5_txc_2_int; +wire fmc_qsfp_5_rx_clk_2_int; +wire fmc_qsfp_5_rx_rst_2_int; +wire [63:0] fmc_qsfp_5_rxd_2_int; +wire [7:0] fmc_qsfp_5_rxc_2_int; +wire fmc_qsfp_5_tx_clk_3_int; +wire fmc_qsfp_5_tx_rst_3_int; +wire [63:0] fmc_qsfp_5_txd_3_int; +wire [7:0] fmc_qsfp_5_txc_3_int; +wire fmc_qsfp_5_rx_clk_3_int; +wire fmc_qsfp_5_rx_rst_3_int; +wire [63:0] fmc_qsfp_5_rxd_3_int; +wire [7:0] fmc_qsfp_5_rxc_3_int; +wire fmc_qsfp_5_tx_clk_4_int; +wire fmc_qsfp_5_tx_rst_4_int; +wire [63:0] fmc_qsfp_5_txd_4_int; +wire [7:0] fmc_qsfp_5_txc_4_int; +wire fmc_qsfp_5_rx_clk_4_int; +wire fmc_qsfp_5_rx_rst_4_int; +wire [63:0] fmc_qsfp_5_rxd_4_int; +wire [7:0] fmc_qsfp_5_rxc_4_int; + +wire fmc_qsfp_5_rx_block_lock_1; +wire fmc_qsfp_5_rx_block_lock_2; +wire fmc_qsfp_5_rx_block_lock_3; +wire fmc_qsfp_5_rx_block_lock_4; + +wire fmc_qsfp_5_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_5_mgt_refclk_inst ( + .I (fmc_qsfp_5_mgt_refclk_p), + .IB (fmc_qsfp_5_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_5_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_5_qpll0lock; +wire fmc_qsfp_5_qpll0outclk; +wire fmc_qsfp_5_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_5_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_5_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_5_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_5_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_5_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_5_tx_p[0]), + .xcvr_txn(fmc_qsfp_5_tx_n[0]), + .xcvr_rxp(fmc_qsfp_5_rx_p[0]), + .xcvr_rxn(fmc_qsfp_5_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_5_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_5_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_5_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_5_txc_1_int), + .phy_rx_clk(fmc_qsfp_5_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_5_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_5_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_5_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_5_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_5_tx_p[1]), + .xcvr_txn(fmc_qsfp_5_tx_n[1]), + .xcvr_rxp(fmc_qsfp_5_rx_p[1]), + .xcvr_rxn(fmc_qsfp_5_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_5_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_5_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_5_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_5_txc_2_int), + .phy_rx_clk(fmc_qsfp_5_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_5_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_5_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_5_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_5_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_5_tx_p[2]), + .xcvr_txn(fmc_qsfp_5_tx_n[2]), + .xcvr_rxp(fmc_qsfp_5_rx_p[2]), + .xcvr_rxn(fmc_qsfp_5_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_5_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_5_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_5_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_5_txc_3_int), + .phy_rx_clk(fmc_qsfp_5_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_5_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_5_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_5_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_5_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_5_tx_p[3]), + .xcvr_txn(fmc_qsfp_5_tx_n[3]), + .xcvr_rxp(fmc_qsfp_5_rx_p[3]), + .xcvr_rxn(fmc_qsfp_5_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_5_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_5_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_5_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_5_txc_4_int), + .phy_rx_clk(fmc_qsfp_5_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_5_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_5_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_5_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 6 +assign fmc_qsfp_6_modsell = 1'b1; +assign fmc_qsfp_6_resetl = 1'b1; +assign fmc_qsfp_6_lpmode = 1'b0; + +wire fmc_qsfp_6_tx_clk_1_int; +wire fmc_qsfp_6_tx_rst_1_int; +wire [63:0] fmc_qsfp_6_txd_1_int; +wire [7:0] fmc_qsfp_6_txc_1_int; +wire fmc_qsfp_6_rx_clk_1_int; +wire fmc_qsfp_6_rx_rst_1_int; +wire [63:0] fmc_qsfp_6_rxd_1_int; +wire [7:0] fmc_qsfp_6_rxc_1_int; +wire fmc_qsfp_6_tx_clk_2_int; +wire fmc_qsfp_6_tx_rst_2_int; +wire [63:0] fmc_qsfp_6_txd_2_int; +wire [7:0] fmc_qsfp_6_txc_2_int; +wire fmc_qsfp_6_rx_clk_2_int; +wire fmc_qsfp_6_rx_rst_2_int; +wire [63:0] fmc_qsfp_6_rxd_2_int; +wire [7:0] fmc_qsfp_6_rxc_2_int; +wire fmc_qsfp_6_tx_clk_3_int; +wire fmc_qsfp_6_tx_rst_3_int; +wire [63:0] fmc_qsfp_6_txd_3_int; +wire [7:0] fmc_qsfp_6_txc_3_int; +wire fmc_qsfp_6_rx_clk_3_int; +wire fmc_qsfp_6_rx_rst_3_int; +wire [63:0] fmc_qsfp_6_rxd_3_int; +wire [7:0] fmc_qsfp_6_rxc_3_int; +wire fmc_qsfp_6_tx_clk_4_int; +wire fmc_qsfp_6_tx_rst_4_int; +wire [63:0] fmc_qsfp_6_txd_4_int; +wire [7:0] fmc_qsfp_6_txc_4_int; +wire fmc_qsfp_6_rx_clk_4_int; +wire fmc_qsfp_6_rx_rst_4_int; +wire [63:0] fmc_qsfp_6_rxd_4_int; +wire [7:0] fmc_qsfp_6_rxc_4_int; + +wire fmc_qsfp_6_rx_block_lock_1; +wire fmc_qsfp_6_rx_block_lock_2; +wire fmc_qsfp_6_rx_block_lock_3; +wire fmc_qsfp_6_rx_block_lock_4; + +wire fmc_qsfp_6_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_6_mgt_refclk_inst ( + .I (fmc_qsfp_6_mgt_refclk_p), + .IB (fmc_qsfp_6_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_6_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_6_qpll0lock; +wire fmc_qsfp_6_qpll0outclk; +wire fmc_qsfp_6_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_6_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_6_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_6_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_6_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_6_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_6_tx_p[0]), + .xcvr_txn(fmc_qsfp_6_tx_n[0]), + .xcvr_rxp(fmc_qsfp_6_rx_p[0]), + .xcvr_rxn(fmc_qsfp_6_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_6_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_6_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_6_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_6_txc_1_int), + .phy_rx_clk(fmc_qsfp_6_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_6_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_6_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_6_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_6_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_6_tx_p[1]), + .xcvr_txn(fmc_qsfp_6_tx_n[1]), + .xcvr_rxp(fmc_qsfp_6_rx_p[1]), + .xcvr_rxn(fmc_qsfp_6_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_6_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_6_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_6_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_6_txc_2_int), + .phy_rx_clk(fmc_qsfp_6_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_6_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_6_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_6_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_6_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_6_tx_p[2]), + .xcvr_txn(fmc_qsfp_6_tx_n[2]), + .xcvr_rxp(fmc_qsfp_6_rx_p[2]), + .xcvr_rxn(fmc_qsfp_6_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_6_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_6_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_6_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_6_txc_3_int), + .phy_rx_clk(fmc_qsfp_6_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_6_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_6_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_6_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_6_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_6_tx_p[3]), + .xcvr_txn(fmc_qsfp_6_tx_n[3]), + .xcvr_rxp(fmc_qsfp_6_rx_p[3]), + .xcvr_rxn(fmc_qsfp_6_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_6_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_6_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_6_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_6_txc_4_int), + .phy_rx_clk(fmc_qsfp_6_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_6_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_6_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_6_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +fpga_core +core_inst ( + /* + * Clock: 156MHz + * Synchronous reset + */ + .clk(clk_156mhz_int), + .rst(rst_156mhz_int), + /* + * GPIO + */ + .btn(btn_int), + .sw(sw_int), + .led(led), + /* + * UART: 115200 bps, 8N1 + */ + .uart_rxd(uart_rxd), + .uart_txd(uart_txd_int), + .uart_rts(uart_rts_int), + .uart_cts(uart_cts), + .uart_rst_n(uart_rst_n), + .uart_suspend_n(uart_suspend_n), + /* + * Ethernet: QSFP28 + */ + .qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int), + .qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int), + .qsfp_1_txd_1(qsfp_1_txd_1_int), + .qsfp_1_txc_1(qsfp_1_txc_1_int), + .qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int), + .qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int), + .qsfp_1_rxd_1(qsfp_1_rxd_1_int), + .qsfp_1_rxc_1(qsfp_1_rxc_1_int), + .qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int), + .qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int), + .qsfp_1_txd_2(qsfp_1_txd_2_int), + .qsfp_1_txc_2(qsfp_1_txc_2_int), + .qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int), + .qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int), + .qsfp_1_rxd_2(qsfp_1_rxd_2_int), + .qsfp_1_rxc_2(qsfp_1_rxc_2_int), + .qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int), + .qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int), + .qsfp_1_txd_3(qsfp_1_txd_3_int), + .qsfp_1_txc_3(qsfp_1_txc_3_int), + .qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int), + .qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int), + .qsfp_1_rxd_3(qsfp_1_rxd_3_int), + .qsfp_1_rxc_3(qsfp_1_rxc_3_int), + .qsfp_1_tx_clk_4(qsfp_1_tx_clk_4_int), + .qsfp_1_tx_rst_4(qsfp_1_tx_rst_4_int), + .qsfp_1_txd_4(qsfp_1_txd_4_int), + .qsfp_1_txc_4(qsfp_1_txc_4_int), + .qsfp_1_rx_clk_4(qsfp_1_rx_clk_4_int), + .qsfp_1_rx_rst_4(qsfp_1_rx_rst_4_int), + .qsfp_1_rxd_4(qsfp_1_rxd_4_int), + .qsfp_1_rxc_4(qsfp_1_rxc_4_int), + .qsfp_2_tx_clk_1(qsfp_2_tx_clk_1_int), + .qsfp_2_tx_rst_1(qsfp_2_tx_rst_1_int), + .qsfp_2_txd_1(qsfp_2_txd_1_int), + .qsfp_2_txc_1(qsfp_2_txc_1_int), + .qsfp_2_rx_clk_1(qsfp_2_rx_clk_1_int), + .qsfp_2_rx_rst_1(qsfp_2_rx_rst_1_int), + .qsfp_2_rxd_1(qsfp_2_rxd_1_int), + .qsfp_2_rxc_1(qsfp_2_rxc_1_int), + .qsfp_2_tx_clk_2(qsfp_2_tx_clk_2_int), + .qsfp_2_tx_rst_2(qsfp_2_tx_rst_2_int), + .qsfp_2_txd_2(qsfp_2_txd_2_int), + .qsfp_2_txc_2(qsfp_2_txc_2_int), + .qsfp_2_rx_clk_2(qsfp_2_rx_clk_2_int), + .qsfp_2_rx_rst_2(qsfp_2_rx_rst_2_int), + .qsfp_2_rxd_2(qsfp_2_rxd_2_int), + .qsfp_2_rxc_2(qsfp_2_rxc_2_int), + .qsfp_2_tx_clk_3(qsfp_2_tx_clk_3_int), + .qsfp_2_tx_rst_3(qsfp_2_tx_rst_3_int), + .qsfp_2_txd_3(qsfp_2_txd_3_int), + .qsfp_2_txc_3(qsfp_2_txc_3_int), + .qsfp_2_rx_clk_3(qsfp_2_rx_clk_3_int), + .qsfp_2_rx_rst_3(qsfp_2_rx_rst_3_int), + .qsfp_2_rxd_3(qsfp_2_rxd_3_int), + .qsfp_2_rxc_3(qsfp_2_rxc_3_int), + .qsfp_2_tx_clk_4(qsfp_2_tx_clk_4_int), + .qsfp_2_tx_rst_4(qsfp_2_tx_rst_4_int), + .qsfp_2_txd_4(qsfp_2_txd_4_int), + .qsfp_2_txc_4(qsfp_2_txc_4_int), + .qsfp_2_rx_clk_4(qsfp_2_rx_clk_4_int), + .qsfp_2_rx_rst_4(qsfp_2_rx_rst_4_int), + .qsfp_2_rxd_4(qsfp_2_rxd_4_int), + .qsfp_2_rxc_4(qsfp_2_rxc_4_int), + .qsfp_3_tx_clk_1(qsfp_3_tx_clk_1_int), + .qsfp_3_tx_rst_1(qsfp_3_tx_rst_1_int), + .qsfp_3_txd_1(qsfp_3_txd_1_int), + .qsfp_3_txc_1(qsfp_3_txc_1_int), + .qsfp_3_rx_clk_1(qsfp_3_rx_clk_1_int), + .qsfp_3_rx_rst_1(qsfp_3_rx_rst_1_int), + .qsfp_3_rxd_1(qsfp_3_rxd_1_int), + .qsfp_3_rxc_1(qsfp_3_rxc_1_int), + .qsfp_3_tx_clk_2(qsfp_3_tx_clk_2_int), + .qsfp_3_tx_rst_2(qsfp_3_tx_rst_2_int), + .qsfp_3_txd_2(qsfp_3_txd_2_int), + .qsfp_3_txc_2(qsfp_3_txc_2_int), + .qsfp_3_rx_clk_2(qsfp_3_rx_clk_2_int), + .qsfp_3_rx_rst_2(qsfp_3_rx_rst_2_int), + .qsfp_3_rxd_2(qsfp_3_rxd_2_int), + .qsfp_3_rxc_2(qsfp_3_rxc_2_int), + .qsfp_3_tx_clk_3(qsfp_3_tx_clk_3_int), + .qsfp_3_tx_rst_3(qsfp_3_tx_rst_3_int), + .qsfp_3_txd_3(qsfp_3_txd_3_int), + .qsfp_3_txc_3(qsfp_3_txc_3_int), + .qsfp_3_rx_clk_3(qsfp_3_rx_clk_3_int), + .qsfp_3_rx_rst_3(qsfp_3_rx_rst_3_int), + .qsfp_3_rxd_3(qsfp_3_rxd_3_int), + .qsfp_3_rxc_3(qsfp_3_rxc_3_int), + .qsfp_3_tx_clk_4(qsfp_3_tx_clk_4_int), + .qsfp_3_tx_rst_4(qsfp_3_tx_rst_4_int), + .qsfp_3_txd_4(qsfp_3_txd_4_int), + .qsfp_3_txc_4(qsfp_3_txc_4_int), + .qsfp_3_rx_clk_4(qsfp_3_rx_clk_4_int), + .qsfp_3_rx_rst_4(qsfp_3_rx_rst_4_int), + .qsfp_3_rxd_4(qsfp_3_rxd_4_int), + .qsfp_3_rxc_4(qsfp_3_rxc_4_int), + .qsfp_4_tx_clk_1(qsfp_4_tx_clk_1_int), + .qsfp_4_tx_rst_1(qsfp_4_tx_rst_1_int), + .qsfp_4_txd_1(qsfp_4_txd_1_int), + .qsfp_4_txc_1(qsfp_4_txc_1_int), + .qsfp_4_rx_clk_1(qsfp_4_rx_clk_1_int), + .qsfp_4_rx_rst_1(qsfp_4_rx_rst_1_int), + .qsfp_4_rxd_1(qsfp_4_rxd_1_int), + .qsfp_4_rxc_1(qsfp_4_rxc_1_int), + .qsfp_4_tx_clk_2(qsfp_4_tx_clk_2_int), + .qsfp_4_tx_rst_2(qsfp_4_tx_rst_2_int), + .qsfp_4_txd_2(qsfp_4_txd_2_int), + .qsfp_4_txc_2(qsfp_4_txc_2_int), + .qsfp_4_rx_clk_2(qsfp_4_rx_clk_2_int), + .qsfp_4_rx_rst_2(qsfp_4_rx_rst_2_int), + .qsfp_4_rxd_2(qsfp_4_rxd_2_int), + .qsfp_4_rxc_2(qsfp_4_rxc_2_int), + .qsfp_4_tx_clk_3(qsfp_4_tx_clk_3_int), + .qsfp_4_tx_rst_3(qsfp_4_tx_rst_3_int), + .qsfp_4_txd_3(qsfp_4_txd_3_int), + .qsfp_4_txc_3(qsfp_4_txc_3_int), + .qsfp_4_rx_clk_3(qsfp_4_rx_clk_3_int), + .qsfp_4_rx_rst_3(qsfp_4_rx_rst_3_int), + .qsfp_4_rxd_3(qsfp_4_rxd_3_int), + .qsfp_4_rxc_3(qsfp_4_rxc_3_int), + .qsfp_4_tx_clk_4(qsfp_4_tx_clk_4_int), + .qsfp_4_tx_rst_4(qsfp_4_tx_rst_4_int), + .qsfp_4_txd_4(qsfp_4_txd_4_int), + .qsfp_4_txc_4(qsfp_4_txc_4_int), + .qsfp_4_rx_clk_4(qsfp_4_rx_clk_4_int), + .qsfp_4_rx_rst_4(qsfp_4_rx_rst_4_int), + .qsfp_4_rxd_4(qsfp_4_rxd_4_int), + .qsfp_4_rxc_4(qsfp_4_rxc_4_int), + .qsfp_5_tx_clk_1(qsfp_5_tx_clk_1_int), + .qsfp_5_tx_rst_1(qsfp_5_tx_rst_1_int), + .qsfp_5_txd_1(qsfp_5_txd_1_int), + .qsfp_5_txc_1(qsfp_5_txc_1_int), + .qsfp_5_rx_clk_1(qsfp_5_rx_clk_1_int), + .qsfp_5_rx_rst_1(qsfp_5_rx_rst_1_int), + .qsfp_5_rxd_1(qsfp_5_rxd_1_int), + .qsfp_5_rxc_1(qsfp_5_rxc_1_int), + .qsfp_5_tx_clk_2(qsfp_5_tx_clk_2_int), + .qsfp_5_tx_rst_2(qsfp_5_tx_rst_2_int), + .qsfp_5_txd_2(qsfp_5_txd_2_int), + .qsfp_5_txc_2(qsfp_5_txc_2_int), + .qsfp_5_rx_clk_2(qsfp_5_rx_clk_2_int), + .qsfp_5_rx_rst_2(qsfp_5_rx_rst_2_int), + .qsfp_5_rxd_2(qsfp_5_rxd_2_int), + .qsfp_5_rxc_2(qsfp_5_rxc_2_int), + .qsfp_5_tx_clk_3(qsfp_5_tx_clk_3_int), + .qsfp_5_tx_rst_3(qsfp_5_tx_rst_3_int), + .qsfp_5_txd_3(qsfp_5_txd_3_int), + .qsfp_5_txc_3(qsfp_5_txc_3_int), + .qsfp_5_rx_clk_3(qsfp_5_rx_clk_3_int), + .qsfp_5_rx_rst_3(qsfp_5_rx_rst_3_int), + .qsfp_5_rxd_3(qsfp_5_rxd_3_int), + .qsfp_5_rxc_3(qsfp_5_rxc_3_int), + .qsfp_5_tx_clk_4(qsfp_5_tx_clk_4_int), + .qsfp_5_tx_rst_4(qsfp_5_tx_rst_4_int), + .qsfp_5_txd_4(qsfp_5_txd_4_int), + .qsfp_5_txc_4(qsfp_5_txc_4_int), + .qsfp_5_rx_clk_4(qsfp_5_rx_clk_4_int), + .qsfp_5_rx_rst_4(qsfp_5_rx_rst_4_int), + .qsfp_5_rxd_4(qsfp_5_rxd_4_int), + .qsfp_5_rxc_4(qsfp_5_rxc_4_int), + .qsfp_6_tx_clk_1(qsfp_6_tx_clk_1_int), + .qsfp_6_tx_rst_1(qsfp_6_tx_rst_1_int), + .qsfp_6_txd_1(qsfp_6_txd_1_int), + .qsfp_6_txc_1(qsfp_6_txc_1_int), + .qsfp_6_rx_clk_1(qsfp_6_rx_clk_1_int), + .qsfp_6_rx_rst_1(qsfp_6_rx_rst_1_int), + .qsfp_6_rxd_1(qsfp_6_rxd_1_int), + .qsfp_6_rxc_1(qsfp_6_rxc_1_int), + .qsfp_6_tx_clk_2(qsfp_6_tx_clk_2_int), + .qsfp_6_tx_rst_2(qsfp_6_tx_rst_2_int), + .qsfp_6_txd_2(qsfp_6_txd_2_int), + .qsfp_6_txc_2(qsfp_6_txc_2_int), + .qsfp_6_rx_clk_2(qsfp_6_rx_clk_2_int), + .qsfp_6_rx_rst_2(qsfp_6_rx_rst_2_int), + .qsfp_6_rxd_2(qsfp_6_rxd_2_int), + .qsfp_6_rxc_2(qsfp_6_rxc_2_int), + .qsfp_6_tx_clk_3(qsfp_6_tx_clk_3_int), + .qsfp_6_tx_rst_3(qsfp_6_tx_rst_3_int), + .qsfp_6_txd_3(qsfp_6_txd_3_int), + .qsfp_6_txc_3(qsfp_6_txc_3_int), + .qsfp_6_rx_clk_3(qsfp_6_rx_clk_3_int), + .qsfp_6_rx_rst_3(qsfp_6_rx_rst_3_int), + .qsfp_6_rxd_3(qsfp_6_rxd_3_int), + .qsfp_6_rxc_3(qsfp_6_rxc_3_int), + .qsfp_6_tx_clk_4(qsfp_6_tx_clk_4_int), + .qsfp_6_tx_rst_4(qsfp_6_tx_rst_4_int), + .qsfp_6_txd_4(qsfp_6_txd_4_int), + .qsfp_6_txc_4(qsfp_6_txc_4_int), + .qsfp_6_rx_clk_4(qsfp_6_rx_clk_4_int), + .qsfp_6_rx_rst_4(qsfp_6_rx_rst_4_int), + .qsfp_6_rxd_4(qsfp_6_rxd_4_int), + .qsfp_6_rxc_4(qsfp_6_rxc_4_int), + .qsfp_7_tx_clk_1(qsfp_7_tx_clk_1_int), + .qsfp_7_tx_rst_1(qsfp_7_tx_rst_1_int), + .qsfp_7_txd_1(qsfp_7_txd_1_int), + .qsfp_7_txc_1(qsfp_7_txc_1_int), + .qsfp_7_rx_clk_1(qsfp_7_rx_clk_1_int), + .qsfp_7_rx_rst_1(qsfp_7_rx_rst_1_int), + .qsfp_7_rxd_1(qsfp_7_rxd_1_int), + .qsfp_7_rxc_1(qsfp_7_rxc_1_int), + .qsfp_7_tx_clk_2(qsfp_7_tx_clk_2_int), + .qsfp_7_tx_rst_2(qsfp_7_tx_rst_2_int), + .qsfp_7_txd_2(qsfp_7_txd_2_int), + .qsfp_7_txc_2(qsfp_7_txc_2_int), + .qsfp_7_rx_clk_2(qsfp_7_rx_clk_2_int), + .qsfp_7_rx_rst_2(qsfp_7_rx_rst_2_int), + .qsfp_7_rxd_2(qsfp_7_rxd_2_int), + .qsfp_7_rxc_2(qsfp_7_rxc_2_int), + .qsfp_7_tx_clk_3(qsfp_7_tx_clk_3_int), + .qsfp_7_tx_rst_3(qsfp_7_tx_rst_3_int), + .qsfp_7_txd_3(qsfp_7_txd_3_int), + .qsfp_7_txc_3(qsfp_7_txc_3_int), + .qsfp_7_rx_clk_3(qsfp_7_rx_clk_3_int), + .qsfp_7_rx_rst_3(qsfp_7_rx_rst_3_int), + .qsfp_7_rxd_3(qsfp_7_rxd_3_int), + .qsfp_7_rxc_3(qsfp_7_rxc_3_int), + .qsfp_7_tx_clk_4(qsfp_7_tx_clk_4_int), + .qsfp_7_tx_rst_4(qsfp_7_tx_rst_4_int), + .qsfp_7_txd_4(qsfp_7_txd_4_int), + .qsfp_7_txc_4(qsfp_7_txc_4_int), + .qsfp_7_rx_clk_4(qsfp_7_rx_clk_4_int), + .qsfp_7_rx_rst_4(qsfp_7_rx_rst_4_int), + .qsfp_7_rxd_4(qsfp_7_rxd_4_int), + .qsfp_7_rxc_4(qsfp_7_rxc_4_int), + .qsfp_8_tx_clk_1(qsfp_8_tx_clk_1_int), + .qsfp_8_tx_rst_1(qsfp_8_tx_rst_1_int), + .qsfp_8_txd_1(qsfp_8_txd_1_int), + .qsfp_8_txc_1(qsfp_8_txc_1_int), + .qsfp_8_rx_clk_1(qsfp_8_rx_clk_1_int), + .qsfp_8_rx_rst_1(qsfp_8_rx_rst_1_int), + .qsfp_8_rxd_1(qsfp_8_rxd_1_int), + .qsfp_8_rxc_1(qsfp_8_rxc_1_int), + .qsfp_8_tx_clk_2(qsfp_8_tx_clk_2_int), + .qsfp_8_tx_rst_2(qsfp_8_tx_rst_2_int), + .qsfp_8_txd_2(qsfp_8_txd_2_int), + .qsfp_8_txc_2(qsfp_8_txc_2_int), + .qsfp_8_rx_clk_2(qsfp_8_rx_clk_2_int), + .qsfp_8_rx_rst_2(qsfp_8_rx_rst_2_int), + .qsfp_8_rxd_2(qsfp_8_rxd_2_int), + .qsfp_8_rxc_2(qsfp_8_rxc_2_int), + .qsfp_8_tx_clk_3(qsfp_8_tx_clk_3_int), + .qsfp_8_tx_rst_3(qsfp_8_tx_rst_3_int), + .qsfp_8_txd_3(qsfp_8_txd_3_int), + .qsfp_8_txc_3(qsfp_8_txc_3_int), + .qsfp_8_rx_clk_3(qsfp_8_rx_clk_3_int), + .qsfp_8_rx_rst_3(qsfp_8_rx_rst_3_int), + .qsfp_8_rxd_3(qsfp_8_rxd_3_int), + .qsfp_8_rxc_3(qsfp_8_rxc_3_int), + .qsfp_8_tx_clk_4(qsfp_8_tx_clk_4_int), + .qsfp_8_tx_rst_4(qsfp_8_tx_rst_4_int), + .qsfp_8_txd_4(qsfp_8_txd_4_int), + .qsfp_8_txc_4(qsfp_8_txc_4_int), + .qsfp_8_rx_clk_4(qsfp_8_rx_clk_4_int), + .qsfp_8_rx_rst_4(qsfp_8_rx_rst_4_int), + .qsfp_8_rxd_4(qsfp_8_rxd_4_int), + .qsfp_8_rxc_4(qsfp_8_rxc_4_int), + .qsfp_9_tx_clk_1(qsfp_9_tx_clk_1_int), + .qsfp_9_tx_rst_1(qsfp_9_tx_rst_1_int), + .qsfp_9_txd_1(qsfp_9_txd_1_int), + .qsfp_9_txc_1(qsfp_9_txc_1_int), + .qsfp_9_rx_clk_1(qsfp_9_rx_clk_1_int), + .qsfp_9_rx_rst_1(qsfp_9_rx_rst_1_int), + .qsfp_9_rxd_1(qsfp_9_rxd_1_int), + .qsfp_9_rxc_1(qsfp_9_rxc_1_int), + .qsfp_9_tx_clk_2(qsfp_9_tx_clk_2_int), + .qsfp_9_tx_rst_2(qsfp_9_tx_rst_2_int), + .qsfp_9_txd_2(qsfp_9_txd_2_int), + .qsfp_9_txc_2(qsfp_9_txc_2_int), + .qsfp_9_rx_clk_2(qsfp_9_rx_clk_2_int), + .qsfp_9_rx_rst_2(qsfp_9_rx_rst_2_int), + .qsfp_9_rxd_2(qsfp_9_rxd_2_int), + .qsfp_9_rxc_2(qsfp_9_rxc_2_int), + .qsfp_9_tx_clk_3(qsfp_9_tx_clk_3_int), + .qsfp_9_tx_rst_3(qsfp_9_tx_rst_3_int), + .qsfp_9_txd_3(qsfp_9_txd_3_int), + .qsfp_9_txc_3(qsfp_9_txc_3_int), + .qsfp_9_rx_clk_3(qsfp_9_rx_clk_3_int), + .qsfp_9_rx_rst_3(qsfp_9_rx_rst_3_int), + .qsfp_9_rxd_3(qsfp_9_rxd_3_int), + .qsfp_9_rxc_3(qsfp_9_rxc_3_int), + .qsfp_9_tx_clk_4(qsfp_9_tx_clk_4_int), + .qsfp_9_tx_rst_4(qsfp_9_tx_rst_4_int), + .qsfp_9_txd_4(qsfp_9_txd_4_int), + .qsfp_9_txc_4(qsfp_9_txc_4_int), + .qsfp_9_rx_clk_4(qsfp_9_rx_clk_4_int), + .qsfp_9_rx_rst_4(qsfp_9_rx_rst_4_int), + .qsfp_9_rxd_4(qsfp_9_rxd_4_int), + .qsfp_9_rxc_4(qsfp_9_rxc_4_int), + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + .fmc_qsfp_1_tx_clk_1(fmc_qsfp_1_tx_clk_1_int), + .fmc_qsfp_1_tx_rst_1(fmc_qsfp_1_tx_rst_1_int), + .fmc_qsfp_1_txd_1(fmc_qsfp_1_txd_1_int), + .fmc_qsfp_1_txc_1(fmc_qsfp_1_txc_1_int), + .fmc_qsfp_1_rx_clk_1(fmc_qsfp_1_rx_clk_1_int), + .fmc_qsfp_1_rx_rst_1(fmc_qsfp_1_rx_rst_1_int), + .fmc_qsfp_1_rxd_1(fmc_qsfp_1_rxd_1_int), + .fmc_qsfp_1_rxc_1(fmc_qsfp_1_rxc_1_int), + .fmc_qsfp_1_tx_clk_2(fmc_qsfp_1_tx_clk_2_int), + .fmc_qsfp_1_tx_rst_2(fmc_qsfp_1_tx_rst_2_int), + .fmc_qsfp_1_txd_2(fmc_qsfp_1_txd_2_int), + .fmc_qsfp_1_txc_2(fmc_qsfp_1_txc_2_int), + .fmc_qsfp_1_rx_clk_2(fmc_qsfp_1_rx_clk_2_int), + .fmc_qsfp_1_rx_rst_2(fmc_qsfp_1_rx_rst_2_int), + .fmc_qsfp_1_rxd_2(fmc_qsfp_1_rxd_2_int), + .fmc_qsfp_1_rxc_2(fmc_qsfp_1_rxc_2_int), + .fmc_qsfp_1_tx_clk_3(fmc_qsfp_1_tx_clk_3_int), + .fmc_qsfp_1_tx_rst_3(fmc_qsfp_1_tx_rst_3_int), + .fmc_qsfp_1_txd_3(fmc_qsfp_1_txd_3_int), + .fmc_qsfp_1_txc_3(fmc_qsfp_1_txc_3_int), + .fmc_qsfp_1_rx_clk_3(fmc_qsfp_1_rx_clk_3_int), + .fmc_qsfp_1_rx_rst_3(fmc_qsfp_1_rx_rst_3_int), + .fmc_qsfp_1_rxd_3(fmc_qsfp_1_rxd_3_int), + .fmc_qsfp_1_rxc_3(fmc_qsfp_1_rxc_3_int), + .fmc_qsfp_1_tx_clk_4(fmc_qsfp_1_tx_clk_4_int), + .fmc_qsfp_1_tx_rst_4(fmc_qsfp_1_tx_rst_4_int), + .fmc_qsfp_1_txd_4(fmc_qsfp_1_txd_4_int), + .fmc_qsfp_1_txc_4(fmc_qsfp_1_txc_4_int), + .fmc_qsfp_1_rx_clk_4(fmc_qsfp_1_rx_clk_4_int), + .fmc_qsfp_1_rx_rst_4(fmc_qsfp_1_rx_rst_4_int), + .fmc_qsfp_1_rxd_4(fmc_qsfp_1_rxd_4_int), + .fmc_qsfp_1_rxc_4(fmc_qsfp_1_rxc_4_int), + .fmc_qsfp_2_tx_clk_1(fmc_qsfp_2_tx_clk_1_int), + .fmc_qsfp_2_tx_rst_1(fmc_qsfp_2_tx_rst_1_int), + .fmc_qsfp_2_txd_1(fmc_qsfp_2_txd_1_int), + .fmc_qsfp_2_txc_1(fmc_qsfp_2_txc_1_int), + .fmc_qsfp_2_rx_clk_1(fmc_qsfp_2_rx_clk_1_int), + .fmc_qsfp_2_rx_rst_1(fmc_qsfp_2_rx_rst_1_int), + .fmc_qsfp_2_rxd_1(fmc_qsfp_2_rxd_1_int), + .fmc_qsfp_2_rxc_1(fmc_qsfp_2_rxc_1_int), + .fmc_qsfp_2_tx_clk_2(fmc_qsfp_2_tx_clk_2_int), + .fmc_qsfp_2_tx_rst_2(fmc_qsfp_2_tx_rst_2_int), + .fmc_qsfp_2_txd_2(fmc_qsfp_2_txd_2_int), + .fmc_qsfp_2_txc_2(fmc_qsfp_2_txc_2_int), + .fmc_qsfp_2_rx_clk_2(fmc_qsfp_2_rx_clk_2_int), + .fmc_qsfp_2_rx_rst_2(fmc_qsfp_2_rx_rst_2_int), + .fmc_qsfp_2_rxd_2(fmc_qsfp_2_rxd_2_int), + .fmc_qsfp_2_rxc_2(fmc_qsfp_2_rxc_2_int), + .fmc_qsfp_2_tx_clk_3(fmc_qsfp_2_tx_clk_3_int), + .fmc_qsfp_2_tx_rst_3(fmc_qsfp_2_tx_rst_3_int), + .fmc_qsfp_2_txd_3(fmc_qsfp_2_txd_3_int), + .fmc_qsfp_2_txc_3(fmc_qsfp_2_txc_3_int), + .fmc_qsfp_2_rx_clk_3(fmc_qsfp_2_rx_clk_3_int), + .fmc_qsfp_2_rx_rst_3(fmc_qsfp_2_rx_rst_3_int), + .fmc_qsfp_2_rxd_3(fmc_qsfp_2_rxd_3_int), + .fmc_qsfp_2_rxc_3(fmc_qsfp_2_rxc_3_int), + .fmc_qsfp_2_tx_clk_4(fmc_qsfp_2_tx_clk_4_int), + .fmc_qsfp_2_tx_rst_4(fmc_qsfp_2_tx_rst_4_int), + .fmc_qsfp_2_txd_4(fmc_qsfp_2_txd_4_int), + .fmc_qsfp_2_txc_4(fmc_qsfp_2_txc_4_int), + .fmc_qsfp_2_rx_clk_4(fmc_qsfp_2_rx_clk_4_int), + .fmc_qsfp_2_rx_rst_4(fmc_qsfp_2_rx_rst_4_int), + .fmc_qsfp_2_rxd_4(fmc_qsfp_2_rxd_4_int), + .fmc_qsfp_2_rxc_4(fmc_qsfp_2_rxc_4_int), + .fmc_qsfp_3_tx_clk_1(fmc_qsfp_3_tx_clk_1_int), + .fmc_qsfp_3_tx_rst_1(fmc_qsfp_3_tx_rst_1_int), + .fmc_qsfp_3_txd_1(fmc_qsfp_3_txd_1_int), + .fmc_qsfp_3_txc_1(fmc_qsfp_3_txc_1_int), + .fmc_qsfp_3_rx_clk_1(fmc_qsfp_3_rx_clk_1_int), + .fmc_qsfp_3_rx_rst_1(fmc_qsfp_3_rx_rst_1_int), + .fmc_qsfp_3_rxd_1(fmc_qsfp_3_rxd_1_int), + .fmc_qsfp_3_rxc_1(fmc_qsfp_3_rxc_1_int), + .fmc_qsfp_3_tx_clk_2(fmc_qsfp_3_tx_clk_2_int), + .fmc_qsfp_3_tx_rst_2(fmc_qsfp_3_tx_rst_2_int), + .fmc_qsfp_3_txd_2(fmc_qsfp_3_txd_2_int), + .fmc_qsfp_3_txc_2(fmc_qsfp_3_txc_2_int), + .fmc_qsfp_3_rx_clk_2(fmc_qsfp_3_rx_clk_2_int), + .fmc_qsfp_3_rx_rst_2(fmc_qsfp_3_rx_rst_2_int), + .fmc_qsfp_3_rxd_2(fmc_qsfp_3_rxd_2_int), + .fmc_qsfp_3_rxc_2(fmc_qsfp_3_rxc_2_int), + .fmc_qsfp_3_tx_clk_3(fmc_qsfp_3_tx_clk_3_int), + .fmc_qsfp_3_tx_rst_3(fmc_qsfp_3_tx_rst_3_int), + .fmc_qsfp_3_txd_3(fmc_qsfp_3_txd_3_int), + .fmc_qsfp_3_txc_3(fmc_qsfp_3_txc_3_int), + .fmc_qsfp_3_rx_clk_3(fmc_qsfp_3_rx_clk_3_int), + .fmc_qsfp_3_rx_rst_3(fmc_qsfp_3_rx_rst_3_int), + .fmc_qsfp_3_rxd_3(fmc_qsfp_3_rxd_3_int), + .fmc_qsfp_3_rxc_3(fmc_qsfp_3_rxc_3_int), + .fmc_qsfp_3_tx_clk_4(fmc_qsfp_3_tx_clk_4_int), + .fmc_qsfp_3_tx_rst_4(fmc_qsfp_3_tx_rst_4_int), + .fmc_qsfp_3_txd_4(fmc_qsfp_3_txd_4_int), + .fmc_qsfp_3_txc_4(fmc_qsfp_3_txc_4_int), + .fmc_qsfp_3_rx_clk_4(fmc_qsfp_3_rx_clk_4_int), + .fmc_qsfp_3_rx_rst_4(fmc_qsfp_3_rx_rst_4_int), + .fmc_qsfp_3_rxd_4(fmc_qsfp_3_rxd_4_int), + .fmc_qsfp_3_rxc_4(fmc_qsfp_3_rxc_4_int), + .fmc_qsfp_4_tx_clk_1(fmc_qsfp_4_tx_clk_1_int), + .fmc_qsfp_4_tx_rst_1(fmc_qsfp_4_tx_rst_1_int), + .fmc_qsfp_4_txd_1(fmc_qsfp_4_txd_1_int), + .fmc_qsfp_4_txc_1(fmc_qsfp_4_txc_1_int), + .fmc_qsfp_4_rx_clk_1(fmc_qsfp_4_rx_clk_1_int), + .fmc_qsfp_4_rx_rst_1(fmc_qsfp_4_rx_rst_1_int), + .fmc_qsfp_4_rxd_1(fmc_qsfp_4_rxd_1_int), + .fmc_qsfp_4_rxc_1(fmc_qsfp_4_rxc_1_int), + .fmc_qsfp_4_tx_clk_2(fmc_qsfp_4_tx_clk_2_int), + .fmc_qsfp_4_tx_rst_2(fmc_qsfp_4_tx_rst_2_int), + .fmc_qsfp_4_txd_2(fmc_qsfp_4_txd_2_int), + .fmc_qsfp_4_txc_2(fmc_qsfp_4_txc_2_int), + .fmc_qsfp_4_rx_clk_2(fmc_qsfp_4_rx_clk_2_int), + .fmc_qsfp_4_rx_rst_2(fmc_qsfp_4_rx_rst_2_int), + .fmc_qsfp_4_rxd_2(fmc_qsfp_4_rxd_2_int), + .fmc_qsfp_4_rxc_2(fmc_qsfp_4_rxc_2_int), + .fmc_qsfp_4_tx_clk_3(fmc_qsfp_4_tx_clk_3_int), + .fmc_qsfp_4_tx_rst_3(fmc_qsfp_4_tx_rst_3_int), + .fmc_qsfp_4_txd_3(fmc_qsfp_4_txd_3_int), + .fmc_qsfp_4_txc_3(fmc_qsfp_4_txc_3_int), + .fmc_qsfp_4_rx_clk_3(fmc_qsfp_4_rx_clk_3_int), + .fmc_qsfp_4_rx_rst_3(fmc_qsfp_4_rx_rst_3_int), + .fmc_qsfp_4_rxd_3(fmc_qsfp_4_rxd_3_int), + .fmc_qsfp_4_rxc_3(fmc_qsfp_4_rxc_3_int), + .fmc_qsfp_4_tx_clk_4(fmc_qsfp_4_tx_clk_4_int), + .fmc_qsfp_4_tx_rst_4(fmc_qsfp_4_tx_rst_4_int), + .fmc_qsfp_4_txd_4(fmc_qsfp_4_txd_4_int), + .fmc_qsfp_4_txc_4(fmc_qsfp_4_txc_4_int), + .fmc_qsfp_4_rx_clk_4(fmc_qsfp_4_rx_clk_4_int), + .fmc_qsfp_4_rx_rst_4(fmc_qsfp_4_rx_rst_4_int), + .fmc_qsfp_4_rxd_4(fmc_qsfp_4_rxd_4_int), + .fmc_qsfp_4_rxc_4(fmc_qsfp_4_rxc_4_int), + .fmc_qsfp_5_tx_clk_1(fmc_qsfp_5_tx_clk_1_int), + .fmc_qsfp_5_tx_rst_1(fmc_qsfp_5_tx_rst_1_int), + .fmc_qsfp_5_txd_1(fmc_qsfp_5_txd_1_int), + .fmc_qsfp_5_txc_1(fmc_qsfp_5_txc_1_int), + .fmc_qsfp_5_rx_clk_1(fmc_qsfp_5_rx_clk_1_int), + .fmc_qsfp_5_rx_rst_1(fmc_qsfp_5_rx_rst_1_int), + .fmc_qsfp_5_rxd_1(fmc_qsfp_5_rxd_1_int), + .fmc_qsfp_5_rxc_1(fmc_qsfp_5_rxc_1_int), + .fmc_qsfp_5_tx_clk_2(fmc_qsfp_5_tx_clk_2_int), + .fmc_qsfp_5_tx_rst_2(fmc_qsfp_5_tx_rst_2_int), + .fmc_qsfp_5_txd_2(fmc_qsfp_5_txd_2_int), + .fmc_qsfp_5_txc_2(fmc_qsfp_5_txc_2_int), + .fmc_qsfp_5_rx_clk_2(fmc_qsfp_5_rx_clk_2_int), + .fmc_qsfp_5_rx_rst_2(fmc_qsfp_5_rx_rst_2_int), + .fmc_qsfp_5_rxd_2(fmc_qsfp_5_rxd_2_int), + .fmc_qsfp_5_rxc_2(fmc_qsfp_5_rxc_2_int), + .fmc_qsfp_5_tx_clk_3(fmc_qsfp_5_tx_clk_3_int), + .fmc_qsfp_5_tx_rst_3(fmc_qsfp_5_tx_rst_3_int), + .fmc_qsfp_5_txd_3(fmc_qsfp_5_txd_3_int), + .fmc_qsfp_5_txc_3(fmc_qsfp_5_txc_3_int), + .fmc_qsfp_5_rx_clk_3(fmc_qsfp_5_rx_clk_3_int), + .fmc_qsfp_5_rx_rst_3(fmc_qsfp_5_rx_rst_3_int), + .fmc_qsfp_5_rxd_3(fmc_qsfp_5_rxd_3_int), + .fmc_qsfp_5_rxc_3(fmc_qsfp_5_rxc_3_int), + .fmc_qsfp_5_tx_clk_4(fmc_qsfp_5_tx_clk_4_int), + .fmc_qsfp_5_tx_rst_4(fmc_qsfp_5_tx_rst_4_int), + .fmc_qsfp_5_txd_4(fmc_qsfp_5_txd_4_int), + .fmc_qsfp_5_txc_4(fmc_qsfp_5_txc_4_int), + .fmc_qsfp_5_rx_clk_4(fmc_qsfp_5_rx_clk_4_int), + .fmc_qsfp_5_rx_rst_4(fmc_qsfp_5_rx_rst_4_int), + .fmc_qsfp_5_rxd_4(fmc_qsfp_5_rxd_4_int), + .fmc_qsfp_5_rxc_4(fmc_qsfp_5_rxc_4_int), + .fmc_qsfp_6_tx_clk_1(fmc_qsfp_6_tx_clk_1_int), + .fmc_qsfp_6_tx_rst_1(fmc_qsfp_6_tx_rst_1_int), + .fmc_qsfp_6_txd_1(fmc_qsfp_6_txd_1_int), + .fmc_qsfp_6_txc_1(fmc_qsfp_6_txc_1_int), + .fmc_qsfp_6_rx_clk_1(fmc_qsfp_6_rx_clk_1_int), + .fmc_qsfp_6_rx_rst_1(fmc_qsfp_6_rx_rst_1_int), + .fmc_qsfp_6_rxd_1(fmc_qsfp_6_rxd_1_int), + .fmc_qsfp_6_rxc_1(fmc_qsfp_6_rxc_1_int), + .fmc_qsfp_6_tx_clk_2(fmc_qsfp_6_tx_clk_2_int), + .fmc_qsfp_6_tx_rst_2(fmc_qsfp_6_tx_rst_2_int), + .fmc_qsfp_6_txd_2(fmc_qsfp_6_txd_2_int), + .fmc_qsfp_6_txc_2(fmc_qsfp_6_txc_2_int), + .fmc_qsfp_6_rx_clk_2(fmc_qsfp_6_rx_clk_2_int), + .fmc_qsfp_6_rx_rst_2(fmc_qsfp_6_rx_rst_2_int), + .fmc_qsfp_6_rxd_2(fmc_qsfp_6_rxd_2_int), + .fmc_qsfp_6_rxc_2(fmc_qsfp_6_rxc_2_int), + .fmc_qsfp_6_tx_clk_3(fmc_qsfp_6_tx_clk_3_int), + .fmc_qsfp_6_tx_rst_3(fmc_qsfp_6_tx_rst_3_int), + .fmc_qsfp_6_txd_3(fmc_qsfp_6_txd_3_int), + .fmc_qsfp_6_txc_3(fmc_qsfp_6_txc_3_int), + .fmc_qsfp_6_rx_clk_3(fmc_qsfp_6_rx_clk_3_int), + .fmc_qsfp_6_rx_rst_3(fmc_qsfp_6_rx_rst_3_int), + .fmc_qsfp_6_rxd_3(fmc_qsfp_6_rxd_3_int), + .fmc_qsfp_6_rxc_3(fmc_qsfp_6_rxc_3_int), + .fmc_qsfp_6_tx_clk_4(fmc_qsfp_6_tx_clk_4_int), + .fmc_qsfp_6_tx_rst_4(fmc_qsfp_6_tx_rst_4_int), + .fmc_qsfp_6_txd_4(fmc_qsfp_6_txd_4_int), + .fmc_qsfp_6_txc_4(fmc_qsfp_6_txc_4_int), + .fmc_qsfp_6_rx_clk_4(fmc_qsfp_6_rx_clk_4_int), + .fmc_qsfp_6_rx_rst_4(fmc_qsfp_6_rx_rst_4_int), + .fmc_qsfp_6_rxd_4(fmc_qsfp_6_rxd_4_int), + .fmc_qsfp_6_rxc_4(fmc_qsfp_6_rxc_4_int) +); + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v new file mode 100644 index 000000000..cfafade3c --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -0,0 +1,1213 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core +( + /* + * Clock: 156.25MHz + * Synchronous reset + */ + input wire clk, + input wire rst, + + /* + * GPIO + */ + input wire btn, + input wire [7:0] sw, + output wire [7:0] led, + + /* + * UART: 115200 bps, 8N1 + */ + output wire uart_rxd, + input wire uart_txd, + input wire uart_rts, + output wire uart_cts, + output wire uart_rst_n, + output wire uart_suspend_n, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp_1_tx_clk_1, + input wire qsfp_1_tx_rst_1, + output wire [63:0] qsfp_1_txd_1, + output wire [7:0] qsfp_1_txc_1, + input wire qsfp_1_rx_clk_1, + input wire qsfp_1_rx_rst_1, + input wire [63:0] qsfp_1_rxd_1, + input wire [7:0] qsfp_1_rxc_1, + input wire qsfp_1_tx_clk_2, + input wire qsfp_1_tx_rst_2, + output wire [63:0] qsfp_1_txd_2, + output wire [7:0] qsfp_1_txc_2, + input wire qsfp_1_rx_clk_2, + input wire qsfp_1_rx_rst_2, + input wire [63:0] qsfp_1_rxd_2, + input wire [7:0] qsfp_1_rxc_2, + input wire qsfp_1_tx_clk_3, + input wire qsfp_1_tx_rst_3, + output wire [63:0] qsfp_1_txd_3, + output wire [7:0] qsfp_1_txc_3, + input wire qsfp_1_rx_clk_3, + input wire qsfp_1_rx_rst_3, + input wire [63:0] qsfp_1_rxd_3, + input wire [7:0] qsfp_1_rxc_3, + input wire qsfp_1_tx_clk_4, + input wire qsfp_1_tx_rst_4, + output wire [63:0] qsfp_1_txd_4, + output wire [7:0] qsfp_1_txc_4, + input wire qsfp_1_rx_clk_4, + input wire qsfp_1_rx_rst_4, + input wire [63:0] qsfp_1_rxd_4, + input wire [7:0] qsfp_1_rxc_4, + input wire qsfp_2_tx_clk_1, + input wire qsfp_2_tx_rst_1, + output wire [63:0] qsfp_2_txd_1, + output wire [7:0] qsfp_2_txc_1, + input wire qsfp_2_rx_clk_1, + input wire qsfp_2_rx_rst_1, + input wire [63:0] qsfp_2_rxd_1, + input wire [7:0] qsfp_2_rxc_1, + input wire qsfp_2_tx_clk_2, + input wire qsfp_2_tx_rst_2, + output wire [63:0] qsfp_2_txd_2, + output wire [7:0] qsfp_2_txc_2, + input wire qsfp_2_rx_clk_2, + input wire qsfp_2_rx_rst_2, + input wire [63:0] qsfp_2_rxd_2, + input wire [7:0] qsfp_2_rxc_2, + input wire qsfp_2_tx_clk_3, + input wire qsfp_2_tx_rst_3, + output wire [63:0] qsfp_2_txd_3, + output wire [7:0] qsfp_2_txc_3, + input wire qsfp_2_rx_clk_3, + input wire qsfp_2_rx_rst_3, + input wire [63:0] qsfp_2_rxd_3, + input wire [7:0] qsfp_2_rxc_3, + input wire qsfp_2_tx_clk_4, + input wire qsfp_2_tx_rst_4, + output wire [63:0] qsfp_2_txd_4, + output wire [7:0] qsfp_2_txc_4, + input wire qsfp_2_rx_clk_4, + input wire qsfp_2_rx_rst_4, + input wire [63:0] qsfp_2_rxd_4, + input wire [7:0] qsfp_2_rxc_4, + input wire qsfp_3_tx_clk_1, + input wire qsfp_3_tx_rst_1, + output wire [63:0] qsfp_3_txd_1, + output wire [7:0] qsfp_3_txc_1, + input wire qsfp_3_rx_clk_1, + input wire qsfp_3_rx_rst_1, + input wire [63:0] qsfp_3_rxd_1, + input wire [7:0] qsfp_3_rxc_1, + input wire qsfp_3_tx_clk_2, + input wire qsfp_3_tx_rst_2, + output wire [63:0] qsfp_3_txd_2, + output wire [7:0] qsfp_3_txc_2, + input wire qsfp_3_rx_clk_2, + input wire qsfp_3_rx_rst_2, + input wire [63:0] qsfp_3_rxd_2, + input wire [7:0] qsfp_3_rxc_2, + input wire qsfp_3_tx_clk_3, + input wire qsfp_3_tx_rst_3, + output wire [63:0] qsfp_3_txd_3, + output wire [7:0] qsfp_3_txc_3, + input wire qsfp_3_rx_clk_3, + input wire qsfp_3_rx_rst_3, + input wire [63:0] qsfp_3_rxd_3, + input wire [7:0] qsfp_3_rxc_3, + input wire qsfp_3_tx_clk_4, + input wire qsfp_3_tx_rst_4, + output wire [63:0] qsfp_3_txd_4, + output wire [7:0] qsfp_3_txc_4, + input wire qsfp_3_rx_clk_4, + input wire qsfp_3_rx_rst_4, + input wire [63:0] qsfp_3_rxd_4, + input wire [7:0] qsfp_3_rxc_4, + input wire qsfp_4_tx_clk_1, + input wire qsfp_4_tx_rst_1, + output wire [63:0] qsfp_4_txd_1, + output wire [7:0] qsfp_4_txc_1, + input wire qsfp_4_rx_clk_1, + input wire qsfp_4_rx_rst_1, + input wire [63:0] qsfp_4_rxd_1, + input wire [7:0] qsfp_4_rxc_1, + input wire qsfp_4_tx_clk_2, + input wire qsfp_4_tx_rst_2, + output wire [63:0] qsfp_4_txd_2, + output wire [7:0] qsfp_4_txc_2, + input wire qsfp_4_rx_clk_2, + input wire qsfp_4_rx_rst_2, + input wire [63:0] qsfp_4_rxd_2, + input wire [7:0] qsfp_4_rxc_2, + input wire qsfp_4_tx_clk_3, + input wire qsfp_4_tx_rst_3, + output wire [63:0] qsfp_4_txd_3, + output wire [7:0] qsfp_4_txc_3, + input wire qsfp_4_rx_clk_3, + input wire qsfp_4_rx_rst_3, + input wire [63:0] qsfp_4_rxd_3, + input wire [7:0] qsfp_4_rxc_3, + input wire qsfp_4_tx_clk_4, + input wire qsfp_4_tx_rst_4, + output wire [63:0] qsfp_4_txd_4, + output wire [7:0] qsfp_4_txc_4, + input wire qsfp_4_rx_clk_4, + input wire qsfp_4_rx_rst_4, + input wire [63:0] qsfp_4_rxd_4, + input wire [7:0] qsfp_4_rxc_4, + input wire qsfp_5_tx_clk_1, + input wire qsfp_5_tx_rst_1, + output wire [63:0] qsfp_5_txd_1, + output wire [7:0] qsfp_5_txc_1, + input wire qsfp_5_rx_clk_1, + input wire qsfp_5_rx_rst_1, + input wire [63:0] qsfp_5_rxd_1, + input wire [7:0] qsfp_5_rxc_1, + input wire qsfp_5_tx_clk_2, + input wire qsfp_5_tx_rst_2, + output wire [63:0] qsfp_5_txd_2, + output wire [7:0] qsfp_5_txc_2, + input wire qsfp_5_rx_clk_2, + input wire qsfp_5_rx_rst_2, + input wire [63:0] qsfp_5_rxd_2, + input wire [7:0] qsfp_5_rxc_2, + input wire qsfp_5_tx_clk_3, + input wire qsfp_5_tx_rst_3, + output wire [63:0] qsfp_5_txd_3, + output wire [7:0] qsfp_5_txc_3, + input wire qsfp_5_rx_clk_3, + input wire qsfp_5_rx_rst_3, + input wire [63:0] qsfp_5_rxd_3, + input wire [7:0] qsfp_5_rxc_3, + input wire qsfp_5_tx_clk_4, + input wire qsfp_5_tx_rst_4, + output wire [63:0] qsfp_5_txd_4, + output wire [7:0] qsfp_5_txc_4, + input wire qsfp_5_rx_clk_4, + input wire qsfp_5_rx_rst_4, + input wire [63:0] qsfp_5_rxd_4, + input wire [7:0] qsfp_5_rxc_4, + input wire qsfp_6_tx_clk_1, + input wire qsfp_6_tx_rst_1, + output wire [63:0] qsfp_6_txd_1, + output wire [7:0] qsfp_6_txc_1, + input wire qsfp_6_rx_clk_1, + input wire qsfp_6_rx_rst_1, + input wire [63:0] qsfp_6_rxd_1, + input wire [7:0] qsfp_6_rxc_1, + input wire qsfp_6_tx_clk_2, + input wire qsfp_6_tx_rst_2, + output wire [63:0] qsfp_6_txd_2, + output wire [7:0] qsfp_6_txc_2, + input wire qsfp_6_rx_clk_2, + input wire qsfp_6_rx_rst_2, + input wire [63:0] qsfp_6_rxd_2, + input wire [7:0] qsfp_6_rxc_2, + input wire qsfp_6_tx_clk_3, + input wire qsfp_6_tx_rst_3, + output wire [63:0] qsfp_6_txd_3, + output wire [7:0] qsfp_6_txc_3, + input wire qsfp_6_rx_clk_3, + input wire qsfp_6_rx_rst_3, + input wire [63:0] qsfp_6_rxd_3, + input wire [7:0] qsfp_6_rxc_3, + input wire qsfp_6_tx_clk_4, + input wire qsfp_6_tx_rst_4, + output wire [63:0] qsfp_6_txd_4, + output wire [7:0] qsfp_6_txc_4, + input wire qsfp_6_rx_clk_4, + input wire qsfp_6_rx_rst_4, + input wire [63:0] qsfp_6_rxd_4, + input wire [7:0] qsfp_6_rxc_4, + input wire qsfp_7_tx_clk_1, + input wire qsfp_7_tx_rst_1, + output wire [63:0] qsfp_7_txd_1, + output wire [7:0] qsfp_7_txc_1, + input wire qsfp_7_rx_clk_1, + input wire qsfp_7_rx_rst_1, + input wire [63:0] qsfp_7_rxd_1, + input wire [7:0] qsfp_7_rxc_1, + input wire qsfp_7_tx_clk_2, + input wire qsfp_7_tx_rst_2, + output wire [63:0] qsfp_7_txd_2, + output wire [7:0] qsfp_7_txc_2, + input wire qsfp_7_rx_clk_2, + input wire qsfp_7_rx_rst_2, + input wire [63:0] qsfp_7_rxd_2, + input wire [7:0] qsfp_7_rxc_2, + input wire qsfp_7_tx_clk_3, + input wire qsfp_7_tx_rst_3, + output wire [63:0] qsfp_7_txd_3, + output wire [7:0] qsfp_7_txc_3, + input wire qsfp_7_rx_clk_3, + input wire qsfp_7_rx_rst_3, + input wire [63:0] qsfp_7_rxd_3, + input wire [7:0] qsfp_7_rxc_3, + input wire qsfp_7_tx_clk_4, + input wire qsfp_7_tx_rst_4, + output wire [63:0] qsfp_7_txd_4, + output wire [7:0] qsfp_7_txc_4, + input wire qsfp_7_rx_clk_4, + input wire qsfp_7_rx_rst_4, + input wire [63:0] qsfp_7_rxd_4, + input wire [7:0] qsfp_7_rxc_4, + input wire qsfp_8_tx_clk_1, + input wire qsfp_8_tx_rst_1, + output wire [63:0] qsfp_8_txd_1, + output wire [7:0] qsfp_8_txc_1, + input wire qsfp_8_rx_clk_1, + input wire qsfp_8_rx_rst_1, + input wire [63:0] qsfp_8_rxd_1, + input wire [7:0] qsfp_8_rxc_1, + input wire qsfp_8_tx_clk_2, + input wire qsfp_8_tx_rst_2, + output wire [63:0] qsfp_8_txd_2, + output wire [7:0] qsfp_8_txc_2, + input wire qsfp_8_rx_clk_2, + input wire qsfp_8_rx_rst_2, + input wire [63:0] qsfp_8_rxd_2, + input wire [7:0] qsfp_8_rxc_2, + input wire qsfp_8_tx_clk_3, + input wire qsfp_8_tx_rst_3, + output wire [63:0] qsfp_8_txd_3, + output wire [7:0] qsfp_8_txc_3, + input wire qsfp_8_rx_clk_3, + input wire qsfp_8_rx_rst_3, + input wire [63:0] qsfp_8_rxd_3, + input wire [7:0] qsfp_8_rxc_3, + input wire qsfp_8_tx_clk_4, + input wire qsfp_8_tx_rst_4, + output wire [63:0] qsfp_8_txd_4, + output wire [7:0] qsfp_8_txc_4, + input wire qsfp_8_rx_clk_4, + input wire qsfp_8_rx_rst_4, + input wire [63:0] qsfp_8_rxd_4, + input wire [7:0] qsfp_8_rxc_4, + input wire qsfp_9_tx_clk_1, + input wire qsfp_9_tx_rst_1, + output wire [63:0] qsfp_9_txd_1, + output wire [7:0] qsfp_9_txc_1, + input wire qsfp_9_rx_clk_1, + input wire qsfp_9_rx_rst_1, + input wire [63:0] qsfp_9_rxd_1, + input wire [7:0] qsfp_9_rxc_1, + input wire qsfp_9_tx_clk_2, + input wire qsfp_9_tx_rst_2, + output wire [63:0] qsfp_9_txd_2, + output wire [7:0] qsfp_9_txc_2, + input wire qsfp_9_rx_clk_2, + input wire qsfp_9_rx_rst_2, + input wire [63:0] qsfp_9_rxd_2, + input wire [7:0] qsfp_9_rxc_2, + input wire qsfp_9_tx_clk_3, + input wire qsfp_9_tx_rst_3, + output wire [63:0] qsfp_9_txd_3, + output wire [7:0] qsfp_9_txc_3, + input wire qsfp_9_rx_clk_3, + input wire qsfp_9_rx_rst_3, + input wire [63:0] qsfp_9_rxd_3, + input wire [7:0] qsfp_9_rxc_3, + input wire qsfp_9_tx_clk_4, + input wire qsfp_9_tx_rst_4, + output wire [63:0] qsfp_9_txd_4, + output wire [7:0] qsfp_9_txc_4, + input wire qsfp_9_rx_clk_4, + input wire qsfp_9_rx_rst_4, + input wire [63:0] qsfp_9_rxd_4, + input wire [7:0] qsfp_9_rxc_4, + + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + input wire fmc_qsfp_1_tx_clk_1, + input wire fmc_qsfp_1_tx_rst_1, + output wire [63:0] fmc_qsfp_1_txd_1, + output wire [7:0] fmc_qsfp_1_txc_1, + input wire fmc_qsfp_1_rx_clk_1, + input wire fmc_qsfp_1_rx_rst_1, + input wire [63:0] fmc_qsfp_1_rxd_1, + input wire [7:0] fmc_qsfp_1_rxc_1, + input wire fmc_qsfp_1_tx_clk_2, + input wire fmc_qsfp_1_tx_rst_2, + output wire [63:0] fmc_qsfp_1_txd_2, + output wire [7:0] fmc_qsfp_1_txc_2, + input wire fmc_qsfp_1_rx_clk_2, + input wire fmc_qsfp_1_rx_rst_2, + input wire [63:0] fmc_qsfp_1_rxd_2, + input wire [7:0] fmc_qsfp_1_rxc_2, + input wire fmc_qsfp_1_tx_clk_3, + input wire fmc_qsfp_1_tx_rst_3, + output wire [63:0] fmc_qsfp_1_txd_3, + output wire [7:0] fmc_qsfp_1_txc_3, + input wire fmc_qsfp_1_rx_clk_3, + input wire fmc_qsfp_1_rx_rst_3, + input wire [63:0] fmc_qsfp_1_rxd_3, + input wire [7:0] fmc_qsfp_1_rxc_3, + input wire fmc_qsfp_1_tx_clk_4, + input wire fmc_qsfp_1_tx_rst_4, + output wire [63:0] fmc_qsfp_1_txd_4, + output wire [7:0] fmc_qsfp_1_txc_4, + input wire fmc_qsfp_1_rx_clk_4, + input wire fmc_qsfp_1_rx_rst_4, + input wire [63:0] fmc_qsfp_1_rxd_4, + input wire [7:0] fmc_qsfp_1_rxc_4, + input wire fmc_qsfp_2_tx_clk_1, + input wire fmc_qsfp_2_tx_rst_1, + output wire [63:0] fmc_qsfp_2_txd_1, + output wire [7:0] fmc_qsfp_2_txc_1, + input wire fmc_qsfp_2_rx_clk_1, + input wire fmc_qsfp_2_rx_rst_1, + input wire [63:0] fmc_qsfp_2_rxd_1, + input wire [7:0] fmc_qsfp_2_rxc_1, + input wire fmc_qsfp_2_tx_clk_2, + input wire fmc_qsfp_2_tx_rst_2, + output wire [63:0] fmc_qsfp_2_txd_2, + output wire [7:0] fmc_qsfp_2_txc_2, + input wire fmc_qsfp_2_rx_clk_2, + input wire fmc_qsfp_2_rx_rst_2, + input wire [63:0] fmc_qsfp_2_rxd_2, + input wire [7:0] fmc_qsfp_2_rxc_2, + input wire fmc_qsfp_2_tx_clk_3, + input wire fmc_qsfp_2_tx_rst_3, + output wire [63:0] fmc_qsfp_2_txd_3, + output wire [7:0] fmc_qsfp_2_txc_3, + input wire fmc_qsfp_2_rx_clk_3, + input wire fmc_qsfp_2_rx_rst_3, + input wire [63:0] fmc_qsfp_2_rxd_3, + input wire [7:0] fmc_qsfp_2_rxc_3, + input wire fmc_qsfp_2_tx_clk_4, + input wire fmc_qsfp_2_tx_rst_4, + output wire [63:0] fmc_qsfp_2_txd_4, + output wire [7:0] fmc_qsfp_2_txc_4, + input wire fmc_qsfp_2_rx_clk_4, + input wire fmc_qsfp_2_rx_rst_4, + input wire [63:0] fmc_qsfp_2_rxd_4, + input wire [7:0] fmc_qsfp_2_rxc_4, + input wire fmc_qsfp_3_tx_clk_1, + input wire fmc_qsfp_3_tx_rst_1, + output wire [63:0] fmc_qsfp_3_txd_1, + output wire [7:0] fmc_qsfp_3_txc_1, + input wire fmc_qsfp_3_rx_clk_1, + input wire fmc_qsfp_3_rx_rst_1, + input wire [63:0] fmc_qsfp_3_rxd_1, + input wire [7:0] fmc_qsfp_3_rxc_1, + input wire fmc_qsfp_3_tx_clk_2, + input wire fmc_qsfp_3_tx_rst_2, + output wire [63:0] fmc_qsfp_3_txd_2, + output wire [7:0] fmc_qsfp_3_txc_2, + input wire fmc_qsfp_3_rx_clk_2, + input wire fmc_qsfp_3_rx_rst_2, + input wire [63:0] fmc_qsfp_3_rxd_2, + input wire [7:0] fmc_qsfp_3_rxc_2, + input wire fmc_qsfp_3_tx_clk_3, + input wire fmc_qsfp_3_tx_rst_3, + output wire [63:0] fmc_qsfp_3_txd_3, + output wire [7:0] fmc_qsfp_3_txc_3, + input wire fmc_qsfp_3_rx_clk_3, + input wire fmc_qsfp_3_rx_rst_3, + input wire [63:0] fmc_qsfp_3_rxd_3, + input wire [7:0] fmc_qsfp_3_rxc_3, + input wire fmc_qsfp_3_tx_clk_4, + input wire fmc_qsfp_3_tx_rst_4, + output wire [63:0] fmc_qsfp_3_txd_4, + output wire [7:0] fmc_qsfp_3_txc_4, + input wire fmc_qsfp_3_rx_clk_4, + input wire fmc_qsfp_3_rx_rst_4, + input wire [63:0] fmc_qsfp_3_rxd_4, + input wire [7:0] fmc_qsfp_3_rxc_4, + input wire fmc_qsfp_4_tx_clk_1, + input wire fmc_qsfp_4_tx_rst_1, + output wire [63:0] fmc_qsfp_4_txd_1, + output wire [7:0] fmc_qsfp_4_txc_1, + input wire fmc_qsfp_4_rx_clk_1, + input wire fmc_qsfp_4_rx_rst_1, + input wire [63:0] fmc_qsfp_4_rxd_1, + input wire [7:0] fmc_qsfp_4_rxc_1, + input wire fmc_qsfp_4_tx_clk_2, + input wire fmc_qsfp_4_tx_rst_2, + output wire [63:0] fmc_qsfp_4_txd_2, + output wire [7:0] fmc_qsfp_4_txc_2, + input wire fmc_qsfp_4_rx_clk_2, + input wire fmc_qsfp_4_rx_rst_2, + input wire [63:0] fmc_qsfp_4_rxd_2, + input wire [7:0] fmc_qsfp_4_rxc_2, + input wire fmc_qsfp_4_tx_clk_3, + input wire fmc_qsfp_4_tx_rst_3, + output wire [63:0] fmc_qsfp_4_txd_3, + output wire [7:0] fmc_qsfp_4_txc_3, + input wire fmc_qsfp_4_rx_clk_3, + input wire fmc_qsfp_4_rx_rst_3, + input wire [63:0] fmc_qsfp_4_rxd_3, + input wire [7:0] fmc_qsfp_4_rxc_3, + input wire fmc_qsfp_4_tx_clk_4, + input wire fmc_qsfp_4_tx_rst_4, + output wire [63:0] fmc_qsfp_4_txd_4, + output wire [7:0] fmc_qsfp_4_txc_4, + input wire fmc_qsfp_4_rx_clk_4, + input wire fmc_qsfp_4_rx_rst_4, + input wire [63:0] fmc_qsfp_4_rxd_4, + input wire [7:0] fmc_qsfp_4_rxc_4, + input wire fmc_qsfp_5_tx_clk_1, + input wire fmc_qsfp_5_tx_rst_1, + output wire [63:0] fmc_qsfp_5_txd_1, + output wire [7:0] fmc_qsfp_5_txc_1, + input wire fmc_qsfp_5_rx_clk_1, + input wire fmc_qsfp_5_rx_rst_1, + input wire [63:0] fmc_qsfp_5_rxd_1, + input wire [7:0] fmc_qsfp_5_rxc_1, + input wire fmc_qsfp_5_tx_clk_2, + input wire fmc_qsfp_5_tx_rst_2, + output wire [63:0] fmc_qsfp_5_txd_2, + output wire [7:0] fmc_qsfp_5_txc_2, + input wire fmc_qsfp_5_rx_clk_2, + input wire fmc_qsfp_5_rx_rst_2, + input wire [63:0] fmc_qsfp_5_rxd_2, + input wire [7:0] fmc_qsfp_5_rxc_2, + input wire fmc_qsfp_5_tx_clk_3, + input wire fmc_qsfp_5_tx_rst_3, + output wire [63:0] fmc_qsfp_5_txd_3, + output wire [7:0] fmc_qsfp_5_txc_3, + input wire fmc_qsfp_5_rx_clk_3, + input wire fmc_qsfp_5_rx_rst_3, + input wire [63:0] fmc_qsfp_5_rxd_3, + input wire [7:0] fmc_qsfp_5_rxc_3, + input wire fmc_qsfp_5_tx_clk_4, + input wire fmc_qsfp_5_tx_rst_4, + output wire [63:0] fmc_qsfp_5_txd_4, + output wire [7:0] fmc_qsfp_5_txc_4, + input wire fmc_qsfp_5_rx_clk_4, + input wire fmc_qsfp_5_rx_rst_4, + input wire [63:0] fmc_qsfp_5_rxd_4, + input wire [7:0] fmc_qsfp_5_rxc_4, + input wire fmc_qsfp_6_tx_clk_1, + input wire fmc_qsfp_6_tx_rst_1, + output wire [63:0] fmc_qsfp_6_txd_1, + output wire [7:0] fmc_qsfp_6_txc_1, + input wire fmc_qsfp_6_rx_clk_1, + input wire fmc_qsfp_6_rx_rst_1, + input wire [63:0] fmc_qsfp_6_rxd_1, + input wire [7:0] fmc_qsfp_6_rxc_1, + input wire fmc_qsfp_6_tx_clk_2, + input wire fmc_qsfp_6_tx_rst_2, + output wire [63:0] fmc_qsfp_6_txd_2, + output wire [7:0] fmc_qsfp_6_txc_2, + input wire fmc_qsfp_6_rx_clk_2, + input wire fmc_qsfp_6_rx_rst_2, + input wire [63:0] fmc_qsfp_6_rxd_2, + input wire [7:0] fmc_qsfp_6_rxc_2, + input wire fmc_qsfp_6_tx_clk_3, + input wire fmc_qsfp_6_tx_rst_3, + output wire [63:0] fmc_qsfp_6_txd_3, + output wire [7:0] fmc_qsfp_6_txc_3, + input wire fmc_qsfp_6_rx_clk_3, + input wire fmc_qsfp_6_rx_rst_3, + input wire [63:0] fmc_qsfp_6_rxd_3, + input wire [7:0] fmc_qsfp_6_rxc_3, + input wire fmc_qsfp_6_tx_clk_4, + input wire fmc_qsfp_6_tx_rst_4, + output wire [63:0] fmc_qsfp_6_txd_4, + output wire [7:0] fmc_qsfp_6_txc_4, + input wire fmc_qsfp_6_rx_clk_4, + input wire fmc_qsfp_6_rx_rst_4, + input wire [63:0] fmc_qsfp_6_rxd_4, + input wire [7:0] fmc_qsfp_6_rxc_4 +); + +// AXI between MAC and Ethernet modules +wire [63:0] rx_axis_tdata; +wire [7:0] rx_axis_tkeep; +wire rx_axis_tvalid; +wire rx_axis_tready; +wire rx_axis_tlast; +wire rx_axis_tuser; + +wire [63:0] tx_axis_tdata; +wire [7:0] tx_axis_tkeep; +wire tx_axis_tvalid; +wire tx_axis_tready; +wire tx_axis_tlast; +wire tx_axis_tuser; + +// Ethernet frame between Ethernet modules and UDP stack +wire rx_eth_hdr_ready; +wire rx_eth_hdr_valid; +wire [47:0] rx_eth_dest_mac; +wire [47:0] rx_eth_src_mac; +wire [15:0] rx_eth_type; +wire [63:0] rx_eth_payload_axis_tdata; +wire [7:0] rx_eth_payload_axis_tkeep; +wire rx_eth_payload_axis_tvalid; +wire rx_eth_payload_axis_tready; +wire rx_eth_payload_axis_tlast; +wire rx_eth_payload_axis_tuser; + +wire tx_eth_hdr_ready; +wire tx_eth_hdr_valid; +wire [47:0] tx_eth_dest_mac; +wire [47:0] tx_eth_src_mac; +wire [15:0] tx_eth_type; +wire [63:0] tx_eth_payload_axis_tdata; +wire [7:0] tx_eth_payload_axis_tkeep; +wire tx_eth_payload_axis_tvalid; +wire tx_eth_payload_axis_tready; +wire tx_eth_payload_axis_tlast; +wire tx_eth_payload_axis_tuser; + +// IP frame connections +wire rx_ip_hdr_valid; +wire rx_ip_hdr_ready; +wire [47:0] rx_ip_eth_dest_mac; +wire [47:0] rx_ip_eth_src_mac; +wire [15:0] rx_ip_eth_type; +wire [3:0] rx_ip_version; +wire [3:0] rx_ip_ihl; +wire [5:0] rx_ip_dscp; +wire [1:0] rx_ip_ecn; +wire [15:0] rx_ip_length; +wire [15:0] rx_ip_identification; +wire [2:0] rx_ip_flags; +wire [12:0] rx_ip_fragment_offset; +wire [7:0] rx_ip_ttl; +wire [7:0] rx_ip_protocol; +wire [15:0] rx_ip_header_checksum; +wire [31:0] rx_ip_source_ip; +wire [31:0] rx_ip_dest_ip; +wire [63:0] rx_ip_payload_axis_tdata; +wire [7:0] rx_ip_payload_axis_tkeep; +wire rx_ip_payload_axis_tvalid; +wire rx_ip_payload_axis_tready; +wire rx_ip_payload_axis_tlast; +wire rx_ip_payload_axis_tuser; + +wire tx_ip_hdr_valid; +wire tx_ip_hdr_ready; +wire [5:0] tx_ip_dscp; +wire [1:0] tx_ip_ecn; +wire [15:0] tx_ip_length; +wire [7:0] tx_ip_ttl; +wire [7:0] tx_ip_protocol; +wire [31:0] tx_ip_source_ip; +wire [31:0] tx_ip_dest_ip; +wire [63:0] tx_ip_payload_axis_tdata; +wire [7:0] tx_ip_payload_axis_tkeep; +wire tx_ip_payload_axis_tvalid; +wire tx_ip_payload_axis_tready; +wire tx_ip_payload_axis_tlast; +wire tx_ip_payload_axis_tuser; + +// UDP frame connections +wire rx_udp_hdr_valid; +wire rx_udp_hdr_ready; +wire [47:0] rx_udp_eth_dest_mac; +wire [47:0] rx_udp_eth_src_mac; +wire [15:0] rx_udp_eth_type; +wire [3:0] rx_udp_ip_version; +wire [3:0] rx_udp_ip_ihl; +wire [5:0] rx_udp_ip_dscp; +wire [1:0] rx_udp_ip_ecn; +wire [15:0] rx_udp_ip_length; +wire [15:0] rx_udp_ip_identification; +wire [2:0] rx_udp_ip_flags; +wire [12:0] rx_udp_ip_fragment_offset; +wire [7:0] rx_udp_ip_ttl; +wire [7:0] rx_udp_ip_protocol; +wire [15:0] rx_udp_ip_header_checksum; +wire [31:0] rx_udp_ip_source_ip; +wire [31:0] rx_udp_ip_dest_ip; +wire [15:0] rx_udp_source_port; +wire [15:0] rx_udp_dest_port; +wire [15:0] rx_udp_length; +wire [15:0] rx_udp_checksum; +wire [63:0] rx_udp_payload_axis_tdata; +wire [7:0] rx_udp_payload_axis_tkeep; +wire rx_udp_payload_axis_tvalid; +wire rx_udp_payload_axis_tready; +wire rx_udp_payload_axis_tlast; +wire rx_udp_payload_axis_tuser; + +wire tx_udp_hdr_valid; +wire tx_udp_hdr_ready; +wire [5:0] tx_udp_ip_dscp; +wire [1:0] tx_udp_ip_ecn; +wire [7:0] tx_udp_ip_ttl; +wire [31:0] tx_udp_ip_source_ip; +wire [31:0] tx_udp_ip_dest_ip; +wire [15:0] tx_udp_source_port; +wire [15:0] tx_udp_dest_port; +wire [15:0] tx_udp_length; +wire [15:0] tx_udp_checksum; +wire [63:0] tx_udp_payload_axis_tdata; +wire [7:0] tx_udp_payload_axis_tkeep; +wire tx_udp_payload_axis_tvalid; +wire tx_udp_payload_axis_tready; +wire tx_udp_payload_axis_tlast; +wire tx_udp_payload_axis_tuser; + +wire [63:0] rx_fifo_udp_payload_axis_tdata; +wire [7:0] rx_fifo_udp_payload_axis_tkeep; +wire rx_fifo_udp_payload_axis_tvalid; +wire rx_fifo_udp_payload_axis_tready; +wire rx_fifo_udp_payload_axis_tlast; +wire rx_fifo_udp_payload_axis_tuser; + +wire [63:0] tx_fifo_udp_payload_axis_tdata; +wire [7:0] tx_fifo_udp_payload_axis_tkeep; +wire tx_fifo_udp_payload_axis_tvalid; +wire tx_fifo_udp_payload_axis_tready; +wire tx_fifo_udp_payload_axis_tlast; +wire tx_fifo_udp_payload_axis_tuser; + +// Configuration +wire [47:0] local_mac = 48'h02_00_00_00_00_00; +wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; +wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; +wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; + +// IP ports not used +assign rx_ip_hdr_ready = 1; +assign rx_ip_payload_axis_tready = 1; + +assign tx_ip_hdr_valid = 0; +assign tx_ip_dscp = 0; +assign tx_ip_ecn = 0; +assign tx_ip_length = 0; +assign tx_ip_ttl = 0; +assign tx_ip_protocol = 0; +assign tx_ip_source_ip = 0; +assign tx_ip_dest_ip = 0; +assign tx_ip_payload_axis_tdata = 0; +assign tx_ip_payload_axis_tkeep = 0; +assign tx_ip_payload_axis_tvalid = 0; +assign tx_ip_payload_axis_tlast = 0; +assign tx_ip_payload_axis_tuser = 0; + +// Loop back UDP +wire match_cond = rx_udp_dest_port == 1234; +wire no_match = !match_cond; + +reg match_cond_reg = 0; +reg no_match_reg = 0; + +always @(posedge clk) begin + if (rst) begin + match_cond_reg <= 0; + no_match_reg <= 0; + end else begin + if (rx_udp_payload_axis_tvalid) begin + if ((!match_cond_reg && !no_match_reg) || + (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin + match_cond_reg <= match_cond; + no_match_reg <= no_match; + end + end else begin + match_cond_reg <= 0; + no_match_reg <= 0; + end + end +end + +assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; +assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; +assign tx_udp_ip_dscp = 0; +assign tx_udp_ip_ecn = 0; +assign tx_udp_ip_ttl = 64; +assign tx_udp_ip_source_ip = local_ip; +assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; +assign tx_udp_source_port = rx_udp_dest_port; +assign tx_udp_dest_port = rx_udp_source_port; +assign tx_udp_length = rx_udp_length; +assign tx_udp_checksum = 0; + +assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; +assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep; +assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; +assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; +assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; +assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; + +assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; +assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep; +assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; +assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; +assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; +assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; + +// Place first payload byte onto LEDs +reg valid_last = 0; +reg [7:0] led_reg = 0; + +always @(posedge clk) begin + if (rst) begin + led_reg <= 0; + end else begin + valid_last <= tx_udp_payload_axis_tvalid; + if (tx_udp_payload_axis_tvalid && !valid_last) begin + led_reg <= tx_udp_payload_axis_tdata; + end + end +end + +assign led = led_reg; + +assign uart_rxd = 1'b1; +assign uart_cts = 1'b1; +assign uart_rst_n = 1'b1; +assign uart_suspend_n = 1'b1; + +// assign qsfp_1_txd_1 = 64'h0707070707070707; +// assign qsfp_1_txc_1 = 8'hff; +assign qsfp_1_txd_2 = 64'h0707070707070707; +assign qsfp_1_txc_2 = 8'hff; +assign qsfp_1_txd_3 = 64'h0707070707070707; +assign qsfp_1_txc_3 = 8'hff; +assign qsfp_1_txd_4 = 64'h0707070707070707; +assign qsfp_1_txc_4 = 8'hff; + +assign qsfp_2_txd_1 = 64'h0707070707070707; +assign qsfp_2_txc_1 = 8'hff; +assign qsfp_2_txd_2 = 64'h0707070707070707; +assign qsfp_2_txc_2 = 8'hff; +assign qsfp_2_txd_3 = 64'h0707070707070707; +assign qsfp_2_txc_3 = 8'hff; +assign qsfp_2_txd_4 = 64'h0707070707070707; +assign qsfp_2_txc_4 = 8'hff; + +assign qsfp_3_txd_1 = 64'h0707070707070707; +assign qsfp_3_txc_1 = 8'hff; +assign qsfp_3_txd_2 = 64'h0707070707070707; +assign qsfp_3_txc_2 = 8'hff; +assign qsfp_3_txd_3 = 64'h0707070707070707; +assign qsfp_3_txc_3 = 8'hff; +assign qsfp_3_txd_4 = 64'h0707070707070707; +assign qsfp_3_txc_4 = 8'hff; + +assign qsfp_4_txd_1 = 64'h0707070707070707; +assign qsfp_4_txc_1 = 8'hff; +assign qsfp_4_txd_2 = 64'h0707070707070707; +assign qsfp_4_txc_2 = 8'hff; +assign qsfp_4_txd_3 = 64'h0707070707070707; +assign qsfp_4_txc_3 = 8'hff; +assign qsfp_4_txd_4 = 64'h0707070707070707; +assign qsfp_4_txc_4 = 8'hff; + +assign qsfp_5_txd_1 = 64'h0707070707070707; +assign qsfp_5_txc_1 = 8'hff; +assign qsfp_5_txd_2 = 64'h0707070707070707; +assign qsfp_5_txc_2 = 8'hff; +assign qsfp_5_txd_3 = 64'h0707070707070707; +assign qsfp_5_txc_3 = 8'hff; +assign qsfp_5_txd_4 = 64'h0707070707070707; +assign qsfp_5_txc_4 = 8'hff; + +assign qsfp_6_txd_1 = 64'h0707070707070707; +assign qsfp_6_txc_1 = 8'hff; +assign qsfp_6_txd_2 = 64'h0707070707070707; +assign qsfp_6_txc_2 = 8'hff; +assign qsfp_6_txd_3 = 64'h0707070707070707; +assign qsfp_6_txc_3 = 8'hff; +assign qsfp_6_txd_4 = 64'h0707070707070707; +assign qsfp_6_txc_4 = 8'hff; + +assign qsfp_7_txd_1 = 64'h0707070707070707; +assign qsfp_7_txc_1 = 8'hff; +assign qsfp_7_txd_2 = 64'h0707070707070707; +assign qsfp_7_txc_2 = 8'hff; +assign qsfp_7_txd_3 = 64'h0707070707070707; +assign qsfp_7_txc_3 = 8'hff; +assign qsfp_7_txd_4 = 64'h0707070707070707; +assign qsfp_7_txc_4 = 8'hff; + +assign qsfp_8_txd_1 = 64'h0707070707070707; +assign qsfp_8_txc_1 = 8'hff; +assign qsfp_8_txd_2 = 64'h0707070707070707; +assign qsfp_8_txc_2 = 8'hff; +assign qsfp_8_txd_3 = 64'h0707070707070707; +assign qsfp_8_txc_3 = 8'hff; +assign qsfp_8_txd_4 = 64'h0707070707070707; +assign qsfp_8_txc_4 = 8'hff; + +assign qsfp_9_txd_1 = 64'h0707070707070707; +assign qsfp_9_txc_1 = 8'hff; +assign qsfp_9_txd_2 = 64'h0707070707070707; +assign qsfp_9_txc_2 = 8'hff; +assign qsfp_9_txd_3 = 64'h0707070707070707; +assign qsfp_9_txc_3 = 8'hff; +assign qsfp_9_txd_4 = 64'h0707070707070707; +assign qsfp_9_txc_4 = 8'hff; + +assign fmc_qsfp_1_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_1_txc_1 = 8'hff; +assign fmc_qsfp_1_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_1_txc_2 = 8'hff; +assign fmc_qsfp_1_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_1_txc_3 = 8'hff; +assign fmc_qsfp_1_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_1_txc_4 = 8'hff; + +assign fmc_qsfp_2_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_2_txc_1 = 8'hff; +assign fmc_qsfp_2_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_2_txc_2 = 8'hff; +assign fmc_qsfp_2_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_2_txc_3 = 8'hff; +assign fmc_qsfp_2_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_2_txc_4 = 8'hff; + +assign fmc_qsfp_3_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_3_txc_1 = 8'hff; +assign fmc_qsfp_3_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_3_txc_2 = 8'hff; +assign fmc_qsfp_3_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_3_txc_3 = 8'hff; +assign fmc_qsfp_3_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_3_txc_4 = 8'hff; + +assign fmc_qsfp_4_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_4_txc_1 = 8'hff; +assign fmc_qsfp_4_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_4_txc_2 = 8'hff; +assign fmc_qsfp_4_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_4_txc_3 = 8'hff; +assign fmc_qsfp_4_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_4_txc_4 = 8'hff; + +assign fmc_qsfp_5_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_5_txc_1 = 8'hff; +assign fmc_qsfp_5_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_5_txc_2 = 8'hff; +assign fmc_qsfp_5_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_5_txc_3 = 8'hff; +assign fmc_qsfp_5_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_5_txc_4 = 8'hff; + +assign fmc_qsfp_6_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_6_txc_1 = 8'hff; +assign fmc_qsfp_6_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_6_txc_2 = 8'hff; +assign fmc_qsfp_6_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_6_txc_3 = 8'hff; +assign fmc_qsfp_6_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_6_txc_4 = 8'hff; + +eth_mac_10g_fifo #( + .ENABLE_PADDING(1), + .ENABLE_DIC(1), + .MIN_FRAME_LENGTH(64), + .TX_FIFO_DEPTH(4096), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(4096), + .RX_FRAME_FIFO(1) +) +eth_mac_10g_fifo_inst ( + .rx_clk(qsfp_1_rx_clk_1), + .rx_rst(qsfp_1_rx_rst_1), + .tx_clk(qsfp_1_tx_clk_1), + .tx_rst(qsfp_1_tx_rst_1), + .logic_clk(clk), + .logic_rst(rst), + + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tuser(tx_axis_tuser), + + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tuser(rx_axis_tuser), + + .xgmii_rxd(qsfp_1_rxd_1), + .xgmii_rxc(qsfp_1_rxc_1), + .xgmii_txd(qsfp_1_txd_1), + .xgmii_txc(qsfp_1_txc_1), + + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + .ifg_delay(8'd12) +); + +eth_axis_rx #( + .DATA_WIDTH(64) +) +eth_axis_rx_inst ( + .clk(clk), + .rst(rst), + // AXI input + .s_axis_tdata(rx_axis_tdata), + .s_axis_tkeep(rx_axis_tkeep), + .s_axis_tvalid(rx_axis_tvalid), + .s_axis_tready(rx_axis_tready), + .s_axis_tlast(rx_axis_tlast), + .s_axis_tuser(rx_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(rx_eth_hdr_valid), + .m_eth_hdr_ready(rx_eth_hdr_ready), + .m_eth_dest_mac(rx_eth_dest_mac), + .m_eth_src_mac(rx_eth_src_mac), + .m_eth_type(rx_eth_type), + .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Status signals + .busy(), + .error_header_early_termination() +); + +eth_axis_tx #( + .DATA_WIDTH(64) +) +eth_axis_tx_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(tx_eth_hdr_valid), + .s_eth_hdr_ready(tx_eth_hdr_ready), + .s_eth_dest_mac(tx_eth_dest_mac), + .s_eth_src_mac(tx_eth_src_mac), + .s_eth_type(tx_eth_type), + .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // AXI output + .m_axis_tdata(tx_axis_tdata), + .m_axis_tkeep(tx_axis_tkeep), + .m_axis_tvalid(tx_axis_tvalid), + .m_axis_tready(tx_axis_tready), + .m_axis_tlast(tx_axis_tlast), + .m_axis_tuser(tx_axis_tuser), + // Status signals + .busy() +); + +udp_complete_64 +udp_complete_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(rx_eth_hdr_valid), + .s_eth_hdr_ready(rx_eth_hdr_ready), + .s_eth_dest_mac(rx_eth_dest_mac), + .s_eth_src_mac(rx_eth_src_mac), + .s_eth_type(rx_eth_type), + .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(tx_eth_hdr_valid), + .m_eth_hdr_ready(tx_eth_hdr_ready), + .m_eth_dest_mac(tx_eth_dest_mac), + .m_eth_src_mac(tx_eth_src_mac), + .m_eth_type(tx_eth_type), + .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // IP frame input + .s_ip_hdr_valid(tx_ip_hdr_valid), + .s_ip_hdr_ready(tx_ip_hdr_ready), + .s_ip_dscp(tx_ip_dscp), + .s_ip_ecn(tx_ip_ecn), + .s_ip_length(tx_ip_length), + .s_ip_ttl(tx_ip_ttl), + .s_ip_protocol(tx_ip_protocol), + .s_ip_source_ip(tx_ip_source_ip), + .s_ip_dest_ip(tx_ip_dest_ip), + .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), + .s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep), + .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), + .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), + .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), + .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), + // IP frame output + .m_ip_hdr_valid(rx_ip_hdr_valid), + .m_ip_hdr_ready(rx_ip_hdr_ready), + .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), + .m_ip_eth_src_mac(rx_ip_eth_src_mac), + .m_ip_eth_type(rx_ip_eth_type), + .m_ip_version(rx_ip_version), + .m_ip_ihl(rx_ip_ihl), + .m_ip_dscp(rx_ip_dscp), + .m_ip_ecn(rx_ip_ecn), + .m_ip_length(rx_ip_length), + .m_ip_identification(rx_ip_identification), + .m_ip_flags(rx_ip_flags), + .m_ip_fragment_offset(rx_ip_fragment_offset), + .m_ip_ttl(rx_ip_ttl), + .m_ip_protocol(rx_ip_protocol), + .m_ip_header_checksum(rx_ip_header_checksum), + .m_ip_source_ip(rx_ip_source_ip), + .m_ip_dest_ip(rx_ip_dest_ip), + .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), + .m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep), + .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), + .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), + .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), + .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), + // UDP frame input + .s_udp_hdr_valid(tx_udp_hdr_valid), + .s_udp_hdr_ready(tx_udp_hdr_ready), + .s_udp_ip_dscp(tx_udp_ip_dscp), + .s_udp_ip_ecn(tx_udp_ip_ecn), + .s_udp_ip_ttl(tx_udp_ip_ttl), + .s_udp_ip_source_ip(tx_udp_ip_source_ip), + .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), + .s_udp_source_port(tx_udp_source_port), + .s_udp_dest_port(tx_udp_dest_port), + .s_udp_length(tx_udp_length), + .s_udp_checksum(tx_udp_checksum), + .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), + .s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep), + .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), + .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), + .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), + .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), + // UDP frame output + .m_udp_hdr_valid(rx_udp_hdr_valid), + .m_udp_hdr_ready(rx_udp_hdr_ready), + .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), + .m_udp_eth_src_mac(rx_udp_eth_src_mac), + .m_udp_eth_type(rx_udp_eth_type), + .m_udp_ip_version(rx_udp_ip_version), + .m_udp_ip_ihl(rx_udp_ip_ihl), + .m_udp_ip_dscp(rx_udp_ip_dscp), + .m_udp_ip_ecn(rx_udp_ip_ecn), + .m_udp_ip_length(rx_udp_ip_length), + .m_udp_ip_identification(rx_udp_ip_identification), + .m_udp_ip_flags(rx_udp_ip_flags), + .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), + .m_udp_ip_ttl(rx_udp_ip_ttl), + .m_udp_ip_protocol(rx_udp_ip_protocol), + .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), + .m_udp_ip_source_ip(rx_udp_ip_source_ip), + .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), + .m_udp_source_port(rx_udp_source_port), + .m_udp_dest_port(rx_udp_dest_port), + .m_udp_length(rx_udp_length), + .m_udp_checksum(rx_udp_checksum), + .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), + .m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep), + .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), + .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), + .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), + .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), + // Status signals + .ip_rx_busy(), + .ip_tx_busy(), + .udp_rx_busy(), + .udp_tx_busy(), + .ip_rx_error_header_early_termination(), + .ip_rx_error_payload_early_termination(), + .ip_rx_error_invalid_header(), + .ip_rx_error_invalid_checksum(), + .ip_tx_error_payload_early_termination(), + .ip_tx_error_arp_failed(), + .udp_rx_error_header_early_termination(), + .udp_rx_error_payload_early_termination(), + .udp_tx_error_payload_early_termination(), + // Configuration + .local_mac(local_mac), + .local_ip(local_ip), + .gateway_ip(gateway_ip), + .subnet_mask(subnet_mask), + .clear_arp_cache(1'b0) +); + +axis_fifo #( + .DEPTH(8192), + .DATA_WIDTH(64), + .KEEP_ENABLE(1), + .KEEP_WIDTH(8), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .FRAME_FIFO(0) +) +udp_payload_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), + .s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep), + .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), + .s_axis_tready(rx_fifo_udp_payload_axis_tready), + .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), + + // AXI output + .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), + .m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep), + .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), + .m_axis_tready(tx_fifo_udp_payload_axis_tready), + .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() +); + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v new file mode 100644 index 000000000..b933316a1 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v @@ -0,0 +1,901 @@ +/* + +Copyright (c) 2015-2017 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * I2C master + */ +module i2c_master ( + input wire clk, + input wire rst, + + /* + * Host interface + */ + input wire [6:0] s_axis_cmd_address, + input wire s_axis_cmd_start, + input wire s_axis_cmd_read, + input wire s_axis_cmd_write, + input wire s_axis_cmd_write_multiple, + input wire s_axis_cmd_stop, + input wire s_axis_cmd_valid, + output wire s_axis_cmd_ready, + + input wire [7:0] s_axis_data_tdata, + input wire s_axis_data_tvalid, + output wire s_axis_data_tready, + input wire s_axis_data_tlast, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * I2C interface + */ + input wire scl_i, + output wire scl_o, + output wire scl_t, + input wire sda_i, + output wire sda_o, + output wire sda_t, + + /* + * Status + */ + output wire busy, + output wire bus_control, + output wire bus_active, + output wire missed_ack, + + /* + * Configuration + */ + input wire [15:0] prescale, + input wire stop_on_idle +); + +/* + +I2C + +Read + __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ +sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/ + ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ +scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP + +Write + __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ +sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/ + ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ +scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP + +Commands: + +read + read data byte + set start to force generation of a start condition + start is implied when bus is inactive or active with write or different address + set stop to issue a stop condition after reading current byte + if stop is set with read command, then m_axis_data_tlast will be set + +write + write data byte + set start to force generation of a start condition + start is implied when bus is inactive or active with read or different address + set stop to issue a stop condition after writing current byte + +write multiple + write multiple data bytes (until s_axis_data_tlast) + set start to force generation of a start condition + start is implied when bus is inactive or active with read or different address + set stop to issue a stop condition after writing block + +stop + issue stop condition if bus is active + +Status: + +busy + module is communicating over the bus + +bus_control + module has control of bus in active state + +bus_active + bus is active, not necessarily controlled by this module + +missed_ack + strobed when a slave ack is missed + +Parameters: + +prescale + set prescale to 1/4 of the minimum clock period in units + of input clk cycles (prescale = Fclk / (FI2Cclk * 4)) + +stop_on_idle + automatically issue stop when command input is not valid + +Example of interfacing with tristate pins: +(this will work for any tristate bus) + +assign scl_i = scl_pin; +assign scl_pin = scl_t ? 1'bz : scl_o; +assign sda_i = sda_pin; +assign sda_pin = sda_t ? 1'bz : sda_o; + +Equivalent code that does not use *_t connections: +(we can get away with this because I2C is open-drain) + +assign scl_i = scl_pin; +assign scl_pin = scl_o ? 1'bz : 1'b0; +assign sda_i = sda_pin; +assign sda_pin = sda_o ? 1'bz : 1'b0; + +Example of two interconnected I2C devices: + +assign scl_1_i = scl_1_o & scl_2_o; +assign scl_2_i = scl_1_o & scl_2_o; +assign sda_1_i = sda_1_o & sda_2_o; +assign sda_2_i = sda_1_o & sda_2_o; + +Example of two I2C devices sharing the same pins: + +assign scl_1_i = scl_pin; +assign scl_2_i = scl_pin; +assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0; +assign sda_1_i = sda_pin; +assign sda_2_i = sda_pin; +assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0; + +Notes: + +scl_o should not be connected directly to scl_i, only via AND logic or a tristate +I/O pin. This would prevent devices from stretching the clock period. + +*/ + +localparam [4:0] + STATE_IDLE = 4'd0, + STATE_ACTIVE_WRITE = 4'd1, + STATE_ACTIVE_READ = 4'd2, + STATE_START_WAIT = 4'd3, + STATE_START = 4'd4, + STATE_ADDRESS_1 = 4'd5, + STATE_ADDRESS_2 = 4'd6, + STATE_WRITE_1 = 4'd7, + STATE_WRITE_2 = 4'd8, + STATE_WRITE_3 = 4'd9, + STATE_READ = 4'd10, + STATE_STOP = 4'd11; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +localparam [4:0] + PHY_STATE_IDLE = 5'd0, + PHY_STATE_ACTIVE = 5'd1, + PHY_STATE_REPEATED_START_1 = 5'd2, + PHY_STATE_REPEATED_START_2 = 5'd3, + PHY_STATE_START_1 = 5'd4, + PHY_STATE_START_2 = 5'd5, + PHY_STATE_WRITE_BIT_1 = 5'd6, + PHY_STATE_WRITE_BIT_2 = 5'd7, + PHY_STATE_WRITE_BIT_3 = 5'd8, + PHY_STATE_READ_BIT_1 = 5'd9, + PHY_STATE_READ_BIT_2 = 5'd10, + PHY_STATE_READ_BIT_3 = 5'd11, + PHY_STATE_READ_BIT_4 = 5'd12, + PHY_STATE_STOP_1 = 5'd13, + PHY_STATE_STOP_2 = 5'd14, + PHY_STATE_STOP_3 = 5'd15; + +reg [4:0] phy_state_reg = STATE_IDLE, phy_state_next; + +reg phy_start_bit; +reg phy_stop_bit; +reg phy_write_bit; +reg phy_read_bit; +reg phy_release_bus; + +reg phy_tx_data; + +reg phy_rx_data_reg = 1'b0, phy_rx_data_next; + +reg [6:0] addr_reg = 7'd0, addr_next; +reg [7:0] data_reg = 8'd0, data_next; +reg last_reg = 1'b0, last_next; + +reg mode_read_reg = 1'b0, mode_read_next; +reg mode_write_multiple_reg = 1'b0, mode_write_multiple_next; +reg mode_stop_reg = 1'b0, mode_stop_next; + +reg [16:0] delay_reg = 16'd0, delay_next; +reg delay_scl_reg = 1'b0, delay_scl_next; +reg delay_sda_reg = 1'b0, delay_sda_next; + +reg [3:0] bit_count_reg = 4'd0, bit_count_next; + +reg s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next; + +reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; +reg m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next; + +reg scl_i_reg = 1'b1; +reg sda_i_reg = 1'b1; + +reg scl_o_reg = 1'b1, scl_o_next; +reg sda_o_reg = 1'b1, sda_o_next; + +reg last_scl_i_reg = 1'b1; +reg last_sda_i_reg = 1'b1; + +reg busy_reg = 1'b0; +reg bus_active_reg = 1'b0; +reg bus_control_reg = 1'b0, bus_control_next; +reg missed_ack_reg = 1'b0, missed_ack_next; + +assign s_axis_cmd_ready = s_axis_cmd_ready_reg; + +assign s_axis_data_tready = s_axis_data_tready_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = m_axis_data_tlast_reg; + +assign scl_o = scl_o_reg; +assign scl_t = scl_o_reg; +assign sda_o = sda_o_reg; +assign sda_t = sda_o_reg; + +assign busy = busy_reg; +assign bus_active = bus_active_reg; +assign bus_control = bus_control_reg; +assign missed_ack = missed_ack_reg; + +wire scl_posedge = scl_i_reg & ~last_scl_i_reg; +wire scl_negedge = ~scl_i_reg & last_scl_i_reg; +wire sda_posedge = sda_i_reg & ~last_sda_i_reg; +wire sda_negedge = ~sda_i_reg & last_sda_i_reg; + +wire start_bit = sda_negedge & scl_i_reg; +wire stop_bit = sda_posedge & scl_i_reg; + +always @* begin + state_next = STATE_IDLE; + + phy_start_bit = 1'b0; + phy_stop_bit = 1'b0; + phy_write_bit = 1'b0; + phy_read_bit = 1'b0; + phy_tx_data = 1'b0; + phy_release_bus = 1'b0; + + addr_next = addr_reg; + data_next = data_reg; + last_next = last_reg; + + mode_read_next = mode_read_reg; + mode_write_multiple_next = mode_write_multiple_reg; + mode_stop_next = mode_stop_reg; + + bit_count_next = bit_count_reg; + + s_axis_cmd_ready_next = 1'b0; + + s_axis_data_tready_next = 1'b0; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + m_axis_data_tlast_next = m_axis_data_tlast_reg; + + missed_ack_next = 1'b0; + + // generate delays + if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin + // wait for phy operation + state_next = state_reg; + end else begin + // process states + case (state_reg) + STATE_IDLE: begin + // line idle + s_axis_cmd_ready_next = 1'b1; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + // start bit + if (bus_active) begin + state_next = STATE_START_WAIT; + end else begin + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + end else begin + // invalid or unspecified - ignore + state_next = STATE_IDLE; + end + end else begin + state_next = STATE_IDLE; + end + end + STATE_ACTIVE_WRITE: begin + // line active with current address and read/write mode + s_axis_cmd_ready_next = 1'b1; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin + // address or mode mismatch or forced start - repeated start + + // repeated start bit + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end else begin + // address and mode match + + // start write + s_axis_data_tready_next = 1'b1; + state_next = STATE_WRITE_1; + end + end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin + // stop command + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + // invalid or unspecified - ignore + state_next = STATE_ACTIVE_WRITE; + end + end else begin + if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin + // no waiting command and stop_on_idle selected, issue stop condition + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_ACTIVE_WRITE; + end + end + end + STATE_ACTIVE_READ: begin + // line active to current address + s_axis_cmd_ready_next = ~m_axis_data_tvalid; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin + // address or mode mismatch or forced start - repeated start + + // write nack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // repeated start bit + state_next = STATE_START; + end else begin + // address and mode match + + // write ack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b0; + // start next read + bit_count_next = 4'd8; + data_next = 8'd0; + state_next = STATE_READ; + end + end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin + // stop command + // write nack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // send stop bit + state_next = STATE_STOP; + end else begin + // invalid or unspecified - ignore + state_next = STATE_ACTIVE_READ; + end + end else begin + if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin + // no waiting command and stop_on_idle selected, issue stop condition + // write ack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // send stop bit + state_next = STATE_STOP; + end else begin + state_next = STATE_ACTIVE_READ; + end + end + end + STATE_START_WAIT: begin + // wait for bus idle + + if (bus_active) begin + state_next = STATE_START_WAIT; + end else begin + // bus is idle, take control + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + end + STATE_START: begin + // send start bit + + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + STATE_ADDRESS_1: begin + // send address + bit_count_next = bit_count_reg - 1; + if (bit_count_reg > 1) begin + // send address + phy_write_bit = 1'b1; + phy_tx_data = addr_reg[bit_count_reg-2]; + state_next = STATE_ADDRESS_1; + end else if (bit_count_reg > 0) begin + // send read/write bit + phy_write_bit = 1'b1; + phy_tx_data = mode_read_reg; + state_next = STATE_ADDRESS_1; + end else begin + // read ack bit + phy_read_bit = 1'b1; + state_next = STATE_ADDRESS_2; + end + end + STATE_ADDRESS_2: begin + // read ack bit + missed_ack_next = phy_rx_data_reg; + + if (mode_read_reg) begin + // start read + bit_count_next = 4'd8; + data_next = 1'b0; + state_next = STATE_READ; + end else begin + // start write + s_axis_data_tready_next = 1'b1; + state_next = STATE_WRITE_1; + end + end + STATE_WRITE_1: begin + s_axis_data_tready_next = 1'b1; + + if (s_axis_data_tready & s_axis_data_tvalid) begin + // got data, start write + data_next = s_axis_data_tdata; + last_next = s_axis_data_tlast; + bit_count_next = 4'd8; + s_axis_data_tready_next = 1'b0; + state_next = STATE_WRITE_2; + end else begin + // wait for data + state_next = STATE_WRITE_1; + end + end + STATE_WRITE_2: begin + // send data + bit_count_next = bit_count_reg - 1; + if (bit_count_reg > 0) begin + // write data bit + phy_write_bit = 1'b1; + phy_tx_data = data_reg[bit_count_reg-1]; + state_next = STATE_WRITE_2; + end else begin + // read ack bit + phy_read_bit = 1'b1; + state_next = STATE_WRITE_3; + end + end + STATE_WRITE_3: begin + // read ack bit + missed_ack_next = phy_rx_data_reg; + + if (mode_write_multiple_reg && !last_reg) begin + // more to write + state_next = STATE_WRITE_1; + end else if (mode_stop_reg) begin + // last cycle and stop selected + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + // otherwise, return to bus active state + state_next = STATE_ACTIVE_WRITE; + end + end + STATE_READ: begin + // read data + + bit_count_next = bit_count_reg - 1; + data_next = {data_reg[6:0], phy_rx_data_reg}; + if (bit_count_reg > 0) begin + // read next bit + phy_read_bit = 1'b1; + state_next = STATE_READ; + end else begin + // output data word + m_axis_data_tdata_next = data_next; + m_axis_data_tvalid_next = 1'b1; + m_axis_data_tlast_next = 1'b0; + if (mode_stop_reg) begin + // send nack and stop + m_axis_data_tlast_next = 1'b1; + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + state_next = STATE_STOP; + end else begin + // return to bus active state + state_next = STATE_ACTIVE_READ; + end + end + end + STATE_STOP: begin + // send stop bit + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end + endcase + end +end + +always @* begin + phy_state_next = PHY_STATE_IDLE; + + phy_rx_data_next = phy_rx_data_reg; + + delay_next = delay_reg; + delay_scl_next = delay_scl_reg; + delay_sda_next = delay_sda_reg; + + scl_o_next = scl_o_reg; + sda_o_next = sda_o_reg; + + bus_control_next = bus_control_reg; + + if (phy_release_bus) begin + // release bus and return to idle state + sda_o_next = 1'b1; + scl_o_next = 1'b1; + delay_scl_next = 1'b0; + delay_sda_next = 1'b0; + delay_next = 1'b0; + phy_state_next = PHY_STATE_IDLE; + end else if (delay_scl_reg) begin + // wait for SCL to match command + delay_scl_next = scl_o_reg & ~scl_i_reg; + phy_state_next = phy_state_reg; + end else if (delay_sda_reg) begin + // wait for SDA to match command + delay_sda_next = sda_o_reg & ~sda_i_reg; + phy_state_next = phy_state_reg; + end else if (delay_reg > 0) begin + // time delay + delay_next = delay_reg - 1; + phy_state_next = phy_state_reg; + end else begin + case (phy_state_reg) + PHY_STATE_IDLE: begin + // bus idle - wait for start command + sda_o_next = 1'b1; + scl_o_next = 1'b1; + if (phy_start_bit) begin + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_1; + end else begin + phy_state_next = PHY_STATE_IDLE; + end + end + PHY_STATE_ACTIVE: begin + // bus active + if (phy_start_bit) begin + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_REPEATED_START_1; + end else if (phy_write_bit) begin + sda_o_next = phy_tx_data; + delay_next = prescale; + phy_state_next = PHY_STATE_WRITE_BIT_1; + end else if (phy_read_bit) begin + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_1; + end else if (phy_stop_bit) begin + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_1; + end else begin + phy_state_next = PHY_STATE_ACTIVE; + end + end + PHY_STATE_REPEATED_START_1: begin + // generate repeated start bit + // ______ + // sda XXX/ \_______ + // _______ + // scl ______/ \___ + // + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_REPEATED_START_2; + end + PHY_STATE_REPEATED_START_2: begin + // generate repeated start bit + // ______ + // sda XXX/ \_______ + // _______ + // scl ______/ \___ + // + + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_1; + end + PHY_STATE_START_1: begin + // generate start bit + // ___ + // sda \_______ + // _______ + // scl \___ + // + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_2; + end + PHY_STATE_START_2: begin + // generate start bit + // ___ + // sda \_______ + // _______ + // scl \___ + // + + bus_control_next = 1'b1; + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_WRITE_BIT_1: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale << 1; + phy_state_next = PHY_STATE_WRITE_BIT_2; + end + PHY_STATE_WRITE_BIT_2: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_WRITE_BIT_3; + end + PHY_STATE_WRITE_BIT_3: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_READ_BIT_1: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_2; + end + PHY_STATE_READ_BIT_2: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_rx_data_next = sda_i_reg; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_3; + end + PHY_STATE_READ_BIT_3: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_4; + end + PHY_STATE_READ_BIT_4: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_STOP_1: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_2; + end + PHY_STATE_STOP_2: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_3; + end + PHY_STATE_STOP_3: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + bus_control_next = 1'b0; + phy_state_next = PHY_STATE_IDLE; + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + phy_state_reg <= phy_state_next; + + phy_rx_data_reg <= phy_rx_data_next; + + addr_reg <= addr_next; + data_reg <= data_next; + last_reg <= last_next; + + mode_read_reg <= mode_read_next; + mode_write_multiple_reg <= mode_write_multiple_next; + mode_stop_reg <= mode_stop_next; + + delay_reg <= delay_next; + delay_scl_reg <= delay_scl_next; + delay_sda_reg <= delay_sda_next; + + bit_count_reg <= bit_count_next; + + s_axis_cmd_ready_reg <= s_axis_cmd_ready_next; + + s_axis_data_tready_reg <= s_axis_data_tready_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tlast_reg <= m_axis_data_tlast_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + scl_i_reg <= scl_i; + sda_i_reg <= sda_i; + + scl_o_reg <= scl_o_next; + sda_o_reg <= sda_o_next; + + last_scl_i_reg <= scl_i_reg; + last_sda_i_reg <= sda_i_reg; + + busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE); + + if (start_bit) begin + bus_active_reg <= 1'b1; + end else if (stop_bit) begin + bus_active_reg <= 1'b0; + end else begin + bus_active_reg <= bus_active_reg; + end + + bus_control_reg <= bus_control_next; + missed_ack_reg <= missed_ack_next; + + if (rst) begin + state_reg <= STATE_IDLE; + phy_state_reg <= PHY_STATE_IDLE; + delay_reg <= 16'd0; + delay_scl_reg <= 1'b0; + delay_sda_reg <= 1'b0; + s_axis_cmd_ready_reg <= 1'b0; + s_axis_data_tready_reg <= 1'b0; + m_axis_data_tvalid_reg <= 1'b0; + scl_o_reg <= 1'b1; + sda_o_reg <= 1'b1; + busy_reg <= 1'b0; + bus_active_reg <= 1'b0; + bus_control_reg <= 1'b0; + missed_ack_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v new file mode 100644 index 000000000..645319304 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v @@ -0,0 +1,62 @@ +/* + +Copyright (c) 2014-2017 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule + +`resetall diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile new file mode 100644 index 000000000..d840fbe00 --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile @@ -0,0 +1,95 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g_fifo.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_rx.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_tx.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_complete_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_checksum_gen_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_complete_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/ip_arb_mux.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_cache.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_rx.v +VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_tx.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_arb_mux.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/arbiter.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/priority_encoder.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v +VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v + +# module parameters +#export PARAM_A := value + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + +# COMPILE_ARGS += -P $(TOPLEVEL).A=$(PARAM_A) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + +# COMPILE_ARGS += -GA=$(PARAM_A) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..73d701d9b --- /dev/null +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,865 @@ +""" + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os + +from scapy.layers.l2 import Ether, ARP +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + dut.btn.setimmediatevalue(0) + dut.sw.setimmediatevalue(0) + + dut.uart_txd.setimmediatevalue(1) + dut.uart_rts.setimmediatevalue(1) + + # Ethernet + cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1, dut.qsfp_1_rx_clk_1, dut.qsfp_1_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1, dut.qsfp_1_tx_clk_1, dut.qsfp_1_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2, dut.qsfp_1_rx_clk_2, dut.qsfp_1_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2, dut.qsfp_1_tx_clk_2, dut.qsfp_1_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3, dut.qsfp_1_rx_clk_3, dut.qsfp_1_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_1_4_source = XgmiiSource(dut.qsfp_1_rxd_4, dut.qsfp_1_rxc_4, dut.qsfp_1_rx_clk_4, dut.qsfp_1_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_1_4_sink = XgmiiSink(dut.qsfp_1_txd_4, dut.qsfp_1_txc_4, dut.qsfp_1_tx_clk_4, dut.qsfp_1_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_2_1_source = XgmiiSource(dut.qsfp_2_rxd_1, dut.qsfp_2_rxc_1, dut.qsfp_2_rx_clk_1, dut.qsfp_2_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_2_1_sink = XgmiiSink(dut.qsfp_2_txd_1, dut.qsfp_2_txc_1, dut.qsfp_2_tx_clk_1, dut.qsfp_2_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_2_2_source = XgmiiSource(dut.qsfp_2_rxd_2, dut.qsfp_2_rxc_2, dut.qsfp_2_rx_clk_2, dut.qsfp_2_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_2_2_sink = XgmiiSink(dut.qsfp_2_txd_2, dut.qsfp_2_txc_2, dut.qsfp_2_tx_clk_2, dut.qsfp_2_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_2_3_source = XgmiiSource(dut.qsfp_2_rxd_3, dut.qsfp_2_rxc_3, dut.qsfp_2_rx_clk_3, dut.qsfp_2_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_2_3_sink = XgmiiSink(dut.qsfp_2_txd_3, dut.qsfp_2_txc_3, dut.qsfp_2_tx_clk_3, dut.qsfp_2_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_2_4_source = XgmiiSource(dut.qsfp_2_rxd_4, dut.qsfp_2_rxc_4, dut.qsfp_2_rx_clk_4, dut.qsfp_2_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_2_4_sink = XgmiiSink(dut.qsfp_2_txd_4, dut.qsfp_2_txc_4, dut.qsfp_2_tx_clk_4, dut.qsfp_2_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_3_1_source = XgmiiSource(dut.qsfp_3_rxd_1, dut.qsfp_3_rxc_1, dut.qsfp_3_rx_clk_1, dut.qsfp_3_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_3_1_sink = XgmiiSink(dut.qsfp_3_txd_1, dut.qsfp_3_txc_1, dut.qsfp_3_tx_clk_1, dut.qsfp_3_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_3_2_source = XgmiiSource(dut.qsfp_3_rxd_2, dut.qsfp_3_rxc_2, dut.qsfp_3_rx_clk_2, dut.qsfp_3_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_3_2_sink = XgmiiSink(dut.qsfp_3_txd_2, dut.qsfp_3_txc_2, dut.qsfp_3_tx_clk_2, dut.qsfp_3_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_3_3_source = XgmiiSource(dut.qsfp_3_rxd_3, dut.qsfp_3_rxc_3, dut.qsfp_3_rx_clk_3, dut.qsfp_3_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_3_3_sink = XgmiiSink(dut.qsfp_3_txd_3, dut.qsfp_3_txc_3, dut.qsfp_3_tx_clk_3, dut.qsfp_3_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_3_4_source = XgmiiSource(dut.qsfp_3_rxd_4, dut.qsfp_3_rxc_4, dut.qsfp_3_rx_clk_4, dut.qsfp_3_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_3_4_sink = XgmiiSink(dut.qsfp_3_txd_4, dut.qsfp_3_txc_4, dut.qsfp_3_tx_clk_4, dut.qsfp_3_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp_4_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_4_1_source = XgmiiSource(dut.qsfp_4_rxd_1, dut.qsfp_4_rxc_1, dut.qsfp_4_rx_clk_1, dut.qsfp_4_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_4_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_4_1_sink = XgmiiSink(dut.qsfp_4_txd_1, dut.qsfp_4_txc_1, dut.qsfp_4_tx_clk_1, dut.qsfp_4_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_4_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_4_2_source = XgmiiSource(dut.qsfp_4_rxd_2, dut.qsfp_4_rxc_2, dut.qsfp_4_rx_clk_2, dut.qsfp_4_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_4_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_4_2_sink = XgmiiSink(dut.qsfp_4_txd_2, dut.qsfp_4_txc_2, dut.qsfp_4_tx_clk_2, dut.qsfp_4_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_4_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_4_3_source = XgmiiSource(dut.qsfp_4_rxd_3, dut.qsfp_4_rxc_3, dut.qsfp_4_rx_clk_3, dut.qsfp_4_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_4_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_4_3_sink = XgmiiSink(dut.qsfp_4_txd_3, dut.qsfp_4_txc_3, dut.qsfp_4_tx_clk_3, dut.qsfp_4_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_4_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_4_4_source = XgmiiSource(dut.qsfp_4_rxd_4, dut.qsfp_4_rxc_4, dut.qsfp_4_rx_clk_4, dut.qsfp_4_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_4_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_4_4_sink = XgmiiSink(dut.qsfp_4_txd_4, dut.qsfp_4_txc_4, dut.qsfp_4_tx_clk_4, dut.qsfp_4_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp_5_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_5_1_source = XgmiiSource(dut.qsfp_5_rxd_1, dut.qsfp_5_rxc_1, dut.qsfp_5_rx_clk_1, dut.qsfp_5_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_5_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_5_1_sink = XgmiiSink(dut.qsfp_5_txd_1, dut.qsfp_5_txc_1, dut.qsfp_5_tx_clk_1, dut.qsfp_5_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_5_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_5_2_source = XgmiiSource(dut.qsfp_5_rxd_2, dut.qsfp_5_rxc_2, dut.qsfp_5_rx_clk_2, dut.qsfp_5_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_5_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_5_2_sink = XgmiiSink(dut.qsfp_5_txd_2, dut.qsfp_5_txc_2, dut.qsfp_5_tx_clk_2, dut.qsfp_5_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_5_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_5_3_source = XgmiiSource(dut.qsfp_5_rxd_3, dut.qsfp_5_rxc_3, dut.qsfp_5_rx_clk_3, dut.qsfp_5_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_5_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_5_3_sink = XgmiiSink(dut.qsfp_5_txd_3, dut.qsfp_5_txc_3, dut.qsfp_5_tx_clk_3, dut.qsfp_5_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_5_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_5_4_source = XgmiiSource(dut.qsfp_5_rxd_4, dut.qsfp_5_rxc_4, dut.qsfp_5_rx_clk_4, dut.qsfp_5_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_5_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_5_4_sink = XgmiiSink(dut.qsfp_5_txd_4, dut.qsfp_5_txc_4, dut.qsfp_5_tx_clk_4, dut.qsfp_5_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp_6_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_6_1_source = XgmiiSource(dut.qsfp_6_rxd_1, dut.qsfp_6_rxc_1, dut.qsfp_6_rx_clk_1, dut.qsfp_6_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_6_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_6_1_sink = XgmiiSink(dut.qsfp_6_txd_1, dut.qsfp_6_txc_1, dut.qsfp_6_tx_clk_1, dut.qsfp_6_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_6_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_6_2_source = XgmiiSource(dut.qsfp_6_rxd_2, dut.qsfp_6_rxc_2, dut.qsfp_6_rx_clk_2, dut.qsfp_6_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_6_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_6_2_sink = XgmiiSink(dut.qsfp_6_txd_2, dut.qsfp_6_txc_2, dut.qsfp_6_tx_clk_2, dut.qsfp_6_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_6_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_6_3_source = XgmiiSource(dut.qsfp_6_rxd_3, dut.qsfp_6_rxc_3, dut.qsfp_6_rx_clk_3, dut.qsfp_6_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_6_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_6_3_sink = XgmiiSink(dut.qsfp_6_txd_3, dut.qsfp_6_txc_3, dut.qsfp_6_tx_clk_3, dut.qsfp_6_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_6_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_6_4_source = XgmiiSource(dut.qsfp_6_rxd_4, dut.qsfp_6_rxc_4, dut.qsfp_6_rx_clk_4, dut.qsfp_6_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_6_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_6_4_sink = XgmiiSink(dut.qsfp_6_txd_4, dut.qsfp_6_txc_4, dut.qsfp_6_tx_clk_4, dut.qsfp_6_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp_7_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_7_1_source = XgmiiSource(dut.qsfp_7_rxd_1, dut.qsfp_7_rxc_1, dut.qsfp_7_rx_clk_1, dut.qsfp_7_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_7_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_7_1_sink = XgmiiSink(dut.qsfp_7_txd_1, dut.qsfp_7_txc_1, dut.qsfp_7_tx_clk_1, dut.qsfp_7_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_7_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_7_2_source = XgmiiSource(dut.qsfp_7_rxd_2, dut.qsfp_7_rxc_2, dut.qsfp_7_rx_clk_2, dut.qsfp_7_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_7_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_7_2_sink = XgmiiSink(dut.qsfp_7_txd_2, dut.qsfp_7_txc_2, dut.qsfp_7_tx_clk_2, dut.qsfp_7_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_7_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_7_3_source = XgmiiSource(dut.qsfp_7_rxd_3, dut.qsfp_7_rxc_3, dut.qsfp_7_rx_clk_3, dut.qsfp_7_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_7_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_7_3_sink = XgmiiSink(dut.qsfp_7_txd_3, dut.qsfp_7_txc_3, dut.qsfp_7_tx_clk_3, dut.qsfp_7_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_7_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_7_4_source = XgmiiSource(dut.qsfp_7_rxd_4, dut.qsfp_7_rxc_4, dut.qsfp_7_rx_clk_4, dut.qsfp_7_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_7_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_7_4_sink = XgmiiSink(dut.qsfp_7_txd_4, dut.qsfp_7_txc_4, dut.qsfp_7_tx_clk_4, dut.qsfp_7_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp_8_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_8_1_source = XgmiiSource(dut.qsfp_8_rxd_1, dut.qsfp_8_rxc_1, dut.qsfp_8_rx_clk_1, dut.qsfp_8_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_8_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_8_1_sink = XgmiiSink(dut.qsfp_8_txd_1, dut.qsfp_8_txc_1, dut.qsfp_8_tx_clk_1, dut.qsfp_8_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_8_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_8_2_source = XgmiiSource(dut.qsfp_8_rxd_2, dut.qsfp_8_rxc_2, dut.qsfp_8_rx_clk_2, dut.qsfp_8_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_8_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_8_2_sink = XgmiiSink(dut.qsfp_8_txd_2, dut.qsfp_8_txc_2, dut.qsfp_8_tx_clk_2, dut.qsfp_8_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_8_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_8_3_source = XgmiiSource(dut.qsfp_8_rxd_3, dut.qsfp_8_rxc_3, dut.qsfp_8_rx_clk_3, dut.qsfp_8_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_8_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_8_3_sink = XgmiiSink(dut.qsfp_8_txd_3, dut.qsfp_8_txc_3, dut.qsfp_8_tx_clk_3, dut.qsfp_8_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_8_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_8_4_source = XgmiiSource(dut.qsfp_8_rxd_4, dut.qsfp_8_rxc_4, dut.qsfp_8_rx_clk_4, dut.qsfp_8_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_8_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_8_4_sink = XgmiiSink(dut.qsfp_8_txd_4, dut.qsfp_8_txc_4, dut.qsfp_8_tx_clk_4, dut.qsfp_8_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp_9_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_9_1_source = XgmiiSource(dut.qsfp_9_rxd_1, dut.qsfp_9_rxc_1, dut.qsfp_9_rx_clk_1, dut.qsfp_9_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_9_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_9_1_sink = XgmiiSink(dut.qsfp_9_txd_1, dut.qsfp_9_txc_1, dut.qsfp_9_tx_clk_1, dut.qsfp_9_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_9_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_9_2_source = XgmiiSource(dut.qsfp_9_rxd_2, dut.qsfp_9_rxc_2, dut.qsfp_9_rx_clk_2, dut.qsfp_9_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_9_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_9_2_sink = XgmiiSink(dut.qsfp_9_txd_2, dut.qsfp_9_txc_2, dut.qsfp_9_tx_clk_2, dut.qsfp_9_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_9_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_9_3_source = XgmiiSource(dut.qsfp_9_rxd_3, dut.qsfp_9_rxc_3, dut.qsfp_9_rx_clk_3, dut.qsfp_9_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_9_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_9_3_sink = XgmiiSink(dut.qsfp_9_txd_3, dut.qsfp_9_txc_3, dut.qsfp_9_tx_clk_3, dut.qsfp_9_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_9_rx_clk_4, 2.56, units="ns").start()) + self.qsfp_9_4_source = XgmiiSource(dut.qsfp_9_rxd_4, dut.qsfp_9_rxc_4, dut.qsfp_9_rx_clk_4, dut.qsfp_9_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_9_tx_clk_4, 2.56, units="ns").start()) + self.qsfp_9_4_sink = XgmiiSink(dut.qsfp_9_txd_4, dut.qsfp_9_txc_4, dut.qsfp_9_tx_clk_4, dut.qsfp_9_tx_rst_4) + + cocotb.start_soon(Clock(dut.fmc_qsfp_1_rx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_1_1_source = XgmiiSource(dut.fmc_qsfp_1_rxd_1, dut.fmc_qsfp_1_rxc_1, dut.fmc_qsfp_1_rx_clk_1, dut.fmc_qsfp_1_rx_rst_1) + cocotb.start_soon(Clock(dut.fmc_qsfp_1_tx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_1_1_sink = XgmiiSink(dut.fmc_qsfp_1_txd_1, dut.fmc_qsfp_1_txc_1, dut.fmc_qsfp_1_tx_clk_1, dut.fmc_qsfp_1_tx_rst_1) + + cocotb.start_soon(Clock(dut.fmc_qsfp_1_rx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_1_2_source = XgmiiSource(dut.fmc_qsfp_1_rxd_2, dut.fmc_qsfp_1_rxc_2, dut.fmc_qsfp_1_rx_clk_2, dut.fmc_qsfp_1_rx_rst_2) + cocotb.start_soon(Clock(dut.fmc_qsfp_1_tx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_1_2_sink = XgmiiSink(dut.fmc_qsfp_1_txd_2, dut.fmc_qsfp_1_txc_2, dut.fmc_qsfp_1_tx_clk_2, dut.fmc_qsfp_1_tx_rst_2) + + cocotb.start_soon(Clock(dut.fmc_qsfp_1_rx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_1_3_source = XgmiiSource(dut.fmc_qsfp_1_rxd_3, dut.fmc_qsfp_1_rxc_3, dut.fmc_qsfp_1_rx_clk_3, dut.fmc_qsfp_1_rx_rst_3) + cocotb.start_soon(Clock(dut.fmc_qsfp_1_tx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_1_3_sink = XgmiiSink(dut.fmc_qsfp_1_txd_3, dut.fmc_qsfp_1_txc_3, dut.fmc_qsfp_1_tx_clk_3, dut.fmc_qsfp_1_tx_rst_3) + + cocotb.start_soon(Clock(dut.fmc_qsfp_1_rx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_1_4_source = XgmiiSource(dut.fmc_qsfp_1_rxd_4, dut.fmc_qsfp_1_rxc_4, dut.fmc_qsfp_1_rx_clk_4, dut.fmc_qsfp_1_rx_rst_4) + cocotb.start_soon(Clock(dut.fmc_qsfp_1_tx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_1_4_sink = XgmiiSink(dut.fmc_qsfp_1_txd_4, dut.fmc_qsfp_1_txc_4, dut.fmc_qsfp_1_tx_clk_4, dut.fmc_qsfp_1_tx_rst_4) + + cocotb.start_soon(Clock(dut.fmc_qsfp_2_rx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_2_1_source = XgmiiSource(dut.fmc_qsfp_2_rxd_1, dut.fmc_qsfp_2_rxc_1, dut.fmc_qsfp_2_rx_clk_1, dut.fmc_qsfp_2_rx_rst_1) + cocotb.start_soon(Clock(dut.fmc_qsfp_2_tx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_2_1_sink = XgmiiSink(dut.fmc_qsfp_2_txd_1, dut.fmc_qsfp_2_txc_1, dut.fmc_qsfp_2_tx_clk_1, dut.fmc_qsfp_2_tx_rst_1) + + cocotb.start_soon(Clock(dut.fmc_qsfp_2_rx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_2_2_source = XgmiiSource(dut.fmc_qsfp_2_rxd_2, dut.fmc_qsfp_2_rxc_2, dut.fmc_qsfp_2_rx_clk_2, dut.fmc_qsfp_2_rx_rst_2) + cocotb.start_soon(Clock(dut.fmc_qsfp_2_tx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_2_2_sink = XgmiiSink(dut.fmc_qsfp_2_txd_2, dut.fmc_qsfp_2_txc_2, dut.fmc_qsfp_2_tx_clk_2, dut.fmc_qsfp_2_tx_rst_2) + + cocotb.start_soon(Clock(dut.fmc_qsfp_2_rx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_2_3_source = XgmiiSource(dut.fmc_qsfp_2_rxd_3, dut.fmc_qsfp_2_rxc_3, dut.fmc_qsfp_2_rx_clk_3, dut.fmc_qsfp_2_rx_rst_3) + cocotb.start_soon(Clock(dut.fmc_qsfp_2_tx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_2_3_sink = XgmiiSink(dut.fmc_qsfp_2_txd_3, dut.fmc_qsfp_2_txc_3, dut.fmc_qsfp_2_tx_clk_3, dut.fmc_qsfp_2_tx_rst_3) + + cocotb.start_soon(Clock(dut.fmc_qsfp_2_rx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_2_4_source = XgmiiSource(dut.fmc_qsfp_2_rxd_4, dut.fmc_qsfp_2_rxc_4, dut.fmc_qsfp_2_rx_clk_4, dut.fmc_qsfp_2_rx_rst_4) + cocotb.start_soon(Clock(dut.fmc_qsfp_2_tx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_2_4_sink = XgmiiSink(dut.fmc_qsfp_2_txd_4, dut.fmc_qsfp_2_txc_4, dut.fmc_qsfp_2_tx_clk_4, dut.fmc_qsfp_2_tx_rst_4) + + cocotb.start_soon(Clock(dut.fmc_qsfp_3_rx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_3_1_source = XgmiiSource(dut.fmc_qsfp_3_rxd_1, dut.fmc_qsfp_3_rxc_1, dut.fmc_qsfp_3_rx_clk_1, dut.fmc_qsfp_3_rx_rst_1) + cocotb.start_soon(Clock(dut.fmc_qsfp_3_tx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_3_1_sink = XgmiiSink(dut.fmc_qsfp_3_txd_1, dut.fmc_qsfp_3_txc_1, dut.fmc_qsfp_3_tx_clk_1, dut.fmc_qsfp_3_tx_rst_1) + + cocotb.start_soon(Clock(dut.fmc_qsfp_3_rx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_3_2_source = XgmiiSource(dut.fmc_qsfp_3_rxd_2, dut.fmc_qsfp_3_rxc_2, dut.fmc_qsfp_3_rx_clk_2, dut.fmc_qsfp_3_rx_rst_2) + cocotb.start_soon(Clock(dut.fmc_qsfp_3_tx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_3_2_sink = XgmiiSink(dut.fmc_qsfp_3_txd_2, dut.fmc_qsfp_3_txc_2, dut.fmc_qsfp_3_tx_clk_2, dut.fmc_qsfp_3_tx_rst_2) + + cocotb.start_soon(Clock(dut.fmc_qsfp_3_rx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_3_3_source = XgmiiSource(dut.fmc_qsfp_3_rxd_3, dut.fmc_qsfp_3_rxc_3, dut.fmc_qsfp_3_rx_clk_3, dut.fmc_qsfp_3_rx_rst_3) + cocotb.start_soon(Clock(dut.fmc_qsfp_3_tx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_3_3_sink = XgmiiSink(dut.fmc_qsfp_3_txd_3, dut.fmc_qsfp_3_txc_3, dut.fmc_qsfp_3_tx_clk_3, dut.fmc_qsfp_3_tx_rst_3) + + cocotb.start_soon(Clock(dut.fmc_qsfp_3_rx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_3_4_source = XgmiiSource(dut.fmc_qsfp_3_rxd_4, dut.fmc_qsfp_3_rxc_4, dut.fmc_qsfp_3_rx_clk_4, dut.fmc_qsfp_3_rx_rst_4) + cocotb.start_soon(Clock(dut.fmc_qsfp_3_tx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_3_4_sink = XgmiiSink(dut.fmc_qsfp_3_txd_4, dut.fmc_qsfp_3_txc_4, dut.fmc_qsfp_3_tx_clk_4, dut.fmc_qsfp_3_tx_rst_4) + + cocotb.start_soon(Clock(dut.fmc_qsfp_4_rx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_4_1_source = XgmiiSource(dut.fmc_qsfp_4_rxd_1, dut.fmc_qsfp_4_rxc_1, dut.fmc_qsfp_4_rx_clk_1, dut.fmc_qsfp_4_rx_rst_1) + cocotb.start_soon(Clock(dut.fmc_qsfp_4_tx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_4_1_sink = XgmiiSink(dut.fmc_qsfp_4_txd_1, dut.fmc_qsfp_4_txc_1, dut.fmc_qsfp_4_tx_clk_1, dut.fmc_qsfp_4_tx_rst_1) + + cocotb.start_soon(Clock(dut.fmc_qsfp_4_rx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_4_2_source = XgmiiSource(dut.fmc_qsfp_4_rxd_2, dut.fmc_qsfp_4_rxc_2, dut.fmc_qsfp_4_rx_clk_2, dut.fmc_qsfp_4_rx_rst_2) + cocotb.start_soon(Clock(dut.fmc_qsfp_4_tx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_4_2_sink = XgmiiSink(dut.fmc_qsfp_4_txd_2, dut.fmc_qsfp_4_txc_2, dut.fmc_qsfp_4_tx_clk_2, dut.fmc_qsfp_4_tx_rst_2) + + cocotb.start_soon(Clock(dut.fmc_qsfp_4_rx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_4_3_source = XgmiiSource(dut.fmc_qsfp_4_rxd_3, dut.fmc_qsfp_4_rxc_3, dut.fmc_qsfp_4_rx_clk_3, dut.fmc_qsfp_4_rx_rst_3) + cocotb.start_soon(Clock(dut.fmc_qsfp_4_tx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_4_3_sink = XgmiiSink(dut.fmc_qsfp_4_txd_3, dut.fmc_qsfp_4_txc_3, dut.fmc_qsfp_4_tx_clk_3, dut.fmc_qsfp_4_tx_rst_3) + + cocotb.start_soon(Clock(dut.fmc_qsfp_4_rx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_4_4_source = XgmiiSource(dut.fmc_qsfp_4_rxd_4, dut.fmc_qsfp_4_rxc_4, dut.fmc_qsfp_4_rx_clk_4, dut.fmc_qsfp_4_rx_rst_4) + cocotb.start_soon(Clock(dut.fmc_qsfp_4_tx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_4_4_sink = XgmiiSink(dut.fmc_qsfp_4_txd_4, dut.fmc_qsfp_4_txc_4, dut.fmc_qsfp_4_tx_clk_4, dut.fmc_qsfp_4_tx_rst_4) + + cocotb.start_soon(Clock(dut.fmc_qsfp_5_rx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_5_1_source = XgmiiSource(dut.fmc_qsfp_5_rxd_1, dut.fmc_qsfp_5_rxc_1, dut.fmc_qsfp_5_rx_clk_1, dut.fmc_qsfp_5_rx_rst_1) + cocotb.start_soon(Clock(dut.fmc_qsfp_5_tx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_5_1_sink = XgmiiSink(dut.fmc_qsfp_5_txd_1, dut.fmc_qsfp_5_txc_1, dut.fmc_qsfp_5_tx_clk_1, dut.fmc_qsfp_5_tx_rst_1) + + cocotb.start_soon(Clock(dut.fmc_qsfp_5_rx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_5_2_source = XgmiiSource(dut.fmc_qsfp_5_rxd_2, dut.fmc_qsfp_5_rxc_2, dut.fmc_qsfp_5_rx_clk_2, dut.fmc_qsfp_5_rx_rst_2) + cocotb.start_soon(Clock(dut.fmc_qsfp_5_tx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_5_2_sink = XgmiiSink(dut.fmc_qsfp_5_txd_2, dut.fmc_qsfp_5_txc_2, dut.fmc_qsfp_5_tx_clk_2, dut.fmc_qsfp_5_tx_rst_2) + + cocotb.start_soon(Clock(dut.fmc_qsfp_5_rx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_5_3_source = XgmiiSource(dut.fmc_qsfp_5_rxd_3, dut.fmc_qsfp_5_rxc_3, dut.fmc_qsfp_5_rx_clk_3, dut.fmc_qsfp_5_rx_rst_3) + cocotb.start_soon(Clock(dut.fmc_qsfp_5_tx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_5_3_sink = XgmiiSink(dut.fmc_qsfp_5_txd_3, dut.fmc_qsfp_5_txc_3, dut.fmc_qsfp_5_tx_clk_3, dut.fmc_qsfp_5_tx_rst_3) + + cocotb.start_soon(Clock(dut.fmc_qsfp_5_rx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_5_4_source = XgmiiSource(dut.fmc_qsfp_5_rxd_4, dut.fmc_qsfp_5_rxc_4, dut.fmc_qsfp_5_rx_clk_4, dut.fmc_qsfp_5_rx_rst_4) + cocotb.start_soon(Clock(dut.fmc_qsfp_5_tx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_5_4_sink = XgmiiSink(dut.fmc_qsfp_5_txd_4, dut.fmc_qsfp_5_txc_4, dut.fmc_qsfp_5_tx_clk_4, dut.fmc_qsfp_5_tx_rst_4) + + cocotb.start_soon(Clock(dut.fmc_qsfp_6_rx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_6_1_source = XgmiiSource(dut.fmc_qsfp_6_rxd_1, dut.fmc_qsfp_6_rxc_1, dut.fmc_qsfp_6_rx_clk_1, dut.fmc_qsfp_6_rx_rst_1) + cocotb.start_soon(Clock(dut.fmc_qsfp_6_tx_clk_1, 2.56, units="ns").start()) + self.fmc_qsfp_6_1_sink = XgmiiSink(dut.fmc_qsfp_6_txd_1, dut.fmc_qsfp_6_txc_1, dut.fmc_qsfp_6_tx_clk_1, dut.fmc_qsfp_6_tx_rst_1) + + cocotb.start_soon(Clock(dut.fmc_qsfp_6_rx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_6_2_source = XgmiiSource(dut.fmc_qsfp_6_rxd_2, dut.fmc_qsfp_6_rxc_2, dut.fmc_qsfp_6_rx_clk_2, dut.fmc_qsfp_6_rx_rst_2) + cocotb.start_soon(Clock(dut.fmc_qsfp_6_tx_clk_2, 2.56, units="ns").start()) + self.fmc_qsfp_6_2_sink = XgmiiSink(dut.fmc_qsfp_6_txd_2, dut.fmc_qsfp_6_txc_2, dut.fmc_qsfp_6_tx_clk_2, dut.fmc_qsfp_6_tx_rst_2) + + cocotb.start_soon(Clock(dut.fmc_qsfp_6_rx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_6_3_source = XgmiiSource(dut.fmc_qsfp_6_rxd_3, dut.fmc_qsfp_6_rxc_3, dut.fmc_qsfp_6_rx_clk_3, dut.fmc_qsfp_6_rx_rst_3) + cocotb.start_soon(Clock(dut.fmc_qsfp_6_tx_clk_3, 2.56, units="ns").start()) + self.fmc_qsfp_6_3_sink = XgmiiSink(dut.fmc_qsfp_6_txd_3, dut.fmc_qsfp_6_txc_3, dut.fmc_qsfp_6_tx_clk_3, dut.fmc_qsfp_6_tx_rst_3) + + cocotb.start_soon(Clock(dut.fmc_qsfp_6_rx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_6_4_source = XgmiiSource(dut.fmc_qsfp_6_rxd_4, dut.fmc_qsfp_6_rxc_4, dut.fmc_qsfp_6_rx_clk_4, dut.fmc_qsfp_6_rx_rst_4) + cocotb.start_soon(Clock(dut.fmc_qsfp_6_tx_clk_4, 2.56, units="ns").start()) + self.fmc_qsfp_6_4_sink = XgmiiSink(dut.fmc_qsfp_6_txd_4, dut.fmc_qsfp_6_txc_4, dut.fmc_qsfp_6_tx_clk_4, dut.fmc_qsfp_6_tx_rst_4) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp_4_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_4_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_4_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_4_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_4_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_4_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_4_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_4_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp_5_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_5_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_5_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_5_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_5_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_5_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_5_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_5_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp_6_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_6_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_6_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_6_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_6_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_6_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_6_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_6_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp_7_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_7_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_7_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_7_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_7_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_7_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_7_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_7_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp_8_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_8_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_8_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_8_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_8_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_8_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_8_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_8_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp_9_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_9_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_9_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_9_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_9_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_9_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_9_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp_9_tx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_1_rx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_1_tx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_1_rx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_1_tx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_1_rx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_1_tx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_1_rx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_1_tx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_2_rx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_2_tx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_2_rx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_2_tx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_2_rx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_2_tx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_2_rx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_2_tx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_3_rx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_3_tx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_3_rx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_3_tx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_3_rx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_3_tx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_3_rx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_3_tx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_4_rx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_4_tx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_4_rx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_4_tx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_4_rx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_4_tx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_4_rx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_4_tx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_5_rx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_5_tx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_5_rx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_5_tx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_5_rx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_5_tx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_5_rx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_5_tx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_6_rx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_6_tx_rst_1.setimmediatevalue(0) + self.dut.fmc_qsfp_6_rx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_6_tx_rst_2.setimmediatevalue(0) + self.dut.fmc_qsfp_6_rx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_6_tx_rst_3.setimmediatevalue(0) + self.dut.fmc_qsfp_6_rx_rst_4.setimmediatevalue(0) + self.dut.fmc_qsfp_6_tx_rst_4.setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + self.dut.qsfp_1_rx_rst_1.value = 1 + self.dut.qsfp_1_tx_rst_1.value = 1 + self.dut.qsfp_1_rx_rst_2.value = 1 + self.dut.qsfp_1_tx_rst_2.value = 1 + self.dut.qsfp_1_rx_rst_3.value = 1 + self.dut.qsfp_1_tx_rst_3.value = 1 + self.dut.qsfp_1_rx_rst_4.value = 1 + self.dut.qsfp_1_tx_rst_4.value = 1 + self.dut.qsfp_2_rx_rst_1.value = 1 + self.dut.qsfp_2_tx_rst_1.value = 1 + self.dut.qsfp_2_rx_rst_2.value = 1 + self.dut.qsfp_2_tx_rst_2.value = 1 + self.dut.qsfp_2_rx_rst_3.value = 1 + self.dut.qsfp_2_tx_rst_3.value = 1 + self.dut.qsfp_2_rx_rst_4.value = 1 + self.dut.qsfp_2_tx_rst_4.value = 1 + self.dut.qsfp_3_rx_rst_1.value = 1 + self.dut.qsfp_3_tx_rst_1.value = 1 + self.dut.qsfp_3_rx_rst_2.value = 1 + self.dut.qsfp_3_tx_rst_2.value = 1 + self.dut.qsfp_3_rx_rst_3.value = 1 + self.dut.qsfp_3_tx_rst_3.value = 1 + self.dut.qsfp_3_rx_rst_4.value = 1 + self.dut.qsfp_3_tx_rst_4.value = 1 + self.dut.qsfp_4_rx_rst_1.value = 1 + self.dut.qsfp_4_tx_rst_1.value = 1 + self.dut.qsfp_4_rx_rst_2.value = 1 + self.dut.qsfp_4_tx_rst_2.value = 1 + self.dut.qsfp_4_rx_rst_3.value = 1 + self.dut.qsfp_4_tx_rst_3.value = 1 + self.dut.qsfp_4_rx_rst_4.value = 1 + self.dut.qsfp_4_tx_rst_4.value = 1 + self.dut.qsfp_5_rx_rst_1.value = 1 + self.dut.qsfp_5_tx_rst_1.value = 1 + self.dut.qsfp_5_rx_rst_2.value = 1 + self.dut.qsfp_5_tx_rst_2.value = 1 + self.dut.qsfp_5_rx_rst_3.value = 1 + self.dut.qsfp_5_tx_rst_3.value = 1 + self.dut.qsfp_5_rx_rst_4.value = 1 + self.dut.qsfp_5_tx_rst_4.value = 1 + self.dut.qsfp_6_rx_rst_1.value = 1 + self.dut.qsfp_6_tx_rst_1.value = 1 + self.dut.qsfp_6_rx_rst_2.value = 1 + self.dut.qsfp_6_tx_rst_2.value = 1 + self.dut.qsfp_6_rx_rst_3.value = 1 + self.dut.qsfp_6_tx_rst_3.value = 1 + self.dut.qsfp_6_rx_rst_4.value = 1 + self.dut.qsfp_6_tx_rst_4.value = 1 + self.dut.qsfp_7_rx_rst_1.value = 1 + self.dut.qsfp_7_tx_rst_1.value = 1 + self.dut.qsfp_7_rx_rst_2.value = 1 + self.dut.qsfp_7_tx_rst_2.value = 1 + self.dut.qsfp_7_rx_rst_3.value = 1 + self.dut.qsfp_7_tx_rst_3.value = 1 + self.dut.qsfp_7_rx_rst_4.value = 1 + self.dut.qsfp_7_tx_rst_4.value = 1 + self.dut.qsfp_8_rx_rst_1.value = 1 + self.dut.qsfp_8_tx_rst_1.value = 1 + self.dut.qsfp_8_rx_rst_2.value = 1 + self.dut.qsfp_8_tx_rst_2.value = 1 + self.dut.qsfp_8_rx_rst_3.value = 1 + self.dut.qsfp_8_tx_rst_3.value = 1 + self.dut.qsfp_8_rx_rst_4.value = 1 + self.dut.qsfp_8_tx_rst_4.value = 1 + self.dut.qsfp_9_rx_rst_1.value = 1 + self.dut.qsfp_9_tx_rst_1.value = 1 + self.dut.qsfp_9_rx_rst_2.value = 1 + self.dut.qsfp_9_tx_rst_2.value = 1 + self.dut.qsfp_9_rx_rst_3.value = 1 + self.dut.qsfp_9_tx_rst_3.value = 1 + self.dut.qsfp_9_rx_rst_4.value = 1 + self.dut.qsfp_9_tx_rst_4.value = 1 + self.dut.fmc_qsfp_1_rx_rst_1.value = 1 + self.dut.fmc_qsfp_1_tx_rst_1.value = 1 + self.dut.fmc_qsfp_1_rx_rst_2.value = 1 + self.dut.fmc_qsfp_1_tx_rst_2.value = 1 + self.dut.fmc_qsfp_1_rx_rst_3.value = 1 + self.dut.fmc_qsfp_1_tx_rst_3.value = 1 + self.dut.fmc_qsfp_1_rx_rst_4.value = 1 + self.dut.fmc_qsfp_1_tx_rst_4.value = 1 + self.dut.fmc_qsfp_2_rx_rst_1.value = 1 + self.dut.fmc_qsfp_2_tx_rst_1.value = 1 + self.dut.fmc_qsfp_2_rx_rst_2.value = 1 + self.dut.fmc_qsfp_2_tx_rst_2.value = 1 + self.dut.fmc_qsfp_2_rx_rst_3.value = 1 + self.dut.fmc_qsfp_2_tx_rst_3.value = 1 + self.dut.fmc_qsfp_2_rx_rst_4.value = 1 + self.dut.fmc_qsfp_2_tx_rst_4.value = 1 + self.dut.fmc_qsfp_3_rx_rst_1.value = 1 + self.dut.fmc_qsfp_3_tx_rst_1.value = 1 + self.dut.fmc_qsfp_3_rx_rst_2.value = 1 + self.dut.fmc_qsfp_3_tx_rst_2.value = 1 + self.dut.fmc_qsfp_3_rx_rst_3.value = 1 + self.dut.fmc_qsfp_3_tx_rst_3.value = 1 + self.dut.fmc_qsfp_3_rx_rst_4.value = 1 + self.dut.fmc_qsfp_3_tx_rst_4.value = 1 + self.dut.fmc_qsfp_4_rx_rst_1.value = 1 + self.dut.fmc_qsfp_4_tx_rst_1.value = 1 + self.dut.fmc_qsfp_4_rx_rst_2.value = 1 + self.dut.fmc_qsfp_4_tx_rst_2.value = 1 + self.dut.fmc_qsfp_4_rx_rst_3.value = 1 + self.dut.fmc_qsfp_4_tx_rst_3.value = 1 + self.dut.fmc_qsfp_4_rx_rst_4.value = 1 + self.dut.fmc_qsfp_4_tx_rst_4.value = 1 + self.dut.fmc_qsfp_5_rx_rst_1.value = 1 + self.dut.fmc_qsfp_5_tx_rst_1.value = 1 + self.dut.fmc_qsfp_5_rx_rst_2.value = 1 + self.dut.fmc_qsfp_5_tx_rst_2.value = 1 + self.dut.fmc_qsfp_5_rx_rst_3.value = 1 + self.dut.fmc_qsfp_5_tx_rst_3.value = 1 + self.dut.fmc_qsfp_5_rx_rst_4.value = 1 + self.dut.fmc_qsfp_5_tx_rst_4.value = 1 + self.dut.fmc_qsfp_6_rx_rst_1.value = 1 + self.dut.fmc_qsfp_6_tx_rst_1.value = 1 + self.dut.fmc_qsfp_6_rx_rst_2.value = 1 + self.dut.fmc_qsfp_6_tx_rst_2.value = 1 + self.dut.fmc_qsfp_6_rx_rst_3.value = 1 + self.dut.fmc_qsfp_6_tx_rst_3.value = 1 + self.dut.fmc_qsfp_6_rx_rst_4.value = 1 + self.dut.fmc_qsfp_6_tx_rst_4.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + self.dut.qsfp_1_rx_rst_1.value = 0 + self.dut.qsfp_1_tx_rst_1.value = 0 + self.dut.qsfp_1_rx_rst_2.value = 0 + self.dut.qsfp_1_tx_rst_2.value = 0 + self.dut.qsfp_1_rx_rst_3.value = 0 + self.dut.qsfp_1_tx_rst_3.value = 0 + self.dut.qsfp_1_rx_rst_4.value = 0 + self.dut.qsfp_1_tx_rst_4.value = 0 + self.dut.qsfp_2_rx_rst_1.value = 0 + self.dut.qsfp_2_tx_rst_1.value = 0 + self.dut.qsfp_2_rx_rst_2.value = 0 + self.dut.qsfp_2_tx_rst_2.value = 0 + self.dut.qsfp_2_rx_rst_3.value = 0 + self.dut.qsfp_2_tx_rst_3.value = 0 + self.dut.qsfp_2_rx_rst_4.value = 0 + self.dut.qsfp_2_tx_rst_4.value = 0 + self.dut.qsfp_3_rx_rst_1.value = 0 + self.dut.qsfp_3_tx_rst_1.value = 0 + self.dut.qsfp_3_rx_rst_2.value = 0 + self.dut.qsfp_3_tx_rst_2.value = 0 + self.dut.qsfp_3_rx_rst_3.value = 0 + self.dut.qsfp_3_tx_rst_3.value = 0 + self.dut.qsfp_3_rx_rst_4.value = 0 + self.dut.qsfp_3_tx_rst_4.value = 0 + self.dut.qsfp_4_rx_rst_1.value = 0 + self.dut.qsfp_4_tx_rst_1.value = 0 + self.dut.qsfp_4_rx_rst_2.value = 0 + self.dut.qsfp_4_tx_rst_2.value = 0 + self.dut.qsfp_4_rx_rst_3.value = 0 + self.dut.qsfp_4_tx_rst_3.value = 0 + self.dut.qsfp_4_rx_rst_4.value = 0 + self.dut.qsfp_4_tx_rst_4.value = 0 + self.dut.qsfp_5_rx_rst_1.value = 0 + self.dut.qsfp_5_tx_rst_1.value = 0 + self.dut.qsfp_5_rx_rst_2.value = 0 + self.dut.qsfp_5_tx_rst_2.value = 0 + self.dut.qsfp_5_rx_rst_3.value = 0 + self.dut.qsfp_5_tx_rst_3.value = 0 + self.dut.qsfp_5_rx_rst_4.value = 0 + self.dut.qsfp_5_tx_rst_4.value = 0 + self.dut.qsfp_6_rx_rst_1.value = 0 + self.dut.qsfp_6_tx_rst_1.value = 0 + self.dut.qsfp_6_rx_rst_2.value = 0 + self.dut.qsfp_6_tx_rst_2.value = 0 + self.dut.qsfp_6_rx_rst_3.value = 0 + self.dut.qsfp_6_tx_rst_3.value = 0 + self.dut.qsfp_6_rx_rst_4.value = 0 + self.dut.qsfp_6_tx_rst_4.value = 0 + self.dut.qsfp_7_rx_rst_1.value = 0 + self.dut.qsfp_7_tx_rst_1.value = 0 + self.dut.qsfp_7_rx_rst_2.value = 0 + self.dut.qsfp_7_tx_rst_2.value = 0 + self.dut.qsfp_7_rx_rst_3.value = 0 + self.dut.qsfp_7_tx_rst_3.value = 0 + self.dut.qsfp_7_rx_rst_4.value = 0 + self.dut.qsfp_7_tx_rst_4.value = 0 + self.dut.qsfp_8_rx_rst_1.value = 0 + self.dut.qsfp_8_tx_rst_1.value = 0 + self.dut.qsfp_8_rx_rst_2.value = 0 + self.dut.qsfp_8_tx_rst_2.value = 0 + self.dut.qsfp_8_rx_rst_3.value = 0 + self.dut.qsfp_8_tx_rst_3.value = 0 + self.dut.qsfp_8_rx_rst_4.value = 0 + self.dut.qsfp_8_tx_rst_4.value = 0 + self.dut.qsfp_9_rx_rst_1.value = 0 + self.dut.qsfp_9_tx_rst_1.value = 0 + self.dut.qsfp_9_rx_rst_2.value = 0 + self.dut.qsfp_9_tx_rst_2.value = 0 + self.dut.qsfp_9_rx_rst_3.value = 0 + self.dut.qsfp_9_tx_rst_3.value = 0 + self.dut.qsfp_9_rx_rst_4.value = 0 + self.dut.qsfp_9_tx_rst_4.value = 0 + self.dut.fmc_qsfp_1_rx_rst_1.value = 0 + self.dut.fmc_qsfp_1_tx_rst_1.value = 0 + self.dut.fmc_qsfp_1_rx_rst_2.value = 0 + self.dut.fmc_qsfp_1_tx_rst_2.value = 0 + self.dut.fmc_qsfp_1_rx_rst_3.value = 0 + self.dut.fmc_qsfp_1_tx_rst_3.value = 0 + self.dut.fmc_qsfp_1_rx_rst_4.value = 0 + self.dut.fmc_qsfp_1_tx_rst_4.value = 0 + self.dut.fmc_qsfp_2_rx_rst_1.value = 0 + self.dut.fmc_qsfp_2_tx_rst_1.value = 0 + self.dut.fmc_qsfp_2_rx_rst_2.value = 0 + self.dut.fmc_qsfp_2_tx_rst_2.value = 0 + self.dut.fmc_qsfp_2_rx_rst_3.value = 0 + self.dut.fmc_qsfp_2_tx_rst_3.value = 0 + self.dut.fmc_qsfp_2_rx_rst_4.value = 0 + self.dut.fmc_qsfp_2_tx_rst_4.value = 0 + self.dut.fmc_qsfp_3_rx_rst_1.value = 0 + self.dut.fmc_qsfp_3_tx_rst_1.value = 0 + self.dut.fmc_qsfp_3_rx_rst_2.value = 0 + self.dut.fmc_qsfp_3_tx_rst_2.value = 0 + self.dut.fmc_qsfp_3_rx_rst_3.value = 0 + self.dut.fmc_qsfp_3_tx_rst_3.value = 0 + self.dut.fmc_qsfp_3_rx_rst_4.value = 0 + self.dut.fmc_qsfp_3_tx_rst_4.value = 0 + self.dut.fmc_qsfp_4_rx_rst_1.value = 0 + self.dut.fmc_qsfp_4_tx_rst_1.value = 0 + self.dut.fmc_qsfp_4_rx_rst_2.value = 0 + self.dut.fmc_qsfp_4_tx_rst_2.value = 0 + self.dut.fmc_qsfp_4_rx_rst_3.value = 0 + self.dut.fmc_qsfp_4_tx_rst_3.value = 0 + self.dut.fmc_qsfp_4_rx_rst_4.value = 0 + self.dut.fmc_qsfp_4_tx_rst_4.value = 0 + self.dut.fmc_qsfp_5_rx_rst_1.value = 0 + self.dut.fmc_qsfp_5_tx_rst_1.value = 0 + self.dut.fmc_qsfp_5_rx_rst_2.value = 0 + self.dut.fmc_qsfp_5_tx_rst_2.value = 0 + self.dut.fmc_qsfp_5_rx_rst_3.value = 0 + self.dut.fmc_qsfp_5_tx_rst_3.value = 0 + self.dut.fmc_qsfp_5_rx_rst_4.value = 0 + self.dut.fmc_qsfp_5_tx_rst_4.value = 0 + self.dut.fmc_qsfp_6_rx_rst_1.value = 0 + self.dut.fmc_qsfp_6_tx_rst_1.value = 0 + self.dut.fmc_qsfp_6_rx_rst_2.value = 0 + self.dut.fmc_qsfp_6_tx_rst_2.value = 0 + self.dut.fmc_qsfp_6_rx_rst_3.value = 0 + self.dut.fmc_qsfp_6_tx_rst_3.value = 0 + self.dut.fmc_qsfp_6_rx_rst_4.value = 0 + self.dut.fmc_qsfp_6_tx_rst_4.value = 0 + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("test UDP RX packet") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') + ip = IP(src='192.168.1.100', dst='192.168.1.128') + udp = UDP(sport=5678, dport=1234) + test_pkt = eth / ip / udp / payload + + test_frame = XgmiiFrame.from_payload(test_pkt.build()) + + await tb.qsfp_1_1_source.send(test_frame) + + tb.log.info("receive ARP request") + + rx_frame = await tb.qsfp_1_1_sink.recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[ARP].hwtype == 1 + assert rx_pkt[ARP].ptype == 0x0800 + assert rx_pkt[ARP].hwlen == 6 + assert rx_pkt[ARP].plen == 4 + assert rx_pkt[ARP].op == 1 + assert rx_pkt[ARP].hwsrc == test_pkt.dst + assert rx_pkt[ARP].psrc == test_pkt[IP].dst + assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' + assert rx_pkt[ARP].pdst == test_pkt[IP].src + + tb.log.info("send ARP response") + + eth = Ether(src=test_pkt.src, dst=test_pkt.dst) + arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, + hwsrc=test_pkt.src, psrc=test_pkt[IP].src, + hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) + resp_pkt = eth / arp + + resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) + + await tb.qsfp_1_1_source.send(resp_frame) + + tb.log.info("receive UDP packet") + + rx_frame = await tb.qsfp_1_1_sink.recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == test_pkt.src + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[IP].dst == test_pkt[IP].src + assert rx_pkt[IP].src == test_pkt[IP].dst + assert rx_pkt[UDP].dport == test_pkt[UDP].sport + assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert rx_pkt[UDP].payload == test_pkt[UDP].payload + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "eth_axis_rx.v"), + os.path.join(eth_rtl_dir, "eth_axis_tx.v"), + os.path.join(eth_rtl_dir, "udp_complete_64.v"), + os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), + os.path.join(eth_rtl_dir, "udp_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_complete_64.v"), + os.path.join(eth_rtl_dir, "ip_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_arb_mux.v"), + os.path.join(eth_rtl_dir, "arp.v"), + os.path.join(eth_rtl_dir, "arp_cache.v"), + os.path.join(eth_rtl_dir, "arp_eth_rx.v"), + os.path.join(eth_rtl_dir, "arp_eth_tx.v"), + os.path.join(eth_rtl_dir, "eth_arb_mux.v"), + os.path.join(axis_rtl_dir, "arbiter.v"), + os.path.join(axis_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + ] + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )