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Update timing constraints to handle clocks from OOC IP that are not constrained during synthesis

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-01-17 13:40:36 -08:00
parent a91e98c105
commit f521fb6435
1 changed files with 5 additions and 5 deletions
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10
syn/vivado/axil_cdc.tcl
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@ -24,13 +24,13 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == axil_cdc_rd || REF_NAME
puts "Inserting timing constraints for axil_cdc instance $inst"
# get clock periods
set m_clk [get_clocks -of_objects [get_pins $inst/m_flag_reg_reg/C]]
set s_clk [get_clocks -of_objects [get_pins $inst/s_flag_reg_reg/C]]
set s_clk [get_clocks -of_objects [get_cells "$inst/s_flag_reg_reg"]]
set m_clk [get_clocks -of_objects [get_cells "$inst/m_flag_reg_reg"]]
set m_clk_period [get_property -min PERIOD $m_clk]
set s_clk_period [get_property -min PERIOD $s_clk]
set s_clk_period [if {[llength $s_clk]} {get_property -min PERIOD $s_clk} {expr 1.0}]
set m_clk_period [if {[llength $m_clk]} {get_property -min PERIOD $m_clk} {expr 1.0}]
set min_clk_period [expr $m_clk_period < $s_clk_period ? $m_clk_period : $s_clk_period]
set min_clk_period [expr min($s_clk_period, $m_clk_period)]
set_property ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/m_flag_sync_reg_\[12\]_reg" -filter "PARENT == $inst"]
set_property ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/s_flag_sync_reg_\[12\]_reg" -filter "PARENT == $inst"]