diff --git a/fpga/common/rtl/port.v b/fpga/common/rtl/port.v
index 464cc20da..7b5e4e857 100644
--- a/fpga/common/rtl/port.v
+++ b/fpga/common/rtl/port.v
@@ -645,6 +645,7 @@ always @(posedge clk) begin
                 axil_ctrl_rdata_reg[0] <= tdma_locked;
                 axil_ctrl_rdata_reg[1] <= tdma_error;
             end
+            16'h0108: axil_ctrl_rdata_reg <= 2**TDMA_INDEX_WIDTH; // TDMA timeslot count
             16'h0114: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[29:0]; // TDMA schedule start ns
             16'h0118: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[63:32]; // TDMA schedule start sec l
             16'h011C: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[79:64]; // TDMA schedule start sec h
diff --git a/fpga/common/tb/mqnic.py b/fpga/common/tb/mqnic.py
index 2b4e413bf..e1b24eb5a 100644
--- a/fpga/common/tb/mqnic.py
+++ b/fpga/common/tb/mqnic.py
@@ -134,6 +134,7 @@ MQNIC_PORT_REG_SCHED_TYPE                 = 0x001C
 MQNIC_PORT_REG_SCHED_ENABLE               = 0x0040
 MQNIC_PORT_REG_TDMA_CTRL                  = 0x0100
 MQNIC_PORT_REG_TDMA_STATUS                = 0x0104
+MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT        = 0x0108
 MQNIC_PORT_REG_TDMA_SCHED_START_FNS       = 0x0110
 MQNIC_PORT_REG_TDMA_SCHED_START_NS        = 0x0114
 MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L     = 0x0118
diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h
index 2560e140a..27753c9f1 100644
--- a/modules/mqnic/mqnic_hw.h
+++ b/modules/mqnic/mqnic_hw.h
@@ -140,6 +140,7 @@ either expressed or implied, of The Regents of the University of California.
 #define MQNIC_PORT_REG_SCHED_ENABLE               0x0040
 #define MQNIC_PORT_REG_TDMA_CTRL                  0x0100
 #define MQNIC_PORT_REG_TDMA_STATUS                0x0104
+#define MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT        0x0108
 #define MQNIC_PORT_REG_TDMA_SCHED_START_FNS       0x0110
 #define MQNIC_PORT_REG_TDMA_SCHED_START_NS        0x0114
 #define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L     0x0118