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Add timeslot count to port registers

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This commit is contained in:
Alex Forencich 2019-11-05 16:59:40 -08:00
parent f65b139797
commit f53a6b20e8
3 changed files with 3 additions and 0 deletions
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1
fpga/common/rtl/port.v
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@ -645,6 +645,7 @@ always @(posedge clk) begin
axil_ctrl_rdata_reg[0] <= tdma_locked;
axil_ctrl_rdata_reg[1] <= tdma_error;
end
16'h0108: axil_ctrl_rdata_reg <= 2**TDMA_INDEX_WIDTH; // TDMA timeslot count
16'h0114: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[29:0]; // TDMA schedule start ns
16'h0118: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[63:32]; // TDMA schedule start sec l
16'h011C: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[79:64]; // TDMA schedule start sec h

1
fpga/common/tb/mqnic.py
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@ -134,6 +134,7 @@ MQNIC_PORT_REG_SCHED_TYPE = 0x001C
MQNIC_PORT_REG_SCHED_ENABLE = 0x0040
MQNIC_PORT_REG_TDMA_CTRL = 0x0100
MQNIC_PORT_REG_TDMA_STATUS = 0x0104
MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT = 0x0108
MQNIC_PORT_REG_TDMA_SCHED_START_FNS = 0x0110
MQNIC_PORT_REG_TDMA_SCHED_START_NS = 0x0114
MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L = 0x0118

1
modules/mqnic/mqnic_hw.h
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@ -140,6 +140,7 @@ either expressed or implied, of The Regents of the University of California.
#define MQNIC_PORT_REG_SCHED_ENABLE 0x0040
#define MQNIC_PORT_REG_TDMA_CTRL 0x0100
#define MQNIC_PORT_REG_TDMA_STATUS 0x0104
#define MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT 0x0108
#define MQNIC_PORT_REG_TDMA_SCHED_START_FNS 0x0110
#define MQNIC_PORT_REG_TDMA_SCHED_START_NS 0x0114
#define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L 0x0118