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Add TLP mux and demux modules
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Alex Forencich
parent
1321e8e41a
commit
f566df2c66
324
rtl/pcie_tlp_demux.v
Normal file
324
rtl/pcie_tlp_demux.v
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/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
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The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
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||||
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* PCIe TLP demultiplexer
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*/
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module pcie_tlp_demux #
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(
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// Output count
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parameter PORTS = 2,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TLP segment data width
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parameter TLP_SEG_DATA_WIDTH = 256,
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// TLP segment strobe width
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parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
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// TLP segment header width
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parameter TLP_SEG_HDR_WIDTH = 128
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)
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(
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input wire clk,
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input wire rst,
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/*
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* TLP input
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*/
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input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data,
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input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr,
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input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
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input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
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input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
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input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
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output wire in_tlp_ready,
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/*
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* TLP output
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*/
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output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data,
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output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb,
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output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr,
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output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
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output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
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output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
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output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
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output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
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output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
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input wire [PORTS-1:0] out_tlp_ready,
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/*
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* Fields
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*/
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output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] match_tlp_hdr,
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output wire [TLP_SEG_COUNT*3-1:0] match_tlp_bar_id,
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output wire [TLP_SEG_COUNT*8-1:0] match_tlp_func_num,
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/*
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* Control
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*/
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input wire enable,
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input wire [TLP_SEG_COUNT-1:0] drop,
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input wire [TLP_SEG_COUNT*PORTS-1:0] select
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);
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parameter CL_PORTS = $clog2(PORTS);
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// check configuration
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initial begin
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if (TLP_SEG_COUNT != 1) begin
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$error("Error: TLP segment count must be 1 (instance %m)");
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$finish;
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end
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if (TLP_SEG_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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if (TLP_SEG_STRB_WIDTH*32 != TLP_SEG_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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end
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reg [CL_PORTS-1:0] select_reg = {CL_PORTS{1'b0}}, select_ctl, select_next;
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reg drop_reg = 1'b0, drop_ctl, drop_next;
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reg frame_reg = 1'b0, frame_ctl, frame_next;
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reg in_tlp_ready_reg = 1'b0, in_tlp_ready_next;
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_in_tlp_data_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_in_tlp_strb_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_in_tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT*3-1:0] temp_in_tlp_bar_id_reg = 0;
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reg [TLP_SEG_COUNT*8-1:0] temp_in_tlp_func_num_reg = 0;
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reg [TLP_SEG_COUNT*4-1:0] temp_in_tlp_error_reg = 0;
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reg [TLP_SEG_COUNT-1:0] temp_in_tlp_valid_reg = 1'b0;
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reg [TLP_SEG_COUNT-1:0] temp_in_tlp_sop_reg = 1'b0;
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reg [TLP_SEG_COUNT-1:0] temp_in_tlp_eop_reg = 1'b0;
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// internal datapath
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_int;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_int;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_int;
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reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
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reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
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reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
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reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_int;
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reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
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reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
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reg out_tlp_ready_int_reg = 1'b0;
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wire out_tlp_ready_int_early;
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assign in_tlp_ready = in_tlp_ready_reg && enable;
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assign match_tlp_hdr = in_tlp_hdr;
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assign match_tlp_bar_id = in_tlp_bar_id;
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assign match_tlp_func_num = in_tlp_func_num;
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integer i;
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always @* begin
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select_next = select_reg;
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select_ctl = select_reg;
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drop_next = drop_reg;
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drop_ctl = drop_reg;
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frame_next = frame_reg;
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frame_ctl = frame_reg;
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in_tlp_ready_next = 1'b0;
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if (in_tlp_valid && in_tlp_ready) begin
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// end of frame detection
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if (in_tlp_eop) begin
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frame_next = 1'b0;
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drop_next = 1'b0;
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end
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end
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if (!frame_reg && in_tlp_valid && in_tlp_ready) begin
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// start of frame, grab select value
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select_ctl = 0;
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drop_ctl = 1'b1;
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frame_ctl = 1'b1;
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for (i = PORTS-1; i >= 0; i = i - 1) begin
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if (select[i]) begin
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select_ctl = i;
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drop_ctl = 1'b0;
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end
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end
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drop_ctl = drop_ctl || drop;
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if (!(in_tlp_ready && in_tlp_valid && in_tlp_eop)) begin
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select_next = select_ctl;
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drop_next = drop_ctl;
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frame_next = 1'b1;
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end
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end
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in_tlp_ready_next = out_tlp_ready_int_early || drop_ctl;
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out_tlp_data_int = in_tlp_data;
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out_tlp_strb_int = in_tlp_strb;
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out_tlp_hdr_int = in_tlp_hdr;
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out_tlp_bar_id_int = in_tlp_bar_id;
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out_tlp_func_num_int = in_tlp_func_num;
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out_tlp_error_int = in_tlp_error;
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out_tlp_valid_int = (in_tlp_valid && in_tlp_ready && !drop_ctl && frame_ctl) << select_ctl;
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out_tlp_sop_int = in_tlp_sop;
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out_tlp_eop_int = in_tlp_eop;
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end
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always @(posedge clk) begin
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select_reg <= select_next;
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drop_reg <= drop_next;
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frame_reg <= frame_next;
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in_tlp_ready_reg <= in_tlp_ready_next;
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if (rst) begin
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select_reg <= 2'd0;
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drop_reg <= 1'b0;
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frame_reg <= 1'b0;
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in_tlp_ready_reg <= 1'b0;
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end
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end
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// output datapath logic
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
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reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
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reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
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reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 1, out_tlp_valid_next;
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reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
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reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
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reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
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reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
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reg [PORTS*TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
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reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
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reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
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// datapath control
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reg store_int_to_output;
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reg store_int_to_temp;
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reg store_temp_to_output;
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assign out_tlp_data = {PORTS{out_tlp_data_reg}};
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assign out_tlp_strb = {PORTS{out_tlp_strb_reg}};
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assign out_tlp_hdr = {PORTS{out_tlp_hdr_reg}};
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assign out_tlp_bar_id = {PORTS{out_tlp_bar_id_reg}};
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assign out_tlp_func_num = {PORTS{out_tlp_func_num_reg}};
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assign out_tlp_error = {PORTS{out_tlp_error_reg}};
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assign out_tlp_valid = out_tlp_valid_reg;
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assign out_tlp_sop = {PORTS{out_tlp_sop_reg}};
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assign out_tlp_eop = {PORTS{out_tlp_eop_reg}};
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign out_tlp_ready_int_early = (out_tlp_ready & out_tlp_valid) || (!temp_out_tlp_valid_reg && (!out_tlp_valid || !out_tlp_valid_int));
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always @* begin
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// transfer sink ready state to source
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out_tlp_valid_next = out_tlp_valid_reg;
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temp_out_tlp_valid_next = temp_out_tlp_valid_reg;
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store_int_to_output = 1'b0;
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store_int_to_temp = 1'b0;
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store_temp_to_output = 1'b0;
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if (out_tlp_ready_int_reg) begin
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// input is ready
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if ((out_tlp_ready & out_tlp_valid) || !out_tlp_valid) begin
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// output is ready or currently not valid, transfer data to output
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out_tlp_valid_next = out_tlp_valid_int;
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store_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_out_tlp_valid_next = out_tlp_valid_int;
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store_int_to_temp = 1'b1;
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end
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end else if (out_tlp_ready & out_tlp_valid) begin
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// input is not ready, but output is ready
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out_tlp_valid_next = temp_out_tlp_valid_reg;
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temp_out_tlp_valid_next = 1'b0;
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store_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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out_tlp_valid_reg <= {PORTS{1'b0}};
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out_tlp_ready_int_reg <= 1'b0;
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temp_out_tlp_valid_reg <= 1'b0;
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end else begin
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out_tlp_valid_reg <= out_tlp_valid_next;
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out_tlp_ready_int_reg <= out_tlp_ready_int_early;
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temp_out_tlp_valid_reg <= temp_out_tlp_valid_next;
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end
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// datapath
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if (store_int_to_output) begin
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out_tlp_data_reg <= out_tlp_data_int;
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out_tlp_strb_reg <= out_tlp_strb_int;
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out_tlp_hdr_reg <= out_tlp_hdr_int;
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out_tlp_bar_id_reg <= out_tlp_bar_id_int;
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out_tlp_func_num_reg <= out_tlp_func_num_int;
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out_tlp_error_reg <= out_tlp_error_int;
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out_tlp_sop_reg <= out_tlp_sop_int;
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out_tlp_eop_reg <= out_tlp_eop_int;
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end else if (store_temp_to_output) begin
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out_tlp_data_reg <= temp_out_tlp_data_reg;
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out_tlp_strb_reg <= temp_out_tlp_strb_reg;
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out_tlp_hdr_reg <= temp_out_tlp_hdr_reg;
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out_tlp_bar_id_reg <= temp_out_tlp_bar_id_reg;
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out_tlp_func_num_reg <= temp_out_tlp_func_num_reg;
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out_tlp_error_reg <= temp_out_tlp_error_reg;
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out_tlp_sop_reg <= temp_out_tlp_sop_reg;
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out_tlp_eop_reg <= temp_out_tlp_eop_reg;
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end
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if (store_int_to_temp) begin
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temp_out_tlp_data_reg <= out_tlp_data_int;
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temp_out_tlp_strb_reg <= out_tlp_strb_int;
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temp_out_tlp_hdr_reg <= out_tlp_hdr_int;
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temp_out_tlp_bar_id_reg <= out_tlp_bar_id_int;
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temp_out_tlp_func_num_reg <= out_tlp_func_num_int;
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temp_out_tlp_error_reg <= out_tlp_error_int;
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temp_out_tlp_sop_reg <= out_tlp_sop_int;
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temp_out_tlp_eop_reg <= out_tlp_eop_int;
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end
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end
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endmodule
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201
rtl/pcie_tlp_demux_bar.v
Normal file
201
rtl/pcie_tlp_demux_bar.v
Normal file
@ -0,0 +1,201 @@
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/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* PCIe TLP demultiplexer (BAR ID)
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*/
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module pcie_tlp_demux_bar #
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(
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// Output count
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parameter PORTS = 2,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TLP segment data width
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parameter TLP_SEG_DATA_WIDTH = 256,
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// TLP segment strobe width
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parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
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// TLP segment header width
|
||||
parameter TLP_SEG_HDR_WIDTH = 128,
|
||||
// Base BAR
|
||||
parameter BAR_BASE = 0,
|
||||
// BAR stride
|
||||
parameter BAR_STRIDE = 1,
|
||||
// Explicit BAR numbers (set to 0 to use base/stride)
|
||||
parameter BAR_IDS = 0
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* TLP input
|
||||
*/
|
||||
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data,
|
||||
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb,
|
||||
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr,
|
||||
input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
|
||||
input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
|
||||
input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
|
||||
input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
|
||||
input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
|
||||
input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
|
||||
output wire in_tlp_ready,
|
||||
|
||||
/*
|
||||
* TLP output
|
||||
*/
|
||||
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data,
|
||||
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb,
|
||||
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr,
|
||||
output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
|
||||
output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
|
||||
output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
|
||||
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
|
||||
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
|
||||
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
|
||||
input wire [PORTS-1:0] out_tlp_ready,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable
|
||||
);
|
||||
|
||||
// default BAR number computation
|
||||
function [PORTS*3-1:0] calcBarIds(input [2:0] base, input [2:0] stride);
|
||||
integer i;
|
||||
reg [2:0] bar;
|
||||
begin
|
||||
calcBarIds = {PORTS*3{1'b0}};
|
||||
bar = base;
|
||||
for (i = 0; i < PORTS; i = i + 1) begin
|
||||
calcBarIds[i*3 +: 3] = bar;
|
||||
bar = bar + stride;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
parameter BAR_IDS_INT = BAR_IDS ? BAR_IDS : calcBarIds(BAR_BASE, BAR_STRIDE);
|
||||
|
||||
integer i, j;
|
||||
|
||||
// check configuration
|
||||
initial begin
|
||||
for (i = 0; i < PORTS; i = i + 1) begin
|
||||
if (BAR_IDS_INT[i*3 +: 3] > 5) begin
|
||||
$error("Error: BAR out of range (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
for (i = 0; i < PORTS; i = i + 1) begin
|
||||
for (j = i+1; j < PORTS; j = j + 1) begin
|
||||
if (BAR_IDS_INT[i*3 +: 3] == BAR_IDS_INT[j*3 +: 3]) begin
|
||||
$display("Duplicate BAR:");
|
||||
$display("%d: %d", i, BAR_IDS_INT[i*3 +: 3]);
|
||||
$display("%d: %d", j, BAR_IDS_INT[j*3 +: 3]);
|
||||
$error("Error: Duplicate BAR (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [TLP_SEG_COUNT*3-1:0] match_tlp_bar_id;
|
||||
|
||||
wire [TLP_SEG_COUNT-1:0] drop;
|
||||
wire [TLP_SEG_COUNT*PORTS-1:0] select;
|
||||
|
||||
generate
|
||||
|
||||
genvar m, n;
|
||||
|
||||
for (n = 0; n < TLP_SEG_COUNT; n = n + 1) begin
|
||||
for (m = 0; m < PORTS; m = m + 1) begin
|
||||
assign select[n*PORTS+m] = match_tlp_bar_id[n*3 +: 3] == BAR_IDS_INT[m*3 +: 3];
|
||||
end
|
||||
assign drop[n] = select[n*PORTS +: PORTS] == 0;
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
pcie_tlp_demux #(
|
||||
.PORTS(PORTS),
|
||||
.TLP_SEG_COUNT(TLP_SEG_COUNT),
|
||||
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
|
||||
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
|
||||
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH)
|
||||
)
|
||||
pcie_tlp_demux_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* TLP input
|
||||
*/
|
||||
.in_tlp_data(in_tlp_data),
|
||||
.in_tlp_strb(in_tlp_strb),
|
||||
.in_tlp_hdr(in_tlp_hdr),
|
||||
.in_tlp_bar_id(in_tlp_bar_id),
|
||||
.in_tlp_func_num(in_tlp_func_num),
|
||||
.in_tlp_error(in_tlp_error),
|
||||
.in_tlp_valid(in_tlp_valid),
|
||||
.in_tlp_sop(in_tlp_sop),
|
||||
.in_tlp_eop(in_tlp_eop),
|
||||
.in_tlp_ready(in_tlp_ready),
|
||||
|
||||
/*
|
||||
* TLP output
|
||||
*/
|
||||
.out_tlp_data(out_tlp_data),
|
||||
.out_tlp_strb(out_tlp_strb),
|
||||
.out_tlp_hdr(out_tlp_hdr),
|
||||
.out_tlp_bar_id(out_tlp_bar_id),
|
||||
.out_tlp_func_num(out_tlp_func_num),
|
||||
.out_tlp_error(out_tlp_error),
|
||||
.out_tlp_valid(out_tlp_valid),
|
||||
.out_tlp_sop(out_tlp_sop),
|
||||
.out_tlp_eop(out_tlp_eop),
|
||||
.out_tlp_ready(out_tlp_ready),
|
||||
|
||||
/*
|
||||
* Fields
|
||||
*/
|
||||
.match_tlp_hdr(),
|
||||
.match_tlp_bar_id(match_tlp_bar_id),
|
||||
.match_tlp_func_num(),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.enable(enable),
|
||||
.drop(drop),
|
||||
.select(select)
|
||||
);
|
||||
|
||||
endmodule
|
||||
280
rtl/pcie_tlp_mux.v
Normal file
280
rtl/pcie_tlp_mux.v
Normal file
@ -0,0 +1,280 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* PCIe TLP multiplexer
|
||||
*/
|
||||
module pcie_tlp_mux #
|
||||
(
|
||||
// Input count
|
||||
parameter PORTS = 2,
|
||||
// TLP segment count
|
||||
parameter TLP_SEG_COUNT = 1,
|
||||
// TLP segment data width
|
||||
parameter TLP_SEG_DATA_WIDTH = 256,
|
||||
// TLP segment strobe width
|
||||
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
|
||||
// TLP segment header width
|
||||
parameter TLP_SEG_HDR_WIDTH = 128,
|
||||
// select round robin arbitration
|
||||
parameter ARB_TYPE_ROUND_ROBIN = 0,
|
||||
// LSB priority selection
|
||||
parameter ARB_LSB_HIGH_PRIORITY = 1
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* TLP input
|
||||
*/
|
||||
input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data,
|
||||
input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb,
|
||||
input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr,
|
||||
input wire [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
|
||||
input wire [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
|
||||
input wire [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error,
|
||||
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid,
|
||||
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop,
|
||||
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop,
|
||||
output wire [PORTS-1:0] in_tlp_ready,
|
||||
|
||||
/*
|
||||
* TLP output
|
||||
*/
|
||||
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data,
|
||||
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb,
|
||||
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr,
|
||||
output wire [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
|
||||
output wire [TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
|
||||
output wire [TLP_SEG_COUNT*4-1:0] out_tlp_error,
|
||||
output wire [TLP_SEG_COUNT-1:0] out_tlp_valid,
|
||||
output wire [TLP_SEG_COUNT-1:0] out_tlp_sop,
|
||||
output wire [TLP_SEG_COUNT-1:0] out_tlp_eop,
|
||||
input wire out_tlp_ready
|
||||
);
|
||||
|
||||
parameter CL_PORTS = $clog2(PORTS);
|
||||
|
||||
// check configuration
|
||||
initial begin
|
||||
if (TLP_SEG_COUNT != 1) begin
|
||||
$error("Error: TLP segment count must be 1 (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (TLP_SEG_HDR_WIDTH != 128) begin
|
||||
$error("Error: TLP segment header width must be 128 (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (TLP_SEG_STRB_WIDTH*32 != TLP_SEG_DATA_WIDTH) begin
|
||||
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
wire [PORTS-1:0] request;
|
||||
wire [PORTS-1:0] acknowledge;
|
||||
wire [PORTS-1:0] grant;
|
||||
wire grant_valid;
|
||||
wire [CL_PORTS-1:0] grant_encoded;
|
||||
|
||||
// internal datapath
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_int;
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_int;
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_int;
|
||||
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
|
||||
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
|
||||
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
|
||||
reg [TLP_SEG_COUNT-1:0] out_tlp_valid_int;
|
||||
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
|
||||
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
|
||||
reg out_tlp_ready_int_reg = 1'b0;
|
||||
wire out_tlp_ready_int_early;
|
||||
|
||||
assign in_tlp_ready = (out_tlp_ready_int_reg && grant_valid) << grant_encoded;
|
||||
|
||||
// mux for incoming packet
|
||||
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] current_in_tlp_data = in_tlp_data[grant_encoded*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH +: TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH];
|
||||
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] current_in_tlp_strb = in_tlp_strb[grant_encoded*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH +: TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH];
|
||||
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] current_in_tlp_hdr = in_tlp_hdr[grant_encoded*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH +: TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH];
|
||||
wire [TLP_SEG_COUNT*3-1:0] current_in_tlp_bar_id = in_tlp_bar_id[grant_encoded*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3];
|
||||
wire [TLP_SEG_COUNT*8-1:0] current_in_tlp_func_num = in_tlp_func_num[grant_encoded*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8];
|
||||
wire [TLP_SEG_COUNT*4-1:0] current_in_tlp_error = in_tlp_error[grant_encoded*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4];
|
||||
wire [TLP_SEG_COUNT-1:0] current_in_tlp_valid = in_tlp_valid[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
|
||||
wire [TLP_SEG_COUNT-1:0] current_in_tlp_sop = in_tlp_sop[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
|
||||
wire [TLP_SEG_COUNT-1:0] current_in_tlp_eop = in_tlp_eop[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
|
||||
wire current_in_tlp_ready = in_tlp_ready[grant_encoded];
|
||||
|
||||
// arbiter instance
|
||||
arbiter #(
|
||||
.PORTS(PORTS),
|
||||
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
|
||||
.ARB_BLOCK(1),
|
||||
.ARB_BLOCK_ACK(1),
|
||||
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
|
||||
)
|
||||
arb_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.request(request),
|
||||
.acknowledge(acknowledge),
|
||||
.grant(grant),
|
||||
.grant_valid(grant_valid),
|
||||
.grant_encoded(grant_encoded)
|
||||
);
|
||||
|
||||
assign request = in_tlp_valid & ~grant;
|
||||
assign acknowledge = grant & in_tlp_valid & in_tlp_ready & in_tlp_eop;
|
||||
|
||||
always @* begin
|
||||
// pass through selected packet data
|
||||
out_tlp_data_int = current_in_tlp_data;
|
||||
out_tlp_strb_int = current_in_tlp_strb;
|
||||
out_tlp_hdr_int = current_in_tlp_hdr;
|
||||
out_tlp_bar_id_int = current_in_tlp_bar_id;
|
||||
out_tlp_func_num_int = current_in_tlp_func_num;
|
||||
out_tlp_error_int = current_in_tlp_error;
|
||||
out_tlp_valid_int = out_tlp_ready_int_reg && grant_valid ? current_in_tlp_valid : 0;
|
||||
out_tlp_sop_int = current_in_tlp_sop;
|
||||
out_tlp_eop_int = current_in_tlp_eop;
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
|
||||
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
|
||||
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
|
||||
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
|
||||
reg [TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 0, out_tlp_valid_next;
|
||||
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
|
||||
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
|
||||
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
|
||||
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
|
||||
reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
|
||||
reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
|
||||
reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
|
||||
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
|
||||
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
|
||||
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
|
||||
|
||||
// datapath control
|
||||
reg store_axis_int_to_output;
|
||||
reg store_axis_int_to_temp;
|
||||
reg store_axis_temp_to_output;
|
||||
|
||||
assign out_tlp_data = out_tlp_data_reg;
|
||||
assign out_tlp_strb = out_tlp_strb_reg;
|
||||
assign out_tlp_hdr = out_tlp_hdr_reg;
|
||||
assign out_tlp_bar_id = out_tlp_bar_id_reg;
|
||||
assign out_tlp_func_num = out_tlp_func_num_reg;
|
||||
assign out_tlp_error = out_tlp_error_reg;
|
||||
assign out_tlp_valid = out_tlp_valid_reg;
|
||||
assign out_tlp_sop = out_tlp_sop_reg;
|
||||
assign out_tlp_eop = out_tlp_eop_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign out_tlp_ready_int_early = out_tlp_ready || (!temp_out_tlp_valid_reg && (!out_tlp_valid_reg || !out_tlp_valid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
out_tlp_valid_next = out_tlp_valid_reg;
|
||||
temp_out_tlp_valid_next = temp_out_tlp_valid_reg;
|
||||
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (out_tlp_ready_int_reg) begin
|
||||
// input is ready
|
||||
if (out_tlp_ready || !out_tlp_valid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
out_tlp_valid_next = out_tlp_valid_int;
|
||||
store_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_out_tlp_valid_next = out_tlp_valid_int;
|
||||
store_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (out_tlp_ready) begin
|
||||
// input is not ready, but output is ready
|
||||
out_tlp_valid_next = temp_out_tlp_valid_reg;
|
||||
temp_out_tlp_valid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
out_tlp_valid_reg <= 1'b0;
|
||||
out_tlp_ready_int_reg <= 1'b0;
|
||||
temp_out_tlp_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
out_tlp_valid_reg <= out_tlp_valid_next;
|
||||
out_tlp_ready_int_reg <= out_tlp_ready_int_early;
|
||||
temp_out_tlp_valid_reg <= temp_out_tlp_valid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
out_tlp_data_reg <= out_tlp_data_int;
|
||||
out_tlp_strb_reg <= out_tlp_strb_int;
|
||||
out_tlp_hdr_reg <= out_tlp_hdr_int;
|
||||
out_tlp_bar_id_reg <= out_tlp_bar_id_int;
|
||||
out_tlp_func_num_reg <= out_tlp_func_num_int;
|
||||
out_tlp_error_reg <= out_tlp_error_int;
|
||||
out_tlp_sop_reg <= out_tlp_sop_int;
|
||||
out_tlp_eop_reg <= out_tlp_eop_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
out_tlp_data_reg <= temp_out_tlp_data_reg;
|
||||
out_tlp_strb_reg <= temp_out_tlp_strb_reg;
|
||||
out_tlp_hdr_reg <= temp_out_tlp_hdr_reg;
|
||||
out_tlp_bar_id_reg <= temp_out_tlp_bar_id_reg;
|
||||
out_tlp_func_num_reg <= temp_out_tlp_func_num_reg;
|
||||
out_tlp_error_reg <= temp_out_tlp_error_reg;
|
||||
out_tlp_sop_reg <= temp_out_tlp_sop_reg;
|
||||
out_tlp_eop_reg <= temp_out_tlp_eop_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_out_tlp_data_reg <= out_tlp_data_int;
|
||||
temp_out_tlp_strb_reg <= out_tlp_strb_int;
|
||||
temp_out_tlp_hdr_reg <= out_tlp_hdr_int;
|
||||
temp_out_tlp_bar_id_reg <= out_tlp_bar_id_int;
|
||||
temp_out_tlp_func_num_reg <= out_tlp_func_num_int;
|
||||
temp_out_tlp_error_reg <= out_tlp_error_int;
|
||||
temp_out_tlp_sop_reg <= out_tlp_sop_int;
|
||||
temp_out_tlp_eop_reg <= out_tlp_eop_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
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Reference in New Issue
Block a user